Slew rate, clock integrity and duty cycle detection in an integrated circuit

Abstract

In a semiconductor Integrated Circuit (IC), a slew rate and / or a clock integrity of a signal may be determined by measuring, using a circuit, a duty cycle of the signal. The circuit may be further configured with an adjustable logic threshold of the signal, for the duty cycle measurement of the signal. The circuit may further include: an input sampling block, including a skewed control input buffer to receive the signal, the input sampling block being configured to provide a sampling output comprising pulses each having a width according to the signal being at or above the adjustable logic threshold; and a duty cycle measurement circuit, configured to output a measurement of a duty cycle of the sampling output, thereby measuring the duty cycle of the signal.

Description

SLEW RATE, CLOCK INTEGRITY AND DUTY CYCLE DETECTION IN AN INTEGRATED CIRCUIT FIELD OF THE INVENTION

[0001] The invention relates to the field of integrated circuits.BACKGROUND

[0002] Semiconductor integrated circuits (ICs) typically include analog and digital electronic circuits on a flat semiconductor substrate, such as a silicon wafer. Microscopic transistors are printed onto the substrate using photolithography techniques to produce complex circuits of billions of transistors in a very small area, making modern electronic circuit design using ICs both low cost and high performance. ICs are produced in assembly lines of factories, termed foundries, which have commoditized the production of ICs, such as complementary metal -oxide-semiconductor (CMOS) ICs.

[0003] Clock signals are fundamental to the operation of modern ICs. These signals are typically generated by a clock source and distributed throughout the chip to synchronize various operations. Precise control and measurement of clock signal characteristics, such as slew rate and duty cycle, are crucial for ensuring proper chip functionality and performance.

[0004] Slew rate, typically defined as the rate of change of a signal's voltage over time, directly impacts signal integrity and noise margins. An excessively fast slew rate can lead to signal distortion, electromagnetic interference (EMI), and increased power consumption. Conversely, a slow slew rate can limit the maximum operating frequency of the chip and introduce timing uncertainties.

[0005] Duty cycle, the ratio of the time the signal is high to the total period, influences the average power consumption of the chip. Deviations from the desired duty cycle can affect the performance of clock-sensitive circuits and introduce timing errors.

[0006] The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the figures.SUMMARY

[0007] The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools and methods which are meant to be exemplary and illustrative, not limiting in scope.

[0008] There is provided a circuit and / or method for measuring a slew rate and / or a clock integrity of a signal in a semiconductor integrated circuit (IC) in accordance with independent claims 1 and 15. A non -transitory computer readable medium having stored thereon a computer -readable encoding of a sensor for measurement a slew rate and / or a clock integrity of a signal in a semiconductor IC is defined in independent claim 25. Further embodiments are defined in the corresponding dependent claims. The description and drawings also present additional aspects, examples, implementations and non-claimed embodiments for the better understanding of the claimed embodiments.

[0009] In an aspect, there is provided a circuit within a semiconductor Integrated Circuit (IC), configured to determine a slew rate and / or a clock integrity of a signal in the IC by measuring a duty cycle of the signal.

[0010] In embodiments, the circuit is further configured with an adjustable logic threshold of the signal for the duty cycle measurement of the signal.

[0011] In embodiments, the circuit further comprises: an input sampling block, comprising a skewed control input buffer to receive the signal, the input sampling block being configured to provide a sampling output comprising pulses each having a width according to the signal being at or above the adjustable logic threshold; and a duty cycle measurement circuit, configured to output a measurement of a duty cycle of the sampling output, thereby measuring the duty cycle of the signal.

[0012] In embodiments, the skewed control input buffer comprises: a plurality of inverter branches, each inverter branch having a respective number of one or more n-type transistors and the same number of p-type transistors, the number differing between branches; and wherein, for each branch, the one or more n-type transistors are controlled by a respective first enable signal and the one or more p-type transistors are controlled by a respective second enable signal, the plurality of first enable signals and plurality of second enable signals thereby controlling the adjustable logic threshold.

[0013] In embodiments, the input sampling block and the duty cycle measurement circuit use a sampling clock distinct from the signal.

[0014] In embodiments, the circuit further comprises: a synchronization circuit, configured to synchronize the sampling output to the sampling clock.

[0015] In embodiments, the duty cycle measurement circuit comprises: a clock counter, configured to count a number of edges for the sampling clock to provide a clock count thereby; and a pulse counter, configured to count a number of edges for the sampling output to provide a pulse count thereby, a ratio of the pulse count to the clock count being indicative of the duty cycle of the sampling output.

[0016] In embodiments, the sampling clock has a non-rational ratio to the signal.

[0017] In embodiments, the circuit further comprises: a ring oscillator circuit (ROSC), configured to generate the sampling clock.

[0018] In embodiments, the input sampling block further comprises: a differential flip-flop, having a data input configured to receive an output from the skewed control input buffer and a clock input configured to receive the sampling clock, the differential register providing a sampled signal output thereby.

[0019] In embodiments, the input sampling block further comprises a clock integrity testing circuit.

[0020] In embodiments, the clock integrity testing circuit comprises: a first synchronization buffer, having a data input configured to receive an enable signal and a clock input configured to receive the signal through a symmetric buffer and configured to provide a first synchronizer output; a second synchronization buffer, having a data input configured to receive an enable signal and a clock input configured to receive the signal through the skewed control input buffer and configured to provide a second synchronizer output; a first counter, configured to generate a first count output from the first synchronizer output; and a second counter, configured to generate a second count output from the second synchronizer output, a comparison between the first and second count outputs being indicative of clock integrity.

[0021] In embodiments, the circuit is configured to: measure a first duty cycle of the signal using a first logic threshold; and measure a second duty cycle of the signal using a second, different logic threshold. Then, the slew rate is determined based on a difference between the first and second duty cycles.

[0022] In embodiments, the circuit is further configurable to selectively output an indication of either: (i) the duty cycle of the signal; or (ii) a duty cycle of an internal reference clock that has been divided by two.

[0023] In an aspect, there is provided a method for determining a slew rate and / or a clock integrity of a signal in a semiconductor Integrated Circuit (IC) by measuring a duty cycle of the signal.

[0024] In embodiments, a logic threshold used for measuring the duty cycle of the signal is adjustable.

[0025] In embodiments, the method further comprises: buffering the signal using a skewed control input buffer to provide a sampling output comprising pulses each having a width according to the signal being at or above the adjustable logic threshold; and wherein measuring the duty cycle of the signal comprises measuring a duty cycle of the sampling output.

[0026] In embodiments, the signal is buffered and the duty cycle measured using a sampling clock distinct from the signal.

[0027] In embodiments, the method further comprises: synchronizing the sampling output to the sampling clock.

[0028] In embodiments, measuring the duty cycle of the sampling output comprises: counting a number of edges for the sampling clock to provide a clock count thereby; and counting a number of edges for the sampling output to provide a pulse count thereby, a ratio of the pulse count to the clock count being indicative of the duty cycle of the sampling output.

[0029] In embodiments, the sampling clock has a non-rational ratio to the signal.

[0030] In embodiments, the sampling clock is generating using a ring oscillator circuit (ROSC).

[0031] In embodiments, determining the clock integrity of the signal comprises: providing a first synchronizer output from a first synchronization buffer, having a data input configured to receive an enable signal and a clock input configured to receive the signal through a symmetric buffer; providing a second synchronizer output from a second synchronization buffer, having a data input configured to receive an enable signal and a clock input configured to receive the signal through the skewed control input buffer; counting the first synchronizer output to generate a first count output thereby; and counting the second synchronizer output to generate a second count output thereby, a comparison between the first and second count outputs being indicative of the clock integrity.

[0032] In embodiments, the method further comprises: measuring a first duty cycle of the signal using a first logic threshold; and measuring a second duty cycle of the signal using a second, different logic threshold. The slew rate is determined based on a difference between the first and second duty cycles.

[0033] In an aspect, there is provided a non-transitory computer readable medium having stored thereon a computer-readable encoding of a circuit for determining in a semiconductor Integrated Circuit (IC) a slew rate and / or a clock integrity of a signal in the IC by measuring a duty cycle of the signal. In embodiments, this may have any of the features associated with the circuit and / or method discloses herein.BRIEF DESCRIPTION OF THE FIGURES

[0034] Exemplary embodiments are illustrated in referenced figures. Dimensions of components and features shown in the figures are generally chosen for convenience and clarity of presentation and are not necessarily shown to scale. The figures are listed below.

[0035] FIG. 1 A shows schematically a block diagram of circuit according to an embodiment;

[0036] FIG. IB shows a first illustration of correlation between slew rate and a pulse width difference;

[0037] FIG. IC shows a second illustration of correlation between slew rate and a pulse width difference;

[0038] FIG. 2 shows a schematic circuit diagram of skewed control input buffer (IB) according to an embodiment;

[0039] FIG. 3 shows an exemplary plots from a simulation of a skewed control IB according to FIG. 2, indicating how changing a trip point of the IB changes skew;

[0040] FIG. 4 shows an exemplary plots from the simulation of a skewed control IB according to FIG. 2, illustrating the effect of input buffer skew on pulse width;

[0041] FIG. 5 shows a schematic illustration of how sampling time can affect pulse width measurement;

[0042] FIG. 6A shows exemplary plots illustrating the measurement a first, relatively low slew rate by comparing pulse widths;

[0043] FIG. 6B shows exemplary plots illustrating the measurement a second, relatively high slew rate by comparing pulse widths;

[0044] FIG. 6C shows an exemplary graph of pulse width difference against average slew rate, showing a correlation;

[0045] FIG. 7 shows a high-level block diagram of an exemplary slew rate and / or clock integrity measurement circuit according to an embodiment;

[0046] FIG. 8 shows an example circuit for a programmable oscillator block of a slew rate and / or clock integrity measurement circuit according to an embodiment;

[0047] FIG. 9 shows an example circuit for an input sampling block of a slew rate and / or clock integrity measurement circuit according to an embodiment;

[0048] FIG. 10 shows an exemplary timing diagram illustrating sampling of signals within a slew rate and / or clock integrity measurement circuit according to an embodiment;

[0049] FIG. 11 shows an example circuit for a synchronizer block of a duty cycle measurement circuit according to an embodiment;

[0050] FIG. 12 shows an example circuit for a counters block of a duty cycle measurement circuit according to an embodiment; and

[0051] FIG. 13 shows an exemplary timing diagram illustrating a measurement mode of a slew rate and / or clock integrity measurement circuit according to an embodiment.DETAILED DESCRIPTION

[0052] Disclosed herein is a technique, embodies in one or more devices, systems, and methods, to determine (for example, to measure, detect, and / or to estimate) a slew rate (SR) and / or clock integrity of a signal in a semiconductor IC (such as, but not limited to, a clock signal) using a duty cycle (DC) measurement circuit.

[0053] The clock path of a semiconductor IC is typically built from clock cells like clock-inverters, clock-buffers, and clock-gating circuits. The clock path starts from the clock source which is a clock-generator based on a phase-locked loop (PLL), and then propagates via various clock-routes to drive the chip sequential circuits (for instance, registers or flip-flops, latches, embedded memory). The length of the clock-path may corelate to the chip size (or core size) and its propagation delay can get to hundreds of picoseconds. When the clock is propagating via the clock path, the clock signal may develop a duty-cycle distortion at the clock end points due to non-symmetrical rise and fall delays along the clock path. The rising and falling clock-path delays may also change differently due to non-symmetrical voltage and temperature effects on each N-transistor and P-transistor. Aging can cause this effect to worsen over time. As a result, the clock duty-cycle may become distorted. The distortion is accumulated along the clock-path, and it generally increases proportionally with the clock path length. In a severe clock duty -cycle distortion, one of the clock phases can shrink to a level that the pulse will no longer propagate via the clock path. By measuring DC distortion, it has been found that an indication about the Slew-Rate of the clock signal can be given. It may thus provide a real time hardware signal to alert thatone of the clock phases is below a configured threshold, or if the clock signal has an integrity issue, for example, high slew-rate and low clock signal amplitude (indicative of rail-to-rail issues).

[0054] In embodiments, a skewed-control input buffer drives the duty cycle measurement circuit, as schematically illustrated in Fig. 1A. The skewed-control input buffer may sample the signal (also referred to herein as an “input signal”) and generate a corresponding signal having a certain pulse width (PW) at the output of the skewed-control input buffer. The PW may then be measured by the duty cycle measurement circuit.

[0055] The change in (that is, delta) PW at the output of the input buffer as the input buffer skew is changed, may be directly proportional to the input signal slew rate. Thus, by characterizing and / or measuring the delta PW as the skew varies, the input signal’s slew rate may be determined or extracted (namely, measured, detected, and / or estimated). The PW may be measured by measuring duty cycle. This is performed by a Duty Cycle measurement circuit (DCS) at the output of the skewed-control IB.

[0056] In embodiments, the technique may be utilized for clock signal monitoring. Clock signals (denoted “CLK” in the figures) often become filtered due to insufficient slew rate in the silicon, but typically there is no DFT (Design for Testability) to monitor both slew rate and duty cycle of the clock signal. In addition, there is typically no way to track duty cycle distortion correlated to or resulting from slew rate problems.

[0057] Accordingly, present embodiments may advantageously constitute a DFT for both duty cycle, slew rate and clock integrity characterization, both during testing of the IC and in mission mode (when the IC is deployed in the field and used with real signals of its user, not special test signals). In mission mode, specifically, present embodiments may periodically monitor the gradual degradation of the duty cycle, slew rate and / or clock integrity resulting from aging of the IC. Whilst a clock signal is used as an input signal for exemplary embodiments, this is not essential and other signals can be measured.

[0058] Figs. IB and IC show two exemplary cases of input signal slew rates:

[0059] The first case, Fig. IB, shows a first case of an input signal with a fast slew rate, where the input signal is driving the input buffer (IB) in two scenarios. In the first scenario, the IB trip point is trimmed to low voltage causing a longer PW (PW low), and in the second scenario the trip point is trimmed to high voltage causing a shorter PW (PW high). The IB generates a PW at its output in these two scenarios of Fig. IB. The delta PW generating the magnitude of PW high - PW low is measured by the DCS (duty cycle sensor, namely the duty cycle measurement circuit).

[0060] The second case, Fig. 1C, shows a second case of an input signal with a slower slew rate, where the input signal is driving the input buffer (IB) in two scenarios. In the first scenario, the IB trip point is trimmed to low voltage causing a longer PW (PW low), and in the 2ndscenario the trip point is trimmed to high voltage causing a shorter PW (PW high). The IB generates a PW at its output in the two scenarios of Fig. 1C. The delta PW generating the magnitude of PW high -PW low is measured by the DCS.

[0061] As can be seen by comparing Fig. 1C with Fig IB, the delta PW that is measured in the second case will be higher than the delta PW measured in the first case, and this indicates a higher slew rate. Correspondingly, the difference in delta PW in the two cases is proportional to the change in input slew-rate between the cases. Effectively, the logic threshold (trip point) of the signal for the duty cycle measurement of the signal is being adjusted.

[0062] Referring for Fig. 2, there is shown a schematic circuit diagram of the contents of the skewed control input buffer (IB) of Fig. 1A according to an exemplary embodiment. In embodiments, as illustrated in Fig. 2, the skewed control IB may be implemented by a four-branch CMOS inverter. Each branch comprises a number of N-transistors in series with the same number of P-transistor: branch-1 size = IN and IP; branch-2 size = 2N and 2P; branch-3 size = 4N and 4P; Branch-4 size = 8N and 8P.

[0063] At the top, each series of transistors is connected to VDD, and at the bottom, to VSS.

[0064] Using different combinations of upper four control bits (cnt_p_[0], ..., cnt_p_[3]), the current output of the four P-devices can be set. The gate of the leftmost P-device can be set to voltage X, the gate of the next P device to 2X, and so on until 8X. Combining different voltages at these four gates will yield 16 different output currents. The same control method is used for the four N devices at the bottom.

[0065] Overall, the input buffer receives a clock signal (Clk in), and outputs a clock signal with a certain slew rate (Clk out, illustrated in Figs. 1B-1C) affected by the 8 bits of N and P control signals. The ratio between the N and P control signals therefore sets the hence the “height” of the trip (inversion) point, thereby affecting the pulse width.

[0066] It should be noted that, in order to generate a skew, the values of the P and N control signals should be different, because if the ratio of P / N is 1 : 1, the output clock will have the same skew as the input clock. A range of values of N and P control signal combinations can be used. In practice, to avoid the overhead required to set 8 bits for every output pulse width, each possible configuration can be encoded using only 5 bits. This is possible because not all 8 bits are truly needed; as explained above, setting the N and P devices to the same voltage has no value in thisapplication, so the 5 bits of configuration can omit all possible identical settings (e.g., 0 and 0, 1 and 1, ... 15 and 15). The circuit may therefore include a decoder (not shown) that sets the 8 bits in accordance with the 5-bit configuration signal.

[0067] This design of skewed-control IB is simply an example and it will be recognized that any other circuit that can provide the same type of controlled pulse width output will achieve the same beneficial end result. For example, the skewed-control IB can include a larger number of branches (e.g., 16 instead of 4), each controlled separately to set a distinct gate voltage level, instead of the configuration of Fig. 2 that uses a combination of 4 voltage levels to achieve the desired 16 different output currents (albeit in an efficient way). The number of branches can also be altered to achieve a different resolution of the output pulse width. An 8-bit resolution was deemed to represent an effective tradeoff between accuracy and circuit complexity.

[0068] The PMOS transistor and the NMOS transistor of each branch may be separately controlled by individual enable signals.

[0069] The Skew of the IB may be determined by the ratio of the total number of activated PMOS transistors vs. the total number of activated NMOS transistors. This will be detailed further below.

[0070] A simulation of the IB trip point vs. skew is illustrated in Fig. 3. The different upper plots show how the application of different numbers of NMOS transistors and PMOS transistors (effected by using different combinations of enable signals) causes different skews. The lower plots then demonstrate that these changes in skew effectively cause different trip points for the IB with reference to the original signal. By controlling the input stage skew, different trip points of the SR input stage may thus be set.

[0071] Input buffer skew will impact the rising and falling edge timing as well as the PW itself, as illustrated in Fig. 4. Different skews cause different trip point values, which in turn lead to changes in PW :

[0072] PW_high = PW while using lowest skew in input stage;

[0073] PW_low = PW while using highest skew in input stage; and

[0074] MAX(APW) = |PWhigh- PWlow|.

[0075] In embodiments, as schematically illustrated in Fig. 5, uniform sampling may advantageously sample Phase High (PH) and Phase Low (PL) equally: Per [X] samples at 50% duty cycle (DC), ~ [X / 2] samples will sample PH and PL.

[0076] For a certain DC:

[0077] Number of samples at PH: [X] • DC; and

[0078] Number of samples at PL: [X] • (1 - DC).

[0079] Uniform sampling may be achieved by a sampling clock with a non-rational ratio to the sampled clock, for example a ROSC (ring oscillator). Generation of the sampling clock (osc clock div) is discussed further below. Use of a distinct sampling clock for the sampling and measurement permits this uniform sampling.

[0080] The output of the slew rate buffer may be measured by the duty cycle circuit (also termed here “sensor”).

[0081] An exemplary measurement of the slew rate of two input signals is illustrated in Figs. 6A and 6B. Fig. 6A illustrated a relatively low slew rate of 8 picoseconds (pS), while Fig 6B illustrates a relatively high slew rate of 49 pS.

[0082] In this example, APW = |PWhigh— PWiow|.

[0083] It is noted that changing the SR will change APW in a linear trend. This is illustrated by the example two input signals in these drawings:

[0084] Fig. 6A: SR « 8pS, PWhigh= 105.5pS, PWjow= 67pS -> APW « 38pS -> lowest SR.

[0085] Fig. 6B: SR « 49pS, PWhigh= 126. IpS, PWjow= 65pS -> APW « 61pS -> highest SR.

[0086] The plot of Fig. 6C shows the linear relation between the delta PW to the signal slew rate. The plot was generated (in a simulation) by scanning the skew of the IB for each input signal slew rate and measuring the delta PW.

[0087] Details of specific exemplary embodiments of the slew rate and / or clock integrity measurement circuit will now be discussed. With reference to FIG. 7, there is shown a high-level block diagram of an exemplary slew rate measurement circuit according to an embodiment. This comprises: an oscillator block (analog); an input sampling (input buffer and sampling) block (analog); a synchronizer block (synchronization circuit); and a counters block. Each of these blocks will be described in more detail below. A 29-bit configuration bus (prtn dcs cfg, not shown in this drawing) is used for setting up the system. The clock to be measured (ptm dcs clock) is provided as an input to the input sampling block. The other signals generated by the blocks and / or passed between the blocks will be discussed further below.

[0088] The slew rate measurement circuit can operate in four mutually exclusive modes set by prtn_dcs_cfg[24 : 23 ] .

[0089] A first mode is a Duty-Cycle Measurement Mode in Operation. In this mode, the circuit continuously measures the Input clock signal Duty Cycle at Operational mode, such that the data stored in the controller is the last measurement. At the end of the measurement, the Duty-Cycledata is output by the DSC controller (prtn dcs ctrl). The Phase-High counts (prtn_dcs_ph_count[l 1 :0]) is output at prtn dcs outl [11 :0], The Phase-Low counts is calculated by the logic and output at prtn_dcs_out2[l 1 :0],

[0090] A second mode is a Duty-Cycle Measurement Mode in Characterization. In characterization, the clock Duty-Cycle can be measured for different Input-Buffer skew for Clock signal Slew-rate estimation. At the end of the measurement, the Duty -Cycle data is output by the DSC controller (prtn dcs ctrl). The Phase-High counts (prtn_dcs_ph_count[ll:0]) is output at prtn_dcs_outl[ll:0]. The Phase-Low counts is calculated by the logic and output at prtn_dcs_out2 [11:0],

[0091] A third mode is a clock integrity measurement mode. In this mode, the DCS measures the input clock signal integrity at characterization, i.e., clock signal filtering caused by clock signal amplitude (rail-to-rail). At the end of the measurement, the Fast clock cycles count (discussed below) is output by the DSC controller (prtn dcs ctrl). The cntl_count[9:0] (fast clock driven by a symmetrical buffer) is output at prtn_dcs_outl[9:0]. The cnt2_count[9:0] (fast clock driven by a skewed buffer) is output at prtn_dcs_out2[l 1:0], This is detailed further with reference to FIG. 9.

[0092] A fourth mode is a DFT Mode. In this mode, the DCS measures the Duty Cycle of an Internal clock generated by a DFT ROSC after a divide by two. At the end of the measurement, the Duty-Cycle data is output by the DSC controller (prtn dcs ctrl). The Phase-High counts is output at prtn dcs outl [11 :0], The Phase-Low counts is output at prtn_dcs_out2[l 1 :0],

[0093] The oscillator block generates the osc clock div signal which is used as the sampling clock (slow clock) that samples the measured clock connected to Din of the input sampling block in operational mode. The slow clock is buffered by the input sampling block and, in its buffered form, output to clock the counters block. As outlined previously, the input sampling block samples the measured clock with an equal setup-time for [0] & [1], The sampling block generates outputs (as will be discussed below): a sampling output ph smp; a first counter output cntl_count[9:0]; and a second counter output cnt2_count[9:0]. The sampling output ph smp is equal to 1’bl (binary, unsigned, 1 -bit wide integral value) if the sampler sampled the PH of the measured clock by the osc clock div rising edge, as will be discussed below with reference to FIG. 10. The first counter output cntl_count[9:0] and second counter output cnt2_count[9:0] represent cycles count of the prtn dcs clock signal generated by two buffers with a different trip point levels (symmetrical and skewed); mismatch between the cntl and cnt2 counts indicates a rail-to-rail issue of prtn dcs clock signal, as will be discussed with reference to FIG. 9 below.

[0094] The Skewed-control IB within the input sampling block is used to explore clock integrity issues (mainly slew-rate). The Skewed-control IB drives a symmetrical sampler. The Skewed-control IB slices the input signal according to its programmable (adjustable) skew and generates a corresponding Phase-High (PH) pulse at its output, the PH Pulse-Width is then sampled to measure the clock Duty-Cycle (DC). Alternatively, a Phase Low (PL) Pulse-Width may conversely be used, since the clock frequency does not change. The DC is proportional to the Pulse-Width. By characterizing the Pulse-Width against the IB skew, it is possible to determine the input signal slew-rate, as explained above.

[0095] In the Logic part (RTL), ph smp is synchronized by the synchronizer block (synchronization circuit) to the rising-edge of the slow clock. The counters block increases its output by one each time the input data at Din is sampled high, thereby indicating DC. The logic generates an alert signal if the measured phase (PL or PH) is below a certain threshold.

[0096] Referring next to FIG. 8, there is shown an example circuit for a programmable oscillator block of a slew rate measurement circuit according to an embodiment. The programmable oscillator block generates the sampling (slow) clock (osc clock div) for the symmetrical sampler. The ratio between the Slow-clock and the measured clock (prtn dcs clk) should be approximately 0.1. The oscillator is enabled by the dcs slow clk osc en signal. A configurable divider is controlled by a divider configuration signal (dcs_osc_div_x8_16). The default value is dcs_osc_div_x8_16 = [0], giving a divider value of 16 and when dcs_osc_div_x8_16 = [1], the divider value is 8. For DFT purposes, the oscillator block generates another clock (osc clock) using a separate DFT ROSC. This clock (an internal reference clock) is used as an un-synchronized slow-clock for measuring the duty-cycle of the osc clock signal after a divide by two, as discussed further below.

[0097] Referring now to FIG. 9, there is shown an example circuit for an input sampling block of a slew rate measurement circuit according to an embodiment. The measured clock signal (dcs clk) is passed through the skewed-control IB and, in parallel, a symmetric buffer. These signals are supplied, together with the DFT ROSC clock (internal reference clock) to a multiplexer, the output of which is provided to a Differential Flip-Flop (Diff FF). The Data signal for this is selected by the dcs_smp_din_sel[l:0] signal applied to the multiplexer.

[0098] When the measured clock is selected, the Differential FF (Diff FF) samples it with an equal setup-time for [0] & [1] (symmetrical FF). In operational mode, the Diff FF data signal is the measured clock (prtn dcs clk) before or after the skewed IB. In test mode (DFT), the data signal is the DTF ROSC clock (dft osc clk) after divide by two. The clock of the Diff FF is sampling clock osc clk div (used as the slow clock).

[0099] The input sampling block also includes a clock integrity testing circuit. This comprises two 10-bit counters: a first counter Cntl; and a second counter Cnt2. These both count the measuredclock cycles, but using different input clocks. The input clocks are generated by two (synchronization) buffers with a different trip point level (symmetrical and skewed) that acts as a voltage slicer. Mismatch between the first counter cntl output and second counter cnt2 output may indicate a rail-to-rail issue of prtn dcs clock signal. The two counters are enabled by the dcs clk intg en signal that is generated by the logic block. The two counters implement a selfstop mechanism. When the most-significant bit (MSB) of the first counter (dcs_cntl_count[9]) or the MSB of the second counter (dcs_cnt2_count[9]) is set to 1, the OR gate feedbacks a signal to set the counters enable to [0] and the count is stopped. The valid signal dcs clk intg valid should be synchronized (to prtn clk domain) in the logic control block, and this will enable sampling the results. The counters reset signal (dcs a cnt rst n) should come from a state machine (should be in prtn clk domain) that should reset the counters in an asynchronous way, and preferably makes sure that the enable signal is set after a wait of 16 prtn clk cycles. The reset is not synchronized to meet timing in reset de-assertion, since it is made multi cycle by waiting 16 prtn clk cycles until the enable is asserted and the counters start to count.

[0100] Referring now to FIG. 10, there is shown an exemplary timing diagram illustrating sampling of signals within a slew rate measurement circuit according to an embodiment. The two main outputs of the input sampling block are shown: the sampling output ph smp; and the counters output. The reference to the sampling (slow) clock is also shown.

[0101] With reference to FIG. 11, there is shown an example circuit for a synchronizer block (synchronization circuit) of a slew rate measurement circuit according to an embodiment. This comprises two serial registers (flip-flops) for the sampling output dcs_ph_smp and two serial registers (flip-flops) for the reset signal, all of which are clocked by the sampling (slow) clock. The synchronized sampling output (ph smp sync) of the synchronizer block is then used in the counters block, as discussed below.

[0102] Reference is now made to FIG. 12 that shows an example circuit for a counters block of a duty cycle measurement circuit according to an embodiment. The counter block comprises a clock counter (Counter [1]) used to count edges of the sampling clock (dcs slow clock); and a pulse counter (Counter [2]), used to count edges of the synchronized sampling output (ph smp sync) .

[0103] The enable signal to the pulse counter should be raised for [X] number sampling clock (dcs slow clock) cycles. [X] is a programmable number that is set by the configuration bus as prtn_dcs_cfg[2:l], [X] can be programed to four optional values:

[0000] = 2A9,

[0001] = 2A10,

[0010] = 2A11 and

[0011] = 2A12. The enable signal to the pulse counter should be raised after one sampling clock (dcs slow clock) cycle after the dcs smp rst n signal is de-asserted and should be stay high for [X] sampling clock (dcs slow clock) cycles. The prtn_dcs_ph_valid signal is output by theclock counter and it raised after the clock counter counts [X] sampling clock (dcs slow clock) cycles.

[0104] The Duty-Cycle measurement accuracy can be analyzed. The following definitions are used:1. Tosc= Oscilator cycle time slow clock after divider)2. Tfast clk= Measured clock cycle time (fast clock)3. PHfcik = Measured clock High phase width4. Tmeas= Measurement time5. N = Number of fosc(slow — clock) rising edges within Tmeas6. Count = Number of PHfcik sampled by the slow — clock within Tmeas7. X = counter 1 count length (programmbel value)

[0105] A number of Duty-Cycle measurement equations can then be determined:> >> > >> >

[0106] Using these equations, the measurement accuracy may be determined by the number of samples within the measurement time (Tmeas), assuming that the samples are distributed evenly across the fast-clock cycle time.> > >2. For example, the required [X] to achieve measurement accuracy of 1 [ps] in measuring the DC of 1GHz clock can be determined:a- Tfast clk= 1000 [ps]d-meas - N X Tosc cik — 10 [us]e. X = N = 1000

[0107] Referring now to FIG. 13, there is shown an exemplary timing diagram illustrating a measurement mode of a slew rate measurement circuit according to an embodiment. The signal being measured, also termed the measurement clock (ptrn clk) is shown initially, followed by the reset signal (rst n) generated in the synchronizer block and the configuration bus (prtn_dcs_cfg[28:0]). The next signal enables the sampling (slow) clock generation (slow clk osc en) and the RO SC -generated clock (osc clock) is then shown followed by its divided version, used as the sampling (slow) clock (slow clock). An optional clock stability signal (elk good) is also shown. Reset signals are then shown for other parts of the sampling and counting logic.

[0108] The reset signal, rst n is an active low, asynchronous reset. The logic enters reset state when rst n is low, asynchronously to the clock. The logic exits reset state when rst n is asserted high and synchronized to the next rising edge of prtn elk.

[0109] Measurement mode flow for Duty-Cycle measurement mode is now detailed. When rst n is de-asserted, the prtn dcs ctrl block should sample the prtn dcs cfg bus. In addition, the following signals should be set to 1 ’b0 (reset value) when prtn dcs rst n is active during the reset stage: dcs slow clk osc en; prtn dcs valid; prtn_dcs_outl[ll:0]; prtn_dcs_out2[ll:0]; and prtn dcs alert. The sampled version of prtn dcs cfg bus should be connected directly to prtn dcs exactly as they appear in the prtn dcs cfg bus. The signals towards the analog block of the circuit are quasi static. Set slow clk osc en to 1’bl . The slow clk osc en signal is used to enable the slow-clock oscillator within the prtn dcs block. Wait for the oscillator to stable. In other words, the logic should create a window and counting pulses should work after the slow clock is available. For example, wait 16 prtn clk cycles after the clock is seen as available. De-assert the dcs_pre_smp_rst_n signal. The dcs_pre_smp_rst_n is an asynchronous reset signal that is sampled by the by synchronizer block. After 1 or 2 dcs slow clock clock cycles, the synchronizer will deassert the dcs smp rst n which is the reset signal to the sampler block. The sampling clock (slow clock) clock cycle begins after the de-assertion of the dcs smp rst n. Start to count the dcs osc clock cycles with the clock counter (Counter [1]) and rise the enable for the pulse counter (Counter [2]). Start to count the synchronizer output signal pl smp sync. When the clock counter (Counter [1]) count equals [X] ([X] is defined by prtn_dcs_cfg[2:l]), the pulse counter (Counter [2]) is sampled to prtn_dcs_ph_count[l 1 :0] output, prtn_dcs_pl_count[l 1 :0] is calculated as [X] -prtn_dcs_ph_count[l 1 :0], the enable for the pulse counter (Counter [2]) is set to zero and the valid signal (prtn dcs valid) is risen. DFT mode works the same way, but with a different input measurement signal, as discussed above.

[0110] In clock integrity measurement mode, when rst n is de-asserted, the prtn dcs ctrl block should sample the prtn dcs cfg bus. In addition, the following signals should be set to 1’bO (reset value) when prtn dcs rst n is active during the reset stage: dcs slow clk osc en; prtn dcs valid; prtn_dcs_outl[ll:0]; prtn_dcs_out2[l 1:0]; and prtn dcs alert. The logic should then de-assert prtn a cnt rst n, wait 16 prtn clock cycles, set high dcs clk intg en and when prtn clk intg valid is high: sample dcs_cntl_count[9:0]; sample dcs_cnt2_count[9:0]; move dcs_cntl_count[9:0] to prtn_dcs_outl[9:0], prtn_dcs_outl[ll:10] =

[0000] ; and move dcs_cnt2_count[9:0] to prtn_dcs_out2[9:0], prtn_dcs_out2[ll:10] =

[0000] ,

[0111] The circuit provides two readouts: Phase High-count and Phase Low-count. These two readouts represent the Phase-High (PH) width and the Phase-Low (PL) width of the clock under monitor. Calculation of the percentage of Duty-Cycle-Distortion (% DCD) of the clock under monitor is possible by using the following equations.

[0112] A hardware alert per Phase High and Phase low threshold may be provided. The DCS measurements are compared to a preset threshold to generate a HW alert signal to detect minimum phase width (reflected by phase count). One threshold can be set for minimum PH and another for minimum PL. The threshold may be derived from the maximum available counts which is equal to 2AX, X being configurable number (part of the DCS configuration bus: prtn_dcs_cfg[2: 1]).

[0113] The threshold value can be compared against the following values: PH-count if prtn_dcs_cfg[25:24] =

[0000] ; PL-count if prtn_dcs_cfg[25:24] =

[0001] ; and a logical OR of PH-count and PL-count bits, if prtn_dcs_cfg[25:24] =

[0010] , If prtn_dcs_cfg[25:24] =

[0011] , the alert is off.

[0114] A range of circuit designs and schematics are described herein. It will be appreciated that these circuit designs can be embodied in an electronic (also ‘digital’) representation (also ‘encoding’). The electronic representation may be stored in a computer readable medium, particularly of a non-transitory nature. A suitable electronic representation may include a representation for Electronic Computer-Aided Design (ECAD) software, also referred to as Electronic Design Automation (EDA) software. In this case, parts of the representation may be stored across multiple electronic documents or files, possibly including one or more libraries of the ECAD software providing details of the components of the circuit. The ECAD representation may provide instructions suitable for manufacture (also ‘fabrication’) of a circuit as represented inthe design. According to the disclosure, there may be provided such an electronic representation. A method of using such an electronic representation of an electronic circuit as part of manufacturing the electronic circuit is further considered.

[0115] Throughout this disclosure, various embodiments may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

[0116] Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases “ranging / ranges between” a first indicate number and a second indicate number and “ranging / ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween.

[0117] In the description and claims of the disclosure, each of the words “comprise” “include” and “have”, and forms thereof, are not necessarily limited to members in a list with which the words may be associated. In addition, where there are inconsistencies between this application and any document incorporated by reference, it is hereby intended that the present application controls.

[0118] To clarify the references in this disclosure, it is noted that the use of nouns as common nouns, proper nouns, named nouns, and the / or like is not intended to imply that embodiments of the invention are limited to a single embodiment, and many configurations of the disclosed components can be used to describe some embodiments of the invention, while other configurations may be derived from these embodiments in different configurations.

[0119] In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It should, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

[0120] Based upon the teachings of this disclosure, it is expected that one of ordinary skill in the art will be readily able to practice the present invention. The descriptions of the various embodiments provided herein are believed to provide ample insight and details of the present invention to enable one of ordinary skill to practice the invention. Moreover, the various features and embodiments of the invention described above are specifically contemplated to be used alone as well as in various combinations.

[0121] Conventional and / or contemporary circuit design and layout tools may be used to implement the invention. The specific embodiments described herein, and in particular the various circuit arrangements, measurements and data flows, are illustrative of exemplary embodiments, and should not be viewed as limiting the invention to such specific implementation choices. Accordingly, plural instances may be provided for components described herein as a single instance. The determination of margin and / or other parameters may be made in different parts of the configuration, for example. Other types of eye parameter than eye width may be determined using the margin measurements. Indeed, an eye parameter need not be calculated at all in some cases. Optionally, the IO-sensor can be expanded to measure simultaneously the two sides of the data eye, by implementing a second delay line on the clock signal.

[0122] While circuits and physical structures are generally presumed, it is well recognized that in modern semiconductor design and fabrication, physical structures and circuits may be embodied in computer readable descriptive form suitable for use in subsequent design, test or fabrication stages as well as in resultant fabricated semiconductor integrated circuits. Accordingly, claims directed to traditional circuits or structures may, consistent with particular language thereof, read upon computer readable encodings (which may be termed programs) and representations of same, whether embodied in media or combined with suitable reader facilities to allow fabrication, test, or design refinement of the corresponding circuits and / or structures. Structures and functionality presented as discrete components in the exemplary configurations may be implemented as a combined structure or component. The invention is contemplated to include circuits, systems of circuits, related methods, and computer-readable (medium) encodings of such circuits, systems, and methods, all as described herein, and as defined in the appended claims. As used herein, a computer readable medium includes at least disk, tape, or other magnetic, optical, or semiconductor (e.g., flash memory cards, ROM) medium that is non -transitory.

[0123] The foregoing detailed description has described only a few of the many possible implementations of the present invention. For this reason, this detailed description is intended by way of illustration, and not by way of limitations. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, withoutdeparting from the scope and spirit of the invention. It is only the following claims, including all equivalents, which are intended to define the scope of this invention. In particular, even though the main embodiments are described in the context of a 3D IC, the teachings of the present invention are believed advantageous for use with other types of semiconductor IC using I / O circuitry. Moreover, the techniques described herein may also be applied to other types of circuit applications. Accordingly, other variations, modifications, additions, and improvements may fall within the scope of the invention as defined in the claims that follow.

[0124] Embodiments of the present invention may be used to fabricate, produce, and / or assemble integrated circuits and / or products based on integrated circuits.

[0125] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0126] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

[0127] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, ortechnical improvement over technologies found in the marketplace, or to enable others of ordinaryskill in the art to understand the embodiments disclosed herein.

Claims

CLAIMSWhat is claimed is:

1. A circuit within a semiconductor Integrated Circuit (IC), configured to determine a slew rate and / or a clock integrity of a signal in the IC by measuring a duty cycle of the signal.

2. The circuit of claim 1, further configured with an adjustable logic threshold of the signal for the duty cycle measurement of the signal.

3. The circuit of claim 2, further comprising:an input sampling block, comprising a skewed control input buffer to receive the signal, the input sampling block being configured to provide a sampling output comprising pulses each having a width according to the signal being at or above the adjustable logic threshold; and a duty cycle measurement circuit, configured to output a measurement of a duty cycle of the sampling output, thereby measuring the duty cycle of the signal.

4. The circuit of claim 3, wherein the skewed control input buffer comprises:a plurality of inverter branches, each inverter branch having a respective number of one or more n-type transistors and the same number of p-type transistors, the number differing between branches; andwherein, for each branch, the one or more n-type transistors are controlled by a respective first enable signal and the one or more p-type transistors are controlled by a respective second enable signal, the plurality of first enable signals and plurality of second enable signals thereby controlling the adjustable logic threshold.

5. The circuit of claim 3 or claim 4, wherein the input sampling block and the duty cycle measurement circuit use a sampling clock distinct from the signal.

6. The circuit of claim 5, further comprising:a synchronization circuit, configured to synchronize the sampling output to the sampling clock.

7. The circuit of claim 5 or claim 6, wherein the duty cycle measurement circuit comprises:a clock counter, configured to count a number of edges for the sampling clock to provide a clock count thereby; anda pulse counter, configured to count a number of edges for the sampling output to provide a pulse count thereby, a ratio of the pulse count to the clock count being indicative of the duty cycle of the sampling output.

8. The circuit of any one of claims 5 to 7, wherein the sampling clock has a non-rational ratio to the signal.

9. The circuit of claim 8, further comprising:a ring oscillator circuit (ROSC), configured to generate the sampling clock.

10. The circuit of any of claims 5 to 9, wherein the input sampling block further comprises:a differential register, having a data input configured to receive an output from the skewed control input buffer and a clock input configured to receive the sampling clock, the differential register providing a sampled signal output thereby.

11. The circuit of any one of claims 3 to 10, wherein the input sampling block further comprises a clock integrity testing circuit.

12. The circuit of claim 11, wherein the clock integrity testing circuit comprises:a first synchronization buffer, having a data input configured to receive an enable signal and a clock input configured to receive the signal through a symmetric buffer and configured to provide a first synchronizer output;a second synchronization buffer, having a data input configured to receive an enable signal and a clock input configured to receive the signal through the skewed control input buffer and configured to provide a second synchronizer output;a first counter, configured to generate a first count output from the first synchronizer output; anda second counter, configured to generate a second count output from the second synchronizer output, a comparison between the first and second count outputs being indicative of clock integrity.

13. The circuit of any one of claims 2 to 12, wherein the circuit is configured to:measure a first duty cycle of the signal using a first logic threshold; andmeasure a second duty cycle of the signal using a second, different logic threshold; and wherein the slew rate is determined based on a difference between the first and second duty cycles.

14. The circuit of any preceding claim, wherein the circuit is further configurable to selectively output an indication of either: (i) the duty cycle of the signal; or (ii) a duty cycle of an internal reference clock that has been divided by two.

15. A method for determining a slew rate and / or a clock integrity of a signal in a semiconductor Integrated Circuit (IC) by measuring a duty cycle of the signal.

16. The method of claim 15, wherein a logic threshold used for measuring the duty cycle of the signal is adjustable.

17. The method of claim 16, further comprising:buffering the signal using a skewed control input buffer to provide a sampling output comprising pulses each having a width according to the signal being at or above the adjustable logic threshold; andwherein measuring the duty cycle of the signal comprises measuring a duty cycle of the sampling output.

18. The method of claim 17, wherein the signal is buffered and the duty cycle measured using a sampling clock distinct from the signal.

19. The method of claim 18, further comprising:synchronizing the sampling output to the sampling clock.

20. The method of claim 18 or claim 19, wherein measuring the duty cycle of the sampling output comprises:counting a number of edges for the sampling clock to provide a clock count thereby; and counting a number of edges for the sampling output to provide a pulse count thereby, a ratio of the pulse count to the clock count being indicative of the duty cycle of the sampling output.

21. The method of any one of claims 18 to 20, wherein the sampling clock has a non-rational ratio to the signal.

22. The method of claim 21, wherein the sampling clock is generating using a ring oscillator circuit (ROSC).

23. The method of any one of claims 18 to 22, wherein determining the clock integrity of the signal comprises:providing a first synchronizer output from a first synchronization buffer, having a data input configured to receive an enable signal and a clock input configured to receive the signal through a symmetric buffer;providing a second synchronizer output from a second synchronization buffer, having a data input configured to receive an enable signal and a clock input configured to receive the signal through the skewed control input buffer;counting the first synchronizer output to generate a first count output thereby; and counting the second synchronizer output to generate a second count output thereby, a comparison between the first and second count outputs being indicative of the clock integrity.

24. The method of any one of claims 15 to 23, further comprising:measuring a first duty cycle of the signal using a first logic threshold; and measuring a second duty cycle of the signal using a second, different logic threshold; and wherein the slew rate is determined based on a difference between the first and second duty cycles.

25. A non -transitory computer readable medium having stored thereon a computer -readable encoding of a circuit for determining in a semiconductor Integrated Circuit (IC) a slew rate and / or a clock integrity of a signal in the IC by measuring a duty cycle of the signal.

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