Semiconductor device

Abstract

The present invention addresses the problem of suppressing deterioration of thermal resistance of a semiconductor device. This semiconductor device comprises a semiconductor substrate, a lower electrode in contact with a lower surface of the semiconductor substrate, and an upper electrode in contact with an upper surface of the semiconductor substrate. The semiconductor substrate comprises: a plurality of IGBT regions having IGBT elements; and a plurality of diode regions having diode elements. The plurality of IGBT regions and the plurality of diode regions extend in a first direction and are alternately disposed in a second direction orthogonal to the first direction. The total area of the plurality of IGBT regions is larger than the total area of the plurality of diode regions. The upper electrode is divided into a plurality of parts by a first separation region extending in the first direction. The first separation region is located within a range of the IGBT regions when viewed from a direction perpendicular to the upper surface.

Description

Semiconductor device

[0001] (Cross-reference to related applications) This application is a related application to Japanese Patent Application No. 2025-004400 filed on January 10, 2025, and Japanese Patent Application No. 2025-139218 filed on August 22, 2025. It claims the priority based on this Japanese patent application and incorporates all the contents described in this Japanese patent application as constituting this specification.

[0002] The technology disclosed in this specification relates to a semiconductor device.

[0003] In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2014-241334, the upper electrode is divided into a plurality by a separation region. Thereby, the warpage of the semiconductor device generated by the difference in the linear expansion coefficient between the semiconductor substrate and the upper electrode can be suppressed.

[0004] The upper electrode has a higher thermal conductivity than the semiconductor substrate. Therefore, in the region where the upper electrode is disposed, heat can be exhausted through the upper electrode, so that the thermal resistance of the semiconductor device can be reduced. However, in the separation region where the upper electrode is not disposed, heat cannot be exhausted through the upper electrode, so that the thermal resistance deteriorates.

[0005] The semiconductor device (3) disclosed in this specification includes a semiconductor substrate (10), a lower electrode (24) in contact with the lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with the upper surface (10a) of the semiconductor substrate. The semiconductor substrate includes a plurality of IGBT regions (1a) having IGBT elements and a plurality of diode regions (1b) having diode elements. The plurality of IGBT regions (1a) and the plurality of diode regions (1b) extend in the first direction (x) and are alternately arranged in the second direction (y) orthogonal to the first direction. The total area of the plurality of IGBT regions (1a) is larger than the total area of the plurality of diode regions (1b). The upper electrode is divided into a plurality by a first separation region (SR1) extending in the first direction (x). The first separation region is located within the range of the IGBT region (1a) when viewed from the direction perpendicular to the upper surface (10a).

[0006] In the above configuration, the total area of ​​the multiple IGBT regions is larger than the total area of ​​the multiple diode regions. Therefore, the current density of the IGBT regions can be made smaller than the current density of the diode regions, and thus the heat generation density of the IGBT regions can be made lower than that of the diode regions. In the above configuration, the first isolation region is located within the range of the IGBT regions with low heat generation density. The first isolation region is a region where there is no upper electrode and has low heat dissipation performance. By placing this first isolation region within the range of low heat generation density (i.e., within the range where high heat dissipation is not required), it is possible to suppress the deterioration of the thermal resistance of the semiconductor device.

[0007] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later.

[0008] This is a top view of the top surface 10a of the semiconductor substrate 10. This is a top view of the semiconductor device 3. This is an enlarged perspective view of the semiconductor substrate 10 in region RIII of Figure 1. This is a cross-sectional view taken along line IV-IV of Figure 3. This is a diagram showing the semiconductor device 3 according to Example 2. This is a partially enlarged view of region RVI of Figure 5. This is a diagram showing the semiconductor device 3 according to Example 3. This is a diagram showing the semiconductor device 3 according to Example 4. This is a diagram showing the semiconductor device 3 according to Example 5. This is a partially enlarged view of region RX of Figure 9. This is a diagram showing the semiconductor device 103 according to Example 6. This is a top view of the semiconductor device 103. This is a top view of a modified semiconductor device according to Example 6. This is a top view and cross-sectional view of the semiconductor device 203 of Example 7. This is a flowchart illustrating the manufacturing method of the upper electrode 20. This is a cross-sectional view illustrating the manufacturing process top view of the semiconductor device 303 of Example 8. This is a cross-sectional view taken along line XX-XX of Figure 19.

[0009] (Upper structure of semiconductor device 3) Hereinafter, embodiments relating to the technology of this specification will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0010] Figure 1 shows a top view of the top surface 10a of the semiconductor substrate 10. Figure 1 shows the state before the upper electrode 20 is placed. In Figure 1, multiple diode regions 1b are shown as solid gray areas. Figure 2 shows a top view of the semiconductor device 3. Figure 2 shows the state with the upper electrode 20 in place. In Figure 2, the IGBT region 1a, diode region 1b, and boundary region 1c hidden beneath the upper electrode 20 are shown as dotted lines. The upper electrode 20 is shown as solid gray.

[0011] The semiconductor device 3 is an RC-IGBT (Reverse-Conducting IGBT) structure that incorporates diode elements along with IGBT elements on a single chip. As shown in Figure 1, the semiconductor device 3 has a semiconductor substrate 10 made of silicon. The semiconductor substrate 10 comprises a cell region 1 and an outer peripheral region 2 surrounding the cell region 1. In the example in Figure 1, two cell regions 1 having the same shape are arranged side by side in the x direction. The cell region 1 comprises a plurality of IGBT regions 1a, a plurality of diode regions 1b, and a plurality of boundary regions 1c. The outer peripheral region 2 is equipped with a voltage-resistant structure (e.g., a guard ring) not shown.

[0012] Multiple IGBT regions 1a are regions containing IGBT elements and extend in the x-direction. Multiple diode regions 1b are regions containing diode elements and extend in the x-direction. The multiple IGBT regions 1a and the multiple diode regions 1b are arranged alternately in the y-direction. Multiple boundary regions 1c are located in each region between the multiple IGBT regions 1a and the multiple diode regions 1b. The multiple boundary regions 1c are regions where neither IGBT elements nor diode elements operate. In other words, the boundary regions 1c are inactive regions that do not function as semiconductor elements.

[0013] Each of the multiple IGBT regions 1a has an IGBT width Wa in the y direction. Each of the multiple diode regions 1b has a diode width Wb in the y direction. The IGBT width Wa is greater than the diode width Wb. Also, the x-direction widths of the multiple IGBT regions 1a and the multiple diode regions 1b are the same. Therefore, the area of ​​each of the multiple IGBT regions 1a is greater than the area of ​​each of the multiple diode regions 1b. Furthermore, the total area of ​​the multiple IGBT regions 1a is greater than the total area of ​​the multiple diode regions 1b.

[0014] The structure of the upper electrode 20 will be explained using Figure 2. The upper electrode 20 is divided into multiple parts in the y direction by a first separation region SR1 extending in the x direction. The upper electrode 20 is also divided into multiple parts in the x direction by a second separation region SR2 extending in the y direction. A protective film (not shown) is placed in the first separation region SR1 and the second separation region SR2. The protective film may be, for example, polyimide.

[0015] The first isolation region SR1, when viewed from a direction perpendicular to the upper surface 10a (+z direction), is located within the range of the IGBT region 1a but not within the range of the diode region 1b. In other words, the first isolation region SR1 is positioned to avoid the diode region 1b.

[0016] The effects of the first separation region SR1 and the second separation region SR2 will be explained. Due to the difference in the coefficient of linear expansion between the upper electrode 20 and the semiconductor substrate 10, warping may occur in the semiconductor device 3. In this embodiment, the upper electrode 20 can be divided into multiple parts in the x and y directions by the first separation region SR1 and the second separation region SR2. This makes it possible to effectively suppress warping of the semiconductor device 3.

[0017] Furthermore, a signal electrode pad 5 is provided on the outer peripheral region 2. The signal electrode pad 5 includes a gate pad that controls the gate voltage of the IGBT.

[0018] (Cross-sectional structure of semiconductor device 3) The cross-sectional structure of the semiconductor device 3 will be described using Figures 3 and 4. Figure 3 is an enlarged perspective view of the semiconductor substrate 10 in region RIII of Figure 1. Note that the interlayer insulating film 19 and the upper electrode 20 are omitted from Figure 3. Figure 4 is a cross-sectional view along line IV-IV of Figure 3 (a cross-sectional view passing through the emitter region 15).

[0019] An N-type field stop (hereinafter referred to as FS) layer 21 is formed on the lower surface 10b of the semiconductor substrate 10, with an impurity concentration higher than that of the drift layer 11.

[0020] In the IGBT region 1a and boundary region 1c, a P-type collector layer 22 is formed on the side opposite the drift layer 11, with the FS layer 21 in between. In the diode region 1b, an N-type cathode layer 23 is formed on the side opposite the drift layer 11, with the FS layer 21 in between. In other words, in this embodiment, the IGBT region 1a and boundary region 1c and the diode region 1b are separated by whether the layer formed on the lower surface 10b side of the semiconductor substrate 10 is a collector layer 22 or a cathode layer 23.

[0021] On the lower surface 10b, a lower electrode 24 is formed on the surface of the collector layer 22 and the cathode layer 23. This lower electrode 24 functions as a collector electrode in the IGBT region 1a and the boundary region 1c, and as a cathode electrode in the diode region 1b.

[0022] A P-type base layer 12 is formed on the drift layer 11. In addition, multiple trenches 14 are formed in the IGBT region 1a, boundary region 1c, and diode region 1b so as to penetrate the base layer 12 and reach the drift layer 11. Each of the multiple trenches 14 extends in the x direction and is arranged at equal intervals in the y direction. These trenches 14 separate the base layer 12 into multiple sections. The base layer 12 of the IGBT region 1a has a higher impurity concentration than the base layer 12 of the diode region 1b and boundary region 1c. Hereinafter, the base layer 12 formed in the IGBT region 1a will also be referred to as the first base layer 12a, and the base layer 12 formed in the diode region 1b and boundary region 1c will also be referred to as the second base layer 12b.

[0023] The first base layer 12a is a portion that functions as both a channel region and a body region. Furthermore, as shown in Figures 2 and 4, the surface portion of the first base layer 12a has a portion that is shallower than the first base layer 12a. ＋ A type emitter region 15 is formed.

[0024] The emitter region 15 is composed of a higher impurity concentration than the drift layer 11, terminates within the first base layer 12a, and is formed to be in contact with the side surface of the trench 14. In this embodiment, multiple emitter regions 15 are scattered at equal intervals between each trench 14 along the longitudinal direction (x direction) of the trench 14.

[0025] Furthermore, the first base layer 12a is formed up to the upper surface 10a of the semiconductor substrate 10 in the portion where the emitter region 15 is not formed. This portion is the first contact region 16a, which is made into ohmic contact with the upper electrode 20, which will be described later.

[0026] In the diode region 1b, the second base layer 12b constitutes the anode layer. Note that the emitter region 15 is not formed in the second base layer 12b. A second contact region 16b is formed on the upper surface of the second base layer 12b. The impurity concentration of the second contact region 16b is higher than that of the second base layer 12b, and it is a region that is in ohmic contact with the upper electrode 20, which will be described later.

[0027] Similarly, in the boundary region 1c, a third contact region 16c is formed on the upper surface of the second base layer 12b. The impurity concentration in the third contact region 16c is higher than that of the second base layer 12b, and it is a region that is in ohmic contact with the upper electrode 20, which will be described later.

[0028] Each trench 14 is filled with a gate insulating film 17 formed to cover the inner wall surface of each trench 14, and a trench electrode 18 formed on this gate insulating film 17. The trench electrode 18 is made of, for example, polysilicon. This constitutes a trench gate structure.

[0029] In this embodiment, the trench electrode 18 formed in the IGBT region 1a is connected to a gate drive circuit (not shown) so that a desired gate voltage is applied. On the other hand, the trench electrodes 18 formed in the diode region 1b and the boundary region 1c are connected to the upper electrode 20, which will be described later. In other words, the trench electrodes 18 formed in the diode region 1b and the boundary region 1c are emitter-connected. As a result, in the IGBT region 1a, when a high-level voltage is applied as the gate voltage for IGBT operation, a channel is formed on the side surface of the trench 14. In the diode region 1b, since the trench electrode 18 is at emitter potential, no channel is formed even during IGBT operation, and a predetermined diode operation is performed.

[0030] As shown in Figure 4, an interlayer insulating film 19 is formed on the upper surface 10a of the semiconductor substrate 10. An upper electrode 20 is formed on the interlayer insulating film 19. In the IGBT region 1a, the upper electrode 20 is electrically connected to the emitter region 15 and the first contact region 16a through a contact hole 19a. In the diode region 1b and the boundary region 1c, the upper electrode 20 is electrically connected to the second base layer 12b, the second contact region 16b, and the third contact region 16c through contact holes 19b and 19c. Furthermore, the upper electrode 20 is connected to the trench electrode 18 through a contact hole 19d. In other words, the upper electrode 20 functions as an emitter electrode in the IGBT region 1a and as an anode electrode in the diode region 1b.

[0031] (Problems and Effects) The problems are explained below. The upper electrode 20 (metal) has a higher thermal conductivity than the semiconductor substrate 10 (silicon). Therefore, in the region where the upper electrode 20 is located, heat can be dissipated through the upper electrode 20, thereby reducing thermal resistance. However, in the first isolation region SR1, the upper electrode 20 is not located, and heat cannot be dissipated through the upper electrode 20. Therefore, the first isolation region SR1 is a region with low heat dissipation performance and high thermal resistance. Consequently, the presence of the first isolation region SR1 may worsen the overall thermal resistance of the semiconductor device 3.

[0032] Let's explain the effects. In the semiconductor device 3 of this specification, the total area of ​​the multiple IGBT regions 1a is larger than the total area of ​​the multiple diode regions 1b. Therefore, the current density of the IGBT regions 1a can be made smaller than the current density of the diode regions 1b, so the heat generation density of the IGBT regions 1a can be made lower than that of the diode regions 1b. In the technology of this specification, the first isolation region SR1 is selectively positioned within the range of the IGBT regions 1a with low heat generation density. In other words, the first isolation region SR1 is positioned while avoiding the heat generation center point with high heat generation density. By positioning the first isolation region SR1, which has high thermal resistance, within the range of low heat generation density (i.e., within the range where high heat dissipation is not required), the effect of the increase in thermal resistance due to the first isolation region SR1 can be suppressed. This makes it possible to suppress the deterioration of the overall thermal resistance of the semiconductor device 3.

[0033] Figure 5 shows the semiconductor device 3 according to Example 2. Figure 5 is a drawing similar to Figure 2 of Example 1. In Example 2, the arrangement of the first isolation region SR21 differs from that of Example 1. Components common to Example 1 are denoted by the same reference numerals, and their explanation is omitted.

[0034] The first isolation region SR21 is positioned at the boundary between the IGBT region 1a and the diode region 1b when viewed from a direction perpendicular to the upper surface 10a (+z direction). Furthermore, the first isolation region SR21 is positioned to span both the IGBT region 1a and the diode region 1b, and to include the boundary region 1c.

[0035] Figure 6 shows a magnified view of a portion of the RVI region in Figure 5. In Figure 5, the IGBT region 1a has a first area A1, and the diode region 1b has a second area A2 (see the gray-filled area). The second area A2 is smaller than the first area A1.

[0036] The first isolation region SR21 includes an IGBT overlapping region SR21a that overlaps with the IGBT region 1a, and a diode overlapping region SR21b that overlaps with the diode region 1b (see hatched region). The IGBT overlapping region SR21a has a third area A3. The diode overlapping region SR21b has a fourth area A4.

[0037] Here, the ratio of the second area A2 to the first area A1 is defined as the element area ratio ERA. That is, "ERA = A2 / A1". Also, the ratio of the fourth area A4 to the third area A3 is defined as the isolation area ratio SRA. That is, "SRA = A4 / A3". In the semiconductor device 3 of Example 2, the relationship "the isolation area ratio SRA is less than or equal to the element area ratio ERA" holds true. Note that Figure 5 is an excerpt of a repeating pattern. Therefore, the above relationship holds true not only in Figure 5 but also for the entire semiconductor device 3.

[0038] (Effects) As the element area ratio ERA decreases, the area of ​​the diode region 1b becomes smaller relative to the area of ​​the IGBT region 1a, resulting in a higher current density (higher heat generation density) in the diode region 1b. Also, as the isolation area ratio SRA decreases, the area of ​​the diode overlapping region SR21b becomes smaller relative to the area of ​​the IGBT overlapping region SR21a, resulting in a smaller area of ​​the first isolation region SR21 overlapping with the diode region 1b (lower thermal resistance of the diode region 1b). Therefore, the lower the element area ratio ERA (higher heat generation density of the diode region 1b), the more necessary it is to lower the isolation area ratio SRA (lower thermal resistance of the diode region 1b). In other words, it can be seen that the upper limit of the isolation area ratio SRA can be determined using the element area ratio ERA. The inventors have found that by setting the upper limit of the isolation area ratio SRA to the element area ratio ERA, the effect of the increase in thermal resistance due to the first isolation region SR21 can be appropriately suppressed. In other words, by satisfying the relationship that "the separation region ratio SRA is less than or equal to the element region ratio ERA," it becomes possible to appropriately suppress the deterioration of the overall thermal resistance of the semiconductor device 3.

[0039] As described above, since the boundary region 1c is an inactive region that does not function as a semiconductor element, the current density is low (the heat generation density is low). By arranging the first separation region SR21 so as to include the boundary region 1c with a low heat generation density, the influence of the increase in thermal resistance due to the first separation region SR21 can be more effectively suppressed.

[0040] (Modified Example of Example 2) The first separation region SR21 may be arranged across the IGBT region 1a and the boundary region 1c and may not include the diode region 1b.

[0041] FIG. 7 shows a semiconductor device 3 according to Example 3. FIG. 7 is the same drawing as FIG. 2 of Example 1. In Example 3, the aspect of the first separation region SR31 is different from that of Example 1. The description of the content common to Example 1 is omitted by attaching the same reference numerals.

[0042] The first separation region SR31 includes an inner first separation region SR31i and an outer first separation region SR31o. The inner first separation region SR31i is a region where the distance to the center point CP of the semiconductor substrate 10 is the first distance D1. The outer first separation region SR31o is a region where the distance to the center point CP is a second distance D2 greater than the first distance D1. In the example of FIG. 7, since the inner first separation region SR31i includes the center point CP, the first distance D1 is zero. Also, the outer first separation region SR31o is arranged at a distance of the second distance D2 from the center point CP in the ±y direction.

[0043] The width of the inner first separation region SR31i in the y direction is the width W31i. The width of the outer first separation region SR31o in the y direction is the width W31o. And in the semiconductor device 3 of Example 3, the relationship that "the width W31o is larger than the width W31i" holds.

[0044] The effects will be described. When the semiconductor device 3 generates heat, the temperature tends to decrease as the distance from the center point CP increases. This is because heat dissipation occurs from the outer periphery of the semiconductor device 3, and thus the heat dissipation property improves as the distance from the center point CP increases. Therefore, in the semiconductor device 3 of Example 3, the width W31o of the outer first separation region SR31o, which is far from the center point CP (less likely to become high temperature), is made larger than the width W31i of the inner first separation region SR31i, which is close to the center point CP (more likely to become high temperature). As a result, in the outer first separation region SR31o, by widening the width of the separation region without deteriorating the thermal resistance, a sufficient effect of relaxing warping can be obtained. Also, in the inner first separation region SR31i, by narrowing the width of the separation region to enhance the heat dissipation property, deterioration of the thermal resistance can be suppressed.

[0045] FIG. 8 shows a semiconductor device 3 according to Example 4. FIG. 8 is the same drawing as FIG. 2 of Example 1. In Example 4, the shape of the first separation region SR41 is different from that of Example 1. For the content common to Example 1, the description will be omitted by attaching the same reference numerals.

[0046] The width of the first separation region SR41 in the y direction changes so as to increase from the center side to the outer periphery side of the semiconductor substrate 10. In the example of FIG. 8, the width of the first separation region SR41 in the y direction changes discontinuously in three steps.

[0047] The effects will be described. As described above, when the semiconductor device 3 generates heat, the temperature distribution tends to decrease from the center side to the outer periphery side. Therefore, in the semiconductor device 3 of Example 4, the width of the first separation region SR41 in the y direction is changed so as to increase from the center side to the outer periphery side of the semiconductor substrate. As a result, on the outer periphery side of the semiconductor device 3, by widening the width of the separation region without deteriorating the thermal resistance, a sufficient effect of relaxing warping can be obtained. Also, on the center side of the semiconductor device 3, by narrowing the width of the separation region to enhance the heat dissipation property, deterioration of the thermal resistance can be suppressed.

[0048] Note that the mode of changing the width of the separation region may be various. For example, it may be changed discontinuously in four or more steps. Also, for example, it may be changed continuously so as to have a taper with respect to the y direction.

[0049] Figure 9 shows the semiconductor device 3 according to Example 5. Figure 9 is a drawing similar to Figure 2 of Example 1. In Example 5, the shape of the second isolation region SR52 is different from that of Example 1. Components common to Example 1 are denoted by the same reference numerals, and their explanation is omitted.

[0050] Figure 10 shows a magnified view of a portion of region RX in Figure 9. In Figure 10, the IGBT region 1a has a first area A1, and the diode region 1b has a second area A2 (see the gray-filled area). The second area A2 is smaller than the first area A1.

[0051] The second separation region SR52 includes the IGBT overlap region SR52a, the diode overlap region SR52b, and the boundary overlap region SR52c. The IGBT overlap region SR52a is the region that overlaps with the IGBT region 1a. The diode overlap region SR52b is the region that overlaps with the diode region 1b. The boundary overlap region SR52c is the region that overlaps with the boundary region 1c. In Figure 10, the IGBT overlap region SR52a and the diode overlap region SR52b are hatched for clarity.

[0052] The width in the x-direction of the IGBT overlapping region SR52a and the boundary overlapping region SR52c is width W52a. The width in the x-direction of the diode overlapping region SR52b is width W52b. Width W52a is greater than width W52b. The IGBT overlapping region SR52a has a third area A13. The diode overlapping region SR52b has a fourth area A14.

[0053] As described above in Example 2, the ratio of the second area A2 to the first area A1 is defined as the element area ratio ERA. Also, the ratio of the fourth area A14 to the third area A13 is defined as the isolation area ratio SRA2. That is, "SRA2 = A14 / A13". In the semiconductor device 3 of Example 5, the relationship "the isolation area ratio SRA2 is less than or equal to the element area ratio ERA" holds true. Note that Figure 10 is an excerpt of a repeating pattern. Therefore, the above relationship holds true not only in Figure 10 but also for the entire semiconductor device 3.

[0054] (Effects) As described above in Example 2, the lower the element region ratio ERA (the higher the heat generation density of the diode region 1b), the more necessary it is to lower the isolation region ratio SRA2 (lower the thermal resistance of the diode region 1b). In other words, the upper limit of the isolation region ratio SRA2 can be determined using the element region ratio ERA. The inventors have found that by setting the upper limit of the isolation region ratio SRA2 to the element region ratio ERA, the effect of the increase in thermal resistance due to the second isolation region SR52 can be appropriately suppressed. That is, by satisfying the relationship that "the isolation region ratio SRA2 is less than or equal to the element region ratio ERA", it is possible to appropriately suppress the deterioration of the overall thermal resistance of the semiconductor device 3.

[0055] (Top view structure of semiconductor device 103) Figure 11 shows a semiconductor device 103 according to Embodiment 6. Figure 11(A) is the same drawing as Figure 1 of Embodiment 1. Figure 12 shows a top view of the semiconductor device 103. Figure 12 shows the state in which the upper electrode 20 is arranged. In Figure 12, the heat-generating center region HC hidden below the upper electrode 20 is shown by a dashed line. The upper electrode 20 is also shown as a solid gray fill. The same reference numerals are used for parts that are common to Embodiment 1, and their explanations are omitted.

[0056] The semiconductor substrate 10 comprises an active region 101 and an outer peripheral region 2 surrounding the active region 101. The active region 101 is a region having an element that controls the current flowing between the lower electrode and the upper electrode. The element included in the active region 101 may be at least one of an IGBT element and a diode element. For example, the active region 101 may contain only an IGBT element or only a diode element.

[0057] The active region 101 has a rectangular shape with a first side SD1 and a second side SD2. The first side SD1 extends in the x direction. The second side SD2 extends in the y direction. A heat-generating center region HC exists within the active region 101. In Figure 11(A), the heat-generating center region HC is shown by a dashed line.

[0058] The heat-generating center region HC is the region that includes the maximum heat-generating point Hmax. The maximum heat-generating point Hmax is the point where the amount of heat generated during operation of the semiconductor device 103 is maximum. The heat-generating center region HC has a rectangular shape with a third side SD3 and a fourth side SD4. The third side SD3 is a side that extends in the x direction. The fourth side SD4 is a side that extends in the y direction. The length L3 of the third side SD3 is 29% or less of the length L1 of the first side SD1. The length L4 of the fourth side SD4 is 29% or less of the length L2 of the second side SD2.

[0059] The active region 101 has a center point 101P. The heat-generating center region HC has a center point HC_P. The center point 101P and the center point HC_P coincide. In this embodiment, the center point 101P and the center point HC_P coincide with the maximum heat-generating point Hmax.

[0060] The method for determining the range of the heat-generating center region HC will now be explained. Figure 11(B) shows the temperature distribution along the B-B line in Figure 11(A). The B-B line passes through the center point HC_P of the heat-generating center region HC. In this embodiment, the center point HC_P coincides with the maximum heat-generating point Hmax. In other embodiments, the positions of the center point HC_P and the maximum heat-generating point Hmax may be different. As shown in Figure 11(B), the temperature of the semiconductor device 103 during operation tends to decrease as it moves further away from the center point HC_P. This is because there is no heat source in the outer peripheral region 2, and therefore heat is dissipated from the outer peripheral region 2.

[0061] Here, the temperature distribution within the active region 101 is approximated by an approximate straight line SL. The approximate straight line SL is a line connecting the center point HC_P and the second side SD2 of the active region 101. The specific profile of the temperature distribution varies depending on the structure of the semiconductor device 103, etc. However, the tendency of the temperature distribution to decrease from the center point HC_P toward the second side SD2 is common regardless of the structure. Therefore, approximation using the approximate straight line SL is possible.

[0062] The inventors determined the half-width HW using an approximate straight line SL. The half-width HW is an indicator of the peak spread. Therefore, it is possible to represent a region where the exothermic temperature is sufficiently high using the half-width HW. The peak temperature value PV in the active region 101 is determined by the difference between the temperature of the second side SD2 and the temperature of the center point HC_P. Here, the width at which the temperature is "1 / √2" times (i.e., 0.71 times) the peak value PV is defined as the half-width HW. As shown in Figure 11(B), a straight line LL is defined that represents 0.71 times the peak value PV. The half-width HW is determined by the intersection IS of this straight line LL and the approximate straight line SL. The half-width HW is approximately 29% of the width FW from the center point HC_P to the second side SD2 (i.e., the width of the active region 101). As a result, as described above, the relationship that "length L3 is 29% or less of length L1" can be determined. Similarly, the relationship "length L4 is less than or equal to 29% of length L2" holds true for lengths L4 and L2.

[0063] The structure of the upper electrode 20 will be explained using Figure 12. The upper electrode 20 is divided into multiple parts in the y direction by a first separation region SR61 that extends in the x direction. The upper electrode 20 is also divided into multiple parts in the x direction by a second separation region SR62 that extends in the y direction. The first separation region SR61 and the second separation region SR62 are located outside the range of the heat-generating center region HC when viewed from a direction perpendicular to the upper surface 10a (+z direction). In other words, the first separation region SR61 and the second separation region SR62 are positioned to avoid the heat-generating center region HC.

[0064] (Effects) In the technology of this embodiment, the first isolation region SR61 and the second isolation region SR62 are arranged while avoiding the heat-generating central region HC, which generates a large amount of heat. By arranging the first isolation region SR61 and the second isolation region SR62, which have high thermal resistance, within a range where the amount of heat generated is small (i.e., within a range where high heat dissipation is not required), the effect of the increase in thermal resistance caused by the first isolation region SR61 and the second isolation region SR62 can be suppressed. This makes it possible to suppress the deterioration of the overall thermal resistance of the semiconductor device 103.

[0065] (Modification of Example 6) Figure 13 shows a semiconductor device 3 according to a modification of Example 6. Figure 13 is the same drawing as Figure 2 of Example 1. Components common to Example 1 and Example 6 are denoted by the same reference numerals, and their explanations are omitted. The semiconductor device 3 is an RC-IGBT equipped with an IGBT element and a diode element on a single chip. As described above in Figure 1, two cell regions 1 having the same shape are arranged side by side in the x direction. Therefore, a divided region DR exists between the two cell regions 1. From the viewpoint of heat generation, if the width of the divided region DR in the x direction is sufficiently small, the two cell regions 1 can be considered as a single unit. Therefore, the two IGBT regions 1a arranged in the x direction can be considered as one active region 101. Within this active region 101, there is a heat-generating center region HC1. As described above, the temperature distribution of the semiconductor device 3 when generating heat tends to decrease from the center to the outer periphery. Therefore, the heat-generating central region HC1 exists only in the IGBT region 1a located at the center in the y-direction. Also, the two diode regions 1b aligned in the x-direction can be considered as a single active region 101. Within this active region 101, the heat-generating central region HC2 exists. As mentioned above, the temperature distribution of the semiconductor device 3 when it generates heat tends to decrease from the center towards the outer edge. Therefore, the heat-generating central region HC2 exists only in the diode region 1b located at the center in the y-direction.

[0066] The first isolation region SR1 and the second isolation region SR2 are located outside the range of the heat-generating core regions HC1 and HC2 when viewed from a direction perpendicular to the upper surface 10a (+z direction). In other words, the first isolation region SR1 and the second isolation region SR2 are positioned to avoid the heat-generating core regions HC1 and HC2. This makes it possible to suppress the deterioration of thermal resistance even in RC-IGBTs.

[0067] (Upper structure of semiconductor device 203) Example 7 is an example characterized by the cross-sectional structure of the upper electrode 20. Figure 14 shows the semiconductor device 203 according to Example 7. Figure 14(A) is a drawing similar to Figure 12 of Example 6. In Figure 14(A), the heat-generating center region HC hidden below the upper electrode 20 is shown by a dashed line. The upper electrode 20 is shown as a solid gray fill. Figure 14(B) is a cross-sectional view taken along the line B-B in Figure 14(A). Figure 14(B) is a cross-sectional view passing through the center of the active region 101. Note that components common to Examples 6 and 7 are denoted by the same reference numerals, and their explanation is omitted.

[0068] The active region 101 comprises a heat-generating core region HC and a surrounding region PA. The surrounding region PA is the region surrounding the heat-generating core region HC. The heat-generating core region HC and the surrounding region PA are covered by the upper electrode 20. The upper electrode 20 is an undivided electrode that does not have a separation region.

[0069] As shown in Figure 14(B), the upper electrode 20 comprises a first layer 20_1 and a second layer 20_2. The first layer 20_1 is in contact with the upper surface 10a of the semiconductor substrate 10. The second layer 20_2 is in contact with the upper surface 20_1a of the first layer 20_1. The first layer 20_1 and the second layer 20_2 are conductive layers containing different metals. In this embodiment, the first layer 20_1 is a conductive layer containing aluminum, and the second layer 20_2 is a conductive layer containing nickel. Specifically, the first layer 20_1 is AlSi and the second layer 20_2 is Ni.

[0070] The height of the top surface 20_1a of the first layer 20_1, relative to the top surface 10a of the semiconductor substrate 10, is H1 in the heat-generating center region HC and H2 in the surrounding region PA. Height H1 is higher than height H2. In other words, the height of the top surface 20_1a is higher towards the center of the active region 101 than towards the outer periphery of the active region 101.

[0071] The cross-sectional shape of the first layer 20_1 in the region connecting the center side of the active region 101 and the outer periphery side of the active region 101 includes a slope that is at an angle with respect to the upper surface 10a of the semiconductor substrate 10 (see region R10). This allows the cross-sectional shape of the second layer 20_2 in the region connecting the center side and the outer periphery side of the active region 101 to be a curved shape (see region R11), as will be described later. Note that the cross-sectional shape of the slope formed in the first layer 20_1 is not limited to a straight line, but can be various. For example, it can be an upwardly convex curved surface, a downwardly convex curved surface, a staircase shape, etc.

[0072] The thickness of the second layer 20_2 in the z direction is T1 in the heat-generating center region HC and T2 in the surrounding region PA. Thickness T1 is greater than thickness T2. In other words, the thickness of the second layer 20_2 is greater in the heat-generating center region HC than in the surrounding region PA.

[0073] The cross-sectional shape of the second layer 20_2 is such that the central side of the active region 101 protrudes upward more than the outer periphery of the active region 101. The cross-sectional shape of the second layer 20_2 in the region connecting the central side and the outer periphery of the active region 101 is curved (see region R11). The effects are as follows: By constructing the region connecting the central side and the outer periphery of the active region 101 as a curved surface, stress due to thermal expansion and contraction can be distributed. This makes it possible to improve the reliability of the upper electrode 20. Furthermore, when various members such as lead frames are joined to the upper electrode 20 by soldering or the like, the formation of voids on the joint surface can be suppressed. This makes it possible to improve the joint strength and reliability.

[0074] (Manufacturing Method) The manufacturing method of the upper electrode 20 will be explained using the flow chart in Figure 15. In step S10, a semiconductor substrate 10 on which the active region 101 is formed is prepared. In step S20, a first layer 20_1 of AlSi is formed on the entire upper surface 10a of the semiconductor substrate 10.

[0075] In step S30, a mask 70 is created on the upper surface of the first layer 20_1. As shown in Figure 16, in the region where the first layer 20_1 is not formed, the aperture ratio of the mask 70 is 100% (see region R12). In the region where the height of the first layer 20_1 is increased (heat-generating core region HC), the aperture ratio of the mask 70 is 0%. In the region where the height of the first layer 20_1 is decreased (surrounding region PA), the aperture ratio of the mask 70 is any value between 0% and 100%. The mask 70 can be formed by well-known photolithography techniques.

[0076] In step S40, the first layer 20_1 is wet-etched. The wet etching is performed at a higher rate the higher the aperture ratio of the mask 70. Therefore, as shown in Figure 17, the first layer 20_1 is removed from the region where the upper electrode 20 is not to be formed (the region with an aperture ratio of 100%) (see region R13). In addition, the height of the first layer 20_1 in the region where the upper electrode 20 is to be formed is made lower on the outer periphery side of the active region 101 (peripheral region PA) than on the center side of the active region 101 (heat-generating center region HC).

[0077] In step S50, a second layer formation process is performed in which a second layer 20_2 is formed on the upper surface of the first layer 20_1. This completes the upper electrode 20. In the second layer formation process, the thickness T1 of the active region on the central side (heat-generating central region HC) is formed to be thicker than the thickness T2 of the active region on the outer periphery side (surrounding region PA). Various film formation methods can be used to create this thickness difference. In this embodiment, the film thickness difference was created by plating or sputtering. These will be described in detail below.

[0078] The case in which a difference in film thickness is formed by the plating process will be explained. As shown in Figure 18, the entire first layer 20_1 is immersed in the plating solution 80, and the plating process is carried out while circulating the plating solution 80. In the region where the height of the upper surface 20_1a of the first layer 20_1 is high (heat-generating center region HC), the flow of the plating solution does not stagnate, and fresh plating solution is always present, so the plating reaction can be promoted (see arrow Y1 and region R15). On the other hand, in the region where the height of the upper surface 20_1a is low (peripheral region PA), the plating solution stagnates, so the plating reaction can be suppressed (see arrow Y2 and region R16). As a result, the plating film deposition rate can be increased in the region where the height of the upper surface 20_1a is high compared to the region where the height of the upper surface 20_1a is low.

[0079] This section describes a case where a difference in film thickness is formed by sputtering. The sputtering is performed via a metal mask (not shown). The aperture ratio of the metal mask is set so that the region with a higher height on the upper surface 20_1a of the first layer 20_1 (heat-generating center region HC) is higher than the region with a lower height (peripheral region PA). As a result, the sputtering deposition rate can be increased in the region with a higher height on the upper surface 20_1a than in the region with a lower height on the upper surface 20_1a.

[0080] (Problems and Effects) The problems are as follows: A second layer 20_2 made of Ni is laminated on a first layer 20_1 made of AlSi. Because the thermal expansion coefficient of Ni is larger than that of AlSi, the semiconductor device 3 may warp. When warping occurs, vacuum adsorption by a collet becomes difficult. Also, when the semiconductor device 3 is joined to the lead frame with solder or the like, voids may occur at the joint. Warping can be reduced by reducing the thickness of the Ni film (second layer 20_2). However, if the Ni film is made thin, the resistance to Ni loss due to electromigration (EM) decreases, and the Ni film becomes more prone to peeling. Furthermore, electromigration tends to occur in high-temperature areas. Therefore, the Ni film in high-temperature areas needs to be thick enough to obtain sufficient EM resistance.

[0081] Therefore, in the technology described herein, the thickness of the second layer 20_2 is made greater in the heat-generating center region HC (thickness T1) than in the surrounding region PA (thickness T2). By increasing the thickness of the Ni film (second layer 20_2) in the heat-generating center region HC, where the amount of heat generated is large, EM resistance can be improved. Conversely, by decreasing the thickness of the Ni film (second layer 20_2) in the surrounding region PA, where the amount of heat generated is smaller than in the heat-generating center region HC, warping can be mitigated. In the semiconductor device 3, it is possible to suppress warping while maintaining EM resistance.

[0082] (Modification of Example 7) The upper electrode 20 may have a separation region and may be divided into multiple parts. Also, the materials of the first layer 20_1 and the second layer 20_2 may vary. For example, the material of the first layer 20_1 may be Cu.

[0083] (Upper structure of semiconductor device 303) Example 8 is an example in which the cross-sectional structure of the upper electrode 20 of Example 7 is applied to the IGBT region 1a and the diode region 1b. Figure 19 shows the semiconductor device 303 according to Example 8. Figure 19 is a drawing similar to Figure 2 of Example 1. In Figure 19, the IGBT region 1a, diode region 1b, and boundary region 1c, which are hidden below the upper electrode 20, are shown by dotted lines. The upper electrode 20 is shown as a solid gray color. Figure 20 also shows a cross-sectional view along the line XX-XX in Figure 19. The left side of Figure 20 is the center side of the active region 101. The right side of Figure 20 is the outer periphery side of the active region 101. Note that the same reference numerals are used for parts common to Examples 7 and 8, and their explanation is omitted.

[0084] The height of the upper surface 20_1a of the first layer 20_1, relative to the upper surface 10a of the semiconductor substrate 10, differs between the IGBT region 1a and the diode region 1b. In the diode region 1b, the height of the first layer 20_1 is H11 towards the center and H12 towards the outer edge. Height H11 is higher than height H12. That is, in the diode region 1b, the height of the first layer 20_1 increases from the outer edge towards the center. On the other hand, in the IGBT region 1a, the height of the first layer 20_1 is a constant H20 regardless of location. The height H20 of the IGBT region 1a is lower than the heights H11 and H12 of the diode region 1b.

[0085] The thickness of the second layer 20_2 in the z direction differs between the IGBT region 1a and the diode region 1b. In the diode region 1b, the thickness of the second layer 20_2 is T11 towards the center and T12 towards the outer edge. Thickness T11 is thicker than thickness T12. That is, in the diode region 1b, the thickness of the second layer 20_2 increases from the outer edge towards the center. On the other hand, in the IGBT region 1a, the thickness of the second layer 20_2 is a constant T20 regardless of location. The thickness T20 in the IGBT region 1a is thinner than the thicknesses T11 and T12 in the diode region 1b. That is, in adjacent diode regions 1b and IGBT region 1a, the thickness of the second layer 20_2 is thicker in the diode region 1b than in the IGBT region 1a.

[0086] Furthermore, the method for making the height of the first layer 20_1 and the thickness of the second layer 20_2 different on the outer and central sides can be the method of Example 7, so a detailed explanation is omitted.

[0087] (Effect) In electromigration (EM), metal atoms move in the direction of the current. The direction of the current is from the lower electrode 24 to the upper electrode in the IGBT region 1a, and from the upper electrode 20 to the lower electrode 24 in the diode region 1b. Therefore, electromigration is more likely to occur in the diode region 1b than in the IGBT region 1a. In the technology described herein, the thickness of the second layer 20_2 (Ni layer) is made thicker in the diode region 1b than in the IGBT region 1a. This makes it possible to maintain EM resistance in the diode region 1b. Furthermore, by relatively thinning the IGBT region 1a, warping can be suppressed.

[0088] Electromigration is more likely to occur at higher temperatures. As mentioned above, heat tends to accumulate more easily and the temperature rises higher at the center of the active region 101 than at the outer edge. Therefore, electromigration is more likely to occur at the center than at the outer edge. In the technology described herein, the thickness of the second layer 20_2 of the diode region 1b is increased from the outer edge to the center of the active region 101. This improves the EM resistance at the center of the active region 101.

[0089] (First modification of Example 8) The thickness of the second layer 20_2 may be such that the IGBT region 1a is thicker than the diode region 1b.

[0090] (Second modification of Example 8) The thickness of the second layer 20_2 of the diode region 1b may be the same on the outer periphery and the center of the active region 101. Furthermore, in adjacent diode regions 1b and IGBT region 1a, the thickness of the second layer 20_2 in the diode region 1b may be thicker than that of the IGBT region 1a. That is, the thickness of the second layer 20_2 of the diode region 1b is constant regardless of location, and may also be thicker than the thickness of the second layer 20_2 of the IGBT region 1a.

[0091] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness.

[0092] (Modification) In this specification, an embodiment in which both the first separation region SR1 and the second separation region SR2 are provided has been described, but the specification is not limited to this embodiment. An embodiment in which only the first separation region SR1 is provided is also possible.

[0093] In the above-described embodiment, a trench-type IGBT was formed in the IGBT region 1a. However, a planar-type IGBT may also be formed in the IGBT region 1a.

[0094] The material of the semiconductor substrate 10 is not limited to silicon, but also wide-bandgap semiconductors (e.g., SiC, GaN, Ga ２ O ３ (etc.) can be used.

[0095] The configuration of the technology disclosed herein is listed below. [Configuration 1] A semiconductor device (3) comprising a semiconductor substrate (10), a lower electrode (24) in contact with the lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with the upper surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises a plurality of IGBT regions (1a) having IGBT elements and a plurality of diode regions (1b) having diode elements, wherein the plurality of IGBT regions (1a) and the plurality of diode regions (1b) extend in a first direction (x) and are alternately arranged in a second direction (y) perpendicular to the first direction, the total area of ​​the plurality of IGBT regions (1a) is greater than the total area of ​​the plurality of diode regions (1b), and the upper electrode is divided into a plurality of first separation regions (SR1) extending in the first direction (x). A semiconductor device wherein the first isolation region is located within the range of the IGBT region (1a) when viewed from a direction perpendicular to the upper surface (10a). [Configuration 2] The semiconductor device according to Configuration 1, wherein each of the plurality of IGBT regions (1a) has an IGBT width (Wa) which is the width in the second direction, and each of the plurality of diode regions (1b) has a diode width (Wb) which is the width in the second direction, the IGBT width is greater than the diode width, and the first isolation region is not located within the range of the diode region (1b) when viewed from the upper surface. [Configuration 3] The semiconductor device according to Configuration 1 or 2, wherein each of the plurality of IGBT regions (1a) has an IGBT width which is the width in the second direction, each of the plurality of diode regions (1b) has a diode width which is the width in the second direction, the IGBT width is greater than the diode width, and the first isolation region is located at the boundary between the IGBT region and the diode region when viewed from a direction perpendicular to the upper surface, and is located across the IGBT region and the diode region.[Configuration 4] The semiconductor device according to Configuration 3, wherein each of the plurality of IGBT regions has a first area (A1), each of the plurality of diode regions has a second area (A2) smaller than the first area, the first isolation region includes an IGBT overlapping region (SR21a) that overlaps with the IGBT region and a diode overlapping region (SR21b) that overlaps with the diode region when viewed from a direction perpendicular to the upper surface, the IGBT overlapping region has a third area (A3), the diode overlapping region has a fourth area (A4), and the ratio of the fourth area to the third area (SRA) is less than or equal to the ratio of the second area to the first area (ERA). [Configuration 5] The semiconductor device according to any one of Configurations 1-4, wherein the semiconductor substrate further comprises a plurality of boundary regions (1c) arranged in each of the regions between the plurality of IGBT regions (1a) and the plurality of diode regions (1b), the plurality of boundary regions being regions in which neither the IGBT elements nor the diode elements operate, and the first isolation region includes at least a part of the boundary region when viewed from a direction perpendicular to the upper surface. [Configuration 6] The semiconductor device according to any one of Configurations 1-5, wherein the first isolation region includes an inner first isolation region (SR31i) whose distance to the center point of the semiconductor substrate is a first distance (D1), and an outer first isolation region (SR31o) whose distance to the center point is a second distance (D2) greater than the first distance, and the width of the outer first isolation region in the second direction is greater than the width of the inner first isolation region in the second direction. [Configuration 7] The semiconductor device according to any one of Configurations 1-6, wherein the width of the first separation region in the second direction increases from the center side to the outer edge side of the semiconductor substrate. [Configuration 8] The semiconductor device according to any one of Configurations 1-7, wherein the upper electrode is divided into multiple parts by a second separation region (SR2) extending in the second direction (y).[Configuration 9] The semiconductor device according to Configuration 8, wherein the second separation region includes an IGBT overlapping region (SR52a) that overlaps with the IGBT region and a diode overlapping region (SR52b) that overlaps with the diode region when viewed from a direction perpendicular to the upper surface, and the width of the IGBT overlapping region in the first direction is greater than the width of the diode overlapping region in the first direction. [Configuration 10] The semiconductor device according to Configuration 8 or 9, wherein each of the plurality of IGBT regions has a first area (A1), each of the plurality of diode regions has a second area (A2) smaller than the first area, the second isolation region includes an IGBT overlapping region that overlaps with the IGBT region and a diode overlapping region that overlaps with the diode region when viewed from a direction perpendicular to the upper surface, the IGBT overlapping region has a third area (A13), the diode overlapping region has a fourth area (A14), and the ratio of the fourth area to the third area is less than or equal to the ratio of the second area to the first area. [Configuration 11] The semiconductor substrate comprises an active region (101) including a plurality of IGBT regions (1a) and a plurality of diode regions (1b), the active region having a rectangular shape with a first side (SD1) extending in a first direction (x) and a second side (SD2) extending in a second direction (y) perpendicular to the first direction, within the active region there is a heat-generating center region (HC) that includes the maximum heat-generating point where the amount of heat generated during the operation of the semiconductor device is maximum, the heat-generating center region having a rectangular shape with a third side (SD3) extending in the first direction and a fourth side (SD4) extending in the second direction, the length of the third side being 29% or less of the length of the first side, the length of the fourth side being 29% or less of the length of the second side, and the heat-generating center region including the center point (101P) of the active region. The semiconductor device according to any one of configurations 1-10, wherein the first separation region is located outside the range of the heat-generating center region when viewed from a direction perpendicular to the upper surface (10a).[Configuration 12] A semiconductor device (103) comprising a semiconductor substrate (10), a lower electrode (24) in contact with the lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with the upper surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises an active region (101) having an element for controlling the current flowing between the lower electrode and the upper electrode, the active region has a rectangular shape comprising a first side (SD1) extending in a first direction (x) and a second side (SD2) extending in a second direction (y) perpendicular to the first direction, within the active region there exists a heat-generating center region (HC) that includes a maximum heat-generating point where the amount of heat generated during operation of the semiconductor device is maximum, the heat-generating center region has a rectangular shape comprising a third side (SD3) extending in the first direction and a fourth side (SD4) extending in the second direction, the length of the third side is 29% or less of the length of the first side, A semiconductor device wherein the length of the fourth side is 29% or less of the length of the second side, the heat-generating center region includes the center point (101P) of the active region, the upper electrode is divided into a plurality of first separation regions (SR61) extending in the first direction (x), and the first separation region is located outside the range of the heat-generating center region when viewed from a direction perpendicular to the upper surface (10a). [Configuration 13] The semiconductor device according to Configuration 12, wherein the center point of the active region and the center point (HC_P) of the heat-generating center region coincide. [Configuration 14] The semiconductor device according to Configuration 12 or 13, wherein the element includes at least one of an IGBT element and a diode element.[Configuration 15] The semiconductor device according to any one of Configurations 12-14, wherein the upper electrode is in contact with the upper surface of the semiconductor substrate and comprises a first layer (20_1) containing a first type metal (Al), and a second layer (20_2) is in contact with the upper surface (20_1a) of the first layer and contains a second type metal (Ni) different from the first type metal, the heat-generating center region (HC) and the surrounding region (PA) surrounding the heat-generating center region are covered by the upper electrode, the height (H1, H2) of the upper surface of the first layer with respect to the upper surface of the semiconductor substrate is higher in the heat-generating center region than in the surrounding region, and the thickness (T1, T2) of the second layer is thicker in the heat-generating center region than in the surrounding region. [Configuration 16] The semiconductor device according to any one of Configurations 1-11, wherein the semiconductor substrate comprises an active region (101) including a plurality of IGBT regions (1a) and a plurality of diode regions (1b), at least a portion of the active region is covered by the upper electrode, the upper electrode comprises a first layer (20_1) in contact with the upper surface of the semiconductor substrate and containing a first type metal (Al), and a second layer (20_2) in contact with the upper surface (20_1a) of the first layer and containing a second type metal (Ni) different from the first type metal, the height of the upper surface of the first layer with respect to the upper surface of the semiconductor substrate is higher on the central side (H1) of the active region than on the outer peripheral side (H2) of the active region, and the thickness of the second layer is thicker on the central side (T1) of the active region than on the outer peripheral side (T2) of the active region. [Configuration 17] The semiconductor device according to Configuration 16, wherein in a cross-section passing through the center of the active region, the cross-sectional shape of the second layer has a shape in which the central side of the active region protrudes upward more than the outer peripheral side of the active region, and the cross-sectional shape of the second layer in the region connecting the central side of the active region and the outer peripheral side of the active region is a curved shape.[Configuration 18] The semiconductor device according to Configuration 16 or 17, wherein in a cross-section passing through the center of the active region, the cross-sectional shape of the first layer has a shape in which the central side of the active region protrudes upward more than the outer peripheral side of the active region, and the cross-sectional shape of the first layer in the region connecting the central side of the active region and the outer peripheral side of the active region includes a slope that is at an angle with respect to the surface of the semiconductor substrate. [Configuration 19] The semiconductor device according to any one of Configurations 16-18, wherein in the diode region and the IGBT region adjacent to each other, the thickness of the second layer (T11, T12, T20) is greater in the diode region than in the IGBT region. [Configuration 20] The semiconductor device according to any one of Configurations 16-19, wherein the thickness of the second layer (T11, T12) in each of the plurality of diode regions is greater on the central side of the active region than on the outer peripheral side of the active region. [Configuration 21] The semiconductor device according to any one of Configurations 16-20, wherein the first type metal is a metal containing aluminum, and the second type metal is a metal containing nickel. [Configuration 22] The semiconductor substrate comprises an active region (101) including a plurality of IGBT regions (1a) and a plurality of diode regions (1b), at least a portion of the active region is covered by the upper electrode, the upper electrode comprises a first layer (20_1) in contact with the upper surface of the semiconductor substrate and containing a first type metal (Al), and a second layer (20_2) in contact with the upper surface (20_1a) of the first layer and containing a second type metal (Ni) different from the first type metal, and in the diode region and the IGBT region adjacent to each other, the thickness of the second layer is greater in the diode region than in the IGBT region, the semiconductor device according to Configuration 1.[Configuration 23] A method for manufacturing a semiconductor device (3) comprising a semiconductor substrate (10) and an upper electrode (20) provided on the upper surface (10a) of the semiconductor substrate, wherein an active region (101) on which various elements are arranged is provided on the upper surface of the semiconductor substrate, at least a part of the active region is covered by the upper electrode, the upper electrode comprises a first layer (20_1) in contact with the upper surface of the semiconductor substrate and containing a first type metal, and a second layer (20_2) in contact with the upper surface of the first layer and containing a second type metal different from the first type metal, the manufacturing method comprises a first layer formation step (S20-S40) for forming the first layer of the upper electrode on the surface of the semiconductor substrate, and a second layer formation step (S50) for forming a second layer on the upper surface of the first layer. A method for manufacturing a semiconductor device, wherein in the first layer formation step, the height of the upper surface of the first layer with respect to the upper surface of the semiconductor substrate is formed to be higher on the central side (H1) of the active region than on the outer periphery side (H2) of the active region, and in the second layer formation step, the thickness of the second layer is formed to be thicker on the central side (T1) of the active region than on the outer periphery side (T2) of the active region. [Configuration 24] A method for manufacturing a semiconductor device according to Configuration 23, wherein the first layer formation step comprises a first film formation step (S20) for forming the first layer on the entire surface of the semiconductor substrate, and an etching step (S40) for processing the first layer formed in the first film formation step into a shape corresponding to the upper electrode by wet etching, wherein the etching step includes processing to remove the first layer in a region where the upper electrode is not formed, and processing to make the height of the first layer in the region where the upper electrode is formed lower on the outer periphery side of the active region than on the central side of the active region. [Configuration 25] The method for manufacturing a semiconductor device according to Configuration 23 or 24, wherein the second layer formation step is performed by a plating process, and the plating process is performed such that the plating film formation rate is higher in areas where the height of the upper surface of the first layer is higher than in areas where the height of the upper surface of the first layer is lower.[Configuration 26] The method for manufacturing a semiconductor device according to Configuration 23 or 24, wherein the second layer formation step is performed by sputtering through a metal mask, and the aperture ratio of the metal mask is such that the region where the height of the upper surface of the first layer is high is higher than the region where the height of the upper surface of the first layer is low.

[0096] According to configuration 2, by not positioning the first isolation region within the range of the diode region with high heat generation density, it becomes possible to more effectively suppress the deterioration of the thermal resistance of the semiconductor device.

[0097] According to configuration 4, it is possible to appropriately suppress the deterioration of the overall thermal resistance of the semiconductor device.

[0098] Boundary regions that do not function as semiconductor elements have low current density (low heat generation density). According to configuration 5, by arranging the first isolation region to include this boundary region with low heat generation density, the effect of the increase in thermal resistance due to the first isolation region can be suppressed more effectively.

[0099] The temperature of a semiconductor device when it generates heat tends to decrease with increasing distance from the center point. According to configuration 6, in the outer first separation region, the warping mitigation effect can be sufficiently obtained by widening the width of the separation region without worsening the thermal resistance. In the inner first separation region, the deterioration of thermal resistance can be suppressed by narrowing the width of the separation region to improve heat dissipation.

[0100] According to configuration 7, on the outer periphery of the semiconductor device, the warping mitigation effect can be sufficiently obtained by widening the width of the isolation region without worsening the thermal resistance. On the central side of the semiconductor device, the deterioration of thermal resistance can be suppressed by narrowing the width of the isolation region to improve heat dissipation.

[0101] According to configuration 8, warping of semiconductor devices can be suppressed more effectively.

[0102] According to configuration 9, by widening the width of the second separation region that overlaps with the IGBT region with low heat generation density, a sufficient warping mitigation effect can be obtained without worsening the thermal resistance.

[0103] According to configuration 10, it is possible to appropriately suppress the deterioration of the overall thermal resistance of the semiconductor device.

[0104] According to configurations 11 and 12, by not positioning the first isolation region within the range of the heat-generating center region that includes the maximum heat-generating point, it becomes possible to more effectively suppress the deterioration of the thermal resistance of the semiconductor device.

[0105] According to configuration 15, it is possible to suppress warping of the semiconductor device while maintaining EM resistance in the heat-generating central region.

[0106] According to configuration 16, it is possible to achieve both the maintenance of EM resistance and the suppression of warping of the semiconductor device.

[0107] According to configuration 17, the reliability and bonding strength of the upper electrode can be improved.

[0108] According to configuration 18, the cross-sectional shape of the second layer in the region connecting the central side and the outer periphery side of the active region can be made into a curved shape.

[0109] According to configuration 19, EM resistance in the diode region can be maintained.

[0110] According to configuration 20, the EM resistance on the central side of the active area can be increased.

[0111] According to configuration 22, EM resistance in the diode region can be maintained.

[0112] According to configuration 23, it is possible to suppress warping of the semiconductor device while maintaining EM resistance on the central side of the active region.

[0113] According to configuration 24, the height of the upper surface of the first layer can be made higher on the central side of the active region than on the outer periphery side.

[0114] According to configurations 25 and 26, the thickness of the second layer can be made thicker on the central side of the active region than on the outer periphery side.

Claims

1. A semiconductor device (3) comprising a semiconductor substrate (10), a lower electrode (24) in contact with the lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with the upper surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises a plurality of IGBT regions (1a) having IGBT elements and a plurality of diode regions (1b) having diode elements, the plurality of IGBT regions (1a) and the plurality of diode regions (1b) extend in a first direction (x) and are alternately arranged in a second direction (y) perpendicular to the first direction, the total area of ​​the plurality of IGBT regions (1a) is greater than the total area of ​​the plurality of diode regions (1b), and the upper electrode is divided into a plurality of first separation regions (SR1) extending in the first direction (x). The first separation region is located within the range of the IGBT region (1a) when viewed from a direction perpendicular to the upper surface (10a) of the semiconductor device.

2. The semiconductor device according to claim 1, wherein each of the plurality of IGBT regions (1a) has an IGBT width (Wa) which is the width in the second direction, each of the plurality of diode regions (1b) has a diode width (Wb) which is the width in the second direction, the IGBT width is greater than the diode width, and the first isolation region is not located within the range of the diode region (1b) when viewed from the top surface.

3. The semiconductor device according to claim 1, wherein each of the plurality of IGBT regions (1a) has an IGBT width which is the width in the second direction, each of the plurality of diode regions (1b) has a diode width which is the width in the second direction, the IGBT width is greater than the diode width, and the first isolation region is located at the boundary between the IGBT region and the diode region when viewed from a direction perpendicular to the upper surface, and is located across the IGBT region and the diode region.

4. The semiconductor device according to claim 3, wherein each of the plurality of IGBT regions has a first area (A1), each of the plurality of diode regions has a second area (A2) smaller than the first area, the first isolation region includes an IGBT overlapping region (SR21a) that overlaps with the IGBT region and a diode overlapping region (SR21b) that overlaps with the diode region when viewed from a direction perpendicular to the upper surface, the IGBT overlapping region has a third area (A3), the diode overlapping region has a fourth area (A4), and the ratio of the fourth area to the third area (SRA) is less than or equal to the ratio of the second area to the first area (ERA).

5. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor substrate further comprises a plurality of boundary regions (1c) disposed in each of the regions between the plurality of IGBT regions (1a) and the plurality of diode regions (1b), the plurality of boundary regions being regions in which neither the IGBT elements nor the diode elements operate, and the first isolation region includes at least a portion of the boundary regions when viewed from a direction perpendicular to the upper surface.

6. The semiconductor device according to claim 1, wherein the first isolation region includes an inner first isolation region (SR31i) whose distance to the center point of the semiconductor substrate is a first distance (D1), and an outer first isolation region (SR31o) whose distance to the center point is a second distance (D2) greater than the first distance, and the width of the outer first isolation region in the second direction is greater than the width of the inner first isolation region in the second direction.

7. The semiconductor device according to claim 1, wherein the width of the first separation region in the second direction increases from the center side to the outer edge side of the semiconductor substrate.

8. The semiconductor device according to claim 1, wherein the upper electrode is divided into a plurality of second separation regions (SR2) extending in the second direction (y).

9. The semiconductor device according to claim 8, wherein the second separation region includes an IGBT overlapping region (SR52a) that overlaps with the IGBT region and a diode overlapping region (SR52b) that overlaps with the diode region when viewed from a direction perpendicular to the upper surface, and the width of the IGBT overlapping region in the first direction is greater than the width of the diode overlapping region in the first direction.

10. The semiconductor device according to claim 8, wherein each of the plurality of IGBT regions has a first area (A1), each of the plurality of diode regions has a second area (A2) smaller than the first area, the second separation region includes an IGBT overlapping region that overlaps with the IGBT region and a diode overlapping region that overlaps with the diode region when viewed from a direction perpendicular to the upper surface, the IGBT overlapping region has a third area (A13), the diode overlapping region has a fourth area (A14), and the ratio of the fourth area to the third area is less than or equal to the ratio of the second area to the first area.

11. The semiconductor substrate comprises an active region (101) including a plurality of IGBT regions (1a) and a plurality of diode regions (1b), the active region having a rectangular shape with a first side (SD1) extending in a first direction (x) and a second side (SD2) extending in a second direction (y) perpendicular to the first direction, the active region having a heat-generating center region (HC) that includes the maximum heat-generating point where the amount of heat generated during the operation of the semiconductor device is maximum, the heat-generating center region having a rectangular shape with a third side (SD3) extending in the first direction and a fourth side (SD4) extending in the second direction, the length of the third side being 29% or less of the length of the first side, the length of the fourth side being 29% or less of the length of the second side, and the heat-generating center region including the center point (101P) of the active region. The semiconductor device according to claim 1, wherein the first separation region is located outside the range of the heat-generating center region when viewed from a direction perpendicular to the upper surface (10a).

12. A semiconductor device (103) comprising a semiconductor substrate (10), a lower electrode (24) in contact with the lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with the upper surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises an active region (101) having an element for controlling the current flowing between the lower electrode and the upper electrode, the active region having a rectangular shape comprising a first side (SD1) extending in a first direction (x) and a second side (SD2) extending in a second direction (y) perpendicular to the first direction, the active region having a heat-generating center region (HC) containing the maximum heat-generating point where the amount of heat generated during operation of the semiconductor device is maximum, the heat-generating center region having a rectangular shape comprising a third side (SD3) extending in the first direction and a fourth side (SD4) extending in the second direction, the length of the third side being 29% or less of the length of the first side, A semiconductor device wherein the length of the fourth side is 29% or less of the length of the second side, the heat-generating center region includes the center point (101P) of the active region, the upper electrode is divided into multiple parts by a first separation region (SR61) extending in the first direction (x), and the first separation region is located outside the range of the heat-generating center region when viewed from a direction perpendicular to the upper surface (10a).

13. The semiconductor device according to claim 12, wherein the center point of the active region and the center point (HC_P) of the heat-generating center region coincide.

14. The semiconductor device according to claim 12, wherein the element includes at least one of an IGBT element and a diode element.

15. The semiconductor device according to any one of claims 12-14, wherein the upper electrode is in contact with the upper surface of the semiconductor substrate and comprises a first layer (20_1) containing a first type metal (Al), and a second layer (20_2) is in contact with the upper surface (20_1a) of the first layer and contains a second type metal (Ni) different from the first type metal, the heat-generating center region (HC) and the surrounding region (PA) surrounding the heat-generating center region are covered by the upper electrode, the height (H1, H2) of the upper surface of the first layer with respect to the upper surface of the semiconductor substrate is higher in the heat-generating center region than in the surrounding region, and the thickness (T1, T2) of the second layer is thicker in the heat-generating center region than in the surrounding region.

16. The semiconductor device according to claim 1, wherein the semiconductor substrate comprises an active region (101) including a plurality of IGBT regions (1a) and a plurality of diode regions (1b), at least a portion of the active region is covered by the upper electrode, the upper electrode comprises a first layer (20_1) in contact with the upper surface of the semiconductor substrate and containing a first type metal (Al), and a second layer (20_2) in contact with the upper surface (20_1a) of the first layer and containing a second type metal (Ni) different from the first type metal, the height of the upper surface of the first layer with respect to the upper surface of the semiconductor substrate is higher on the central side (H1) of the active region than on the outer peripheral side (H2) of the active region, and the thickness of the second layer is thicker on the central side (T1) of the active region than on the outer peripheral side (T2) of the active region.

17. The semiconductor device according to claim 16, wherein, in a cross-section passing through the center of the active region, the cross-sectional shape of the second layer has a shape in which the central side of the active region protrudes upward more than the outer peripheral side of the active region, and the cross-sectional shape of the second layer in the region connecting the central side of the active region and the outer peripheral side of the active region is curved.

18. The semiconductor device according to claim 17, wherein, in a cross-section passing through the center of the active region, the cross-sectional shape of the first layer has a shape in which the central side of the active region protrudes upward more than the outer peripheral side of the active region, and the cross-sectional shape of the first layer in the region connecting the central side of the active region and the outer peripheral side of the active region includes a slope that is at an angle with respect to the surface of the semiconductor substrate.

19. The semiconductor device according to any one of claims 16-18, wherein in the diode region and the IGBT region which are adjacent to each other, the thickness of the second layer (T11, T12, T20) is greater in the diode region than in the IGBT region.

20. The semiconductor device according to claim 19, wherein the thickness (T11, T12) of the second layer in each of the plurality of diode regions is thicker on the central side of the active region than on the outer periphery side of the active region.

21. The semiconductor device according to claim 16, wherein the first type metal is a metal containing aluminum, and the second type metal is a metal containing nickel.

22. The semiconductor device according to claim 1, wherein the semiconductor substrate comprises an active region (101) including a plurality of IGBT regions (1a) and a plurality of diode regions (1b), at least a portion of the active region is covered by the upper electrode, the upper electrode comprises a first layer (20_1) in contact with the upper surface of the semiconductor substrate and containing a first type metal (Al), and a second layer (20_2) in contact with the upper surface (20_1a) of the first layer and containing a second type metal (Ni) different from the first type metal, and in adjacent diode regions and IGBT regions, the thickness of the second layer is greater in the diode region than in the IGBT region.

23. A method for manufacturing a semiconductor device (3) comprising a semiconductor substrate (10) and an upper electrode (20) provided on the upper surface (10a) of the semiconductor substrate, wherein an active region (101) on which various elements are arranged is provided on the upper surface of the semiconductor substrate, at least a part of the active region is covered by the upper electrode, the upper electrode comprises a first layer (20_1) in contact with the upper surface of the semiconductor substrate and containing a first type metal, and a second layer (20_2) in contact with the upper surface of the first layer and containing a second type metal different from the first type metal, the manufacturing method comprising a first layer formation step (S20-S40) for forming the first layer of the upper electrode on the surface of the semiconductor substrate, and a second layer formation step (S50) for forming a second layer on the upper surface of the first layer, A method for manufacturing a semiconductor device, wherein in the first layer formation step, the height of the upper surface of the first layer, with respect to the upper surface of the semiconductor substrate, is formed so that the central side (H1) of the active region is higher than the peripheral side (H2) of the active region, and in the second layer formation step, the thickness of the second layer is formed so that the central side (T1) of the active region is thicker than the peripheral side (T2) of the active region.

24. The method for manufacturing a semiconductor device according to claim 23, wherein the first layer formation step comprises: a first film formation step (S20) for forming the first layer over the entire surface of the semiconductor substrate; and an etching step (S40) for processing the first layer formed in the first film formation step into a shape corresponding to the upper electrode by wet etching, wherein the etching step includes: removing the first layer in areas where the upper electrode is not to be formed; and making the height of the first layer in the area where the upper electrode is to be formed lower on the outer periphery side of the active region than on the center side of the active region.

25. The method for manufacturing a semiconductor device according to claim 23 or 24, wherein the second layer formation step is performed by a plating process, and the plating process is performed such that the plating film formation rate is higher in areas where the height of the upper surface of the first layer is higher than in areas where the height of the upper surface of the first layer is lower.

26. The method for manufacturing a semiconductor device according to claim 23 or 24, wherein the second layer formation step is performed by sputtering through a metal mask, and the aperture ratio of the metal mask is such that the region where the height of the upper surface of the first layer is high is higher than the region where the height of the upper surface of the first layer is low.

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