Power conversion device
The multilayer wiring board design with a conductor region addresses high gate impedance and loss imbalance in GaN power systems, improving reliability and enabling high-frequency operation by balancing impedance and reducing parasitic effects.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- ASTEMO LTD
- Filing Date
- 2025-11-27
- Publication Date
- 2026-07-16
AI Technical Summary
Power system products using gallium nitride (GaN) face issues with high gate impedance leading to false turn-on, imbalance of losses causing resonance, and reduced reliability due to unequal gate wiring inductance.
A power conversion device with a multilayer wiring board design that includes a conductor region insulated from and overlapping with wiring regions, with specific coverage rates to reduce parasitic inductance and capacitance, thereby balancing impedance and improving reliability.
The solution effectively reduces parasitic inductance and capacitance, preventing resonance and thermal runaway, enhancing reliability and enabling high-frequency driving.
Smart Images
Figure JP2025041400_16072026_PF_FP_ABST
Abstract
Description
Power Conversion Device
[0001] The present invention relates to a power conversion device.
[0002] For power system products applying gallium nitride (GaN), it is necessary to reduce the gate impedance of switching elements in order to prevent high-frequency driving and false turn-on, and it is also necessary to suppress the imbalance of losses leading to resonance and shortened life. In addition, power system products need to meet the requirements of high efficiency, high output, and high reliability. To solve such problems, for example, Patent Document 1 below discloses a configuration of a power conversion device that solves the inequality of gate wiring inductance by covering only the longer wiring.
[0003] Japanese Patent Laid-Open No. 09-135565
[0004] In view of the configuration described in Patent Document 1, an object of the present invention is to provide a power conversion device that realizes reduction of inductance, improvement of imbalance of switching losses, prevention of resonance, and improvement of reliability.
[0005] The power converter comprises a first semiconductor switching element, a second semiconductor switching element connected in parallel to the first semiconductor switching element, the first semiconductor switching element, the second semiconductor switching element, and a control terminal to which a control signal is input, and a substrate on which these are mounted, wherein the substrate has a first wiring region on which wiring is formed to electrically connect the first semiconductor switching element and the control terminal, and a second wiring region on which wiring is formed to electrically connect the second semiconductor switching element and the control terminal, wherein at least one of the plurality of wiring layers on the substrate has a conductor region on which a conductor is formed, and the conductor The region is insulated from the first wiring region and the second wiring region, and is arranged to overlap with the first wiring region and the second wiring region in the thickness direction of the substrate. The region where the conductor region and the region with twice the width of the first wiring region overlap in the thickness direction of the substrate is defined as the first overlapping region, and the value calculated by dividing the area of the first overlapping region by the area with twice the width of the first wiring region is defined as the first coverage rate. The region where the conductor region and the region with twice the width of the second wiring region overlap in the thickness direction of the substrate is defined as the second overlapping region, and the value calculated by dividing the area of the second overlapping region by the area with twice the width of the second wiring region is defined as the second coverage rate. In this case, the first coverage rate is greater than the second coverage rate.
[0006] We can provide power conversion devices that achieve reduced inductance, improved switching loss imbalance, resonance prevention, and enhanced reliability.
[0007] Circuit diagram of a power converter according to the first embodiment of the present invention. Structural diagram of each layer of the multilayer wiring board of a power converter according to the first embodiment of the present invention. Diagram illustrating the effect of the structure in each layer according to the first embodiment of the present invention. Diagram illustrating the effect of the structure in each layer according to the first embodiment of the present invention. Structural diagram of each layer of the multilayer wiring board of a power converter according to the second embodiment of the present invention. Structural diagram of each layer of the multilayer wiring board of a power converter according to the third embodiment of the present invention. Diagram illustrating the effect of the structure in each layer according to the third embodiment of the present invention. Structural diagram of each layer of the multilayer wiring board of a power converter according to the fourth embodiment of the present invention. Structural diagram of each layer of the multilayer wiring board of a power converter according to the fifth embodiment of the present invention. Structural diagram of each layer of the multilayer wiring board of a power converter according to the sixth embodiment of the present invention. Structural diagram of each layer of the multilayer wiring board of a power converter according to the seventh embodiment of the present invention.
[0008] Embodiments of the present invention will be described below with reference to the drawings. The following description and drawings are illustrative for illustrating the present invention, and have been omitted and simplified as appropriate for clarity of explanation. The present invention can also be carried out in various other forms. Unless otherwise specified, each component may be singular or plural.
[0009] The positions, sizes, shapes, and ranges of the components shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.
[0010] (First Embodiment and Overall Configuration) (Figure 1) In the power converter 1, the semiconductor switching elements Sa and Sb are composed of IGBTs, SiC-MOSFETs, GaN-HEMTs, etc. Each semiconductor switching element is provided with terminals such as a high-voltage terminal for the main circuit (collector terminal for IGBTs, drain terminal for MOSFETs), a low-voltage terminal for the main circuit (emitter terminal for IGBTs, source terminal for MOSFETs), and a control terminal (gate terminal).
[0011] Each semiconductor switching element is connected in parallel to each other according to the desired output current value. Figure 1 shows a power converter 1 with a two-parallel configuration in which a first semiconductor switching element Sa1 and a second semiconductor switching element Sa2 are connected in parallel to each other, and a first semiconductor switching element Sb1 and a second semiconductor switching element Sb2 are also connected in parallel to each other.
[0012] The positive terminal wiring 2 is connected to a DC voltage source such as a battery (not shown) or to the positive terminal of the smoothing capacitor 4. The negative terminal wiring 3 is connected to a DC voltage source such as a battery (not shown) or to the negative terminal of the smoothing capacitor 4. With this configuration, a smoothed DC voltage is supplied to the power converter 1.
[0013] The positive electrode wiring 2 is connected to the high-voltage terminals of the semiconductor switching elements Sa1 and Sa2. The low-voltage terminals for the main circuit of the semiconductor switching elements Sa1 and Sa2 are connected to the output wiring AC of the power converter 1 via the midpoint M, and are also connected to the high-voltage terminals for the main circuit of the semiconductor switching elements Sb1 and Sb2. The high-voltage terminals for the main circuit of the semiconductor switching elements Sb1 and Sb2 are also connected to the output wiring AC of the power converter 1 via the midpoint M. The low-voltage terminals for the main circuit of the semiconductor switching elements Sb1 and Sb2 are connected to the negative electrode wiring 3.
[0014] The output wiring AC of the power converter 1 is connected to a load such as a motor or transformer (not shown). The signal terminals g and s, which are control terminals for each semiconductor switching element, are connected to the control terminals G and S of the control circuit described later. Based on the signal input from a control device such as a gate driver, an on or off voltage signal is applied between signal terminal g and signal terminal s. As a result, each semiconductor switching element is switched on or off, and AC power is output to the load such as a motor or transformer via the output wiring AC. Furthermore, semiconductor switching elements connected in parallel are controlled and driven by the same signal terminals g and s.
[0015] In the power converter 1, a capacitive component (parasitic capacitance) Cgd exists between the high-voltage terminal and the signal terminal g of each semiconductor switching element. Furthermore, a parasitic capacitance Cgs exists between the signal terminal g and the signal terminal s. Additionally, a capacitive component Cds exists between the high-voltage terminal and the low-voltage terminal of the semiconductor switching element. Furthermore, parasitic inductances Ld1 and Ld2 exist on the high-voltage terminal side of the semiconductor switching element, and parasitic inductances Ls1 and Ls2 exist on the low-voltage terminal side of the semiconductor switching element.
[0016] In the following description, the power semiconductor composed of semiconductor switching elements Sa1 and Sa2, and switching elements Sb1 and Sb2, which are connected in parallel to each other, will be referred to as the first power semiconductor 11, and the power semiconductor composed of semiconductor switching elements Sa2 and Sb2 will be referred to as the second power semiconductor 12. Furthermore, although the first embodiment of the present invention has a configuration in which two switching elements are connected in parallel, a multi-parallel configuration with two or more switching elements is also possible.
[0017] (Figure 2) The mounting on the multilayer wiring board 10 constituting the power conversion device 1 will be explained. In Figure 2, the multilayer wiring board 10 has a two-layer structure, but the embodiments of the present invention can be applied even if it is not limited to a two-layer structure. For example, the embodiments of the present invention can be applied to any two of the multiple wiring layers that the multilayer wiring board 10 has. Alternatively, a substrate structure in which the structure of the first layer and the structure of the second layer are swapped may also be used.
[0018] In the multilayer wiring board 10, the first layer 10a of the multilayer wiring board 10 shown in Figure 2(a) has power semiconductors 11 and 12, control terminals G and S mounted in parallel. Power semiconductor 11 is positioned on the board at a distance from control terminals G and S compared to power semiconductor 12. Control terminals G and S are formed on the board while maintaining an insulating distance from each other, and are terminals to which control signals from a control circuit (not shown) are input.
[0019] Furthermore, the first layer 10a has a first wiring region L1 where a first wiring is formed to electrically connect the first semiconductor switching element S1 of the power semiconductor 11 to the control terminal G, and a second wiring region L2 where a second wiring is formed to electrically connect the second semiconductor switching element S2 of the power semiconductor 12 to the control terminal G. The common wiring region T is the region where the first wiring region L1 and the second wiring region L2 merge and is connected to the control terminal G. The first wiring region L1 is a wiring region formed from the branching point 8 where the common wiring region T branches into the first wiring region L1 and the second wiring region L2, to the signal terminal g of the power semiconductor 11. The second wiring region L2 is a wiring region formed from the branching point 8 of the common wiring region T to the signal terminal g of the power semiconductor 12. The length of the wiring from the control terminal G to the signal terminal g is greater for the first wiring region L1 than for the second wiring region L2. The signal terminal g is, for example, the gate terminal of the semiconductor switching element. Furthermore, the signal terminals s of the power semiconductors 11 and 12 are, for example, the source terminals of the semiconductor switching elements.
[0020] In the multilayer wiring board 10, a conductor region C is formed in at least one of the multiple wiring layers. Specifically, the second layer 10b shown in Figure 2(b) has a conductor region C formed thereon. Since the conductor region C is formed in a different wiring layer from the wiring layer in which the first wiring region L1 and the second wiring region L2 are formed, it is insulated from the first wiring region L1 and the second wiring region L2, and in the thickness direction of the substrate, part or all of it overlaps with the first wiring region L1 and the second wiring region L2. Furthermore, the conductor region C is insulated from the control terminals G and S mounted on the same wiring layer.
[0021] The conductor region C may be a floating conductor, or a portion of the conductor region C may be connected to ground. By connecting the conductor region C to ground and grounding it, parasitic charges can be returned to ground, parasitic capacitance can be reduced, and noise reduction can be achieved. This enables high-frequency driving of the power converter 1. In addition, a portion of the conductor region C may be connected to the high-voltage side terminal of the power semiconductor. Furthermore, the conductor region C may be formed as a single, unified region on the wiring layer, or multiple conductor regions C may be formed by separating them on the wiring layer.
[0022] Figure 2(c) shows only the overlapping portion of the first wiring region L1 and the second wiring region L2 of the first layer 10a and the conductor region C of the second layer 10b in the multilayer wiring board 10. Here, region B1 is defined as the region obtained by doubling the width of the first wiring region L1. Region B2 is defined as the region obtained by doubling the width of the second wiring region L2. The region where the conductor region C and region B1 overlap in the substrate thickness direction is defined as the first overlapping region K1. The portion where the conductor region C and region B2 overlap is defined as the second overlapping region K2. The value obtained by dividing the area of the first overlapping region K1 by the area of region B1 is defined as the coverage rate C1 of the first wiring region L1 by the conductor region C. The value obtained by dividing the area of the second overlapping region K2 by the area of region B2 is defined as the coverage rate C2 of the second wiring region L2 by the conductor region C.
[0023] In the example shown in Figure 2(c), the area of the first overlapping region K1 is approximately the same as the area of region B1, so the coverage rate C1 is approximately 1. On the other hand, the area of the second overlapping region K2 is approximately half the area of region B2, so the coverage rate C2 is approximately 1 / 2. Therefore, according to the configuration shown in Figure 2, the coverage rate C1 is greater than the coverage rate C2.
[0024] (Figure 3) Figure 3(a) shows a perspective view of the overlapping structure in the stacking direction of the first wiring region L1 and the second wiring region L2 shown in Figure 2, and the conductor region C. Projection LA is the projection of the first wiring region L1 onto the conductor region C, and projection LB is the projection of the second wiring region L2 onto the conductor region C. Currents I1 and I2 flow through the first wiring region L1 and the second wiring region L2, respectively. The magnetic fields excited by the current changes in currents I1 and I2 induce eddy currents U1 and U2 in the conductor region C, which flow in the opposite direction to currents I1 and I2.
[0025] The current directions of eddy currents U1 and U2 are opposite to those of currents I1 and I2, which has the effect of mitigating (delaying) the current changes of currents I1 and I2. As a result, the parasitic inductance of the first wiring region L1 and the second wiring region L2 is reduced. Also, since the coverage ratio C1 is greater than the coverage ratio C2, the reduction effect of eddy current U1 is greater than that of eddy current U2. As shown in the figure, eddy current U1 is induced both inside and outside the projection LA of the first wiring region L1 in the conductor region C. In contrast, eddy current U2 is induced only within the projection LB of the second wiring region L2. Therefore, eddy current U1 induced outside the projection LA of the first wiring region L1 greatly reduces the inductance component of the first wiring region L1.
[0026] The reason why the aforementioned coverage rates are calculated using an area twice the width of each wiring region is that, compared to calculating each coverage rate using an area that is a multiple of more than twice the width of each wiring region, for example, it is possible to obtain a sufficient degree of influence due to the induced magnetic field. Furthermore, using an area twice the width of each wiring region makes it easier to consider the necessary mounting area on the multilayer wiring board 10, allowing for efficient use of the mounting area, which is advantageous for high-density mounting in the power conversion device 1. Thus, the reason for calculating each coverage rate using an area twice the width of each wiring region is the same for the subsequent coverage rates.
[0027] Figure 3(b) shows the effect of the structure illustrated in Figure 3(a). Of the four bar graphs, the two graphs on the left are examples of the effect when the conductor region C is not provided in the second layer 10b, and the two graphs on the right are examples of the effect when the conductor region C is provided in the second layer 10b as shown in the embodiment of the present invention. As shown in the left figure of Figure 2(b), when the conductor region C is not provided in the second layer 10b, the parasitic inductance Lsg1 of the first wiring region L1 differs greatly from the parasitic inductance Lsg2 of the second wiring region L2, and the switching loss imbalance, which is expressed by dividing the parasitic inductance Lsg1 of the first wiring region L1 by the parasitic inductance Lsg2 of the second wiring region L2, remains large.
[0028] On the other hand, in the embodiment of the present invention shown in the right-hand figure of Figure 2(b), by placing a conductor region C in the second layer 10b, the conductor region C is positioned to overlap with the first wiring region L1 and the second wiring region L2, which are two gate wirings in the first layer 10a, in the thickness direction of the substrate. As a result, the coverage rate C1 of the first wiring region L1, which is the longer of the two gate wirings in the first layer 10a, is made greater than the coverage rate C2 of the second wiring region L2, which is the shorter of the two gate wirings. Consequently, both the parasitic inductance Lsg1 of the first wiring region L1 and the parasitic inductance Lsg2 of the second wiring region L2 are reduced.
[0029] Furthermore, since the reduction in parasitic inductance Lsg1 is greater than the reduction in parasitic inductance Lsg2, the difference between the parasitic inductance Lsg1 of the first wiring region L1 and the parasitic inductance Lsg2 of the second wiring region L2 becomes smaller. In other words, the degree of switching loss imbalance, which is expressed by dividing the parasitic inductance Lsg1 of the first wiring region L1 by the parasitic inductance Lsg2 of the second wiring region L2, is reduced, and the effective inductance of the first wiring region L1 and the second wiring region L2 is reduced, and the impedance imbalance is reduced. This makes it possible to prevent false on-on and drive at high frequencies. It can also contribute to improving the driving range of the vehicle and the product life of the power converter 1.
[0030] (Figure 4) Figure 4 shows the effect of improving the balance of impedance components between the first wiring region L1 and the second wiring region L2 according to an embodiment of the present invention. The left diagram of Figure 4 shows the effect when a conductor region C is not provided, and the right diagram of Figure 5 shows the effect when an embodiment of the present invention is configured.
[0031] In power semiconductors, the gate rise time that occurs when a semiconductor switching element is turned on is determined by the impedance (parasitic inductance and resistance) between the gate and source wiring, and the capacitance between the gate and source. A mechanism is in place to reduce the gate rise time if the parasitic inductance, resistance, or capacitance between the gate and source increases.
[0032] As shown in the left diagram of Figure 4, if the conductor region C is not provided, the parasitic inductance Lsg1 of the first wiring region L1 is greater than the parasitic inductance Lsg2 of the second wiring region L2, as shown in Figure 3(b) above. Therefore, if the resistance and the capacitance between the gate and source are the same, the gate rise speed Vgs1 of the power semiconductor 11 is slower than the gate rise speed Vgs2 of the power semiconductor 12. As a result, the main current Id1 of the power semiconductor 11 becomes smaller than the main current Id2 of the power semiconductor 12, and the difference in switching losses caused by the difference in main currents results in an imbalance in switching losses. Consequently, the power semiconductor 12 generates more heat than the power semiconductor 11, raising concerns about thermal runaway and shortened lifespan. Furthermore, the thermal imbalance may cause resonance between the power semiconductor 11 and the power semiconductor 12.
[0033] Therefore, as shown in the embodiment of the present invention, a conductor region C is provided, and the coverage ratio C1 is configured to be greater than the coverage ratio C2. This reduces the difference between the parasitic inductance Lsg1 of the first wiring region L1 and the parasitic inductance Lsg2 of the second wiring region L2, thereby reducing the impedance imbalance as described above. As a result, as shown in the right figure of Figure 4, the difference between the gate rise speed Vgs1 of the power semiconductor 11 and the gate rise speed Vgs2 of the power semiconductor 12 becomes smaller, and consequently, the difference between the main current Id1 and the main current Id2 also becomes smaller. This reduces concerns about thermal runaway and shortened lifespan, as well as the possibility of resonance occurring between the power semiconductor 11 and the power semiconductor 12. Furthermore, by improving the balance between the resistance values of the first wiring region L1 and the second wiring region L2, and the capacitance value between the gate and the source, the same effects as described above can be obtained.
[0034] (Second Embodiment) (Figure 5) In the second embodiment, the objective is to improve the remaining impedance difference when the parasitic inductance difference between the first wiring region L1 and the second wiring region L2 is reduced in the first embodiment. In the second embodiment, the first resistor 5 is mounted on the first wiring region L1. As a result, the resistance value of the first wiring region L1 becomes greater than the resistance value of the second wiring region L2, and the impedance balance between the first wiring region L1 and the second wiring region L2 can be further improved. Note that assuming that the resistance value of the first wiring region L1 is greater than the resistance value of the second wiring region L2, a resistor (second resistor) may be mounted not only on the first wiring region L1 but also on the second wiring region L2.
[0035] (Third Embodiment) (Figure 6) The third embodiment will describe only the parts that differ from the first embodiment. Figure 6(a) is the first layer 10a of the multilayer wiring board 10, Figure 6(b) is the second layer 10b of the multilayer wiring board 10, Figure 6(c) is the third layer 10c of the multilayer wiring board 10, and Figure 6(d) is a diagram that describes only the parts in which the source wiring region and the conductor region C overlap for the wiring layer in Figure 6(b) and the wiring layer in Figure 6(c). In the description of the third embodiment, the multilayer wiring board 10 shown in Figure 6 will be described using a three-layer structure as an example, but embodiments of the present invention are not limited to a three-layer structure, and may consist of three layers out of multiple layers of the multilayer wiring board 10.
[0036] The third layer 10c of the multilayer wiring board 10 shown in Figure 6(c) has parallel-connected power semiconductors 11 and 12, control terminal G, and control terminal S mounted on it. The control terminal S is connected to the signal terminal s of the power semiconductor 11 via a common wiring region Tr and a first source wiring region Lr1 formed on the wiring layer. The control terminal S is also connected to the signal terminal s of the power semiconductor 12 via a common wiring region Tr and a second source wiring region Lr2 formed on the wiring layer. The signal terminal s is, for example, the source terminal of a semiconductor switching element.
[0037] As shown in Figure 6(b), in accordance with the mounting structure of the third layer 10c, the second layer 10b of the multilayer wiring board 10 has a conductor region C with the same area as the second source wiring region Lr2, in addition to the mounting structure similar to that of Figure 2(b) described above. In other words, a part of the conductor region C is positioned in the thickness direction of the board between the first wiring region L1 or the second wiring region L2 and the first source wiring region Lr1 and the second source wiring region Lr2.
[0038] Figure 6(d) shows the overlapping portion of the conductor region C and the source wiring region of the multilayer wiring board 10, where the second layer 10b and the third layer 10c overlap in the substrate stacking direction. Region Br1 is defined as the region obtained by doubling the width of the first source wiring region Lr1. Region Br2 is defined as the region obtained by doubling the width of the second source wiring region Lr2. The region where the conductor region C and region Br1 overlap is defined as the first overlapping region Kr1. The portion where the conductor region C and region Br2 overlap is defined as the second overlapping region Kr2. The value obtained by dividing the area of the first overlapping region K1 by the area of region B1 is defined as the coverage rate Cr1 of the first wiring region L1 by the conductor region C. Also, the value obtained by dividing the area of the second overlapping region Kr2 by the area of region Br2 is defined as the coverage rate Cr2 of the second source wiring region Lr2 by the conductor region C.
[0039] Since the area of the first overlapping region Kr1 is approximately 80% of the area of region Br1, the coverage rate Cr1 is approximately 0.8. Also, since the area of the second overlapping region Kr2 is approximately half the area of region Br2, the coverage rate Cr2 is approximately 1 / 2. Therefore, it can be seen that the coverage rate Cr1 is greater than the coverage rate Cr2. In this way, by placing the conductor region C between the gate wiring layer, which consists of the first wiring region L1 and the second wiring region L2, and the source layer wiring region, which consists of the first source wiring region Lr1 and the second source wiring region Lr2, the parasitic capacitance between the gate and the source can be reduced, and the impedance of the first source wiring region Lr1 and the second source wiring region Lr2 can be reduced, similar to the first embodiment.
[0040] (Figure 7) By applying the third embodiment, the parasitic capacitance component between the gate and source can be reduced. In this regard, a parasitic capacitance Cgs exists between the gate wiring layer and the source wiring layer, and the magnitude of this parasitic capacitance Cgs is proportional to the wiring distance between the gate wiring layer and the source wiring layer. As shown in Figure 7(b), by placing the conductor region C at an intermediate position in the thickness direction of the substrate between the gate wiring layer and the source wiring layer, as shown in Figure 7(a), the wiring distance 2d becomes larger than the distance d between the wiring layers when no wiring layer with a conductor region C is provided between the gate wiring layer and the source wiring layer. As a result, although the parasitic capacitance Cgs is larger in Figure 7(a) compared to Figure 7(b), the parasitic capacitance Cgs is reduced because the conductor region C is provided between the gate wiring layer and the source wiring layer. Furthermore, if the conductor region C is connected to ground and earthed, parasitic charges can be returned to ground, and the parasitic capacitance Cgs can be further reduced. Furthermore, reducing the parasitic capacitance Cgs lowers the impedance of the gate wiring, resulting in faster gate charging and discharging. This increases the rise time of the gate voltage Vgs during turn-on, enabling higher frequency driving.
[0041] (Fourth Embodiment) (Fig. 8) In the fourth embodiment, the multilayer wiring board 10 will be described by taking a four-layer structure as an example, but it is not limited to the four-layer structure, and it is also applicable to four layers of the multilayer wiring board 10. Note that Fig. 8(a) shows the first layer 10a of the multilayer wiring board 10, Fig. 8(b) shows the second layer 10b of the multilayer wiring board 10, Fig. 8(c) shows the third layer 10c of the multilayer wiring board 10, and Fig. 8(d) shows the fourth layer 10d of the multilayer wiring board 10, and it is a figure for explaining them.
[0042] In the fourth embodiment, different from the third embodiment, the conductor regions C are mounted on the first layer 10a and the third layer 10c of the multilayer wiring board 10. Note that the mounting structures of the first layer 10a and the third layer 10c of the multilayer wiring board 10 are the same, and the second layer 10b and the fourth layer 10d are the same as those in Fig. 6(a) and Fig. 6(c) described above, respectively. That is, the wiring layers in which the conductor regions C are formed are adjacent to the wiring layers in which the first wiring region L1 or the second wiring region L2 is formed on the upper side and the lower side in the thickness direction of the substrate, and are provided with a predetermined insulation distance.
[0043] As a result, the coverage rate C1 of the first wiring region L1 and the coverage rate C2 of the second wiring region L2 increase compared with the above-described embodiments, so the parasitic inductance of both the first wiring region L1 and the second wiring region L2 is further reduced compared with the above-described embodiments. In addition, the impedance of the gate wiring decreases, the charging and discharging of the gate become faster, and the rising speed (switching speed) of the gate voltage VgS at turn-on can be improved. Also, this enables high-frequency driving.
[0044] Note that the mounting of the first layer 10a may be made different from the mounting of the third layer 10c. For example, the conductor region C of the first layer 10a is arranged only in the layer above the first wiring region L1 of the second layer 10b in the thickness direction of the substrate, whereby the imbalance between the first wiring region L1 and the second wiring region L2 can be improved. Also, the conductor region C of the first layer 10a may have the same coverage rate for the first wiring region L1 and the second wiring region L2, whereby the impedance of both the first wiring region L1 and the second wiring region L2 can be further reduced.
[0045] Furthermore, in a wiring layer in which a conductor region C is formed, which is provided adjacent in the thickness direction of the substrate to a wiring layer in which a first wiring region L1 or a second wiring region L2 is formed, and which is not adjacent in the thickness direction of the substrate to a wiring layer in which a source wiring region is formed, a part of the conductor region C may be connected to the high-voltage terminals of the first semiconductor switching element and the second semiconductor switching element.
[0046] This makes it possible to increase the parasitic capacitance Cgd between the high-voltage terminal and the gate wiring. Furthermore, this adjusts LS / Cgd, calculated by dividing the parasitic inductance LS on the high-voltage side terminal of the semiconductor switching element by the parasitic capacitance Cgd, to fall within the range between Ld / Cgs, calculated by dividing the parasitic inductance Ld on the low-voltage side terminal of the semiconductor switching element by the parasitic capacitance Cgs between the gate wiring layer and the source wiring layer, and Lg / Cds, calculated by dividing the parasitic inductance Lg by the capacitive component Cds between the high-voltage side terminal and the low-voltage side terminal of the semiconductor switching element, thereby suppressing resonance between the power semiconductor 11 and the power semiconductor 12.
[0047] (Fifth Embodiment) (Figure 9) The fifth embodiment will be described below only in terms of the differences from the fourth embodiment. The fifth embodiment differs from the fourth embodiment in that the conductor region C of the first layer 10a and the conductor region C of the third layer 10c of the multilayer wiring board 10 are connected to each other by vias 7. In other words, in the multilayer wiring board 10, vias 7 are formed in each of the multiple wiring layers to connect parts of the conductor region C to each other between the wiring layers. The vias 7 are arranged on the wiring layer to surround the first wiring region L1 or the second wiring region L2. As a result, the first wiring region L1 or the second wiring region L2, and the first source wiring region Lr1 or the second source wiring region Lr2 are shielded, and the influence of external noise on each wiring region can be reduced.
[0048] (6th Embodiment) (Fig. 10) In the 6th embodiment, only the parts different from the 3rd embodiment will be described below. Since the conductor region C has a large area ratio mounted on each layer of the multilayer wiring board 10, there is a possibility that other mounting configurations of each layer may be restricted. Therefore, in the 6th embodiment, in the thickness direction of the multilayer wiring board 10 and the substrate, a conductor plate 6 is installed at a position separated by a predetermined distance. Note that a floating conductor may be provided at the position of the conductor plate 6, or the conductor plate 6 may be connected to the ground. Also, a part of the conductor plate 6 may be connected to the high-voltage side terminals of each semiconductor switching element. In the multilayer wiring board 10, the first layer to the third layer are illustrated as the first layer 10a, the second layer 10b, and the third layer 10c, respectively.
[0049] For the conductor plate 6, regarding the coverage rate C1 with respect to the first wiring region L1 in the first layer 10a and the coverage rate C2 with respect to the second wiring region L2 in the first layer 10a, it is desirable that the coverage rate C1 is the same as the coverage rate C2 or the coverage rate C1 is larger than the coverage rate C2. By doing so, while ensuring the area that can be effectively utilized for mounting the multilayer wiring board 10, the effects of the above-described embodiments can be obtained.
[0050] (7th Embodiment) (Fig. 11) Regarding the 7th embodiment, only the parts different from the 6th embodiment will be described below. In the 7th embodiment, a plurality of conductor plates 6 provided at a predetermined distance from each layer of the multilayer wiring board 10 are used. For example, as illustrated, a conductor plate 6a is disposed above the first wiring region L1 in the first layer 10a, and a conductor plate 6b is disposed above the second wiring region L2 in the first layer 1Pa. That is, the first conductor plate 6a is adjacent to the wiring layer 10a in which the first wiring region L1 is formed in the thickness direction of the substrate and is insulated from the first wiring region L1. Also, the second conductor plate 6b is adjacent to the wiring layer 10a in which the second wiring region L2 is formed in the thickness direction of the substrate and is insulated from the second wiring region L2.
[0051] Here, the distance between the conductor plate 6a and the first layer 10a is defined as the first distance d1, and the distance between the conductor plate 6b and the first layer 10a is defined as the second distance d2. The first distance d1 is greater than the second distance d2. Note that conductor plates 6a and 6b are different conductor plates. In this case, the effect of reducing the inductance component due to eddy currents is greater as the distance decreases. Therefore, even if the coverage ratio C1 and C2 are the same, the reduction in parasitic inductance in the first wiring region L1 will be greater than that in the second wiring region L2. This reduces parasitic capacitance and enables high-frequency driving.
[0052] It should be noted that the present invention is not limited to the embodiments described above, and various modifications and combinations of other configurations can be made without departing from the spirit of the invention. Furthermore, the present invention is not limited to having all the configurations described in the embodiments described above, and may also include configurations in which some of those configurations are omitted.
[0053] 1 Power converter 2 Positive electrode wiring 3 Negative electrode wiring 4 Smoothing capacitor 5 Resistor 6 Conductor board 6a First conductor board 6b Second conductor board 7 Via 8 Branch point 10 Multilayer wiring board 11 First power semiconductor 12 Second power semiconductor AC Output wiring B1 Region with twice the width of the first wiring region Br1 Region with twice the width of the first source wiring region B2 Region with twice the width of the second wiring region Br2 Region with twice the width of the second source wiring region C Conductor region Cgd, Cgs, Cds Capacitive components G Control terminal g Signal terminal I1 Current in the first wiring region I2 Current in the second wiring region Id1 Main current of the first power semiconductor Id2 Main current of the second power semiconductor K1, Kr1 First overlapping region K2, Kr2 Second overlapping region L1 First wiring region LA Projection of the first wiring region Lr1 First source wiring region L2 Second wiring region LB Projection of second wiring region Lr2 Second source wiring region Lsg1 First wiring parasitic inductance Lsg2 Second wiring parasitic inductance M Midpoint S Control terminal s Signal terminals Sa1, Sb1 First semiconductor switching elements Sb2, Sb2 Second semiconductor switching elements T, Tr Common wiring region U1, U2 Eddy current Vgs1 Gate voltage of first power semiconductor Vgs2 Gate voltage of second power semiconductor
Claims
1. A power converter comprising: a first semiconductor switching element; a second semiconductor switching element connected in parallel to the first semiconductor switching element; a substrate on which the first semiconductor switching element, the second semiconductor switching element, and a control terminal to which a control signal is input, wherein the substrate has a first wiring region on which wiring is formed to electrically connect the first semiconductor switching element and the control terminal; and a second wiring region on which wiring is formed to electrically connect the second semiconductor switching element and the control terminal, wherein at least one of the plurality of wiring layers of the substrate has a conductor region on which a conductor is formed, the conductor region is insulated from the first wiring region and the second wiring region, and is arranged to overlap the first wiring region and the second wiring region in the thickness direction of the substrate, the region on which the conductor region and a region twice the width of the first wiring region overlap in the thickness direction of the substrate is defined as a first overlapping region, and the value calculated by dividing the area of the first overlapping region by the area of the region twice the width of the first wiring region is defined as a first coverage rate. A power converter in which the conductor region and a region with twice the width of the second wiring region overlap in the thickness direction of the substrate, and the second coverage rate is the value obtained by dividing the area of the second overlapping region by the area of the region with twice the width of the second wiring region, wherein the first coverage rate is greater than the second coverage rate.
2. The power conversion device according to claim 1, wherein the plurality of wiring layers have a wiring layer on which a source wiring region is formed, and a part of the conductor region is arranged in the thickness direction of the substrate at a position between the first wiring region or the second wiring region and the source wiring region.
3. The power conversion device according to claim 2, wherein a portion of the conductor region is connected to ground.
4. The power conversion device according to any one of claims 1 to 3, wherein the distance between a first conductor plate adjacent to the wiring layer on which the first wiring region is formed in the thickness direction of the substrate and insulated from the first wiring region and the wiring layer on which the first wiring region is formed is defined as the first distance, and the distance between a second conductor plate adjacent to the wiring layer on which the second wiring region is formed in the thickness direction of the substrate and insulated from the second wiring region and the wiring layer on which the second wiring region is formed is defined as the second distance, wherein the first distance is greater than the second distance.
5. The power conversion device according to claim 1, wherein a first resistor is mounted on the first wiring region, a second resistor is mounted on the second wiring region, and the resistance value of the first resistor is greater than the resistance value of the second resistor.
6. The power conversion device according to claim 1 or claim 2, wherein the wiring layer on which the conductor region is formed is provided adjacent to the wiring layer on the upper and lower sides in the thickness direction of the substrate, with respect to the wiring layer on which the first wiring region or the second wiring region is formed.
7. The power conversion device according to claim 6, wherein vias are formed in each of the plurality of wiring layers to connect parts of the conductor regions to each other between the wiring layers, and the vias are arranged on the wiring layer to surround the first wiring region or the second wiring region.
8. The power conversion device according to claim 3, wherein, among the wiring layers on which the conductor region is formed, a wiring layer is provided adjacent in the thickness direction of the substrate to the wiring layer on which the first wiring region or the second wiring region is formed, and is not adjacent in the thickness direction of the substrate to the wiring layer on which the source wiring region is formed, and a part of the conductor region is connected to the high-voltage terminals of the first semiconductor switching element and the second semiconductor switching element.