Semiconductor integrated circuit device
The layout design for double-height cells with fork-sheet transistors in semiconductor integrated circuits addresses scaling issues by enhancing manufacturing precision and transistor performance estimation, reducing variations, and improving yield.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SOCIONEXT INC
- Filing Date
- 2025-12-17
- Publication Date
- 2026-07-16
AI Technical Summary
Existing semiconductor integrated circuit devices face challenges with excessive scaling leading to increased off-current and power consumption, particularly in double-height cells using CFETs, where specific considerations for the layout structure of filler cells using fork-sheet transistors have not been adequately addressed.
A layout design for semiconductor integrated circuit devices incorporating double-height cells with fork-sheet transistors, where standard cells are arranged in specific configurations with overlapping nanosheets and gate wirings to improve manufacturing precision and transistor performance estimation, including arrangements that maintain consistent active region widths and positions across cell boundaries.
The proposed layout enhances manufacturing precision and accuracy of transistor performance estimation by regularizing gate and local wiring arrangements, reducing manufacturing variations, and improving yield and reliability in semiconductor integrated circuit devices.
Smart Images
Figure JP2025044026_16072026_PF_FP_ABST