Early program termination for NAND SLC program
Early program termination in the trigger plane with slow SLC programming addresses defects in multi-plane semiconductor memory systems, preventing program failures and block loss in victim planes, thus improving system reliability and efficiency.
WO2026151468A1PCT designated stage Publication Date: 2026-07-16SANDISK TECHNOLOGIES LLC
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SANDISK TECHNOLOGIES LLC
- Filing Date
- 2025-06-12
- Publication Date
- 2026-07-16
AI Technical Summary
Technical Problem
In semiconductor memory systems with multi-plane architectures, defects in one plane can cause slow programming, leading to reduced program voltage in other planes, resulting in program failures and block loss, particularly in victim planes.
Method used
Implementing early program termination in the trigger plane with slow SLC programming to prevent negative impacts on victim planes, thereby ensuring successful completion of programming and preventing block loss.
Benefits of technology
Prevents program failures and block loss in victim planes by terminating programming early in the trigger plane with defects, enhancing the reliability and efficiency of multi-plane architectures.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure US2025033416_16072026_PF_FP_ABST
Abstract
Technology for handling neighbor plane disturb when programming non-volatile memory such as NAND. A memory system performs single level cell (SLC) programming with multiple program loops with verify. The memory system determines SLC programming speed during the SLC programming. The memory system terminates programming early in a plane having slow SLC programming.
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