Data reading control method and memory storage apparatus

Abstract

Provided in the present invention are a data reading control method and a memory storage apparatus, which can improve the quality and efficiency of sequential mapping table construction and improve the performance of a memory storage apparatus. The data reading control method is used for a rewritable non-volatile memory module. The data reading control method comprises: receiving a reading instruction and a first logical address interval corresponding thereto; on the basis of a status table, determining whether there is a first sequential mapping table corresponding to the first logical address interval; if there is the first sequential mapping table, executing a reading operation on the basis of the first sequential mapping table; and if there is no first sequential mapping table, executing the reading operation on the basis of a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

Description

Data read control method and memory storage device Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a data read control method and a memory storage device. Background Technology

[0002] The rapid growth of smartphones, tablets, and personal computers in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the various portable multimedia devices exemplified above due to their characteristics such as data non-volatility, low power consumption, small size, and lack of mechanical structure.

[0003] Generally, memory storage devices establish and maintain one or more mapping tables to record the mapping relationship between physical addresses and logical addresses. When the host system wants to read or write data from a rewritable non-volatile memory module, the memory management circuitry (e.g., the memory controller) may, for example, look up the mapping table to obtain the physical address corresponding to the logical address in order to perform data access operations on the rewritable non-volatile memory module. However, in memory storage devices, looking up or searching the mapping table is typically a time-consuming and energy-intensive operation.

[0004] Optimizing the operation of looking up the mapping table is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] Exemplary embodiments of the present invention provide a data read control method and a memory storage device, which can improve the performance of the memory storage device.

[0006] An exemplary embodiment of the present invention provides a data read control method for a rewritable non-volatile memory module. The data read control method includes: receiving a read instruction and its corresponding first logical address range; determining, based on a status table, whether a first sequential mapping table corresponding to the first logical address range exists; if the first sequential mapping table exists, performing a read operation according to the first sequential mapping table; if the first sequential mapping table does not exist, performing the read operation according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

[0007] In an exemplary embodiment of the present invention, the data reading control method further includes: constructing the status table; and constructing a plurality of sequential mapping tables, wherein the status table includes a plurality of status identifiers, the plurality of status identifiers respectively correspond to a plurality of logical address ranges, each status identifier is used to characterize whether there is a sequential mapping table corresponding to its corresponding logical address range, wherein the plurality of sequential mapping tables includes the first sequential mapping table, and the plurality of logical address ranges include the first logical address range.

[0008] In an exemplary embodiment of the present invention, the data reading control method further includes: detecting that a trigger condition is reached when multiple read operations are performed, then traversing the state table to query multiple consecutive segments; determining whether the multiple consecutive segments meet a preset condition; if so, arranging the multiple consecutive segments from largest to smallest, and copying a second sequential mapping table corresponding to the first number of consecutive segments in the multiple consecutive segments to a sequential mapping buffer memory, wherein the multiple sequential mapping tables include the second sequential mapping table.

[0009] In an exemplary embodiment of the present invention, the step of determining whether the plurality of consecutive segments meet the preset conditions includes: determining whether the number of the plurality of consecutive segments is within a preset interval; if the number is within the preset interval, determining whether the total number of state identifiers in the plurality of consecutive segments is greater than a third number; if so, determining that the plurality of consecutive segments meet the preset conditions.

[0010] In an exemplary embodiment of the present invention, the step of determining whether the plurality of consecutive segments meet the preset conditions further includes: if the quantity is not located in the preset interval, determining whether the quantity is greater than the preset quantity; if the quantity is greater than the preset quantity, determining whether the total number of state identifiers in the second number of consecutive segments with more state identifiers is greater than the third quantity; if so, determining that the plurality of consecutive segments meet the preset conditions.

[0011] In an exemplary embodiment of the present invention, the triggering condition is that the number of the plurality of read operations is greater than a preset value or the amount of data read corresponding to the plurality of read operations is greater than a preset amount of data.

[0012] In an exemplary embodiment of the present invention, the state identifier belonging to a first logical value among the plurality of state identifiers is used to indicate the existence of the sequential mapping table corresponding to its corresponding logical address range, and the state identifier belonging to a second logical value among the plurality of state identifiers is used to indicate the absence of the sequential mapping table corresponding to its corresponding logical address range.

[0013] In an exemplary embodiment of the present invention, each of the continuous segments includes a continuous state identifier, and the continuous state identifier is at least two adjacent state identifiers among the plurality of state identifiers, wherein the at least two adjacent state identifiers are both the first logic value.

[0014] In an exemplary embodiment of the present invention, the step of traversing the state table to query the plurality of consecutive segments includes: if a state identifier belonging to the second logical value is found, the subsequent fourth number of state identifiers are not queried.

[0015] In an exemplary embodiment of the present invention, the fourth quantity is associated with the logical address range corresponding to the consecutive write operations.

[0016] In an exemplary embodiment of the present invention, the step of arranging the plurality of consecutive segments from largest to smallest includes: arranging the plurality of consecutive segments from largest to smallest according to the number of state identifiers they include.

[0017] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit includes a sequentially mapped buffer memory. The connection interface unit is used to couple to a host system. The memory control circuit unit is used to receive a read instruction and its corresponding first logical address range. The memory control circuit unit is further used to determine, based on a status table, whether a first sequential mapping table corresponding to the first logical address range exists. If the first sequential mapping table exists, the memory control circuit unit is further used to perform a read operation according to the first sequential mapping table. If the first sequential mapping table does not exist, the memory control circuit unit is further used to perform the read operation according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

[0018] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to construct the state table and a plurality of sequential mapping tables, wherein the state table includes a plurality of state identifiers, the plurality of state identifiers respectively correspond to a plurality of logical address ranges, each state identifier is used to characterize whether there is a sequential mapping table corresponding to its corresponding logical address range, wherein the plurality of sequential mapping tables includes the first sequential mapping table, and the plurality of logical address ranges include the first logical address range.

[0019] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to detect that a trigger condition is met when multiple read operations are performed. The memory control circuit unit is further configured to traverse the state table to query multiple consecutive segments. The memory control circuit unit is further configured to determine whether the multiple consecutive segments satisfy a preset condition. If so, the memory control circuit unit is further configured to arrange the multiple consecutive segments in descending order and copy a second sequential mapping table corresponding to the first number of consecutive segments among the multiple consecutive segments to a sequential mapping buffer memory, wherein the multiple sequential mapping tables include the second sequential mapping table.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine whether the number of the plurality of consecutive segments is within a preset range. If the number is within the preset range, the memory control circuit unit is further configured to determine whether the total number of state identifiers in the plurality of consecutive segments is greater than a third number. If so, the memory control circuit unit is further configured to determine that the plurality of consecutive segments satisfy the preset condition.

[0021] In an exemplary embodiment of the present invention, if the quantity is not within the preset range, the memory control circuit unit is further configured to determine whether the quantity is greater than a preset quantity. If the quantity is greater than the preset quantity, the memory control circuit unit is further configured to determine whether the total number of state identifiers in a second number of consecutive segments with more state identifiers is greater than the third quantity. If so, the memory control circuit unit is further configured to determine that the multiple consecutive segments satisfy the preset condition.

[0022] In an exemplary embodiment of the present invention, if the status identifier belonging to the second logical value is found, the memory control circuit unit is further configured not to query the subsequent fourth number of status identifiers.

[0023] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to arrange the plurality of consecutive segments in descending order of the number of state identifiers they include.

[0024] Based on the above, the present invention provides a data read control method and a memory storage device, which can optimize the management mechanism for the sequential mapping table based on the continuity of the state table (i.e., multiple consecutive segments in the state table) and perform read operations according to the sequential mapping table, so as to reduce the time required to load the mapping table and thereby improve the performance of the memory storage device.

[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0026] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0031] Figure 6 is a schematic diagram of a module for managing a rewritable non-volatile memory according to an exemplary embodiment of the present invention;

[0032] Figure 7 is a schematic diagram of a state table and a sequence mapping table according to an exemplary embodiment of the present invention;

[0033] Figure 8 is a flowchart illustrating a data reading control method according to an exemplary embodiment of the present invention;

[0034] Figure 9 is a flowchart illustrating a data reading control method according to an exemplary embodiment of the present invention. Detailed Implementation

[0035] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0036] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0037] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device, and I / O device according to an exemplary embodiment of the present invention.

[0038] Referring to Figures 1 and 2, the host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be coupled to a system bus 110.

[0039] In one exemplary embodiment, the host system 11 can be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 can be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0040] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0041] In one exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0042] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the host system 11 is an in-vehicle system. In one exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include the memory storage device 30 and the host system 31 of FIG3.

[0043] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0044] Referring to Figure 3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0045] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0046] Referring to Figure 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0047] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0048] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0049] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0050] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0051] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical units. Specifically, memory cells on the same word line can form one or more physical programmable units. If each memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0052] In one exemplary embodiment, an entity programming unit is the smallest unit of programming. That is, an entity programming unit is the smallest unit for writing data. For example, an entity programming unit can be an entity page or an entity sector. If the entity programming unit is an entity page, these entity programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple entities for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit area contains 32 entities, and the size of one entity sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer entities, and the size of each entity sector may also be larger or smaller. On the other hand, an entity unit is the smallest unit of erasure. That is, each entity unit contains a minimum number of storage units that are erased together. For example, an entity unit is an entity block.

[0053] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0054] Please refer to Figure 5. The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0055] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0056] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware format. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are written to the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0057] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0058] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuitry is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuitry 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0059] The host interface 52 is coupled to the memory management circuitry 51. The memory management circuitry 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuitry 51 through the host interface 52. In addition, the memory management circuitry 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0060] The memory interface 53 is coupled to the memory management circuit 51 and used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0061] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, a power management circuit 56, and a sequential mapping buffer memory 57.

[0062] Error checking and correction circuit 54 is coupled to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0063] Buffer memory 55 is coupled to memory management circuit 51 and is used to temporarily store data. Power management circuit 56 is coupled to memory management circuit 51 and is used to control the power supply of memory storage device 10. Sequential mapping buffer memory 57 is coupled to memory management circuit 51 and is used to store sequential mapping table.

[0064] In one exemplary embodiment, the rewritable non-volatile memory module 43 of FIG4 may include a flash memory module. In one exemplary embodiment, the memory control circuit unit 42 of FIG4 may include a flash memory controller. In one exemplary embodiment, the memory management circuit 51 of FIG5 may include flash memory management circuitry.

[0065] Figure 6 is a schematic diagram of a management module for a rewritable nonvolatile memory according to an exemplary embodiment of the present invention.

[0066] Referring to Figure 6, the memory management circuit 51 can logically group the physical cells 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602. A physical cell refers to a virtual block (VB). A virtual block may include multiple physical cells. For example, a virtual block may contain one or more physical cells.

[0067] Entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG1). For example, entity units 610(0) to 610(A) in storage area 601 can store valid data and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit can be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) can be erased. When new data is written, one or more entity units can be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0068] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in memory area 601. In an exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0069] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data stored in this entity unit currently contains valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data stored in this entity unit currently does not contain any valid data.

[0070] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logical units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in this logic-to-entity mapping table.

[0071] Figure 7 is a schematic diagram of a state table and a sequence mapping table according to an exemplary embodiment of the present invention.

[0072] Referring to Figure 7, the memory management circuit 51 can record management information describing the mapping relationship between logical address ranges and physical address ranges in a sequential mapping table, and construct a status table (PTE) to manage the sequential mapping table. In an exemplary embodiment, the status table PTE may include, for example, multiple (e.g., 512) status identifiers, and each status identifier corresponds to a logical address range. For example, each status identifier corresponds to a logical address range of size 4kB. For example, the logical address range includes the addresses of multiple logical units. For example, the physical address range includes the addresses of multiple physical units.

[0073] In one exemplary embodiment, each state identifier is used to indicate whether a sequential mapping table corresponding to its corresponding logical address range exists. Specifically, multiple state identifiers may belong to a first logical value (e.g., logical value 1) or a second logical value (e.g., logical value 0). For example, a state identifier belonging to logical value 1 indicates that its corresponding logical address range has been mapped to one or more entity address ranges. That is, a state identifier belonging to logical value 1 indicates that a sequential mapping table corresponding to its corresponding logical address range exists. For example, a state identifier belonging to logical value 0 indicates that its corresponding logical address range has not been mapped to an entity address range. That is, a state identifier belonging to logical value 0 indicates that a sequential mapping table corresponding to its corresponding logical address range does not exist.

[0074] In one exemplary embodiment, the memory management circuit 51 can perform a read operation on the memory storage device 10 according to a sequential mapping table or the aforementioned logical-to-physical mapping table. Specifically, when the host system 11 wants to read data from the memory storage device 10, the memory management circuit 51 can receive a read instruction and its corresponding logical address range (also referred to as the first logical address range). The memory management circuit 51 can determine whether a sequential mapping table (also referred to as the first sequential mapping table) corresponding to the first logical address range exists according to the status table PTE.

[0075] In one exemplary embodiment, it is assumed that the first logical address range corresponds to the 5th status identifier in the status table PTE. As shown in FIG7, the 5th status identifier belongs to the first logical value (i.e., logical value 1), which indicates that there exists a first sequential mapping table M1 corresponding to the first logical address range. Therefore, the memory management circuit 51 can perform a read operation according to the first sequential mapping table M1.

[0076] Specifically, the sequential mapping table M1 includes, but is not limited to, a starting logical address Addr-l, a length L, and a starting entity address Addr-phy. The starting logical address Addr-l is the starting address of the logical address range included in the sequential mapping table M1. The length L is the length of the logical address range included in the sequential mapping table M1. The starting entity address Addr-phy is the starting address of the entity address range corresponding to the logical address range. As shown in Figure 7, the starting logical address Addr-l is 4 and the length L is 3. Since the first logical address range corresponds to the 5th state identifier in the state table PTE (meaning the first logical address range is the 5th logical address range represented by the state table PTE) and the starting logical address Addr-l is 4 (meaning the starting address of the logical address range included in the sequential mapping table M1 is the starting address of the 4th logical address range), the memory management circuit 51 can calculate that the difference (also called the offset) between the starting address (meaning the starting address of the 4th logical address range) and the starting address of the currently requested logical address range (meaning the 5th logical address range) is 1 (meaning the length of 1 logical address range). Then, the memory management circuit 51 can obtain the physical address of the physical address range to which the first logical address range is mapped based on the starting physical address Addr-phy, the length L, and the offset, and complete the read operation accordingly.

[0077] In one exemplary embodiment, assume that the first logical address range corresponds to the fourth status identifier in the status table PTE. As shown in Figure 7, the fourth status identifier belongs to the second logical value (i.e., logical value 0), which indicates that there is no first sequential mapping table corresponding to the first logical address range. Therefore, the memory management circuit 51 needs to perform a read operation according to the above-mentioned logical-to-physical mapping table.

[0078] It should be noted that, because the logical-to-entity mapping table records the mapping relationship between each logical unit and an entity unit, while the sequential mapping table only includes the following information: starting entity address Addr-phy, length L, and starting entity address Addr-phy, and only this information is needed to represent the mapping relationship between logical address ranges and entity address ranges, the logical-to-entity mapping table requires more storage space than the sequential mapping table. Furthermore, the loading time of the logical-to-entity mapping table is also longer than that of the sequential mapping table.

[0079] It is worth mentioning that if the data written from the host system 11 is discontinuous, a logical unit corresponding to the written data may be mapped to multiple physical units. In this case, when the host system 11 wants to read the data belonging to this logical unit, the memory management circuit 51 needs to load different logical-to-physical mapping tables multiple times to perform the read operation. This approach will slow down the read speed and seriously affect the performance of the memory storage device 10.

[0080] Accordingly, the memory management circuit 51 of the present invention can determine whether to use a logic-to-entity mapping table or a sequential mapping table to perform a read operation through the status table PTE, which can speed up the execution efficiency of the read operation and thus improve the performance of the memory storage device 10.

[0081] Figure 8 is a flowchart illustrating a data reading control method according to an exemplary embodiment of the present invention.

[0082] Referring to Figure 8, in step S801, the memory management circuit 51 detects that a trigger condition has been met when multiple read operations are performed. In one exemplary embodiment, the read operations may be, for example, sequential read operations or random read operations. In one exemplary embodiment, the trigger condition is that the number of multiple read operations is greater than a preset value. In one exemplary embodiment, the trigger condition is that the amount of data read corresponding to the multiple read operations is greater than a preset data amount. The values ​​of the preset value and the preset data amount can be designed according to actual needs, and the present invention does not impose any limitations.

[0083] In step S802, the memory management circuit 51 can traverse the state table PTE to query multiple consecutive segments. In an exemplary embodiment, the memory management circuit 51 can examine multiple state identifiers in the state table PTE to query multiple consecutive segments. Specifically, each consecutive segment includes consecutive state identifiers, and consecutive state identifiers are at least two adjacent state identifiers among the multiple state identifiers in the state table PTE, wherein at least two adjacent state identifiers are both a first logic value (i.e., logic value 1). For example, as shown in FIG7, the first 3 state identifiers in the state table PTE are all logic values ​​1, so these 3 state identifiers constitute a consecutive segment.

[0084] In one exemplary embodiment, when the memory management circuit 51 queries a status flag belonging to the second logical value (i.e., logical value 0), the memory management circuit 51 may not query the subsequent fourth number (e.g., 64) status flags. In one exemplary embodiment, the fourth number is associated with the logical address range corresponding to the consecutive write operations.

[0085] Generally, the logical address range corresponding to a continuous write operation is in units of 512kB. Therefore, during the process of the memory management circuit 51 searching for a continuous segment, each search unit needs to be less than 512kB (for example, 256kB). Therefore, the fourth quantity can be defined as 256kB (meaning 64 status flags).

[0086] For example, as shown in Figure 7, if the fourth status identifier in the status table PTE is a logical value of 0, the memory management circuit 51 does not need to query the 64 status identifiers following this status identifier. To further explain, a logical value of 0 for the fourth status identifier indicates that there is no sequential mapping table corresponding to the logical address range corresponding to the fourth status identifier. In other words, the logical address range corresponding to the fourth status identifier is not mapped to a physical address range. Therefore, the logical address ranges corresponding to the 64 status identifiers following the fourth status identifier should mostly correspond to non-contiguous physical addresses. In other words, the probability of these 64 status identifiers having a continuous segment is small, so these 64 status identifiers can be omitted to quickly find the next continuous segment and improve the speed of traversing the status table PTE.

[0087] After traversing the state table PTE, the memory management circuit 51 can then determine whether multiple consecutive segments meet preset conditions. For example, the memory management circuit 51 can then execute step 803 and / or step 807 to determine whether multiple consecutive segments meet preset conditions.

[0088] In step S803, the memory management circuit 51 determines whether the number of multiple consecutive segments falls within a preset range. In an exemplary embodiment, the preset range may be, for example, 4 to 8 segments. The range of the preset range can be designed according to actual needs, and the present invention does not impose any limitations. If the number of multiple consecutive segments falls within the preset range, the process proceeds to step S804. Conversely, if the number of multiple consecutive segments does not fall within the preset range, the process proceeds to step S807.

[0089] In step S804, the memory management circuit 51 can determine whether the total number of status identifiers in multiple consecutive segments is greater than the third number (for example, 128, 128 status identifiers is 512kB).

[0090] In one exemplary embodiment, assuming the number of consecutive segments is 8, the memory management circuit 51 can determine whether the total number of state markers in these 8 consecutive segments is greater than 128. The value of this third quantity can be designed according to actual needs, and the present invention does not impose any limitations.

[0091] If the total number of status identifiers in multiple consecutive segments is no greater than 128, the data read control method in Figure 8 ends. Specifically, when the total number of status identifiers in multiple consecutive segments is no greater than 128, it indicates that the Status Table (PTE) is in a highly random state, and the effectiveness of using a sequential mapping table to record the mapping relationship between logical address ranges and physical address ranges is limited. Therefore, if the total number of status identifiers in multiple consecutive segments is no greater than 128, the data read control method in Figure 8 ends, and the Status Table (PTE) is no longer used.

[0092] Conversely, if the total number of status markers in these 8 consecutive segments is greater than 128, then proceed to step S805.

[0093] In step S805, the memory management circuit 51 can determine that multiple consecutive segments meet preset conditions.

[0094] In step S806, the memory management circuit 51 can arrange the plurality of consecutive segments from largest to smallest and copy the sequential mapping table (also called the second sequential mapping table) corresponding to the first number (e.g., the first 4) consecutive segments among the plurality of consecutive segments to the sequential mapping buffer memory 57. In an exemplary embodiment, the memory management circuit 51 can arrange the plurality of consecutive segments from largest to smallest according to the number of state identifiers they include. Then, the memory management circuit 51 can copy the second sequential mapping table corresponding to the first 4 consecutive segments with the most state identifiers in the state table PTE to the sequential mapping buffer memory 57. Accordingly, the memory management circuit 51 can construct a high-quality (e.g., corresponding to multiple logical address ranges) sequential mapping table based on all sequential mapping tables corresponding to the previous 4 consecutive segments (i.e., all second sequential mapping tables), thereby improving the performance of the memory storage device 10.

[0095] Accordingly, the memory management circuit 51 can pre-read the data that may be needed into the buffer memory 55 based on the information in all sequential mapping tables corresponding to the previous four consecutive segments, thereby improving the performance of the memory storage device 10. In addition, copying the first four consecutive segments to the sequential mapping buffer memory 57 can avoid the time spent loading the sequential mapping table when performing subsequent data access operations, and can reduce the situation of loading different logical to physical mapping tables multiple times, thereby improving the data access speed of the memory storage device 10.

[0096] On the other hand, if the number of multiple consecutive segments is not within the preset range (i.e., 4 to 8), in step S807, the memory management circuit 51 can determine whether the number of multiple consecutive segments is greater than a preset number (e.g., 4). The value of the preset number can be designed according to actual needs, and the present invention does not impose any limitations. If the number of multiple consecutive segments is not greater than 4, the data reading control method of FIG8 ends, and the state table PTE is no longer used. Specifically, when the number of multiple consecutive segments is not greater than 4, it indicates that the state table PTE is in a highly random state, so the state table PTE is no longer used.

[0097] Conversely, if the number of multiple consecutive segments is greater than 4, proceed to step S808.

[0098] In step S808, the memory management circuit 51 can determine whether the total number of state identifiers in a second number (e.g., the first 8) of consecutive segments with more state identifiers is greater than a third number (i.e., 128). In an exemplary embodiment, assuming there are 10 consecutive segments, the memory management circuit 51 can select 8 consecutive segments with more state identifiers from these 10 consecutive segments and determine whether the total number of state identifiers in these 8 consecutive segments is greater than 128. If the total number of nodes in these 8 consecutive segments is not greater than 128, it indicates that the state table PTE is in a highly random state, and the data read control method of FIG8 ends, and the state table PTE is no longer used.

[0099] Conversely, if the total number of status flags in these 8 consecutive segments is greater than 128, the memory management circuit 51 can then proceed to complete steps S805 and S806. The implementation details of steps S805 and S806 have been explained in detail above and will not be repeated here.

[0100] Based on the above, the memory management circuit 51 can optimize the management mechanism for the sequential mapping table based on the continuity of the status table PTE to construct a high-quality (e.g., corresponding to multiple logical address ranges) sequential mapping table, thereby improving the performance of the memory storage device 10.

[0101] Figure 9 is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Please refer to Figure 9. In step S901, a read instruction and its corresponding first logical address range are received. In step S902, it is determined whether a first sequential mapping table corresponding to the first logical address range exists based on a status table. In step S903, if a first sequential mapping table exists, a read operation is performed according to the first sequential mapping table. In step S904, if a first sequential mapping table does not exist, a read operation is performed according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

[0102] However, the steps in Figure 9 have been described in detail above and will not be repeated here. It is worth noting that each step in Figure 9 can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, the method in Figure 9 can be used in conjunction with the above embodiments or used alone, and this invention is not limited thereto.

[0103] In summary, the data reading control method and memory storage device proposed in the exemplary embodiments of the present invention can optimize the management mechanism for the sequential mapping table based on the continuity of the state table, and use the sequential mapping table to perform the reading operation, which can speed up the execution efficiency of the reading operation and thus improve the performance of the memory storage device 10.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data read control method, characterized by, For a rewritable non-volatile memory module, the data read control method includes: Receive the read instruction and its corresponding first logical address range; Determine whether a first sequential mapping table corresponding to the first logical address range exists based on the status table; If the first sequential mapping table exists, then perform a read operation based on the first sequential mapping table; If the first sequential mapping table does not exist, the read operation is performed according to the logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

2. The data reading control method according to claim 1 further includes: Construct the state table; as well as Construct multiple sequential mapping tables, The status table includes multiple status identifiers, each corresponding to a multiple logical address range. Each status identifier is used to indicate whether a sequential mapping table exists corresponding to its corresponding logical address range. The plurality of sequential mapping tables include the first sequential mapping table, and the plurality of logical address ranges include the first logical address range.

3. The data reading control method according to claim 2 further includes: If the trigger condition is detected when multiple read operations are performed, the state table is traversed to query multiple consecutive segments; Determine whether the plurality of consecutive segments meet the preset conditions; If so, the plurality of consecutive segments are arranged from largest to smallest, and a second sequential mapping table corresponding to the first number of consecutive segments in the plurality of consecutive segments is copied to a sequential mapping buffer memory, wherein the plurality of sequential mapping tables includes the second sequential mapping table.

4. The data reading control method according to claim 3, wherein the step of determining whether the plurality of consecutive segments meet the preset conditions includes: Determine whether the number of the plurality of consecutive segments is within a preset range; If the quantity is within the preset range, then determine whether the total number of state identifiers in the multiple consecutive segments is greater than the third quantity; If so, then the plurality of consecutive segments are determined to satisfy the preset conditions.

5. The data reading control method according to claim 4, wherein the step of determining whether the plurality of consecutive segments meet the preset conditions further includes: If the quantity is not within the preset range, determine whether the quantity is greater than the preset quantity; If the number is greater than the preset number, then determine whether the total number of state identifiers in the second number of consecutive segments that include more state identifiers is greater than the third number. If so, then the plurality of consecutive segments are determined to satisfy the preset conditions.

6. The data reading control method according to claim 3, wherein the triggering condition is that the number of the plurality of reading operations is greater than a preset value or the amount of data read corresponding to the plurality of reading operations is greater than a preset amount of data.

7. The data reading control method according to claim 3, wherein... The state identifier belonging to the first logical value among the plurality of state identifiers is used to indicate the existence of the sequential mapping table corresponding to its corresponding logical address range. The status identifier belonging to the second logical value among the plurality of status identifiers is used to indicate that there is no sequential mapping table corresponding to the logical address range it corresponds to.

8. The data reading control method according to claim 7, wherein each of the continuous segments includes a continuous state identifier, and the continuous state identifier is at least two adjacent state identifiers among the plurality of state identifiers, wherein the at least two adjacent state identifiers are both the first logic value.

9. The data reading control method according to claim 7, wherein the step of traversing the state table to query the plurality of consecutive segments includes: If the status identifier belonging to the second logical value is found, the subsequent fourth number of status identifiers are not queried.

10. The data read control method according to claim 9, wherein the fourth quantity is associated with the logical address range corresponding to the continuous write operation.

11. The data reading control method according to claim 3, wherein the step of arranging the plurality of consecutive segments from largest to smallest includes: The multiple consecutive segments are arranged in descending order of the number of state identifiers they contain.

12. A memory storage device, comprising: include: A connection interface unit for coupling to the host system; Rewritable non-volatile memory module; as well as The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, and includes a sequentially mapped buffer memory. The memory control circuit unit is used to: Receive the read instruction and its corresponding first logical address range; Determine whether a first sequential mapping table corresponding to the first logical address range exists based on the status table; If the first sequential mapping table exists, then perform a read operation based on the first sequential mapping table; If the first sequential mapping table does not exist, the read operation is performed according to the logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

13. The memory storage device according to claim 12, wherein the memory control circuit unit is further configured to: Construct the state table; and Construct multiple sequential mapping tables, The status table includes multiple status identifiers, each corresponding to a multiple logical address range. Each status identifier is used to indicate whether a sequential mapping table exists corresponding to its corresponding logical address range. The plurality of sequential mapping tables include the first sequential mapping table, and the plurality of logical address ranges include the first logical address range.

14. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: If the trigger condition is detected when multiple read operations are performed, the state table is traversed to query multiple consecutive segments; Determine whether the plurality of consecutive segments meet the preset conditions; If so, the plurality of consecutive segments are arranged from largest to smallest, and a second sequential mapping table corresponding to the first number of consecutive segments in the plurality of consecutive segments is copied to a sequential mapping buffer memory, wherein the plurality of sequential mapping tables includes the second sequential mapping table.

15. The memory storage device according to claim 14, wherein the memory control circuit unit is further configured to: Determine whether the number of the plurality of consecutive segments is within a preset range; If the quantity is within the preset range, then determine whether the total number of state identifiers in the multiple consecutive segments is greater than the third quantity; If so, then the plurality of consecutive segments are determined to satisfy the preset conditions.

16. The memory storage device according to claim 15, wherein the memory control circuit unit is further configured to: If the quantity is not within the preset range, determine whether the quantity is greater than the preset quantity; If the number is greater than the preset number, then determine whether the total number of state identifiers in the second number of consecutive segments that include more state identifiers is greater than the third number. If so, then the plurality of consecutive segments are determined to satisfy the preset conditions.

17. The memory storage device according to claim 14, wherein the triggering condition is that the number of the plurality of read operations is greater than a preset value or the amount of data corresponding to the read data of the plurality of read operations is greater than a preset amount of data.

18. The memory storage device according to claim 14, wherein The state identifier belonging to the first logical value among the plurality of state identifiers is used to indicate the existence of the sequential mapping table corresponding to its corresponding logical address range. The status identifier belonging to the second logical value among the plurality of status identifiers is used to indicate that there is no sequential mapping table corresponding to the logical address range it corresponds to.

19. The memory storage device of claim 18, wherein each of the consecutive segments includes a consecutive state identifier, and the consecutive state identifier is at least two adjacent state identifiers among the plurality of state identifiers, wherein the at least two adjacent state identifiers are both the first logic value.

20. The memory storage device according to claim 18, wherein the memory control circuit unit is further configured to: If the status identifier belonging to the second logical value is found, the subsequent fourth number of status identifiers are not queried.

21. The memory storage device of claim 20, wherein the fourth quantity is associated with the logical address range corresponding to a series of write operations.

22. The memory storage device according to claim 14, wherein the memory control circuit unit is further configured to: The multiple consecutive segments are arranged in descending order of the number of state identifiers they contain.

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