Method for evaluating routing success rate of routing switch box in FPGA place-and-route process and placement optimization method based on evaluation result

Abstract

The present application relates to the field of integrated circuits, and discloses a method for evaluating a routing success rate of a routing switch box (RSB) in a field programmable gate array (FPGA) place-and-route process. In the method, driver nodes and sink nodes of an RSB are analyzed, and in view of a placement result, sink nodes needing to be connected are counted, searching is performed for routable paths, and a routability success rate of the RSB is calculated. The present application further discloses a placement optimization method based on an evaluation result, wherein a routability success rate of each RSB is calculated, and re-placement is performed on a region in which an RSB having a routability success rate lower than a threshold is located, until the routability satisfies a requirement. The present application can more accurately quantify and evaluate resource usage and a routing success rate of an RSB. Placement adjustment is guided by evaluating routability on the basis of an RSB as a unit before routing, so that the difficulty of routing in the RSB is reduced, congestion is reduced, routing convergence speed is accelerated, and the design efficiency and reliability of an FPGA are improved.

Description

Method for evaluating interconnection switch block routing success rate in FPGA placement and routing process and placement optimization method based on evaluation result TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design automation, and in particular to a FPGA placement optimization method based on routing success rate. BACKGROUND

[0002] FPGA(Field Programmable Gate Array) is widely used in the field of digital circuit design due to its flexible programmable characteristics. The design process of FPGA mainly includes design reading, synthesis mapping, placement and routing and other links. Among them, placement and routing is one of the most critical steps in the whole design process, which directly affects the performance and realizability of the design.

[0003] In the placement and routing process of FPGA, the routing process needs to realize the signal connection between logic units through interconnection switch block(RSB, Routing Switch Box). RSB contains a large number of programmable switch nodes inside, which is responsible for realizing the connection of signals from the input end(Driver) to the output end(Sink). The traditional routing method is to take the wire net as the basic unit after the placement is completed, and to eliminate congestion through multiple iterations of disconnection and redistribution to realize the final routing.

[0004] However, this traditional routing method has several significant problems: first, due to the lack of pre-evaluation of RSB routing capacity, in the case of high routing demand density, the routing difficulty inside a single RSB may be very large, and multiple routing iterations are needed to find a feasible solution, sometimes even unable to find a feasible routing scheme. Secondly, frequent routing iterations not only increase the design time, but also consume a large amount of computing resources. Finally, when the routing fails, the designer often needs to return to the placement stage to start again, and this trial-and-error method seriously affects the design efficiency.

[0005] For example, when a placement scheme is determined, there may be a situation that some RSBs need to handle too many signal connections. In this case, even if a lot of time is spent on routing iteration, it may not be possible to find a suitable routing scheme within the RSB. Worse still, the traditional method cannot predict the occurrence of such a situation before routing, and can only discover the problem after routing fails.

[0006] Furthermore, existing technologies suffer from a fundamental problem: the separation between the placement and routing phases. The placement phase primarily considers the location of logic cells without adequately addressing the feasibility of subsequent routing; the routing phase passively accepts the placement results, resorting to repeated attempts to resolve routing difficulties. This separation leads to inefficiencies in the design flow, particularly pronounced in large-scale or highly complex FPGA designs.

[0007] Therefore, the FPGA design flow urgently needs a method that can assess routing difficulty before routing and guide placement optimization accordingly. This method should be able to: accurately assess the routing capability of RSBs; identify potential routing bottlenecks early; effectively guide placement optimization to improve routing success rate; and reduce unnecessary routing iterations. Only by solving these problems can the efficiency and reliability of the FPGA design flow be truly improved. Summary of the Invention

[0008] The purpose of this application is to provide a method for evaluating the success rate of interconnect switch block routing in FPGA placement and routing process, and a placement optimization method based on the evaluation results, so as to solve the problems mentioned in the background art.

[0009] This application discloses a method for evaluating the success rate of interconnect switch block routing in FPGA placement and routing process, including the following steps:

[0010] Analyze the interconnection switch blocks in the FPGA, record the set of drain nodes that each driver node can connect to and the switch nodes that need to be passed from the driver node to the drain node, and count the total number of driver nodes in the interconnection switch blocks.

[0011] Based on the layout results, the set of drain nodes that need to be connected within the interconnection switch block is counted.

[0012] Select one drain node from the set of drain nodes that need to be connected as the node to be analyzed, find the driving node that can be routed to the node to be analyzed, and check whether the switch node that needs to be passed from the driving node to the node to be analyzed has been occupied.

[0013] If all the switch nodes that must be traversed from the driving end node to the node to be analyzed are not occupied, then the count of the traversable path is incremented by 1, and all switch nodes traversed by the path are marked as occupied; wherein, for each combination of driving end node and leaking end node, the traversable path is counted only once, and the case of multiple paths occupying the same switch node is excluded.

[0014] Determine whether all driver nodes and the missing nodes that need to be connected have been traversed. If yes, calculate the routing success rate of the interconnection switch block. The routing success rate is equal to the minimum of the routing path count and the total number of driver nodes, divided by the total number of driver nodes and multiplied by 100. If no, return to the above steps of finding routing paths until the traversal is complete.

[0015] In a preferred embodiment, the driving terminal node is used to receive external signals into the interconnect switch block, and the drain terminal node is used to output signals to the input ports of programmable function blocks or other logic units outside the interconnect switch block.

[0016] In a preferred embodiment, the step of determining the set of drain nodes that need to be connected within the interconnect switch block based on the layout results includes:

[0017] Obtain the input pins of each programmable logic block in the current layout result;

[0018] The input pins are integrated to determine the drain nodes located within each interconnect switch block that need to be connected to the driven end nodes.

[0019] In a preferred embodiment, if all the switch nodes traversed from the driving end node to the node to be analyzed are unoccupied, the count of the traversable path is incremented by 1, and all switch nodes traversed by the path are marked as occupied. Specifically, the step of counting the traversable path only once for each combination of driving end nodes and missing end nodes, and excluding cases where multiple paths occupy the same switch node, is described.

[0020] For multiple selectable paths from the driving node to the node to be analyzed, if any two of these paths share the same switch node, then only one of these paths is selected to be included in the count of the traversable paths.

[0021] In a preferred embodiment, after calculating the routing success rate of the interconnecting switch block, the method further includes:

[0022] The success rate of routing the interconnected switch block is compared with a preset threshold.

[0023] When the routing success rate is lower than the preset threshold, a warning message containing the location information of the interconnect switch block and the routing success rate value is output, and the layout and signal connection of the interconnect switch block area are optimized accordingly.

[0024] Return to the above steps for finding a routeable path until the routeability success rate of the interconnect switch block is higher than a preset threshold or the maximum number of layout iterations is reached.

[0025] This application also discloses a layout optimization method based on the evaluation results, including the following steps:

[0026] After performing the initial layout, the routing success rate of each interconnect switch block in the FPGA is calculated using the method described above;

[0027] Check whether the routing success rate of all interconnected switch blocks in the FPGA is higher than the preset routing success rate threshold;

[0028] If there is an interconnect switch block with a routing success rate lower than the routing success rate threshold, then a layout adjustment area centered on the interconnect switch block is determined. While keeping the layout of other areas unchanged, the logic units in the layout adjustment area are rearranged until the routing success rate of the interconnect switch block is increased to above the routing success rate threshold or the current number of layout adjustments reaches a preset upper limit.

[0029] Determine whether there are still interconnect switch blocks in the FPGA with a routing success rate lower than the routing success rate threshold and whether the total number of layout adjustments has not reached the preset upper limit. If yes, return to execute the check step; if no, determine the final layout result and enter the routing process.

[0030] The final layout result is used to perform the routing operation.

[0031] In a preferred embodiment, the step of calculating the routing success rate of each interconnect switch block in the FPGA using the method described above after performing the initial layout includes:

[0032] Obtain information on the drive end nodes and drain end nodes that need to be connected within each interconnected switch block in the initial layout;

[0033] Call the method described above to calculate the routing success rate of each interconnect switch block in the current layout.

[0034] In a preferred embodiment, in the step of checking whether the routing success rate of all interconnect switch blocks in the FPGA is higher than a preset routing success rate threshold, the routing success rate threshold is determined according to the specific model and design requirements of the FPGA.

[0035] In a preferred embodiment, when the layout iteration reaches the maximum number of iterations or the routing success rate of all interconnected switch blocks is higher than the routing success rate threshold, the final layout result is determined and the routing process begins.

[0036] This application provides a method for evaluating the success rate of interconnect switch blocks in the FPGA placement and routing process, as well as a placement optimization method based on this evaluation method. By evaluating the success rate of interconnect switch blocks before routing and guiding placement optimization, the technical problems of high routing difficulty, long time consumption, and even inability to complete routing in the prior art are effectively solved.

[0037] Specifically, this application analyzes the connection relationships between the drive-end nodes and drain-end nodes within the interconnect switch block, and, combined with the current layout results, uses the ratio of the number of traversable paths to the total number of drive-end nodes to quantitatively evaluate the routing success rate of the interconnect switch block. This evaluation method considers the internal structural characteristics of the interconnect switch block and the actual layout requirements, and can accurately reflect the resource utilization and wiring difficulty of the interconnect switch block under the current layout.

[0038] Building upon this, this application proposes a layout optimization method based on the success rate of interconnect switch blocks. This method assesses and monitors the success rate of each interconnect switch block in real time, promptly identifying areas with low success rates and making targeted layout adjustments. This layout optimization strategy, guided by the success rate of interconnect switch blocks, can anticipate and eliminate potential routing bottlenecks before routing, significantly reducing routing complexity.

[0039] The implementation of the method in this application can bring the following technical effects: First, by identifying and optimizing interconnect switches with low routing success rates early, congestion during the routing process is reduced, significantly improving the routing success rate; Second, by reducing the number of routing iterations and avoiding unnecessary routing attempts, routing time is greatly reduced, improving the overall efficiency of the FPGA design process; Finally, the method in this application improves the routing success rate by optimizing the layout, avoiding the inefficient approach of repeatedly attempting routing in traditional methods, and reducing the consumption of computing resources.

[0040] Furthermore, the method presented in this application exhibits strong adaptability and scalability. By adjusting the routing rate threshold and placement adjustment strategy, this method can adapt to the needs of FPGA designs of varying sizes and complexities. Simultaneously, this method also provides a foundation for the subsequent development of more complex placement optimization algorithms, possessing significant theoretical and practical value.

[0041] In summary, the method provided in this application can effectively improve the quality and efficiency of the place-and-route stage in the FPGA design flow, demonstrating significant technical benefits and practical value. This innovative place-and-route method is of great importance for improving the performance and reliability of FPGA design tools.

[0042] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0043] Figure 1 shows a typical internal wiring diagram of an RSB.

[0044] Figure 2 shows a flowchart of a method for evaluating the success rate of interconnect switch block routing in an FPGA placement and routing process according to a first embodiment of this application.

[0045] Figure 3 shows a flowchart of the layout optimization method based on the evaluation results according to the second embodiment of this application.

[0046] Figure 4 shows a flowchart illustrating a method for evaluating the success rate of interconnect switch block routing in an FPGA placement and routing process according to a first embodiment of this application.

[0047] Figure 5 shows a schematic flowchart of the layout optimization method based on the evaluation results according to the second embodiment of this application. Detailed Implementation

[0048] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0049] Explanation of some concepts:

[0050] FPGA (Field Programmable Gate Array): A type of programmable logic device that enables user-defined digital circuit functions by configuring internal programmable logic units and interconnect resources.

[0051] Placement: In the FPGA design flow, placement is the process of mapping synthesized logic cells to the physical resources within the device, determining the specific location of each logic cell. The goal of placement is to minimize the length and congestion of interconnects while meeting timing constraints and resource limitations.

[0052] Routing: After placement is complete, the process of establishing the actual physical circuitry using the FPGA's internal interconnect resources (such as interconnects, crossbars, etc.) based on the connection relationships between logic units. The task of routing is to complete the routing of all connections within limited routing resources and optimize the circuit's timing performance, power consumption, and other metrics.

[0053] Interconnect switch blocks: These are key modules within an FPGA used to implement programmable interconnects. They typically contain a large number of configurable switching units used to control the transmission and forwarding of signals between different lines. The topology and routing strategy of the interconnect switch blocks directly affect the routing efficiency and circuit performance of the FPGA.

[0054] Routability reflects the probability that an interconnecting switch block can successfully complete all internal connection routing under a given layout. A higher routability indicates lower routing difficulty and a greater likelihood of routing completion for the interconnecting switch block in the current layout. This application uses the ratio of the number of routable paths to the number of driver-end nodes to quantify and evaluate the routability.

[0055] Driver Pin: A node located on the input side of the interconnecting switch block, responsible for introducing external signals into the switch block and serving as the starting point for internal connection lines. The number and distribution of driver pins affect the wiring capability of the interconnecting switch block.

[0056] Sink Pin: A node located on the output side of the interconnect switch block, responsible for bringing out the signals from the internal circuitry and connecting them to the input pins of other logic units. The number and location of sink pins determine the routing requirements of the internal circuitry of the interconnect switch block.

[0057] PFB (Programmable Function Block): A programmable function block is a basic module that constitutes the internal logic unit of an FPGA. Various complex logic functions can be implemented by programming and combining PFBs. PFBs typically include programmable elements such as lookup tables (LUTs), flip-flops (FFs), and multipliers.

[0058] EDA (Electronic Design Automation): Electronic design automation is a technology that uses computer software tools to automate various stages of electronic circuit design (such as design input, synthesis, simulation, placement and routing). EDA tools greatly improve the efficiency and reliability of modern electronic system design.

[0059] The following is a brief summary of some of the innovative aspects of this application:

[0060] To address the technical problems of high difficulty and low efficiency in RSB routing in FPGA design, the inventors of this application, after in-depth research, have proposed an innovative solution. The core idea of ​​this solution is to introduce an RSB routing success rate evaluation mechanism into the FPGA placement and routing process, and use the evaluation results (evaluating the usage of local interconnect resources) to guide placement optimization, thereby reducing the difficulty of RSB routing from the source.

[0061] The overall technical solution of this application can be divided into three main stages: First, in the layout stage, the resource usage and routing success rate of each RSB are evaluated based on the current layout results and the connection structure characteristics of the RSBs. This evaluation process comprehensively considers the number of sink ports that the RSB needs to connect in the layout results, as well as the number of available paths from the driver to the sink within the RSB, accurately reflecting the routing difficulty of the RSB. Second, the routing success rate of the RSB is used as a key indicator to measure the layout quality. By setting a reasonable routing success rate threshold, RSBs with low routing success rates and high routing difficulty are identified in a timely manner. Finally, the location information of RSBs with substandard routing success rates is fed back to the layout tool, guiding it to focus on optimizing the cell placement in these areas in subsequent layout iterations, thereby improving the overall routing success rate. Through multiple rounds of layout iteration optimization, a layout scheme with good routing performance can be obtained, creating favorable conditions for subsequent routing.

[0062] This application offers significant advantages in terms of technical effectiveness: by introducing an RSB routing success rate pre-evaluation mechanism during the placement phase, potential routing difficulties can be identified in advance, effectively reducing uncertainty during the routing stage. Simultaneously, driving placement optimization with the RSB routing success rate metric minimizes connection conflicts and congestion within RSBs, fundamentally reducing routing difficulty. This optimization mechanism significantly improves the convergence speed and success rate of the routing process, effectively shortening routing time and accelerating design progress. The effectiveness is particularly pronounced for large-scale FPGA designs with dense RSB connections, significantly improving design efficiency and reducing design iteration costs.

[0063] From the perspective of technological innovation, this application provides a novel approach to solving the RSB routing challenge, enriching and developing FPGA placement and routing technology. This solution establishes a linkage mechanism between the placement and routing stages, achieving collaborative optimization of the placement and routing process. It not only addresses the pain point of difficult RSB routing but also achieves significant technical results in improving routing quality and efficiency, and shortening the design cycle, thus having important practical significance for promoting the advancement of FPGA design technology.

[0064] Traditional FPGA routing algorithms (such as the PathFinder algorithm) typically employ an iterative "rip-up and reroute" approach to resolve congestion. However, in modern large-scale FPGAs, with millions of interconnect resources, this trial-and-error iteration consumes enormous amounts of memory and CPU time. If the RSB's topology is fundamentally incompatible with the current layout, traditional forced iterative routing can lead to infinite loops or ineffective computations, severely degrading the efficiency of EDA software.

[0065] This application achieves early "pruning" of the ineffective layout search space by performing a rapid graph-based pre-evaluation of the RSB before routing. This is not merely a statistical analysis, but a technical means to optimize the computer computation process. Experiments show that using this method significantly reduces the memory usage of EDA tools during the placement and routing phase, and significantly reduces the overall compilation time. Therefore, this application directly improves the overall performance of the EDA computing system by improving the data processing flow.

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0067] First, let's explain Figure 1. Figure 1 shows a typical internal wiring diagram of an RSB. In an RSB, the switching node used to receive external signals is called the Driver, and the switching node used to output signals to external logic modules is called the Sink (these external logic modules are usually the input ports of the PFB or other logic units). The signal transmission path from the Driver to the Sink typically passes through multiple internal switching nodes. In a specific FPGA chip, the number of available switching nodes in the RSB is fixed. By selectively activating different switching nodes, the connection between the Driver and the Sink can be achieved. It is important to note that each switching node can only be used once by a single connected path.

[0068] After the design files are read in and synthesized into internal logic cells of the FPGA chip, the placement process begins. At this stage, dedicated EDA software needs to assign each logic cell to a suitable physical location, such as placing it within the physical cell locations of the PFB (Power Feeder). This placement process determines which sink nodes are needed within each RSB (Resource Buffer Block) to connect to the logic cells of the PFB.

[0069] Once the routing process begins, dedicated EDA software constructs signal transmission paths using multiple programmable switches (this process typically spans multiple RSBs). Especially when processing RSBs where signals ultimately enter logic units, the EDA software needs to attempt to establish driver-to-sink connections within that RSB. If the number of sinks requiring connections is large, and the available driver-to-sink connection paths are relatively few, the internal routing difficulty of that RSB increases significantly, leading to routing convergence difficulties.

[0070] Based on the above considerations, this method proposes a scheme to evaluate the routing success rate of RSBs during the placement and routing process. This scheme analyzes the required connectivity of sinks within RSBs in the placement result, combined with the inherent connection characteristics of RSBs, to evaluate the routing success rate of RSBs under a specific placement result. This evaluation result can be used to guide iterative adjustments in the placement process, thereby reducing the routing difficulty of RSBs and accelerating routing convergence.

[0071] The first embodiment of this application relates to a method for evaluating the success rate of interconnect switch blocks in an FPGA placement and routing process, the process of which is shown in Figures 2 and 4. The method includes the following steps:

[0072] S100: Analyze the interconnection switch block in the FPGA, record the set of drain nodes that each driver node can connect to and the switch nodes that need to be passed from the driver node to the drain node, and count the total number of driver nodes in the interconnection switch block.

[0073] S200: Based on the layout results, count the set of drain nodes that need to be connected within the interconnection switch block.

[0074] S300: Select a drain node from the set of drain nodes to be connected as the node to be analyzed, find a driver node that can be routed to the node to be analyzed, and check whether the switch node that needs to be passed from the driver node to the node to be analyzed has been occupied.

[0075] S400: If all the switch nodes that need to be passed from the driving end node to the node to be analyzed are not occupied, then the count of the traversable path is incremented by 1, and all the switch nodes passed through by the path are marked as occupied; wherein, for each combination of driving end node and leaking end node, the traversable path is counted only once, and the case of multiple paths occupying the same switch node is excluded.

[0076] S500: Determine whether all driver nodes and the missing nodes that need to be connected have been traversed. If yes, calculate the routing success rate of the interconnection switch block. The routing success rate is equal to the minimum of the routing path count and the total number of driver nodes, divided by the total number of driver nodes and multiplied by 100. If no, return to the above steps of finding routing paths until the traversal is complete.

[0077] Optionally, for S100, the driving terminal node is used to receive external signals into the interconnect switch block, and the drain terminal node is used to output the signals to the input ports of programmable function blocks or other logic units outside the interconnect switch block.

[0078] Optionally, for S200, the step of calculating the set of drain nodes to be connected within the statistical interconnection switch block includes:

[0079] Obtain the input pins of each programmable logic block in the current layout result;

[0080] The input pins are integrated to determine the drain nodes located within each interconnect switch block that need to be connected to the driven end nodes.

[0081] Optionally, for S400, for multiple selectable paths from the driving end node to the node to be analyzed, if any two of these paths share the same switch node, then only one of these paths is selected to be included in the count of the traversable paths.

[0082] Optionally, for S500, after calculating the routing success rate of the interconnecting switch block, the following is also included:

[0083] The success rate of routing the interconnected switch block is compared with a preset threshold.

[0084] When the routing success rate is lower than the preset threshold, a warning message containing the location information of the interconnect switch block and the routing success rate value is output, and the layout and signal connection of the interconnect switch block area are optimized accordingly.

[0085] Return to the above steps for finding a routeable path until the routeability success rate of the interconnect switch block is higher than a preset threshold or the maximum number of layout iterations is reached.

[0086] Specifically, the purpose of S100 is to comprehensively analyze the internal connection structure characteristics of the RSB, providing a basis for subsequent routing success rate assessment and optimization. Through in-depth analysis of the RSB's internal topology, the following key information can be obtained: 1) Which drain nodes each driver node can connect to. This determines the routing capability and flexibility of each driver. 2) The number of switching nodes required to reach the target drain from a specific driver. The number and distribution of switching nodes affect the routing difficulty. 3) The total number of driver nodes within the RSB. This total number is a key parameter when evaluating routing success rate.

[0087] By collecting this information, RSBs can be characterized and quantified from the perspective of local resource usage. This analysis method, which starts from the internal structure of RSBs, can accurately assess the resource utilization of RSBs and potential routing difficulties under the current layout. Compared with traditional overall routing difficulty assessment methods, this localized analysis can more accurately predict routing bottlenecks, providing a reliable basis for subsequent targeted layout optimization.

[0088] Furthermore, this step lays the foundation for subsequent calculations of RSB routing success rate. By statistically analyzing the total number of drivers as a key indicator, combined with the number of routeable paths calculated in subsequent steps, the RSB routing success rate can be quantitatively assessed. This makes it possible to identify RSBs with low routing success rates before routing, helping to eliminate potential routing bottlenecks during the placement phase.

[0089] In summary, step S100 analyzes the internal connection characteristics of RSBs to deeply assess the utilization of local interconnect resources, which is crucial for accurately predicting RSB routing difficulty. The information obtained in this step will be fully utilized in subsequent steps to guide layout optimization, improve routing success rate, and reduce routing time.

[0090] The purpose of S200 is to determine the actual number and distribution of drain nodes that need to be connected within each RSB in the current layout. This information directly reflects the routing requirements and pressure of the RSB. Specifically, the calculation of the drain node set is mainly achieved through the following two sub-steps: 1) Obtain the input pin distribution of each Programmable Logic Block (PLB) in the current layout. A PLB is a logic unit inside an FPGA, and a PLB usually contains multiple Programmable Function Blocks (PFBs). The input pins of the PLB need to be connected through RSBs. 2) Integrate the input pins of the PLBs to determine the set of drain nodes that need to be connected within each RSB. Typically, one RSB is responsible for supporting the interconnection resources of the corresponding PLB.

[0091] These two sub-steps yield a set of drained nodes within each RSB that is closely related to the layout result. The size of this set directly determines the routing load of the RSB. The more drained nodes there are, the greater the routing requirements within the RSB, and the more difficult the routing will be.

[0092] The innovation of this step lies in linking a key factor affecting cabling difficulty—the number of leaky nodes—to the specific layout scheme. Traditional cabling difficulty assessment methods typically only focus on the overall utilization of interconnect resources, ignoring the impact of the layout scheme. However, the method in this application fully considers the actual connection requirements of each RSB under the current layout, making the difficulty assessment more closely reflect reality.

[0093] Furthermore, this step provides another crucial parameter for subsequent routing success rate calculations: the number of leaky nodes that need to be connected. In step S400, the statistics of traversable paths are based on this set of leaky nodes. Only by fully considering the leaky node information can the routing success rate of RSBs be accurately assessed.

[0094] In summary, step S200 accurately characterizes the routing requirements of each RSB by analyzing the layout results, making the assessment of routing difficulty more precise and reliable. This is of great significance for identifying routing bottlenecks, optimizing resource allocation, and improving routing success rate during the layout phase. Simultaneously, it embodies a core idea of ​​this application's method: closely integrating the usage of local interconnect resources with the overall layout scheme to achieve accurate prediction and optimization of routing difficulty.

[0095] S300 is one of the core steps in evaluating RSB routing availability. It analyzes the internal cabling resource occupancy of the RSB to determine whether a specific drain node can be successfully connected under current conditions. This process can be divided into three main sub-steps: 1) Select a node from the drain set obtained in step S200 as the current analysis object. This node represents a specific cabling requirement. 2) Find the driver node that can be routed to this drain node. This process is essentially finding potential cabling paths. Based on the information collected in step S100, we know which drains each driver can connect to. 3) Check if there are any occupied switch nodes on the potential path from the driver to the drain. If a switch node is already occupied by another connection, then the current path is unavailable. A path is only routeable when all nodes on it are idle.

[0096] It should be noted that the purpose of this step is to determine whether a specific driver-to-drain connection is feasible under the current wiring conditions. It comprehensively considers the internal topology of the RSB and the current resource usage, and can dynamically reflect the possibility of routing.

[0097] This method of analyzing the routing status of each leaky node individually offers higher accuracy and reliability compared to assessing the routing difficulty of the entire RSB all at once. It considers the dynamic changes in cabling requirements and resource consumption, making the assessment results closer to the actual cabling process. By accumulating the analysis results for each leaky node, the routing success rate of the entire RSB can be obtained, thus accurately predicting the cabling difficulty.

[0098] Furthermore, this step also reflects a key idea of ​​this application: assessing the overall cabling difficulty through local resource occupancy. Compared with traditional assessment methods based on indicators such as overall cable length and congestion, this localized analysis method is more intuitive and reliable, enabling the earlier detection of local cabling bottlenecks and providing more targeted guidance for layout optimization.

[0099] In summary, the S300 step is crucial for RSB routing success rate assessment. By analyzing the routing status of specific leaky nodes, it accurately determines the utilization efficiency of local interconnect resources. This refined analysis makes the prediction of routing difficulty more accurate, providing strong support for eliminating potential bottlenecks during the placement phase. Simultaneously, this step also demonstrates the core idea of ​​this application: using local routing analysis to guide placement optimization, ultimately achieving the goal of improving routing success rate and reducing routing difficulty.

[0100] The purpose of step S500 is to determine the final routing success rate of the RSB. This process can be divided into two main parts: 1) Determining whether the traversal analysis of all drivers and drains has been completed. Only after each driver and each drain that needs to be connected has been analyzed in steps S300 and S400 can an accurate routing success rate be obtained. If the traversal is not yet complete, it is necessary to return to step S300, select the next drain node to be analyzed, and continue the analysis. 2) If the traversal is complete, the routing success rate of the RSB is calculated using the previous analysis results. The formula for this success rate is: Routing success rate = min(Number of routing paths, Total number of driver nodes) / Total number of driver nodes * 100% Where the number of routing paths comes from the statistical results of step S400, and the total number of driver nodes comes from the statistical results of step S100. The reason for choosing the minimum value between the number of routing paths and the total number of drivers in the calculation is to ensure the reasonableness of the success rate. In actual cabling, the number of routing paths cannot exceed the number of drivers. Therefore, if the number of traversable paths obtained from the statistics is greater than the total number of driver terminals, in reality, only a maximum of the total number of driver terminals can be connected.

[0101] It should be noted that the S500 step is a necessary supplement and application to the preceding analysis. It completes the final calculation of the routing success rate, providing a direct basis for quantitatively assessing the routing difficulty of RSBs. By judging the completion status of the traversal, the thoroughness of the analysis is ensured; by reasonably designing the routing success rate calculation formula, the accuracy of the evaluation results is ensured.

[0102] S500 provides a quantitative metric to evaluate the routing performance of RSBs. Traditional routing methods often lack consideration for the efficiency of local resource utilization and are difficult to accurately predict the routing difficulty before routing. However, the routing success rate metric of this application fully incorporates the analysis results of the previous steps, comprehensively considers the internal connection characteristics of RSBs, resource consumption, and actual routing requirements, and can accurately reflect the routing capability of RSBs under the current layout.

[0103] Furthermore, the S500 provides clear direction for subsequent layout optimization. By calculating the routing success rate of each RSB, weak points in the layout—namely, RSBs with low routing success rates—can be identified. In subsequent optimization, the cell layout around these RSBs can be adjusted in a targeted manner to improve their routing success rates. Because the optimization focuses on critical low-route-success-rate areas, the overall routing success probability can be significantly improved with relatively small layout adjustments.

[0104] In summary, S500 intuitively quantifies the routing performance of RSBs by calculating the routing success rate, making the assessment of routing difficulty more accurate and reliable. It not only provides an important basis for layout optimization but also offers reliable predictions for the final routing results. The completion of this step signifies the establishment of the core evaluation metrics of this application's method, laying a solid foundation for subsequent layout optimization and routing operations. It reflects a key value of this application: driving optimization through fine-grained resource assessment in the early stages of layout and routing, thereby maximizing routing efficiency and reducing design costs.

[0105] After step S500, if the success rate of RSB deployment is not ideal, this application also provides an iterative optimization method: compare the deployment rate of RSB with a preset threshold. If the threshold is not reached, output a warning message containing the RSB location and deployment rate value, and perform targeted optimization of the layout and connection of the area around the RSB; then return to step S300 and re-execute the subsequent analysis until the deployment rate of RSB meets the requirements or the upper limit of the number of layout iterations is reached.

[0106] This iterative optimization mechanism further enhances the adaptability and practicality of this application. By setting a routing success rate threshold, a clear optimization goal is established during the placement phase. The placement tool can refer to this goal to focus on adjusting bottleneck areas. Simultaneously, the optimization process is gradual and iterative; each round of optimization is based on the evaluation results of the previous round, continuously approaching a better solution. Even when the maximum number of placement iterations is reached, the solution with the highest routing success rate from historical solutions can be selected as the final solution. This optimization strategy improves routing success rate while maintaining optimization efficiency, demonstrating significant engineering practical value.

[0107] In summary, the RSB routing success rate evaluation method and the layout optimization method based on the evaluation results provided in this embodiment effectively solve the problems of routing difficulty prediction and optimization from the perspectives of fine-grained analysis and dynamic optimization. By introducing quantifiable and computable routing success rate indicators in the placement stage and establishing a feedback optimization mechanism between placement and routing, the entire routing process becomes more intelligent and efficient, and the routing results are more predictable and controllable. This is of great significance for improving FPGA design efficiency and reducing design costs.

[0108] Furthermore, Figures 3 and 5 illustrate a layout optimization method based on the evaluation results according to a second embodiment of this application, comprising the following steps:

[0109] S10: After performing the initial layout, the routing success rate of each interconnect switch block in the FPGA is calculated using the method described in claim 1, wherein the position of each interconnect switch block is represented by row coordinates and column coordinates (c, r), and the corresponding routing success rate is denoted as R(c, r).

[0110] S20: Check whether the routing success rate of all interconnected switch blocks in the FPGA is higher than the preset routing success rate threshold.

[0111] S30: If there is an interconnect switch block with a routing success rate lower than the routing success rate threshold, then determine the layout adjustment area centered on the interconnect switch block. While keeping the layout of other areas unchanged, rearrange the logic units in the layout adjustment area until the routing success rate of the interconnect switch block increases to above the routing success rate threshold or the current layout adjustment number reaches the preset upper limit.

[0112] S40: Determine whether there are still interconnect switch blocks in the FPGA with a routing success rate lower than the routing rate threshold and whether the total number of layout adjustments has not reached the preset upper limit. If yes, return to execute the inspection step; if no, determine the final layout result and enter the routing process.

[0113] S50: Perform routing operations using the final layout result.

[0114] Optionally, for S10, the step of calculating the routing success rate of each interconnect switch block after performing the initial layout includes:

[0115] Obtain information on the drive end nodes and drain end nodes that need to be connected within each interconnected switch block in the initial layout;

[0116] Using the method described in claim 1, calculate the routing success rate of each interconnect switch block in the current layout.

[0117] Optionally, for S20, the routing rate threshold is determined based on the specific FPGA model and design requirements.

[0118] Optionally, for S40-S50, when the layout iteration reaches the maximum number or the routing success rate of all interconnected switch blocks is higher than the routing success rate threshold, the final layout result is determined and the routing process begins.

[0119] The "evaluation" and "layout optimization" described in this application are not simply numerical calculations; their ultimate goal is to generate a bitstream file or configuration data for configuring the physical FPGA chip based on the evaluation or layout optimization results. Specifically, after the final placement and routing are completed according to the evaluation results of this method, the EDA system converts the final circuit connections into binary configuration data. This configuration data is downloaded into the FPGA chip's configuration memory (SRAM), thereby physically controlling the on / off switching of the transistors inside the RSB, transforming the FPGA chip into a hardware circuit with specific functions. Therefore, this method is an indispensable part of the FPGA physical implementation flow, directly determining whether the generated bitstream file is usable and whether the chip can function properly.

[0120] The above embodiments have the following technical innovations and effects:

[0121] The above embodiments propose several innovative solutions for FPGA placement and routing process optimization. The primary innovation is a novel RSB (Remotely Accessible Bundle) routing capability evaluation method. This method not only comprehensively considers the drain information within the RSB in the placement result but also deeply analyzes the RSB's own characteristics and potential routing paths, quantifying the RSB's routing capability. This innovative use of RSB routing capability as an evaluation index for placement optimization provides a quantifiable basis for placement optimization.

[0122] The second innovation lies in the establishment of an effective layout optimization feedback mechanism. The above-described embodiment can assess the routing difficulty of RSBs before cabling and adjust the layout strategy in a timely manner based on the RSB routing success rate, especially focusing on optimizing areas with low RSB success rates. This method achieves coordinated optimization between the layout and cabling stages, breaking the traditional separation between layout and cabling. Simultaneously, the above-described embodiment also proposes a layout optimization strategy based on local resource congestion. By assessing the resource usage in local areas, it finds the optimal layout scheme for resource utilization, effectively balancing the cabling load in local areas.

[0123] In terms of technical effectiveness, the above embodiments significantly improve the routing success rate. By accurately assessing the routing difficulty of RSBs, designers can anticipate and avoid routing bottlenecks in advance, effectively reducing the difficulty of internal routing within RSBs and minimizing routing congestion. Simultaneously, the above embodiments significantly improve design efficiency, reduce the number of routing iterations, accelerate routing convergence, significantly save computational resources, and effectively reduce design time costs.

[0124] Furthermore, the above embodiments significantly enhance design reliability. Optimization based on quantitative metrics provides predictable routing results, effectively avoiding routing failure risks and improving the first-pass success rate of the design. Overall, the above embodiments, by establishing an RSB routing success rate evaluation mechanism, achieve proactive optimization of the placement and routing process, thereby comprehensively improving the efficiency, reliability, and success rate of FPGA design.

[0125] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0126] As shown in Figure 2, this example includes the following steps:

[0127] First, the RSB is analyzed, recording the set of sinks that each available driver can connect to and the switch nodes required for that connection. The total number of all available drivers is counted, denoted as num_total_drivers. Simultaneously, based on the layout results, the sink nodes that need to be connected within the RSB are counted, forming the Need_routed_sinks set.

[0128] Next, select a need_routed_sink from the Need_routed_sinks set, find a Driver that can connect to the need_routed_sink, and check the path_nodes that need to be traversed from the Driver to the need_routed_sink. When all path_nodes are not occupied, increment the path count num_path by 1 and mark all path_nodes used by that path as occupied.

[0129] Next, check if all potential Drivers and Need_routed_sinks have been traversed. If the traversal is complete, perform the final calculation of RSB deployability; if not, continue the above process until all Drivers and Need_routed_sinks have been traversed.

[0130] Finally, the deployment success rate R of RSB is calculated using the following formula:

[0131] Here, `num_path` represents the total number of valid paths that can connect to all relevant sinks, obtained through the above process. This value has two important characteristics: first, it excludes cases where multiple paths occupy the same switch node; second, it only counts once for each potential driver and sink node combination. `num_total_drivers` represents the total number of available drivers in this RSB. Generally, the larger `num_path` is, the more paths the RSB has that can be used to connect to the target sink, and the lower the difficulty of subsequent routing. Therefore, we can use this value to quantitatively evaluate the routing success rate of the RSB in subsequent routing. Using this evaluation result to assist in placement iteration can effectively improve the routing success rate of the RSB and accelerate the routing convergence speed.

[0132] It should be noted that the RSB routing success rate evaluation method proposed in the above examples can effectively assist the placement iteration process, improve the efficiency and reliability of FPGA design, and reduce routing difficulty and time costs. Figure 3 shows a specific implementation method for applying the RSB routing success rate evaluation results to the placement and routing process.

[0133] The specific steps are as follows:

[0134] After the initial layout is completed, the deployability R(c, r) of each RSB in the FPGA is calculated. Here, c and r represent the row and column coordinates of the RSB, respectively, and R(c, r) represents the deployability of the RSB located in the c-th row and r-th column.

[0135] The deployability of all RSBs is compared with a preset threshold. This threshold can be flexibly adjusted according to the specific chip model and design requirements.

[0136] For RSB regions with a deployability rate below the threshold, layout optimization is required: re-execute the layout iteration; attempt to increase the deployability rate of the corresponding RSB; until the deployability rate of all RSBs reaches a high level, or the number of layout iterations reaches the preset upper limit.

[0137] After completing the layout optimization, the wiring process begins.

[0138] It should be noted that this is just one application example of RSB routing success rate evaluation results. In practical applications, the RSB routing success rate metric can be monitored at various stages of the placement and routing process, serving as an important reference for auxiliary optimization.

[0139] It should be noted that in this patent application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0140] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A method for evaluating the success rate of routing a switch block in an FPGA place and route flow, comprising: Includes the following steps: ​ Analyze the interconnection switch blocks in the FPGA, record the set of drain nodes that each driver node can connect to and the switch nodes that need to be passed from the driver node to the drain node, and count the total number of driver nodes in the interconnection switch blocks. Based on the layout results, the set of drain nodes that need to be connected within the interconnection switch block is counted. Select one drain node from the set of drain nodes that need to be connected as the node to be analyzed, find the driving node that can be routed to the node to be analyzed, and check whether the switch node that needs to be passed from the driving node to the node to be analyzed has been occupied. If all the switch nodes that must be traversed from the driving end node to the node to be analyzed are not occupied, then the count of the traversable path is incremented by 1, and all switch nodes traversed by the path are marked as occupied; wherein, for each combination of driving end node and leaking end node, the traversable path is counted only once, and the case of multiple paths occupying the same switch node is excluded. Determine whether all driver nodes and the missing nodes that need to be connected have been traversed. If yes, calculate the routing success rate of the interconnection switch block. The routing success rate is equal to the minimum of the routing path count and the total number of driver nodes, divided by the total number of driver nodes and multiplied by 100. If no, return to the above steps of finding routing paths until the traversal is complete.

2. The method of claim 1, wherein, The driving terminal node is used to receive external signals into the interconnect switch block, and the drain terminal node is used to output signals to the input ports of programmable function blocks or other logic units outside the interconnect switch block.

3. The method of claim 1, wherein, Based on the layout results, the step of calculating the set of drain nodes that need to be connected within the interconnection switch block includes: Obtain the input pins of each programmable logic block in the current layout result; The input pins are integrated to determine the drain nodes located within each interconnect switch block that need to be connected to the driven end nodes.

4. The method of claim 1, wherein, If all the switch nodes traversed from the driving node to the node to be analyzed are unoccupied, the count of the traversable path is incremented by 1, and all switch nodes traversed by the path are marked as occupied. Specifically, for each combination of driving and leaky nodes, the traversable path is counted only once, excluding cases where multiple paths occupy the same switch node. For multiple selectable paths from the driving node to the node to be analyzed, if any two of these paths share the same switch node, then only one of these paths is selected to be included in the count of the traversable paths.

5. The method of claim 1, wherein, After calculating the successful deployment rate of the interconnecting switch block, the following steps are also included: The success rate of routing the interconnected switch block is compared with a preset threshold. When the routing success rate is lower than the preset threshold, a warning message containing the location information of the interconnect switch block and the routing success rate value is output, and the layout and signal connection of the interconnect switch block area are optimized accordingly. Return to the above steps for finding a routeable path until the routeability success rate of the interconnect switch block is higher than a preset threshold or the maximum number of layout iterations is reached.

6. A layout optimization method based on evaluation results, characterized by, Includes the following steps: After performing the initial layout, the routing success rate of each interconnect switch block in the FPGA is calculated using the method described in claim 1; Check whether the routing success rate of all interconnected switch blocks in the FPGA is higher than the preset routing success rate threshold; If there is an interconnect switch block with a routing success rate lower than the routing success rate threshold, then a layout adjustment area centered on the interconnect switch block is determined. While keeping the layout of other areas unchanged, the logic units in the layout adjustment area are rearranged until the routing success rate of the interconnect switch block is increased to above the routing success rate threshold or the current number of layout adjustments reaches a preset upper limit. Determine whether there are still interconnect switch blocks in the FPGA with a routing success rate lower than the routing success rate threshold and whether the total number of layout adjustments has not reached the preset upper limit. If yes, return to execute the check step; if no, determine the final layout result and enter the routing process. The final layout result is used to perform the routing operation.

7. The method of claim 6, wherein, After performing the initial layout, the step of calculating the routing success rate of each interconnect switch block in the FPGA using the method of claim 1 includes: Obtain information on the drive end nodes and drain end nodes that need to be connected within each interconnected switch block in the initial layout; Using the method described in claim 1, calculate the routing success rate of each interconnect switch block in the current layout.

8. The method of claim 6, wherein, In the step of checking whether the routing success rate of all interconnected switch blocks in the FPGA is higher than the preset routing success rate threshold, the routing success rate threshold is determined according to the specific model and design requirements of the FPGA.

9. The method of claim 6, wherein, When the layout iteration reaches the maximum number of iterations or the routing success rate of all interconnected switch blocks is higher than the routing success rate threshold, the final layout result is determined and the routing process begins.

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