High electron mobility transistor, chip and electronic device

Abstract

The present application relates to the technical field of semiconductors, in particular to a high electron mobility transistor, a chip and an electronic device. The transistor comprises a semiconductor layer and a wiring layer; the semiconductor layer comprises a first active region and a first passive region; the semiconductor layer comprises a plurality of gates; at least some of the plurality of gates are not connected to each other in the semiconductor layer; the semiconductor layer further comprises a dielectric layer, the dielectric layer being at least disposed in the first passive region; the wiring layer comprises a gate metal line, the gate metal line comprises a first portion and a second portion connected to each other, the first portion is stacked over the first passive region in the thickness direction, the first portion and the first passive region are separated by the dielectric layer, and the second portion is stacked over the first active region; each gate is electrically connected to the second portion of the gate metal line. In this way, there is no need to provide a gate bus within the semiconductor layer, such that surface leakage caused by gate surface damage is avoided, thereby improving the stability and reliability of HEMT devices.

Description

High electron mobility transistors, chips and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510185450.0, filed on February 18, 2025, entitled "High Electron Mobility Transistor, Chip and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a high electron mobility transistor, chip, and electronic device. Background Technology

[0003] High-electron-mobility transistors (HEMTs) are power semiconductor devices that are widely used in power electronics, microwave radio frequency, and optoelectronic devices due to their advantages such as high breakdown electric field, high channel electron concentration, high electron mobility, and high temperature stability.

[0004] The structure of a HEMT device mainly consists of a device structure layer and a semiconductor layer disposed on the device structure layer. The device structure layer typically forms a heterojunction structure such as AlGaN / GaN. The semiconductor layer contains the gate, source, and drain. During operation, the heterojunction structure generates a certain concentration of two-dimensional electron gas (2DEG) due to polarization effects. This 2DEG forms a channel between the drain and source, thus enabling the device to conduct. By adjusting the gate voltage, the density of the 2DEG can be controlled, thereby controlling the conductivity of the device.

[0005] There are typically multiple gates in a semiconductor layer, interconnected by a gate bus within the semiconductor layer. Currently, during the fabrication of HEMT devices, the gate bus may be damaged, leading to surface leakage and reduced reliability of the HEMT device. Summary of the Invention

[0006] This application provides a high electron mobility transistor, chip, and electronic device to reduce surface leakage caused by gate bus damage, thereby improving the reliability of HEMT devices.

[0007] In a first aspect, embodiments of this application provide a high electron mobility transistor, comprising: a semiconductor layer, the semiconductor layer including a first active region and a first passive region arranged along a first direction; the semiconductor layer including a plurality of gates extending along the first direction; wherein the plurality of gates are spaced apart along a second direction, at least a portion of the extension of each gate is located in the first active region, and at least a portion of the plurality of gates are not connected to each other in the semiconductor layer; the semiconductor layer further including a dielectric layer, the dielectric layer being at least disposed in the first passive region; the first direction and the second direction intersect, and both the first direction and the second direction are perpendicular to the thickness direction of the semiconductor layer; a wiring layer, the wiring layer including a gate metal line, the gate metal line including a connected first portion and a second portion, the first portion being stacked on the first passive region along the thickness direction, and the first portion being spaced apart from the first passive region by a dielectric layer, the second portion being stacked on the first active region, and each gate being electrically connected to the second portion of the gate metal line.

[0008] It is understandable that, since no gate bus is present in the semiconductor layer, the sidewalls of the gate bus will not be damaged during ion implantation to form the passive region. This avoids surface leakage caused by gate surface damage. Simultaneously, since the gate bus can be considered part of the gate, omitting it reduces the total gate area, thereby reducing the contact area between the gate and the active region. This reduces leakage paths, improves leakage in the bulk direction of the HEMT device, and thus enhances the stability and reliability of the HEMT device. Furthermore, supplying power to the gate via the gate metal line reduces the complexity of the gate power supply, making the gate power supply method more flexible, and lowers the resistance between the gate and the power supply line, improving power supply efficiency.

[0009] In some alternative embodiments of the first aspect, the gate includes a cap layer and a gate metal layer stacked along the thickness direction, a Schottky contact is formed between the gate metal layer and the cap layer, and a gate metal line is electrically connected to the gate metal layer.

[0010] In this embodiment, a Schottky contact is formed between the gate metal layer and the cap layer, which can improve the threshold voltage of the high electron mobility transistor, thereby enhancing the device's high voltage withstand capability and reliability. Furthermore, the connection between the gate metal line and the gate metal layer can reduce gate power supply losses.

[0011] In some alternative embodiments of the first aspect, the size of the gate along the first direction is greater than or equal to the size of the first active region along the first direction; the semiconductor layer further includes a plurality of drains extending along the first direction; wherein the plurality of drains are spaced apart along the second direction, each drain is located in the first active region, each drain is located between two adjacent gates, and the two gates located on both sides of each drain are not connected to each other in the semiconductor layer.

[0012] In this embodiment, the gates on both sides of the drain are not connected to each other in the semiconductor layer, that is, the gate metal layers in the gate are not connected to form a gate bus, thereby reducing surface leakage caused by damage to the gate bus and improving the reliability of HEMT devices.

[0013] In some optional embodiments of the first aspect, the high electron mobility transistor further includes a second passive region, and the first active region is located between the first passive region and the second passive region; the semiconductor layer further includes a plurality of sources extending along a first direction, each source being located between two adjacent gates; the two gates adjacent to the source include a first gate and a second gate, the first gate including a first end near the first passive region and a second end near the second passive region, the second gate including a first end near the first passive region and a second end near the second passive region, the first end of the first gate and the first end of the second gate being connected through a first gate connection portion, the second end of the first gate and the second end of the second gate being connected through a second gate connection portion, the first gate, the first gate connection portion, the second gate and the second gate connection portion forming a ring gate structure surrounding the source.

[0014] In this embodiment, the gates on both sides of the source are connected through the gate connection portion to form a ring gate structure surrounding the source. Since the ring gate structure has no end, it can effectively avoid the edge effect of the strip gate, reduce the device breakdown phenomenon caused by the concentration of edge electric field, and improve the reliability of the device.

[0015] In some alternative embodiments of the first aspect, each drain is located between two adjacent ring gate structures.

[0016] In this embodiment, the drain is located between two ring gate structures, which can better control the drain current, reduce its instability, and improve the reliability of the device.

[0017] In some alternative embodiments of the first aspect, the size of the gate along the first direction is greater than or equal to the size of the first active region along the first direction; the semiconductor layer further includes a plurality of sources extending along the first direction; wherein the plurality of sources are spaced apart along the second direction, each source is located in the first active region, each source is located between two adjacent gates, and the two gates located on both sides of each source are not connected to each other in the semiconductor layer.

[0018] In this embodiment, the gates on both sides of the source are not connected to each other in the semiconductor layer, that is, the gate metal layers in the gate are not connected to form a gate bus, thereby reducing surface leakage caused by damage to the gate bus and improving the reliability of HEMT devices.

[0019] In some optional embodiments of the first aspect, the high electron mobility transistor further includes a second passive region, and the first active region is located between the first passive region and the second passive region; the semiconductor layer further includes a plurality of drains extending along a first direction, each drain being located between two adjacent gates; the two gates adjacent to the drains include a first gate and a second gate, the first gate including a first end near the first passive region and a second end near the second passive region, the second gate including a first end near the first passive region and a second end near the second passive region, the first end of the first gate and the first end of the second gate being connected through a first gate connection portion, the second end of the first gate and the second end of the second gate being connected through a second gate connection portion, the first gate, the first gate connection portion, the second gate and the second gate connection portion forming a ring gate structure surrounding the drain.

[0020] In this embodiment, the gates on both sides of the drain are connected through the gate connection portion to form a ring gate structure surrounding the drain. Since the ring gate structure has no end, it can effectively avoid the edge effect of the strip gate, reduce the device breakdown phenomenon caused by the concentration of edge electric field, and improve the reliability of the device.

[0021] In some alternative embodiments of the first aspect, each source is located between two adjacent ring gate structures.

[0022] In this embodiment, the source is located between two ring gate structures, which can better control the source current, reduce its instability, and improve the reliability of the device.

[0023] In some alternative embodiments of the first aspect, the gate metal line is electrically connected to the first gate connection and / or the second gate connection.

[0024] In this embodiment, the first gate connection portion and / or the second gate connection portion can serve as electrical connection locations to connect with the gate metal wiring, thereby providing more electrical connection locations and improving the flexibility of the gate metal wiring.

[0025] In some alternative embodiments of the first aspect, the high electron mobility transistor further includes a second passive region, the first active region being located between the first passive region and the second passive region; the gate includes a first end near the first passive region and a second end near the second passive region, the first end of the gate extending at least to the boundary between the first active region and the first passive region, and the second end of the gate extending at least to the boundary between the first active region and the second passive region.

[0026] In this embodiment, the first end of the gate extends at least to the boundary between the first active region and the first passive region, and the second end of the gate extends at least to the boundary between the first active region and the second passive region, thereby improving gate control capability and enhancing the reliability of HEMT devices.

[0027] In some alternative embodiments of the first aspect, a first end of the gate extends into a first passive region; and / or, a second end of the gate extends into a second passive region.

[0028] In this embodiment, the first end of the gate extends to the first passive region; and / or the second end of the gate extends to the second passive region, which can ensure that the length of the gate is not less than the width of the active region, thereby avoiding insufficient gate length due to process errors and improving the control capability of the gate.

[0029] In some alternative embodiments of the first aspect, a first portion of the gate metal line covers a first passive region.

[0030] In this embodiment, the first part of the gate metal wiring covers the first passive region, so that the gate metal wiring can be powered by the gate in the active region on both sides of the passive region, reducing the number of gate metal wirings, improving wiring efficiency, and thus reducing the processing cost of HEMT devices.

[0031] In some alternative embodiments of the first aspect, the second portion of the gate metal line has a dimension of less than or equal to 10 μm along the first direction.

[0032] In this embodiment, the second portion of the gate metal line has a dimension of less than or equal to 10 μm along the first direction, which can ensure that the overlap area between the gate metal line and the active region is small, thereby reducing the large parasitic capacitance generated between the gate metal wiring and the semiconductor layer.

[0033] In some optional embodiments of the first aspect, a dielectric layer is disposed in a first active region and a first passive region, and a gate metal line is stacked on the dielectric layer along the thickness direction; the dielectric layer includes a via penetrating the dielectric layer along the thickness direction of the dielectric layer, and a metal lead is disposed in the via, one end of the metal lead being connected to the gate and the other end being connected to the gate metal line.

[0034] In this embodiment, the gate metal wiring is electrically connected to the gate through metal lead vias, which can improve the reliability of the wiring.

[0035] Secondly, embodiments of this application provide a chip, which includes a packaging substrate and a high electron mobility transistor provided in the first aspect, wherein the high electron mobility transistor is electrically connected to the packaging substrate.

[0036] Thirdly, embodiments of this application provide an electronic device, which includes a circuit board and a chip provided in the second aspect, the chip being electrically connected to the circuit board.

[0037] The beneficial effects that can be achieved by the second and third aspects described above can be referred to the relevant descriptions in the first aspect and various embodiments of the first aspect, and will not be repeated here. Attached Figure Description

[0038] To more clearly illustrate the technical solution of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0039] Figure 1 is a schematic diagram of an application scenario provided by an embodiment of this application;

[0040] Figure 2A is a schematic diagram of the structure of a HEMT device;

[0041] Figure 2B is a schematic diagram of the semiconductor layer structure of a HEMT device;

[0042] Figure 2C is a schematic diagram of the cross-sectional structure of AA in Figure 2B;

[0043] Figure 2D is a schematic diagram of the cross-sectional structure of BB in Figure 2B;

[0044] Figure 2E is a schematic diagram of the cross-sectional structure of CC in Figure 2B;

[0045] Figure 3A is a schematic diagram of a high electron mobility transistor provided in an embodiment of this application;

[0046] Figure 3B is a top view of a device cell provided in an embodiment of this application;

[0047] Figure 3C is a schematic diagram of the cross-sectional structure of DD in Figure 3A;

[0048] Figure 3D is a cross-sectional view of a high electron mobility transistor provided in an embodiment of this application;

[0049] Figure 3E is a cross-sectional view of another high electron mobility transistor provided in an embodiment of this application;

[0050] Figure 3F is a schematic diagram of the cross-sectional structure of BB in Figure 3A provided in an embodiment of this application;

[0051] Figure 3G is a schematic diagram of the cross-sectional structure of CC in Figure 3A provided in an embodiment of this application;

[0052] Figure 4A is a schematic diagram of another high electron mobility transistor provided in an embodiment of this application;

[0053] Figure 4B is a top view of another device cell provided in an embodiment of this application;

[0054] Figure 4C shows a schematic diagram of the cross-sectional structure of BB in Figure 4A;

[0055] Figure 5A is a schematic diagram of another high electron mobility transistor provided in an embodiment of this application;

[0056] Figure 5B is a top view of another device cell provided in an embodiment of this application;

[0057] Figure 5C is a schematic diagram of the cross-sectional structure of BB in Figure 5A;

[0058] Figure 6A is a schematic diagram of another high electron mobility transistor provided in an embodiment of this application;

[0059] Figure 6B is a top view of another device cell provided in an embodiment of this application;

[0060] Figure 6C is a schematic diagram of the cross-sectional structure of DD in Figure 6A. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0062] This application provides a high electron mobility transistor, chip, and electronic device.

[0063] The electronic devices provided in this application embodiment may include communication equipment (e.g., base stations, mobile phones, etc.), charging equipment, small household appliances that require charging (e.g., soymilk makers, robot vacuum cleaners), vehicles, drones, aerospace equipment, lidar drivers, lasers, detectors, medical devices, radar, navigation equipment, radio frequency (RF) plasma lighting equipment, RF sensing, microwave heating equipment, or display devices, etc. This application embodiment does not impose any special limitations on the specific form of the above-mentioned electronic devices.

[0064] The aforementioned electronic device includes a circuit board and a chip. The chip can be electrically connected to the circuit board.

[0065] For ease of understanding, the following uses a mobile phone as an example of an electronic device to illustrate the embodiments of this application.

[0066] Figure 1 illustrates the structure of an electronic device. Referring to Figure 1, the electronic device 100 may include a display screen 101, a mid-frame 102, and a back cover 103. The display screen 101 and the back cover 103 are located on opposite sides of the mid-frame 102, and the display screen 101, mid-frame 102, and back cover 103 can collectively form the housing 110 of the electronic device 100. The mid-frame 102 and back cover 103 can be independent structures or an integral structure. The housing 110 can form a receiving cavity 111, in which multiple components of the electronic device 100 can be housed, such as a motherboard 105, a speaker 106, a microphone 107, a motor 108, etc.

[0067] The motherboard 105 (as an example of a circuit board) contains an RF chip (as an example of a chip). The RF chip may include electronic components such as power amplifiers, filters, and RF switches. These electronic components work together to amplify, filter, and tune signals, ensuring that the signals remain of high quality during reception and transmission.

[0068] The main function of a power amplifier is to amplify the weak radio frequency signal after the baseband signal has been modulated by radio frequency, giving it sufficient power to be transmitted through the antenna. In mobile phones, the power amplifier is usually located in the transmission link to ensure that the signal can cover a longer distance while maintaining signal strength and quality.

[0069] The radio frequency (RF) chip may also include a packaging substrate, wherein electronic components such as power amplifiers, filters, and RF switches within the RF chip can be electrically connected to the packaging substrate. The packaging substrate serves to house and protect the aforementioned electronic components within the RF chip, and to enable electrical connections between the electronic components and the circuit board.

[0070] With the development of 5G technology, mobile phones need to support more frequency bands and communication modes. Power amplifiers need to have higher operating frequencies, greater bandwidth, and higher power output capabilities to meet communication requirements. In this embodiment, the power amplifier may include a HEMT device.

[0071] HEMT devices, due to their high power density and high operating frequency, can be used as power amplifiers in radio frequency (RF) modules of electronic devices. For example, GaN-based HEMT devices (GaN HEMTs) possess high electron mobility and high-frequency characteristics, enabling them to amplify low-power RF signals generated by the mobile phone baseband to sufficient power for transmission through the antenna. This ensures signal transmission distance and quality, allowing users to make calls and transmit data smoothly in various environments. In other embodiments, HEMT devices can also be used as low-noise amplifiers, bidirectional switches in battery management systems, RF switches in mobile phone RF front-end modules, and power converters in power adapters.

[0072] It is understandable that HEMT devices can play different roles in various electronic devices. For example, in wireless communication and radar systems, GaN HEMTs (i.e., multiple GaN HEMTs) can play an important role in the power amplifiers of wireless communication devices such as 5G, Wi-Fi, and Bluetooth, providing higher data transmission rates and lower power consumption. In power management devices such as high-efficiency switching power supplies, DC-DC converters, and inverters, GaN HEMTs can achieve fast switching and low losses, improving conversion efficiency. In electric vehicle charging equipment and on-board chargers, GaN HEMTs can be used in high-voltage DC-DC converters, providing high efficiency and miniaturized design. In server power supplies and cooling equipment in data centers, GaN HEMTs can be used for high-efficiency power conversion, reducing energy consumption. In lighting and LED driver equipment, GaN HEMTs can be used in high-brightness light-emitting diode (LED) drivers, providing high efficiency and long lifespan. In motor drives and frequency converters, GaN HEMTs can achieve high-performance power control and optimized energy utilization. In the aerospace field, GaN HEMTs can be used in high-power amplifiers for radar and communication systems due to their high-temperature performance and small, lightweight characteristics. In high-voltage, high-current power systems, GaN HEMTs can be used in high-voltage inverters and power quality improvement equipment.

[0073] The following describes an exemplary structure of a HEMT device with reference to the accompanying drawings. It should be noted that in the figures, the X direction (an example of the first direction) can be the length direction of the HEMT device, and the Y direction (an example of the second direction) can be the width direction of the HEMT device. In some embodiments, the Y direction can be the flow direction of the two-dimensional electron gas in the HEMT device, and the Z direction (an example of the third direction) can be the thickness direction of the HEMT device.

[0074] In this embodiment, the X and Y directions intersect, and the X and Y directions are perpendicular to the Z direction. In some embodiments, the X, Y, and Z directions can be mutually perpendicular to each other.

[0075] Figure 2A illustrates an exemplary structure of a HEMT device. Referring to Figure 2A, the HEMT device includes a semiconductor layer 20, an interconnect metal layer 30 disposed above the semiconductor layer 20, and pads (not shown) located on the top layer (the interconnect metal layer 30 facing away from the surface of the semiconductor layer 20). The pads and device cells are interconnected through the interconnect metal layer 30, forming a specific circuit structure. The interconnect metal layer 30 may include multiple layers of interconnect metal lines 301. The interconnect metal lines 301 are separated from the semiconductor layer 20, and between interconnect metal lines 301 themselves, by insulating layers 302.

[0076] Generally, based on the type of electrode connected, interconnect metal lines 301 can be classified into source interconnect metal lines, drain interconnect metal lines, and gate interconnect metal lines. In some embodiments, if the substrate of the device cell is provided with corresponding terminals, the interconnect metal line 301 may also include interconnect metal lines of the substrate. It is understood that in other embodiments, the interconnect metal line 301 may also have other types, which will not be listed here. Between interconnect metal lines 301 of the same layer and of the same type, there are generally bus (BUS) 301a and finger (finger) 301b, with potential transferred from bus 301a to finger 301b.

[0077] Figure 2B illustrates an exemplary structure of the semiconductor layer 20 of a HEMT device. Referring to Figure 2B, the semiconductor layer 20 includes a plurality of active regions 203 and a plurality of passive regions 204. The active regions 203 refer to the regions in the HEMT device that participate in electron flow and control, while the passive regions 204 refer to the regions in the HEMT device that do not directly participate in electron flow and control. The active regions 203 and passive regions 204 can be arranged along the X-direction, and the active regions 203 can also be surrounded by the passive regions 204. In some embodiments, the active regions 203 and passive regions 204 can also be spaced apart along the X-direction.

[0078] Referring to Figure 2B, the active region 203 can form multiple source electrodes 205, multiple drain electrodes 206, and multiple gate electrodes 207 extending along the first direction. The multiple source electrodes 205, multiple drain electrodes 206, and multiple gate electrodes 207 can be arranged at intervals along the Y direction. Furthermore, each source electrode 205 has a gate electrode 207 on both sides along the Y direction, and each drain electrode 206 has a gate electrode 207 on both sides along the Y direction. That is, the gate electrode 207, source electrode 205, gate electrode 207, and drain electrode 206 form a repeating unit, which is repeatedly arranged along the Y direction in the active region 203. One repeating unit can correspond to one device cell.

[0079] Figure 2C shows the cross-sectional structure of AA in Figure 2B, which can be regarded as a device cell. Referring to Figure 2C, the device cell may include a substrate 201, a device functional layer 202 stacked on the substrate 201 along the Z direction, and a source 205, a drain 206, and a gate 207 stacked on the device functional layer 202 along the Z direction.

[0080] The substrate 201 provides mechanical support for the entire device cell, ensuring the stability and reliability of the device. Optionally, the substrate 201 layer can be one of the following substrates: silicon substrate, silicon oxide substrate, silicon-on-insulator substrate, silicon carbide substrate, silicon-on-insulator substrate, sapphire substrate, etc.

[0081] Referring to Figure 2C, the device functional layer 202 includes the basic structure for implementing the functions of a HEMT device. The device functional layer 202 can be divided into an active region 203 and a passive region 204. The active region 203 may include a buffer layer, a channel layer, and a barrier layer stacked along the Z-direction. The buffer layer is formed on the substrate 201, the channel layer is formed on the buffer layer, and the barrier layer is formed on the channel layer.

[0082] Referring to Figure 2C, the source 205, drain 206, and gate 207 can be formed on the barrier layer. The source 205 and drain 206 can be made of conductive materials, such as metals like titanium, aluminum, copper, nickel, molybdenum, tungsten, silver, gold, platinum, palladium, and rhodium, or metal oxides and metal nitrides. The gate 207 can include a cap layer 207e and a gate metal layer 207f stacked along the Z-direction, with a Schottky contact formed between the gate metal layer 207f and the cap layer 207e. The cap layer 207e can be a semiconductor with a predetermined doping type, such as a P-type doped semiconductor; optionally, the cap layer 207e can be P-type GaN. The gate metal layer 207f can be made of conductive materials, such as metals like titanium, aluminum, copper, nickel, molybdenum, tungsten, silver, gold, platinum, palladium, and rhodium, or metal oxides and metal nitrides.

[0083] The buffer layer can be made of gallium nitride (GaN) and can be formed on the substrate 201 via heteroepitaxial growth. In some embodiments, the buffer layer can also be composed of multiple layers of aluminum gallium nitride (AGaN) with varying concentrations. The channel layer can be made of gallium nitride and can be formed on the buffer layer via epitaxy, thin film lift-off, or other methods. The buffer layer can serve as a transition layer between the substrate 201 and the channel layer, adapting to the lattice in the substrate 201 and the gallium nitride lattice in the channel layer. The channel layer can be made of gallium nitride and can be formed on the buffer layer via epitaxy, for example, by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or other methods. The barrier layer can be made of aluminum gallium nitride (AGaN) and can be formed on the channel layer via epitaxy. Optionally, the methods for forming the barrier layer include, but are not limited to, MOCVD, MBE, and HVPE.

[0084] The channel layer and barrier layer can form a heterojunction structure. Under the influence of polarization, a two-dimensional electron gas is generated in the heterojunction structure. That is, a high-concentration, high-mobility two-dimensional electron gas is generated at the interface between the channel layer and the barrier layer. When the gate voltage 207 is lower than the threshold voltage, the two-dimensional electron gas density decreases sufficiently to pinch off the channel current, and the device is in the off state. When the gate voltage 207 is higher than the threshold voltage, the two-dimensional electron gas density increases, and the two-dimensional electron gas forms a channel between the drain 206 and the source 205, and the device is in the on state.

[0085] The gates 207 formed therein can be connected and powered via a common gate bus 208. Referring to FIG2B, the gate bus 208 can extend along the Y direction and connect to the end of each gate 207.

[0086] Figure 2D shows the cross-sectional structure of BB in Figure 2B. Referring to Figure 2D, gate buses 208 are provided at the two opposite ends of the source 205 along the X direction. The structure of the gate bus 208 is similar to that of the gate 207. The gate bus 208 may include a semiconductor material layer 208a and a bus metal layer 208b, with a Schottky contact formed between the semiconductor material layer 208a and the bus metal layer 208b. Typically, the semiconductor material layer 208a is made of the same material as the cap layer 207e in the gate 207, and the bus metal layer 208b is made of the same material as the gate metal layer 207f in the gate 207. Therefore, the gate bus 208 can often be considered as part of the gate 207.

[0087] Figure 2E shows the cross-sectional structure of CC in Figure 2B. Referring to Figure 2E, gate buses 208 are provided at the two opposite ends of the drain 206 along the X direction.

[0088] Gate bus 208 and gate 207 are at the same potential, and gate bus 208 is arranged as close as possible to the edge of active region 203. In some cases, gate bus 208 may even slightly extend beyond the edge of active region 203 into passive region 204. However, passive region 204 is defined by ion implantation, during which the sidewalls of gate bus 208 may be damaged, causing surface leakage. Furthermore, since gate bus 208 and gate 207 are at the same potential, gate bus 208 can be considered part of gate 207, thus increasing the area of ​​gate 207 and exacerbating leakage problems in the body direction of HEMT devices.

[0089] In view of this, embodiments of this application provide a high electron mobility transistor, which may include a semiconductor layer 20. The semiconductor layer 20 includes a first active region 203a and a first passive region 204a arranged along a first direction. The semiconductor layer 20 also includes a plurality of gates 207 extending along the first direction, the plurality of gates 207 being spaced apart along a second direction. At least a portion of the extension of each gate 207 is located in the first active region 203a, and at least a portion of the gates 207 are not connected to each other in the semiconductor layer 20. A dielectric layer 209 is disposed in the first passive region 204a. The first and second directions intersect, and both the first and second directions are perpendicular to the thickness direction of the semiconductor layer 20. Unlike the HEMT device shown in Figure 2B, the semiconductor layer 20 does not have a gate bus 208. Instead, a wiring layer is stacked on the semiconductor layer 20. The wiring layer may include a gate metal line 210. The first part 210a of the gate metal line 210 is stacked on the first passive region 204a, and a dielectric layer 209 is spaced between the first part 210a and the first passive region 204a. The second part 210b of the gate metal line 210 is stacked on the first active region 203a. Each gate 207 is electrically connected to the second part 210b of the gate metal line 210, thereby reducing the possibility of the gate 207 being damaged, thus reducing the problem of surface leakage caused by damage to the surface of the gate 207. It also reduces the area of ​​the gate 207 (the gate bus 208 can also be regarded as the gate 207), thereby reducing the problem of body leakage of the HEMT device.

[0090] It is understandable that since the gate bus 208 is not provided in the semiconductor layer 20, the sidewalls of the gate bus 208 will not be damaged during ion implantation to form the passive region 204. This avoids surface leakage caused by damage to the gate 207 surface. Simultaneously, since the gate bus 208 is not provided in the semiconductor layer 20, and since it can be considered part of the gate 207, omitting the gate bus 208 effectively reduces the total area of ​​the gate 207, thereby reducing the contact area between the gate 207 and the active region 203. This reduces leakage paths, improves leakage in the body direction of the HEMT device, and thus enhances the stability and reliability of the HEMT device. Furthermore, supplying power to the gate via the gate metal line reduces the complexity of the gate power supply, making the gate power supply method more flexible, and lowers the resistance between the gate and the power supply line, improving power supply efficiency.

[0091] The high electron mobility transistors provided in the embodiments of this application will be described in detail below.

[0092] In the following description, "embodiment" or "implementation" means that a particular feature, structure, or characteristic described in connection with an implementation may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0093] Figure 3A illustrates the structure of a high electron mobility transistor (HEMT) according to one embodiment. In this embodiment, instead of providing a gate bus 208 to connect and power the gate 207 in the semiconductor layer 20, a gate metal line 210 is stacked on the semiconductor layer 20 to power the gate 207. This avoids the problem of surface leakage caused by damage to the surface of the gate 207, and also reduces the area of ​​the gate 207, thereby reducing the body leakage of the HEMT device.

[0094] Referring to Figure 3A, the high electron mobility transistor (HEMT) may include a semiconductor layer 20, which may include a second passive region 204b, a first active region 203a, and a second active region 203b spaced apart along the X direction. Specifically, the first active region 203a is located between the first passive region 204a and the second passive region 204b, and the first passive region 204a is located between the first active region 203a and the second active region 203b. It is understood that Figure 3A shows only a portion of the HEMT device; in some embodiments, the semiconductor layer 20 may include more active regions 203 and passive regions 204.

[0095] Referring to Figure 3A, the semiconductor layer 20 includes a plurality of gates 207, a plurality of sources 205, and a plurality of drains 206 extending along the X direction. It can be understood that the number of gates 207, sources 205, and drains 206 can be set according to the number of device cells. The plurality of gates 207, sources 205, and drains 206 can all be arranged at intervals along the Y direction and disposed in the active region 203. For ease of explanation, the arrangement of the gates 207, sources 205, and drains 206 will be described below using the first active region 203a as an example.

[0096] Generally, a device cell may include a gate 207, a source 205, and a drain 206. The source 205, drain 206, and gate 207 can extend along the X direction in the first active region 203a. That is, the length direction of the source 205, drain 206, and gate 207 can be parallel to the X direction. Multiple device cells can correspond to the first active region 203a, and the gates 207, sources 205, and drains 206 of the multiple device cells can be arranged along the Y direction. Specifically, referring to FIG3A, each source 205 is located between two adjacent gates 207, that is, each source 205 has one gate 207 on each side along the Y direction. Similarly, each drain 206 is located between two adjacent gates 207, that is, each drain 206 has one gate 207 on each side along the Y direction, and the two gates 207 on each side of each drain 206 are not connected to each other in the semiconductor layer 20. Gate 207, source 205, and drain 206 can be arranged repeatedly along the Y direction in the first active region 203a as a repeating unit.

[0097] To improve the control capability of the gate 207, the end of the gate 207 can be extended to the junction of the active region 203 and the passive region 204 to reduce leakage current in the active region 203, thereby improving the stability and reliability of the HEMT device.

[0098] Specifically, Figure 3B shows a top view of a device cell provided in one embodiment. Referring to Figure 3B, the gate 207 includes a first end near the first passive region 204a and a second end near the second passive region 204b. The first end of the gate 207 can extend to the boundary between the first active region 203a and the first passive region 204a, and the second end of the gate 207 can extend to the boundary between the first active region 203a and the second passive region 204b. That is, the first end of the gate 207 is flush with the edge of the first active region 203a, and the second end of the gate 207 is flush with the edge of the second active region 203b, so as to block the leakage current path in the active region 203 and ensure the effective operation of the device.

[0099] In this embodiment, no gate bus 208 is provided in the semiconductor layer 20, meaning that at least some of the gates are not connected to each other in the semiconductor layer. Specifically, the size of the gate along the X direction is greater than or equal to the size of the first active region along the X direction. The two gates located on both sides of each drain are not connected to each other in the semiconductor layer, and / or, the two gates located on both sides of each source are not connected to each other in the semiconductor layer.

[0100] The gate 207 can be powered via a gate metal line 210 stacked on the semiconductor layer 20. Specifically, the gate metal line 210 may include a first portion 210a and a second portion 210b connected together. The first portion 210a is stacked on the first passive region 204a, and the second portion 210b is stacked on the first active region 203a. Each gate 207 is electrically connected to the second portion 210b of the gate metal line 210.

[0101] Figure 3C shows the cross-sectional structure of DD in Figure 3A. Referring to Figure 3C, the semiconductor layer 20 also includes a dielectric layer 209, which can be formed on the surface of the device functional layer 202 away from the substrate, i.e., the dielectric layer 209 is disposed in the second passive region 204b, the first active region 203a, the first passive region 204a, and the second active region 203b. The dielectric layer 209 can fill the gaps between electrodes (including between the gate 207 and the source 205, and between the gate 207 and the drain 206) and can cover the electrodes (gate 207, source 205, and drain 206) to provide a planarized surface, so that the gate metal line 210 can be formed on the planarized surface. Optionally, the dielectric layer 209 can be made of one of the following materials: silicon oxide, silicon nitride, alumina, polyimide, epoxy resin, epoxy molding compound, etc.

[0102] The gate metal line 210 can be formed on the surface of the dielectric layer 209 facing away from the substrate. The gate metal line 210 can be made of metal, such as one or more of aluminum, copper, tungsten, titanium, nickel, platinum, gold, and silver. The gate metal line 210 can be electrically connected to the gate 207 via a metal interconnect 211. Specifically, referring to FIG3C, the dielectric layer 209 includes a via 209a penetrating the dielectric layer 209 along the thickness direction (Z direction), and the via 209a is provided with a metal interconnect 211. The gate 207 may include a cap layer 207e and a gate metal layer 207f along the Z direction. A Schottky contact is formed between the gate metal layer 207f and the cap layer 207e. One end of the metal interconnect 211 is electrically connected to the gate metal layer 207f, and the other end is connected to the gate metal line 210.

[0103] In some embodiments, the distribution area of ​​the gate metal line 210 on the dielectric layer 209 can cover the entire surface of the dielectric layer 209, that is, the gate metal line 210 can overlap with the active region 203 and the passive region 204 in the semiconductor layer 20. As an example, FIG3D shows a cross-sectional structure of a high electron mobility transistor, the cutting angle of which can correspond to the cutting line BB in FIG3A. Referring to FIG3D, the gate metal line 210 is stacked on the dielectric layer 209 and covers the active region 203 and the passive region 204 below the dielectric layer. The gate metal line 210 is used to supply power to the gate. In order to supply power to the source 205 or the drain 206, a wiring via 212 can be provided in the gate metal line 210. The wiring via 212 penetrates the gate metal line 210 and the dielectric layer, and a metal lead can be provided in the wiring via 212 to bring the source 205 or the drain 206 out to the outside of the gate metal line 210.

[0104] However, since the active region 203 contains the active electrode 205 and the drain electrode 206, and the gate metal line 210 is used to power the gate 207, the potential of the gate 207 differs from that of the source 205 and the drain 206 during HEMT device operation. If the overlap between the gate metal line 210 and the active region 203 is too large, parasitic capacitance will be generated between the gate metal line 210 and the active region 203. Therefore, in some embodiments, to reduce the parasitic capacitance between the gate metal line 210 and the underlying active region 203, the gate metal line 210 may only cover the edge of the active region 203 to achieve the connection between the gate metal line 210 and the gate 207. As another example, Figure 3E shows a cross-sectional structure of another high electron mobility transistor, the cutting angle of which corresponds to the cutting line DD in Figure 3A. Referring to Figure 3E, for the first passive region 204a, two gate metal lines 210 are provided above it. One of these two gate metal lines 210 is used to supply power to the first active region 203a, and the other is used to supply power to the second active region 203b.

[0105] It should be noted that if the size of the gate metal line 210 is too small, its resistance will be relatively high. Therefore, in some embodiments, to reduce the resistance of the gate metal line 210, it can cover the edge of the active region 203 and the passive region 204. That is, except for the area below the gate metal line 210 that connects to the gate 207, the remaining area is the passive region 204. This reduces the overlap between the gate metal line 210 and the active region 203 and increases the width of the gate metal line 210, thereby reducing its resistance.

[0106] Referring to Figure 3C, the first portion 210a of the gate metal line 210 can cover the first passive region 204a. To achieve the connection between the gate 207 and the gate metal line 210, the second portion 210b of the gate metal line 210 can cover the edges of the first active region 203a and the second active region 203b, respectively. It can be understood that the smaller the overlap area between the gate metal line 210 and the active region 203, the smaller the parasitic capacitance. Therefore, the size of the second portion 210b of the gate metal line 210 needs to meet the connection requirements between the gate 207 and the gate metal line 210, while also being as small as possible. Optionally, the dimension of the second portion 210b of the gate metal line 210 along the X direction is less than or equal to 10 μm. Generally, the dimension L of the second portion 210b of the gate metal line 210 along the X direction can be selected based on the number of metal interconnects 211 arranged side by side along the X direction (or the number of vias 209a). The more metal interconnects 211 arranged side by side along the X direction, the larger the dimension L of the second portion 210b of the gate metal line 210 along the X direction. When the number of metal interconnects 211 arranged along the X direction is 1, the dimension L of the second portion 210b of the gate metal line 210 along the X direction can be 1 μm.

[0107] In this embodiment, the gate metal line 210 spans the first passive region 204a, with only a portion of its edge overlapping the first active region 203a (second active region 203b) to supply power to the gate 207 at its end. Thus, most of the area below the gate metal line 210 is the passive region 204, which contains no two-dimensional electron gas, thereby reducing the overlap area between the gate metal line 210 and the active region 203, and consequently reducing parasitic capacitance. Simultaneously, the passive region 204 directly beneath the gate metal line 210 allows for an increase in the width of the gate metal line 210, thereby reducing its resistance.

[0108] Figure 3F shows the cross-sectional structure of BB in Figure 3A. Referring to Figure 3F, compared with the structure shown in Figure 2D, the source 205 does not have a gate bus 208 at both ends along the X direction. Figure 3G shows the cross-sectional structure of CC in Figure 3A. Referring to Figure 3G, compared with the structure shown in Figure 2E, the drain 206 does not have a gate bus 208 at both ends along the X direction. Since the active region 203 does not have a gate bus 208, the possibility of damage to the gate 207 can be reduced, thereby reducing the problem of surface leakage caused by damage to the surface of the gate 207. At the same time, the area of ​​the gate 207 is also reduced, which reduces the leakage path and improves the leakage in the body direction of the HEMT device, thereby improving the stability and reliability of the HEMT device. In addition, supplying power to the gate 207 at the ends of the gate 207 can reduce the overlap area between the gate metal line 210 and the active region 203, thereby reducing the generation of parasitic capacitance.

[0109] In the device structure shown in Figure 2B, the gate 207 is powered by the gate bus 208, with the potential transfer direction along the Y direction, meaning the current flows from one end of the gate bus 208 to the other along the Y direction. During this process, a voltage drop is unavoidable due to the resistance, affecting current uniformity. Furthermore, the current flowing from one end of the gate bus 208 to the other can also affect phase characteristics in high-frequency applications, causing phase inconsistencies between the devices corresponding to the two ends of the gate bus 208. In contrast, in the device structures shown in Figures 3A to 3G, the conductivity of the gate 207 is achieved through a conductive layer, ensuring current uniformity. Moreover, eliminating the gate bus 208 within the active region 203 reduces the likelihood of damage to the gate 207, minimizing surface leakage caused by surface damage. It also reduces the area of ​​the gate 207 (the gate bus 208 can also be considered as the gate 207), further reducing device bulk leakage.

[0110] Figure 4A illustrates the structure of a high electron mobility transistor provided in another embodiment. Referring to Figure 4A, unlike the device structure shown in Figure 3A, in the device structure shown in Figure 4A, the two gates 207 adjacent to the source 205 are connected by a gate connection portion to form a ring gate structure, thereby improving the control capability of the gate 207 and improving the switching characteristics and current drive capability of the HEMT device.

[0111] Specifically, Figure 4B shows a top view of a device cell provided in one embodiment. Referring to Figure 4B, the two gates 207 adjacent to the source 205 may include a first gate 207a and a second gate 207b. The first gate 207a includes a first end near the first passive region 204a and a second end near the second passive region 204b. The second gate 207b includes a first end near the first passive region 204a and a second end near the second passive region 204b. The first end of the first gate 207a and the first end of the second gate 207b are connected through a first gate connection portion 207c, and the second end of the first gate 207a and the second end of the second gate 207b are connected through a second gate connection portion 207d, such that the first gate 207a, the first gate connection portion 207c, the second gate 207b, and the second gate connection portion 207d form a closed structure surrounding the source 205, i.e., a gate ring structure. The drain 206 may be located between two adjacent gate ring structures. Optionally, in the ring gate structure, the length of the gate 207 along the X direction can be less than or equal to the width of the active region along the X direction. This application embodiment does not impose any restrictions on this.

[0112] Similar to gate 207, gate connection portion may also include cap layer 207e and metal layer disposed on cap layer 207e, wherein the material of metal layer may be the same as the material of gate metal layer 207f, or may be different from the material of gate metal layer 207f.

[0113] In practical applications, the first gate 207a, the first gate connection portion 207c, the second gate 207b, and the second gate connection portion 207d can be formed by the same processing technology. Therefore, the first gate connection portion 207c and the second gate connection portion 207d can be regarded as part of the gate 207.

[0114] It is understood that the gate metal line 210 can also be connected to the first gate connection portion 207c and / or the second gate connection portion 207d via the metal interconnect 211, thereby realizing the electrical connection between the gate metal line 210 and the gate 207. As an example, FIG4C shows the cross-sectional structure of BB in FIG4A. Referring to FIG4C, the gate metal line 210 can be electrically connected to the first gate connection portion 207c via the metal interconnect 211 penetrating the dielectric layer 209. That is, the first gate connection portion 207c and the second gate connection portion 207d can serve as electrical contact locations to realize the electrical contact between the ring gate structure and the gate metal line 210.

[0115] In this embodiment, the ends of the two gates 207 adjacent to the source 205 are connected to each other through a gate connection portion, forming an annular gate structure surrounding the source 205. This completely blocks the conductive path from the source to the drain within the active region 203, thereby reducing the risk of leakage and enhancing gate control capability. Furthermore, the annular gate structure increases the overlap area with the gate metal line 210, providing more drilling positions to form vias 209a. Metal interconnects 211 are then placed in the vias 209a to connect with the gate metal line 210, reducing the resistance of the gate 207. Referring to FIG4B, for the annular gate structure, the position of the end of the gate 207 (e.g., P1) can be used as a drilling position to connect with the gate metal line 210. Similarly, the position of the gate connection portion (e.g., P2) can also be used as a drilling position to connect with the gate metal line 210.

[0116] Figure 5A illustrates the structure of a high electron mobility transistor provided in another embodiment. Referring to Figure 5A, unlike the device structure shown in Figure 4A, in the device structure shown in Figure 5A, the gate ring structure surrounds the drain instead of the source.

[0117] Specifically, Figure 5B shows a top view of a device cell provided in one embodiment. Referring to Figure 5B, the two gates 207 adjacent to the drain 206 may include a first gate 207a and a second gate 207b. The first gate 207a includes a first end near the first passive region 204a and a second end near the second passive region 204b. The second gate 207b includes a first end near the first passive region 204a and a second end near the second passive region 204b. The first end of the first gate 207a and the first end of the second gate 207b are connected through a first gate connection portion 207c, and the second end of the first gate 207a and the second end of the second gate 207b are connected through a second gate connection portion 207d, such that the first gate 207a, the first gate connection portion 207c, the second gate 207b, and the second gate connection portion 207d form a closed structure surrounding the drain 206, i.e., a gate ring structure. The source 205 may be located between two adjacent gate ring structures.

[0118] Referring to Figure 5B, for the ring gate structure, the position of the end of the gate 207 (e.g., P1) can be used as a hole position to achieve connection with the gate metal line 210. Similarly, the position of the gate connection portion (e.g., P2) can also be used as a hole position to achieve connection with the gate metal line 210.

[0119] Figure 5C shows the cross-sectional structure of BB in Figure 5A. Referring to Figure 5C, similar to Figure 4C, the gate metal line 210 can be electrically connected to the first gate connection portion 207c through the metal interconnect 211 penetrating the dielectric layer 209. That is, the first gate connection portion 207c and the second gate connection portion 207d can serve as electrical contact locations to achieve electrical contact between the ring gate structure and the gate metal line 210.

[0120] In this embodiment, the ends of the two gates 207 adjacent to the drain 206 are connected to each other through a gate connection portion, forming an annular gate structure surrounding the drain 206. This structure can completely block the conductive path from the source to the drain within the active region 203, thereby reducing the risk of leakage and enhancing gate control capability. Furthermore, the annular gate structure increases the overlap area with the gate metal line 210, providing more drilling positions to form vias 209a. Metal interconnects 211 are then placed in the vias 209a to connect with the gate metal line 210, thereby reducing the resistance of the gate 207.

[0121] Figure 6A illustrates the structure of a high electron mobility transistor provided in another embodiment. Referring to Figure 6A, unlike the device structure shown in Figure 3A, in the device structure shown in Figure 6A, the ends of the two gates 207 adjacent to the source 205 extend into the passive region 204. This ensures that the gates 207 can block the leakage current path of the active region 203, ensuring the effective operation of the HEMT device.

[0122] For the device structure shown in Figure 3A, due to process limitations, the end of the source 205 is difficult to be located exactly at the edge of the active region 203. Therefore, in order to improve gate control capability, the end of the gate 207 can be extended a certain distance into the passive region 204 to block the leakage current path of the active region 203 and ensure that the device can operate effectively.

[0123] Specifically, FIG6B shows a top view of a device cell provided in one embodiment. Referring to FIG6B, the first end of the gate 207 extends to a first passive region 204a, and the second end extends to a second passive region 204b.

[0124] Figure 6C shows the cross-sectional structure of DD in Figure 6A. Referring to Figure 6C, the two segments of the gate 207 extend along the X direction into the passive regions 204 on both sides of the first active region 203a. Thus, although the end portion of the gate 207 extending into the passive region 204 will be damaged during the formation of the passive region 204, the size of the gate 207 is smaller than that of the gate bus 208 in Figure 2B, meaning the area of ​​the gate 207 that is damaged is smaller. Therefore, compared to the HEMT devices shown in Figures 2B to 2D, leakage current can still be reduced, thereby improving the reliability of the device.

[0125] This application also provides a chip, which includes a packaging substrate and a high electron mobility transistor, wherein the high electron mobility transistor is electrically connected to the packaging substrate.

[0126] The high electron mobility transistor in the chip is the same as the high electron mobility transistor described above. For details on the specific implementation of the high electron mobility transistor, please refer to the description above, which will not be repeated here.

[0127] This application also provides an electronic device, which includes a circuit board and the aforementioned chip. The chip is electrically connected to the circuit board.

[0128] In this embodiment, the chip containing the aforementioned high electron mobility transistor can be applied to various electronic devices. For a description of the electronic devices, please refer to the above description; further details will not be repeated here.

[0129] In the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0130] In the embodiments of this application, it should be understood that the directional terms mentioned, such as "up", "down", "left", "right", "inner", "outer", etc., are only for reference to the direction of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0131] In the embodiments of this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," "third," and "fourth" may explicitly or implicitly include one or more of that feature.

[0132] In embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0133] In the embodiments of this application, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0134] In the embodiments of this application, it should be noted that the descriptions of "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range. This error range can be a range with a deviation angle of less than or equal to 5°, 8° or 10° relative to absolute verticality and absolute parallelism, respectively, and is not specifically limited here.

[0135] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A high electron mobility transistor, characterized in that, include: A semiconductor layer includes a first active region and a first passive region arranged along a first direction; the semiconductor layer includes a plurality of gates extending along the first direction; wherein the plurality of gates are spaced apart along a second direction, at least a portion of the extension of each gate is located in the first active region, and at least a portion of the gates are not connected to each other in the semiconductor layer; the semiconductor layer further includes a dielectric layer, the dielectric layer being at least disposed in the first passive region; the first direction and the second direction intersect, and both the first direction and the second direction are perpendicular to the thickness direction of the semiconductor layer; A wiring layer, the wiring layer including a gate metal line, the gate metal line including a first part and a second part connected together, the first part being stacked on the first passive region along the thickness direction, and the first part being spaced apart from the first passive region by the dielectric layer, the second part being stacked on the first active region, and each gate being electrically connected to the second part of the gate metal line.

2. The high electron mobility transistor according to claim 1, characterized in that, The gate includes a cap layer and a gate metal layer stacked along the thickness direction, a Schottky contact is formed between the gate metal layer and the cap layer, and the gate metal line is electrically connected to the gate metal layer.

3. The high electron mobility transistor according to claim 1 or 2, characterized in that, The dimension of the gate along the first direction is greater than or equal to the dimension of the first active region along the first direction; The semiconductor layer further includes a plurality of drains extending along a first direction; wherein the plurality of drains are spaced apart along a second direction, each drain is located in the first active region, each drain is located between two adjacent gates, and the two gates located on both sides of each drain are not connected to each other in the semiconductor layer.

4. The high electron mobility transistor according to claim 3, characterized in that, The high electron mobility transistor further includes a second passive region, and the first active region is located between the first passive region and the second passive region; The semiconductor layer further includes a plurality of sources extending along the first direction, each source being located between two adjacent gates; The two gates adjacent to the source include a first gate and a second gate. The first gate includes a first end near the first passive region and a second end near the second passive region. The second gate includes a first end near the first passive region and a second end near the second passive region. The first end of the first gate and the first end of the second gate are connected through a first gate connection portion. The second end of the first gate and the second end of the second gate are connected through a second gate connection portion. The first gate, the first gate connection portion, the second gate, and the second gate connection portion form a ring gate structure surrounding the source.

5. The high electron mobility transistor according to claim 4, characterized in that, Each of the drains is located between two adjacent ring gate structures.

6. The high electron mobility transistor according to claim 1 or 2, characterized in that, The dimension of the gate along the first direction is greater than or equal to the dimension of the first active region along the first direction; The semiconductor layer further includes a plurality of sources extending along a first direction; wherein the plurality of sources are spaced apart along a second direction, each source is located in the first active region, each source is located between two adjacent gates, and the two gates located on both sides of each source are not connected to each other in the semiconductor layer.

7. The high electron mobility transistor according to claim 6, characterized in that, The high electron mobility transistor further includes a second passive region, and the first active region is located between the first passive region and the second passive region; The semiconductor layer further includes a plurality of drains extending along the first direction, each drain being located between two adjacent gates; The two gates adjacent to the drain include a first gate and a second gate. The first gate includes a first end near the first passive region and a second end near the second passive region. The second gate includes a first end near the first passive region and a second end near the second passive region. The first end of the first gate and the first end of the second gate are connected through a first gate connection portion. The second end of the first gate and the second end of the second gate are connected through a second gate connection portion. The first gate, the first gate connection portion, the second gate, and the second gate connection portion form a ring gate structure surrounding the drain.

8. The high electron mobility transistor according to claim 7, characterized in that, Each of the sources is located between two adjacent ring gate structures.

9. The high electron mobility transistor according to claim 4 or 7, characterized in that, The gate metal line is electrically connected to the first gate connection portion and / or the second gate connection portion.

10. The high electron mobility transistor according to claim 1 or 2, characterized in that, The high electron mobility transistor further includes a second passive region, and the first active region is located between the first passive region and the second passive region; The gate includes a first end near the first passive region and a second end near the second passive region. The first end of the gate extends at least to the boundary between the first active region and the first passive region, and the second end of the gate extends at least to the boundary between the first active region and the second passive region.

11. The high electron mobility transistor according to claim 10, characterized in that, The first end of the gate extends into the first passive region; and / or, the second end of the gate extends into the second passive region.

12. The high electron mobility transistor according to claim 1 or 2, characterized in that, The first portion of the gate metal line covers the first passive region.

13. The high electron mobility transistor according to claim 1 or 2, characterized in that, The second portion of the gate metal line has a dimension of less than or equal to 10 μm along the first direction.

14. The high electron mobility transistor according to claim 1 or 2, characterized in that, The dielectric layer is disposed in the first active region and the first passive region, and the gate metal line is stacked on the dielectric layer along the thickness direction; The dielectric layer includes a through-hole that penetrates the dielectric layer along its thickness direction. A metal lead is provided in the through-hole, one end of which is connected to the gate and the other end of which is connected to the gate metal line.

15. A chip, characterized in that, include: The packaging substrate and the high electron mobility transistor as described in any one of claims 1 to 14, wherein the high electron mobility transistor is electrically connected to the packaging substrate.

16. An electronic device, characterized in that, include: The circuit board and the chip as described in claim 15, wherein the chip is electrically connected to the circuit board.

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