Switching circuit, switching system, optical module and control method for switching circuit

Abstract

Disclosed in the embodiments of the present application are a switching circuit, a switching system, an optical module and a control method for the switching circuit. The switching circuit comprises: an input terminal, receiving an input signal; an output terminal, providing an output signal; a first transistor, having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal; a timing control terminal, receiving a timing signal generated on the basis of the input signal; a soft-start control terminal, receiving a soft start signal generated on the basis of the timing signal; and a control circuit, having a first input terminal coupled to the timing control terminal to receive the timing signal, a second input terminal coupled to the soft-start control terminal to receive the soft start signal, and a first output terminal coupled to a control terminal of the first transistor. When an input signal is input to the input terminal, the control circuit receives a timing signal from the timing control terminal. When the timing signal increases to a first voltage threshold, the soft-start control terminal receives a soft start signal, and, on the basis of the soft start signal, the conduction degree of the first transistor is controlled. The present application solves the problem of inrush current during soft start.

Description

Switching circuit, switching system, optical module and control method of switching circuit

[0001] The present application claims priority to the Chinese patent application No. 202510205990.0, filed on February 24, 2025, and entitled “Switching circuit, switching system, optical module and control method of switching circuit”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of switching circuit, in particular to a switching circuit, a switching system, an optical module and a control method of the switching circuit. BACKGROUND

[0003] The slow power-on (slow start) circuit usually uses a switching circuit to complete the slow power-on function. However, the switching circuit for slow power-on in the prior art is usually composed of multiple separate device components, and has low integration and simple function, only having a simple slow power-on function.

[0004] The switching circuit for realizing slow power-on of the optical module is prone to causing damage to the optical module due to overvoltage when the system side power-off causes circuit oscillation. In addition, for the optical module with double-row gold fingers, the power-off and power-on will occur in sequence during the plug-out process, and then the power-off will occur again. During this process, the conventional switching circuit will cause inrush current to exceed the standard due to the failure to turn off in time after power-on. Similarly, during the plug-in process, the power-on and power-off will occur in sequence, and then the power-on will occur again, which will also cause the inrush current to exceed the standard.

[0005] In addition, there are problems such as power-on jitter caused by poor contact during plug-in, input signal falling below the working voltage caused by power supply side overload, input signal overvoltage failure, and slow response of fast hot plug. SUMMARY

[0006] The present application provides a switching circuit, a control method of the switching circuit, and a switching system, aiming to solve the problem of inrush current exceeding the standard during power-on of the switching circuit for optical module plug-in in the prior art.

[0007] According to a first aspect of the present application, the present application provides a switching circuit, comprising: an input terminal receiving an input signal; an output terminal providing an output signal; a first transistor having a first terminal coupled to the input terminal, a second terminal coupled to the output terminal, and a control terminal; a timing control terminal receiving a timing signal, wherein the timing signal is generated based on the input signal; a soft start control terminal receiving a soft start signal, wherein the soft start signal is generated based on the timing signal; and a control circuit having a first input terminal coupled to the timing control terminal to receive the timing signal, a second input terminal coupled to the soft start control terminal to receive the soft start signal, and a first output terminal coupled to the control terminal of the first transistor.

[0008] When the input signal is input to the input terminal, the control circuit receives the timing signal from the timing control terminal; when the timing signal increases to a first voltage threshold, the soft start control terminal receives the soft start signal, and the control circuit controls the conduction degree of the first transistor according to the soft start signal.

[0009] According to a second aspect of the present application, the present application provides a switching system, comprising the switching circuit according to any one of the first aspect described above; a timing capacitor having a first terminal coupled to the timing control terminal and a second terminal coupled to a reference ground; and a soft start capacitor having a first terminal coupled to the soft start control terminal and a second terminal coupled to the reference ground.

[0010] According to a third aspect of the present application, the present application provides an optical module, comprising: an input detection unit having an input terminal receiving an input signal and an output terminal providing an enable signal; the switching circuit according to any one of the first aspect described above; a timing capacitor having a first terminal coupled to the timing control terminal and a second terminal coupled to a reference ground; and a soft start capacitor having a first terminal coupled to the soft start control terminal and a second terminal coupled to the reference ground.

[0011] According to a fourth aspect of the present application, the present application provides a control method of a switching circuit, applicable to the switching circuit according to any one of the first aspect described above, comprising: receiving an input signal; generating a timing signal based on the input signal; generating a soft start signal based on the timing signal; controlling the conduction and turn-off of the first transistor based on the soft start signal; when the input signal remains in a voltage preset range within a first preset time, the timing signal gradually increases to a first voltage threshold, when the timing signal reaches the first voltage threshold, the soft start signal starts to increase, the control circuit controls the conduction degree of the first transistor to increase synchronously with the soft start signal, and when the first transistor is fully turned on, the output signal is equal to the input signal.

[0012] Through one of the above-mentioned embodiments or multiple embodiments of the present application, at least the following technical effects can be achieved:

[0013] By setting a timing signal before the soft-start signal for prediction, the soft-start signal begins to increase and the first transistor is turned on synchronously after the timing signal reaches the first voltage threshold. This continues until the soft-start signal increases to a certain threshold and the first transistor is fully turned on. During the increase of the timing signal and the soft-start signal, any fluctuation in the input signal due to power instability will cause the timing signal and the soft-start signal to drop to 0, interrupting the power-on process. This avoids the problem of inrush current caused by input signal fluctuations during power-on. Attached Figure Description

[0014] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0015] Figure 1 shows a schematic diagram of a switching circuit according to an embodiment of this application;

[0016] Figure 2 shows a schematic diagram of the circuit structure of a switching circuit according to an embodiment of this application;

[0017] Figure 3 shows a signal waveform diagram of a switching circuit according to an embodiment of this application;

[0018] Figure 4 shows a signal waveform diagram of a switching circuit according to an embodiment of this application;

[0019] Figure 5 shows a signal waveform diagram of a switching circuit according to an embodiment of this application;

[0020] Figure 6 shows the signal waveform of a switching circuit according to an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0022] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document, unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0023] Figure 1 shows a schematic diagram of a switching circuit 100 according to an embodiment of this application. The switching circuit 100 includes an input terminal IN, an output terminal OUT, a timing control terminal TMR, a soft-start control terminal SS, a first transistor M1, and a control circuit 10. The input terminal IN receives the input signal Vin, and the output terminal OUT provides the output signal Vout.

[0024] The first transistor M1 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the input terminal IN, and the second terminal is coupled to the output terminal OUT. The timing control terminal TMR receives a timing signal Vtmr, which is generated based on the input signal Vin. The soft-start control terminal SS receives a soft-start signal Vss, which is generated based on the timing signal Vtmr. The control circuit 10 has a first input terminal IN coupled to the timing control terminal TMR to receive the timing signal Vtmr, a second input terminal IN coupled to the soft-start control terminal SS to receive the soft-start signal Vss, and a first output terminal OUT coupled to the control terminal of the first transistor M1.

[0025] When the input signal Vin is input to the input terminal IN, the control circuit 10 receives the timing signal Vtmr from the timing control terminal TMR. When the timing signal Vtmr increases to the first voltage threshold Vt1, the soft-start control terminal SS receives the soft-start signal Vss, and the control circuit 10 controls the conduction level of the first transistor M1 according to the soft-start signal Vss. When the timing signal Vtmr reaches the first voltage threshold Vt1, the control circuit 10 controls the first transistor M1 to start conducting, the timing control terminal TMR discharges, and the timing signal Vtmr drops to a set value, which can be 0, for example. When the control circuit 10 controls the first transistor M1 to be fully conducted, the soft-start control terminal SS discharges, and the soft-start signal Vss drops to the set value, which can be 0, for example.

[0026] When the input signal Vin first appears, the gate-source voltage Vgs of the first transistor M1 is less than the turn-on voltage Vth of its control terminal (gate terminal), and the first transistor M1 is in the off state. At this time, the input signal Vin cannot be output through the first transistor M1, thus achieving a power-on delay. As the control circuit 10 charges the gate capacitor of the first transistor M1, the first transistor M1 begins to conduct, the input signal Vin is output through the first transistor M1, and the output signal Vout begins to increase. After the first transistor M1 starts conducting, as Vgs continues to increase, its drain-source resistance Rds will decrease rapidly, causing the output voltage to gradually increase until it is basically consistent with the input signal. In this embodiment, when the timing signal Vtmr is used to predict the input signal Vss before it starts to increase, when the input signal Vin remains within the preset voltage range for a period of time, the timing signal Vtmr gradually increases to the first voltage threshold Vt1. When the timing signal Vtmr reaches the first voltage threshold Vt1, the soft-start signal Vss starts to increase. The control circuit 10 controls the conduction degree of the first transistor M1 to increase synchronously with the soft-start signal Vss. When the first transistor M1 is fully turned on, the output signal Vout is equal to the input signal Vin. By setting a timing signal Vtmr before the soft-start signal Vss for prediction, the soft-start signal Vss begins to increase and the first transistor M1 is turned on simultaneously after the timing signal Vtmr reaches the first voltage threshold Vt1. This continues until the soft-start signal Vss increases to a certain threshold and the first transistor M1 is fully turned on. During the increase of the timing signal Vtmr and the soft-start signal Vss, any fluctuation in the input signal Vin due to power instability will cause the timing signal Vtmr and the soft-start signal Vss to drop to the set value, interrupting the power-on process. This avoids the problem of false power-on caused by signal fluctuations.

[0027] In some embodiments, the time when the timing signal Vtmr next reaches the first voltage threshold Vt1 is separated from the time when it previously reached the first voltage threshold Vt1 by a preset waiting time. For example, the preset waiting time ranges from 100µs to 256µs. The preset waiting time is set to be greater than the discharge time of the timing signal Vtmr, thereby ensuring that the timing capacitor Ctmr is completely discharged before the timing control terminal TMR is turned on each time. This avoids the problem of inaccurate timing signal Vtmr caused by the timing control terminal TMR not being fully discharged before being re-powered in extreme cases.

[0028] Figure 2 shows a schematic diagram of the circuit structure of a switching circuit 100 according to an embodiment of this application. In the embodiment shown in Figure 2, the timing control terminal TMR of the switching circuit 100 is electrically connected to an external timing capacitor Ctmr. When the timing capacitor Ctmr is charged, the timing signal Vtmr increases. The switching circuit 100 also includes a first current source A1, which has an output terminal OUT coupled to the timing control terminal TMR. The output terminal OUT of the first current source A1 is also coupled to the first input terminal IN of the control circuit 10. The timing capacitor Ctmr is coupled between a reference ground and the timing control terminal TMR. When the input signal Vin remains within a preset voltage range for a first preset time, the control circuit 10 controls the first current source A1 to charge the timing capacitor Ctmr to increase the timing signal Vtmr. The timing signal Vtmr gradually increases to a first voltage threshold Vt1.

[0029] In the embodiment shown in Figure 2, the switching circuit 100 further includes a second transistor M2. The second transistor M2 has a first terminal coupled to the output terminal OUT of the first current source A1, a second terminal coupled to a reference ground, and a control terminal for receiving a discharge control signal PD. The discharge control signal PD is generated based on the input signal, the timing signal Vtmr, and the soft-start signal Vss. The second transistor M2 is turned on or off under the control of the discharge control signal PD. When the discharge control signal PD is at a logic high level, the second transistor M2 is turned on, the timing control terminal TMR discharges, and the timing signal Vtmr drops to a set value.

[0030] In the embodiment shown in Figure 2, the soft-start control terminal SS of the switching circuit 100 is electrically connected to an external soft-start capacitor Css. When the soft-start capacitor Css is charged, the soft-start signal Vss increases. The switching circuit 100 also includes a second current source A2, which has an output terminal OUT coupled to the soft-start control terminal SS. The output terminal OUT of the second current source A2 is also coupled to the second input terminal IN of the control circuit 10. The soft-start control terminal SS is also coupled to the first terminal of the soft-start capacitor Css, and the second terminal of the soft-start capacitor Css is coupled to a reference ground. When the timing signal Vtmr reaches the first voltage threshold Vt1, the control circuit 10 controls the second current source A2 to charge the soft-start capacitor Css to increase the soft-start signal Vss. When the soft-start signal Vss reaches the second voltage threshold Vt2, the first transistor M1 is fully turned on.

[0031] During the charging process of the soft-start capacitor, the control circuit 10 raises the output voltage based on the voltage rise of the soft-start capacitor, which is calculated by the formula Vout(V) = 3*T. SS (ms)*I SS (uA) / C SS (nF), where Tss(ms) is the charging time of the soft-start capacitor Css, ISS (uA) represents the charging current of the soft-start capacitor, C SS (nF) represents the capacitance value of the soft-start capacitor Css. For the output terminal, its inrush current I... inrush =C OUT *Vout / T SS Therefore, the capacitance value C of the soft-start capacitor Css can be changed. SS This is to suppress the inrush current.

[0032] In the embodiment shown in Figure 2, the switching circuit 100 further includes a third transistor M3. The third transistor M3 has a first terminal coupled to the output terminal OUT of the second current source A2, a second terminal coupled to reference ground, and a control terminal receiving a discharge control signal PD. The third transistor M3 is turned on or off under the control of the discharge control signal PD, which is generated based on the input signal, the timing signal Vtmr, and the soft-start signal Vss. When the discharge control signal PD is at a logic high level, the third transistor M3 is turned on, the soft-start control terminal SS discharges, and the soft-start signal Vss drops to a set value.

[0033] In the embodiment shown in Figure 2, the switching circuit 100 further includes a temperature control unit 70. The temperature control unit 70 has an input terminal IN coupled to the control circuit 10 and an output terminal OUT coupled to the second current source A2. The temperature control unit 70 controls the current value output by the second current source A2 according to the ambient temperature at which the switching circuit 100 is located. Exemplarily, the second current source A2 includes N controlled constant current sources connected in parallel. Each controlled constant current source has two states: on and off. The current value output by the second current source A2 is the sum of the currents of the controlled constant current sources in the on state, where N is an integer greater than or equal to 2. The number of controlled constant current sources in the on state is determined based on the voltage value of the output signal Vout. The larger the voltage value of the output signal Vout, the more controlled constant current sources are in the on state, thus reducing the inrush current. When the output signal Vout approaches the input signal, all controlled constant current sources are turned on, and the charging speed reaches its maximum.

[0034] In some embodiments, the number of controlled constant current sources in the ON state among the N controlled constant current sources is determined based on the ambient temperature of the switching circuit 100. Since capacitors have the characteristic that their capacitance increases with temperature, when the ambient temperature of the switching circuit 100 reaches a certain threshold, for example, above 65°C, to compensate for the temperature characteristics of the capacitor, the charging current to the capacitor is reduced by decreasing the number of ON controlled constant current sources. That is, at the same time, the number of ON controlled constant current sources when the ambient temperature reaches a certain threshold is less than the number of ON controlled constant current sources when the ambient temperature does not reach the threshold, thereby ensuring consistent control of the inrush current at both normal and high temperatures. For example, when the voltage value of the output signal Vout is the first output voltage and the ambient temperature of the switching circuit 100 is greater than the first temperature threshold, K controlled constant current sources are ON; when the voltage value of the output signal Vout is the first output voltage and the ambient temperature is less than or equal to the first temperature threshold, K controlled constant current sources are ON, where 1 ≤ M < K ≤ N, and M and K are both integers. The first temperature threshold is determined based on the actual application.

[0035] In the embodiment shown in Figure 2, the switching circuit 100 further includes an enable control terminal EN, which receives an enable signal Vm. The enable signal Vm is generated based on the input signal Vin, and its magnitude characterizes the magnitude of the input signal Vin. Exemplarily, the enable signal Vm can be generated by an external input detection unit, as shown in Figure 2. This input detection unit may include a first resistor R1 and a second resistor R2. The first resistor R1 includes a first terminal and a second terminal, with the first terminal of R1 coupled to the input signal Vin. The second resistor R2 also includes a first terminal and a second terminal, with the first terminal of R2 coupled to the second terminal of R1, and the second terminal of R2 coupled to a reference ground. The enable signal Vm, characterizing the magnitude of the input signal Vin, is sampled from the connection point of the first resistor R1 and the second resistor R2 using a voltage divider. The range of the enable signal Vm is determined based on the resistance ratio of the first resistor R1 and the second resistor R2.

[0036] In the embodiment shown in FIG2, the switching circuit 100 further includes an enable unit 20, an overvoltage protection unit 30, an undervoltage protection unit 40, and a logic AND circuit LC.

[0037] Enable unit 20 is coupled between enable control terminal EN and control circuit 10, and is used to generate enable feedback signal Vm_n based on enable signal Vm. Enable unit 20 includes a first comparator Amp1, which has a non-inverting input terminal IN coupled to enable control terminal EN to receive enable signal Vm, an inverting input terminal IN to receive a first reference voltage V1, and an output terminal OUT to provide enable feedback signal Vm_n. When enable signal Vm is greater than or equal to the first reference voltage V1, enable feedback signal Vm_n outputs a logic high level, indicating that input signal Vin is greater than a preset value. For example, the first reference voltage V1 is between 0.49V and 0.51V.

[0038] An overvoltage protection unit 30 is coupled between the input terminal IN of the switching circuit 100 and the control circuit 10, and is used to generate an overvoltage feedback signal Vovp_n based on the input signal Vin. The overvoltage protection unit 30 includes a second comparator Amp2, which has a non-inverting input terminal IN to receive a second reference voltage V2, an inverting input terminal IN coupled to the input terminal IN of the switching circuit 100, and an output terminal OUT to provide the overvoltage feedback signal Vovp_n. When the input signal Vin is less than or equal to the second reference voltage V2, the overvoltage feedback signal Vovp_n outputs a logic high level. For example, the second reference voltage V2 is between 3.7V and 3.84V.

[0039] An undervoltage protection unit 40 is coupled between the input terminal IN of the switching circuit 100 and the control circuit 10, and is used to generate an undervoltage feedback signal Vuvlo_n based on the input signal Vin. The undervoltage protection unit 40 includes a third comparator Amp3, which has a non-inverting input terminal IN coupled to the input terminal IN of the switching circuit 100, an inverting input terminal IN receiving a third reference voltage V3, and an output terminal OUT providing the undervoltage feedback signal Vuvlo_n. When the input signal Vin is greater than or equal to the third reference voltage V3, the undervoltage feedback signal Vuvlo_n is at a logic high level. For example, the third reference voltage V3 is between 2.63V and 2.785V.

[0040] The logic AND circuit LC has a first input terminal IN that receives an enable feedback signal Vm_n, a second input terminal IN that receives an overvoltage feedback signal Vovp_n, a third input terminal IN that receives an undervoltage feedback signal Vuvlo_n, and an output terminal OUT coupled to the control circuit 10. The enable feedback signal Vm_n indicates that the input signal Vin exists and is greater than a preset threshold; the overvoltage feedback signal Vovp_n indicates that the input signal Vin is less than or equal to a second reference voltage V2; and the undervoltage feedback signal Vuvlo_n indicates that the input signal Vin is greater than or equal to a third reference voltage V3. The logic AND circuit LC generates a power-on control signal based on the enable feedback signal Vm_n, the overvoltage feedback signal Vovp_n, and the undervoltage feedback signal Vuvlo_n. When the enable feedback signal Vm_n, the overvoltage feedback signal Vovp_n, and the undervoltage feedback signal Vuvlo_n are all at a logic high level, the power-on control signal is at a logic high level, indicating that the input signal Vin is within a preset voltage range.

[0041] In the embodiment shown in Figure 2, the switching circuit 100 further includes a current detection terminal IMON and a current detection unit 80. The current detection terminal IMON outputs a second current I2. The current detection unit 80 is coupled between the current detection terminal IMON and the control circuit 10. The current detection unit 80 detects a first current I1 between the input terminal IN of the switching circuit 100 and the first terminal of the first transistor M1, and generates a second current I2 based on the first current I1, and then outputs the second current I2 to the current detection terminal IMON. For example, the second current I2 is output in a ratio of 10μA / A (±2%) to the first current I1. The second current I2 is coupled to an external current detection module, which includes an analog-to-digital converter (ADC). In the current detection module, the second current I2 is connected in series with a grounding resistor to generate a voltage to be measured. The ADC acquires the voltage to be measured (analog signal) and converts it into a digital signal for output. This digital signal characterizes the magnitude of the first current I1 between the input terminal IN of the switching circuit 100 and the first terminal of the first transistor M1.

[0042] In the embodiment shown in Figure 2, the switching circuit 100 further includes a power detection unit 90 and a power detection terminal PG. The power detection unit 90, coupled to the power detection terminal PG, is used to generate a power detection signal Vpg based on the input signal Vin and the output signal Vout. The power detection signal Vpg characterizes whether the first transistor M1 between the input terminal IN and the output terminal OUT of the switching circuit 100 is stably turned on. When the first transistor M1 is stably turned on, the switching circuit 100 is in normal operating condition and can provide a stable output voltage.

[0043] In the embodiment shown in Figure 2, the power detection unit 90 includes a fourth comparator Amp4 and a fourth transistor M4. The fourth comparator Amp4 has a non-inverting input terminal IN that receives a second input signal Vin2 that has a preset difference from the input signal Vin, and an inverting input terminal IN that receives an output signal Vout output from the output terminal OUT of the switching circuit 100. The output terminal OUT provides a power feedback signal Vpg_n. The fourth transistor M4 has a first terminal coupled to the power detection terminal PG, a second terminal coupled to reference ground, and a control terminal that receives the power feedback signal Vpg_n. For example, the second input signal Vin2 has a small difference from the input signal Vin, for example, Vin2 = Vin - 0.15V. Since the output signal Vout is almost equal to the input signal Vin when the first transistor M1 is fully turned on, the second input signal Vin2 needs to be set to a voltage with a small difference from the input signal Vin. The second input signal Vin2 is compared with the output signal Vout. When the second input signal Vin2 is less than the output signal Vout, it means that the output signal Vout is almost equal to the input signal Vin, and the power supply is stable.

[0044] When the second input signal Vin2 is greater than or equal to the output signal Vout, the power feedback signal Vpg_n is in a logic high state, the fourth transistor M4 is turned on, and the power detection signal Vpg is at a logic low level, indicating that the first transistor M1 between the input terminal IN and the output terminal OUT of the switching circuit 100 is not stably turned on. When the second input signal Vin2 is less than the output signal Vout, the power feedback signal Vpg_n is in a logic low state, the fourth transistor M4 is turned off, and the power detection signal Vpg is at a logic high level, indicating that the first transistor M1 between the input terminal IN and the output terminal OUT of the switching circuit 100 is stably turned on.

[0045] In the embodiment shown in Figure 2, the switching circuit 100 further includes a fifth transistor M5. The fifth transistor M5 has a first terminal coupled to the output terminal OUT, a second terminal coupled to a reference ground, and a control terminal that receives a discharge control signal PD. The fifth transistor M5 is turned on or off under the control of the discharge control signal PD. The discharge control signal PD is generated based on the input signal, the timing signal Vtmr, and the soft-start signal Vss. When the discharge control signal PD is at a logic high level, the fifth transistor M5 is turned on, the output terminal OUT discharges, and the output signal Vout drops to 0.

[0046] This application also provides a switching system, including the aforementioned switching circuit 100, a timing capacitor Ctmr, and a soft-start capacitor Css. The timing capacitor Ctmr has a first terminal coupled to the timing control terminal TMR and a second terminal coupled to a reference ground. The soft-start capacitor Css has a first terminal coupled to the soft-start control terminal SS and a second terminal coupled to a reference ground.

[0047] This application also provides an optical module, including an input detection unit, the aforementioned switching circuit 100, a timing capacitor Ctmr, and a soft-start capacitor Css. The input detection unit has an input terminal IN to receive an input signal Vin and an output terminal OUT to provide an enable signal Vm. The timing capacitor Ctmr has a first terminal coupled to a timing control terminal TMR and a second terminal coupled to a reference ground. The soft-start capacitor Css has a first terminal coupled to a soft-start control terminal SS and a second terminal coupled to a reference ground.

[0048] This application also provides a control method for a switching circuit 100, applicable to the aforementioned switching circuit 100, including steps 101 to 105.

[0049] Step 101: Receive the input signal Vin.

[0050] Step 102: Generate timing signal Vtmr based on input signal Vin.

[0051] Step 103: Generate a soft-start signal Vss based on the timing signal Vtmr.

[0052] Step 104: Control the turn-on and turn-off of the first transistor M1 based on the soft-start signal Vss.

[0053] Step 105: When the input signal Vin remains within the voltage preset range for the first preset time, the timing signal Vtmr gradually increases to the first voltage threshold Vt1. When the timing signal Vtmr reaches the first voltage threshold Vt1, the soft-start signal Vss begins to increase. The control circuit 10 controls the conduction degree of the first transistor M1 to increase synchronously with the soft-start signal Vss. When the first transistor M1 is fully turned on, the output signal Vout is equal to the input signal Vin.

[0054] Figure 3 shows a signal waveform diagram of a switching circuit 100 according to an embodiment of this application. The waveforms of each signal in Figure 3 are explained with reference to the structure of the switching circuit 100 shown in Figure 2. It should be noted that, for the switching circuit 100 applied to an optical module, when the optical module is inserted into the communication device through the gold fingers, the optical module starts to be powered on through the switching circuit 100. The scenario shown in Figure 3 is the scenario after the gold fingers of the optical module are quickly inserted.

[0055] From time t0 to time t1, the input signal Vin appears and stabilizes at a certain value, the enable signal Vm appears and stabilizes at a certain value, and the timing signal Vtmr begins to increase until it reaches the first voltage threshold Vt1.

[0056] From time t1 to time t2, the timing signal Vtmr discharges to 0 after reaching the first voltage threshold Vt1. The soft-start signal Vss begins to increase, and the control circuit 10 controls the first transistor M1 to start conducting. The output signal Vout increases with the increase of the soft-start signal Vss. When the soft-start signal Vss reaches the second voltage threshold Vt2, the first transistor M1 is fully turned on, and the value of the output signal Vout is equal to the value of the input signal Vin.

[0057] From time t2 to time t3, the soft-start signal Vss continues to increase to a certain threshold and then discharges. After the soft-start signal Vss discharges, the power detection signal Vpg goes high, indicating that the optical module connection is stable. After a period of time, the current detection unit 80 collects the first current I1 to generate the second current I2. The voltage Vimon to be measured can be generated based on the second current I2. The voltage Vimon to be measured represents the value of the first current I1 between the input terminal IN and the first terminal of the first transistor M1.

[0058] Figure 4 shows the signal waveforms of a switching circuit 100 according to an embodiment of this application. The waveforms of each signal in Figure 4 are explained with reference to the structure of the switching circuit 100 shown in Figure 2. The scenario shown in Figure 4 is a power outage caused by power instability during the increasing phase of the timing signal Vtmr.

[0059] From time t0 to time t1, the input signal Vin appears and stabilizes at a certain value, the enable signal Vm appears and stabilizes at a certain value, the timing signal Vtmr begins to increase until it reaches the first voltage threshold Vt1, the timing signal Vtmr discharges to 0 after reaching the first voltage threshold Vt1, the soft start signal Vss begins to increase, the control circuit 10 controls the first transistor M1 to start conducting, and the output signal Vout increases with the increase of the soft start signal Vss.

[0060] From time t1 to time t2, due to the unstable power supply of the optical module during the insertion and removal phase, the input signal Vin fluctuates at time t1, and then the power is turned on again. After the power is turned off, the soft start signal Vss decreases to 0, and the output voltage gradually decreases.

[0061] From time t2 to time t3, the timing signal Vtmr is configured to start increasing when the output voltage is less than a certain value. At time t2, the output voltage drops to a certain value, for example, the output voltage is less than 0.3V. At this time, the timing signal Vtmr starts increasing again. At time t3, the timing signal Vtmr increases to the first voltage threshold Vt1.

[0062] After time t3, the timing signal Vtmr discharges to 0 after reaching the first voltage threshold Vt1. The soft-start signal Vss begins to increase, and the control circuit 10 controls the first transistor M1 to turn on. The output signal Vout increases with the increase of the soft-start signal Vss. When the soft-start signal Vss reaches the second voltage threshold Vt2, the first transistor M1 is fully turned on, and the value of the output signal Vout is equal to the value of the input signal Vin. The soft-start signal Vss continues to increase to a certain threshold and then discharges. After the soft-start signal Vss discharges, the power detection signal Vpg goes high, indicating that the optical module connection is stable.

[0063] In this embodiment, the optical module with the aforementioned switching circuit 100 can detect the stability of the power supply. If the power supply becomes unstable during the phase when the timing signal Vtmr is increasing, the timing signal Vtmr will be reset to the set value and increased again. That is, the power supply must remain stable for a period of time in order for the timing signal Vtmr to increase to the first voltage threshold Vt1. This process corresponds to the insertion and removal phase of the optical module. When the insertion of the optical module is unstable, the conventional switching circuit 100 will be mistakenly turned on. The switching circuit 100 will be in the open state. At this time, the power supply will be powered on again, causing the inrush current to exceed the standard. The problem of inrush current when the optical module is unstable during insertion and removal is solved by increasing the setting of the timing signal Vtmr.

[0064] Figure 5 shows the signal waveforms of a switching circuit 100 according to an embodiment of this application. The waveforms of each signal in Figure 5 are explained with reference to the structure of the switching circuit 100 shown in Figure 2. The scenario shown in Figure 5 is a power outage caused by power instability during the increasing phase of the soft-start signal Vss.

[0065] From time t0 to time t1, the input signal Vin appears and stabilizes at a certain value, the enable signal Vm appears and stabilizes at a certain value, and the timing signal Vtmr begins to increase.

[0066] From time t1 to time t2, due to potential power instability during the insertion and removal of the optical module, the input signal Vin fluctuates at time t1, resulting in a power-down and subsequent power-up. After the power-down, the timing signal Vtmr decreases to 0, then begins to increase again after a period of time. At time t2, the timing signal Vtmr increases to the first voltage threshold Vt1.

[0067] From time t2 to time t3, the soft-start signal Vss begins to increase, and the control circuit 10 controls the first transistor M1 to start conducting. The output signal Vout increases as the soft-start signal Vss increases.

[0068] In this application, the device with the aforementioned switching circuit 100 can detect the stability of the power supply. If the power supply becomes unstable during the phase when the timing signal Vtmr is increasing, the timing signal Vtmr will be reset to the set value and increased again. That is, the power supply must remain stable for a period of time in order for the timing signal Vtmr to increase to the first voltage threshold Vt1. This process corresponds to the insertion and removal phase of the optical module. When the insertion of the optical module is unstable, the conventional switching circuit 100 will be mistakenly turned on. The switching circuit 100 will be in the open state. At this time, the secondary power supply will cause the inrush current to exceed the standard. By increasing the setting of the timing signal Vtmr, the problem of inrush current when the optical module is unstable during insertion and removal is solved.

[0069] Figure 6 shows a signal waveform diagram of a switching circuit 100 according to an embodiment of this application. The waveforms of each signal in Figure 6 are explained with reference to the structure of the switching circuit 100 shown in Figure 2. The scenario shown in Figure 6 is a scenario where the input signal Vin exhibits signal fluctuations.

[0070] From time t0 to time t1, the input signal Vin drops below the normal operating range of the system, but remains above the third reference voltage V3 of the undervoltage protection unit 40, thus not triggering the undervoltage protection mechanism. For example, the normal range is 2.9V-3V, and the third reference voltage V3 is set to 2.85V. At this time, the input signal Vin is less than 2.9V but greater than 2.85V. Starting from time t0, the time interval between time t1 and time t0 is less than a preset delay time, and the output voltage remains essentially unchanged (the output voltage will also slightly decrease between time t1 and time t0, not shown in the figure). For example, this preset delay time can be 16ms.

[0071] From time t1 to time t2, the input signal Vin returns to its normal range.

[0072] From time t2 to time t3, the input signal Vin drops to a value lower than the normal range, but is higher than the third reference voltage V3, so the undervoltage protection mechanism is not triggered. Starting from time t2, after the input signal Vin has been lower than the normal range for a longer than the preset delay time, the control circuit 10 controls the first transistor M1 to turn off, and the output voltage gradually decreases to 0, and the input current decreases to 0.

[0073] In some embodiments, when the fluctuation of the input signal Vin is greater than the normal range but less than the second reference voltage V2 of the overvoltage protection unit 30, the processing mechanism is similar to that shown in Figure 6 above. When the input signal Vin increases to a value greater than the normal range during normal system operation but less than the second reference voltage V2 of the overvoltage protection unit 30, the overvoltage protection mechanism is not triggered. For example, the normal range is 2.9V-3V, and the second reference voltage V2 is set to 3.8V. At this time, the input signal Vin is greater than 3V but less than 3.8V. Timing begins from the moment the input signal Vin is greater than 3V but less than 3.8V. If the time interval is less than a preset delay time, the output voltage remains essentially unchanged. If the time interval is greater than the preset delay time, the output voltage remains essentially unchanged. For example, the preset delay time can be 16ms.

[0074] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional circuits and modules is merely an example. In practical applications, the above functions can be assigned to different functional circuits and modules as needed, that is, the internal structure of the device can be divided into different functional circuits or modules to complete all or part of the functions described above. The functional circuits and modules in the embodiments can be integrated into one processing circuit, or each circuit can exist physically separately, or two or more circuits can be integrated into one circuit. The integrated circuit can be implemented in hardware or software. Furthermore, the specific names of the functional circuits and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the circuits and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0075] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A switching circuit, characterized in that, include: The input terminal receives input signals. The output terminal provides the output signal; A first transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the input terminal and the second terminal is coupled to the output terminal; The timing control terminal receives a timing signal, wherein the timing signal is generated based on the input signal; The soft-start control terminal receives a soft-start signal, wherein the soft-start signal is generated based on the timing signal; and The control circuit has a first input terminal coupled to a timing control terminal to receive the timing signal, a second input terminal coupled to a soft-start control terminal to receive the soft-start signal, and a first output terminal coupled to the control terminal of the first transistor. When the input signal is input to the input terminal, the control circuit receives the timing signal from the timing control terminal; when the timing signal increases to the first voltage threshold, the soft-start control terminal receives the soft-start signal, and the control circuit controls the conduction level of the first transistor according to the soft-start signal.

2. The switching circuit according to claim 1, characterized in that, When the timing signal reaches the first voltage threshold, the control circuit controls the first transistor to start conducting, the timing control terminal discharges, and the timing signal drops to the set value; when the control circuit controls the first transistor to be fully conducted, the soft-start control terminal discharges, and the soft-start signal drops to the set value.

3. The switching circuit according to claim 1, characterized in that, The time interval between the next time the timing signal reaches the first voltage threshold and the previous time it reaches the first voltage threshold is a preset waiting time.

4. The switching circuit according to claim 3, characterized in that, The preset waiting time ranges from 100us to 256us.

5. The switching circuit according to claim 1, characterized in that, The timing control terminal of the switching circuit is electrically connected to an external timing capacitor. The timing signal increases when the timing capacitor is charged. The switching circuit also includes: The first current source has an output terminal coupled to the timing control terminal, and the output terminal of the first current source is also coupled to the first input terminal of the control circuit. The timing capacitor is coupled between the reference ground and the timing control terminal; when the input signal remains within the voltage preset range for a first preset time, the control circuit controls the first current source to charge the timing capacitor to increase the timing signal, and the timing signal gradually increases to the first voltage threshold.

6. The switching circuit according to claim 5, characterized in that, It also includes a second transistor having a first terminal coupled to the output terminal of the first current source, a second terminal coupled to a reference ground, and a control terminal for receiving a discharge control signal; The discharge control signal is generated based on the input signal, the timing signal, and the soft-start signal. The second transistor is turned on or off under the control of the discharge control signal. When the discharge control signal is at a logic high potential, the second transistor is turned on, the timing control terminal discharges, and the timing signal drops to 0.

7. The switching circuit according to claim 1, characterized in that, The soft-start control terminal of the switching circuit is electrically connected to an external soft-start capacitor. When the soft-start capacitor is charged, the soft-start signal increases. The switching circuit also includes: The second current source has an output terminal coupled to the soft-start control terminal, and the output terminal of the second current source is also coupled to the second input terminal of the control circuit; The soft-start control terminal is also coupled to the first terminal of the soft-start capacitor, and the second terminal of the soft-start capacitor is coupled to the reference ground; when the timing signal reaches the first voltage threshold, the control circuit controls the second current source to charge the soft-start capacitor to increase the soft-start signal; when the soft-start signal reaches the second voltage threshold, the first transistor is fully turned on.

8. The switching circuit according to claim 7, characterized in that, It also includes a third transistor; the third transistor has a first terminal coupled to the output terminal of the second current source, a second terminal coupled to a reference ground, and a control terminal for receiving a discharge control signal; the third transistor is turned on or off under the control of the discharge control signal, the discharge control signal being generated based on the input signal, the timing signal, and the soft-start signal; The third transistor is turned on or off under the control of the discharge control signal. When the discharge control signal is at a logic high potential, the third transistor is turned on, the soft-start control terminal discharges, and the soft-start signal drops to 0.

9. The switching circuit according to claim 7, characterized in that, The switching circuit further includes a temperature control unit; the temperature control unit has an input terminal coupled to the control circuit and an output terminal coupled to the second current source; the temperature control unit controls the current value output by the second current source according to the ambient temperature of the switching circuit.

10. The switching circuit according to claim 7, characterized in that, The second current source includes N controlled constant current sources connected in parallel; each controlled constant current source has two states: on and off; the current output of the second current source is the sum of the currents of the controlled constant current sources in the on state, where N is an integer greater than or equal to 2. The number of controlled constant current sources in the ON state is determined based on the voltage value of the output signal. The higher the voltage value of the output signal, the more controlled constant current sources are in the ON state.

11. The switching circuit according to claim 10, characterized in that, The number of controlled constant current sources that are in the ON state among the N controlled constant current sources is determined based on the ambient temperature of the switching circuit.

12. The switching circuit according to claim 10, characterized in that, When the voltage value of the output signal is the first output voltage and the ambient temperature of the switching circuit is greater than the first temperature threshold, M controlled constant current sources are turned on. When the voltage value of the output signal is the first output voltage and the ambient temperature is less than or equal to the first temperature threshold, K controlled constant current sources are turned on, where 1≤M<K≤N, and M and K are both integers.

13. The switching circuit according to claim 1, characterized in that, The switching circuit further includes an enable control terminal for receiving an enable signal; wherein the enable signal is generated based on the input signal, and the magnitude of the enable signal characterizes the magnitude of the input signal; The switching circuit also includes an enable unit, an overvoltage protection unit, an undervoltage protection unit, and an AND logic circuit. The enabling unit is coupled between the enabling control terminal and the control circuit, and is used to generate an enabling feedback signal according to the enabling signal; when the enabling signal is greater than or equal to the first reference voltage, the enabling feedback signal outputs a logic high potential; The overvoltage protection unit is coupled between the input terminal of the switching circuit and the control circuit, and is used to generate an overvoltage feedback signal according to the input signal; when the input signal is less than or equal to the second reference voltage, the overvoltage feedback signal outputs a logic high potential; The undervoltage protection unit is coupled between the input terminal of the switching circuit and the control circuit, and is used to generate an undervoltage feedback signal according to the input signal; when the input signal is greater than or equal to the third reference voltage, the undervoltage feedback signal is at a logic high potential; The logic and circuit have a first input terminal for receiving an enable feedback signal, a second input terminal for receiving an overvoltage feedback signal, a third input terminal for receiving an undervoltage feedback signal, and an output terminal coupled to the control circuit. The logic and circuit generate a power-on control signal based on the enable feedback signal, the overvoltage feedback signal, and the undervoltage feedback signal. When the enable feedback signal, the overvoltage feedback signal, and the undervoltage feedback signal are all at a logic high potential, the power-on control signal is at a logic high potential, indicating that the input signal is within the preset voltage range.

14. The switching circuit according to claim 13, characterized in that, The enabling unit includes a first comparator, which has a non-inverting input terminal coupled to the enabling control terminal to receive the enabling signal, an inverting input terminal to receive a first reference voltage, and an output terminal to provide an enabling feedback signal. When the enabling signal is greater than or equal to the first reference voltage, the enabling feedback signal outputs a logic high level, indicating that the input signal is greater than a preset value. The overvoltage protection unit includes a second comparator, which has a non-inverting input terminal to receive a second reference voltage, an inverting input terminal coupled to the input terminal of the switching circuit, and an output terminal to provide an overvoltage feedback signal. The undervoltage protection unit includes a third comparator, which has a non-inverting input terminal coupled to the input terminal of the switching circuit, an inverting input terminal receiving a third reference voltage, and an output terminal providing an undervoltage feedback signal.

15. The switching circuit according to claim 1, characterized in that, The switching circuit also includes: A current detection terminal, wherein the current detection terminal outputs a second current; and A current detection unit is coupled between the current detection terminal and the control circuit; The current detection unit detects the first current between the input terminal of the switching circuit and the first terminal of the first transistor, generates a second current based on the first current, and outputs the second current to the current detection terminal.

16. The switching circuit according to claim 1, characterized in that, The switching circuit also includes a power detection unit and a power detection terminal; The power detection unit is coupled to the power detection terminal and is used to generate a power detection signal based on the input signal and the output signal. The power detection signal is used to characterize whether the first transistor between the input and output terminals of the switching circuit is stably turned on. When the first transistor is stably turned on, the switching circuit is in normal working condition and can provide a stable output voltage.

17. The switching circuit according to claim 16, characterized in that, The power detection unit includes: The fourth comparator has a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal receives a second input signal that has a preset difference from the input signal. The inverting input terminal receives the output signal output by the output terminal of the switching circuit. The output terminal provides a power feedback signal. The fourth transistor has a first terminal coupled to a power detection terminal, a second terminal coupled to a reference ground, and a control terminal for receiving a power feedback signal. When the second input signal is greater than or equal to the output signal, the power feedback signal is in a logic high state, the fourth transistor is turned on, and the power detection signal is in a logic low state, indicating that the first transistor between the input and output terminals of the switching circuit is not stably turned on; when the second input signal is less than the output signal, the power feedback signal is in a logic low state, the fourth transistor is turned off, and the power detection signal is in a logic high state, indicating that the first transistor between the input and output terminals of the switching circuit is stably turned on.

18. The switching circuit according to claim 1, characterized in that, The switching circuit further includes a fifth transistor, having a first terminal coupled to the output terminal, a second terminal coupled to a reference ground, and a control terminal for receiving a discharge control signal. The fifth transistor is turned on or off under the control of the discharge control signal, wherein the discharge control signal is generated based on the input signal, the timing signal and the soft-start signal. When the discharge control signal is at a logic high potential, the fifth transistor is turned on, the output terminal discharges, and the output signal drops to 0.

19. A switching system, characterized in that, include: The switching circuit as described in any one of claims 1 to 18; A timing capacitor has a first end coupled to a timing control terminal and a second end coupled to a reference ground; A soft-start capacitor has a first terminal coupled to the soft-start control terminal and a second terminal coupled to the reference ground.

20. An optical module, characterized in that, include: The input detection unit has an input terminal for receiving input signals and an output terminal for providing enable signals. The switching circuit as described in any one of claims 1 to 18; A timing capacitor has a first end coupled to a timing control terminal and a second end coupled to a reference ground; A soft-start capacitor has a first terminal coupled to the soft-start control terminal and a second terminal coupled to the reference ground.

21. A control method for a switching circuit, applicable to the switching circuit as described in any one of claims 1 to 18, characterized in that, include: Receive input signals; A timing signal is generated based on the input signal; A soft-start signal is generated based on the timing signal; The soft-start signal controls the turning on and off of the first transistor; When the input signal remains within a preset voltage range for a first preset time, the timing signal gradually increases to a first voltage threshold. When the timing signal reaches the first voltage threshold, the soft-start signal begins to increase. The control circuit controls the conduction degree of the first transistor to increase synchronously with the soft-start signal. When the first transistor is fully turned on, the output signal is equal to the input signal.

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