Data processing method and apparatus, and system

Abstract

Disclosed in embodiments of the present application are a data processing method and apparatus, and a system. Specifically, first data processing is performed on p first data streams that have undergone RS encoding, to obtain m second data streams, the first data processing comprising demultiplexing and alignment marker locking, wherein p=m or 2m, and m is an integer greater than or equal to 1. Second data processing is separately performed on the m second data streams to obtain m third data streams, the second data processing comprising convolutional interleaving. The convolutional interleaving is used for delaying, on the basis of three delay lines, bits in one data stream on which convolutional interleaving has not been performed, the bits in said one data stream are sequentially inputted into the three delay lines according to the sequence numbers of the three delay lines, d bits are inputted to and outputted from each delay line at a single time, and the three delay lines are respectively used for delaying 0 bits, Q×d bits, and 2×Q×d bits. When m=1, Q≥181; when m=2, Q≥91; when m=4, Q≥45; or when m=8, Q≥23.

Description

A data processing method, apparatus and system

[0001] This application claims priority to Chinese Patent Application No. 202510201499.0, filed on February 22, 2025, entitled "A Data Processing Method, Apparatus and System", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0003] Driven by technologies such as 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. Forward error correction (FEC) coding is used to correct errors in the transmitted data, resolving transmission errors and allowing the receiver to recover the original data sent by the transmitter from the received data.

[0004] A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, modulates the bit sequence resulting from the second FEC encoding to generate a corresponding modulation symbol sequence, and finally generates an optical signal based on the modulation symbol sequence, which is transmitted to the receiving end via optical fiber. The first FEC encoding is also called external code encoding, and the second FEC encoding is also called internal code encoding. Modulation is also called symbol mapping.

[0005] Typically, the transmitting processing module performs interleaving before the second FEC encoding to shuffle the data order, thereby enhancing the error correction performance of the cascaded FEC scheme. For direct detection transmission scenarios, existing technologies provide cascaded FEC schemes for 200G / lane transmission, but not for 400G / lane. Existing cascaded FEC schemes for 200G / lane transmission cannot be directly applied to 400G / lane transmission. Specifically, as the transmission rate of each channel increases, the amount of data allocated to each channel for the outer codewords increases, causing the interleaver in existing cascaded FEC to be unable to distribute the outer codewords into more inner codewords, thus affecting the overall error correction performance of the cascaded FEC scheme. For 400G / lane transmission scenarios, a low-latency, high-performance cascaded FEC scheme is urgently needed. Summary of the Invention

[0006] This application provides a data processing method, apparatus, and system that enable concatenated codes to have better performance, which is beneficial for hardware implementation. At the same time, it can reduce system latency and make it applicable to a wide range of transmission scenarios.

[0007] In a first aspect, embodiments of this application provide a data processing method applied at a transmitting end. Specifically, the transmitting end performs a first data processing on p first data streams encoded by Reed-Solomon (RS) to obtain m second data streams. Here, p = m or 2m, where m is an integer greater than or equal to 1. The first data processing includes demultiplexing and alignment flag locking. Furthermore, the transmitting end performs a second data processing on each of the m second data streams to obtain m third data streams. The second data processing includes convolutional interleaving; convolutional interleaving is used to delay bits in one data stream before convolutional interleaving according to three delay lines. Bits in the one data stream before convolutional interleaving are sequentially input to the three delay lines according to their numbers, with d bits input to each delay line and d bits output from each delay line at a time. The three delay lines are used to delay 0 bits, Q×d bits, and 2×Q×d bits, respectively.

[0008] Among them, the Ethernet service rate carried by m second data streams can be 400GEBASE-R, 800GBASE-R, 1.6TBASE-R, 3.2TBASE-R, etc., based on the nominal rate of 425.0 Gbits per second (b / s) for each second data stream. The value range of Q is provided below for different scenarios.

[0009] For example, m=1 means that the Ethernet service carried by m second data streams is at a rate of 400GEBASE-R, or that m second data streams carry 400GEBASE-R Ethernet service, i.e., a 400GBASE-R scenario, where Q≥181.

[0010] For example, m=2 means that the Ethernet service carried by m second data streams is at a rate of 800GBASE-R, or that m second data streams carry 800GEBASE-R Ethernet service, i.e., in the 800GBASE-R scenario, Q≥91.

[0011] For example, m=4, which means that the Ethernet service carried by m second data streams has a rate of 1.6TBASE-R, or that m second data streams carry 1.6TBASE-R Ethernet service, i.e., in the 1.6TBASE-R scenario, Q≥45.

[0012] For example, m=8, which is equivalent to the Ethernet service carried by m second data streams having a rate of 3.2TBASE-R, or equivalent to m second data streams carrying 3.2TBASE-R Ethernet service, i.e., in the 3.2TBASE-R scenario, Q≥23.

[0013] In this embodiment, RS encoding can be called external code encoding, and FEC encoding in the second data processing can be called internal code encoding. The RS symbol boundaries can be obtained before internal code encoding through the first data processing, allowing one RS symbol to be assigned to one internal codeword. Utilizing the burst correction performance of RS, the concatenated code can achieve better performance with a smaller interleaving depth. For a scenario where the nominal rate of the second data stream is 425.0 Gbits per second (b / s), this application provides a new convolutional interleaving method. Specifically, the three delay lines used in the convolutional interleaving are used to delay 0 bits, Q×d bits, and 2×Q×d bits, respectively, and the specific values ​​of Q are given for different scenarios. Through the design of the convolutional interleaving, every 12 consecutive symbols in the convolutionally interleaved data stream come from 12 RS codewords, resulting in better performance of the concatenated code, which is beneficial for hardware implementation. Simultaneously, it reduces system latency and can be used in a wider range of transmission scenarios. By combining the RS symbol boundaries obtained from the first data processing, an RS symbol can be assigned to an internal codeword. By utilizing the burst correction performance of RS, the concatenated code can achieve better performance with a smaller interleaving depth.

[0014] In some possible implementations, d = 40. Based on the obtained 4-symbol boundary, the 40 bits input to each delay line in a single pass come from 40 consecutive bits in a second data stream, corresponding to 4 RS symbols, i.e., one RS FEC 4 symbol (RS-FEC-symbol-quartet). By configuring an appropriate Q value, every 12 consecutive symbols in the convolutionally interleaved data stream can come from 12 RS codewords, resulting in better performance for the concatenated code.

[0015] In some possible implementations, the second data processing includes distribution, whereby the one data stream before distribution is processed to obtain 16 distributed data streams. This improves the concatenated code's resistance to colored noise for scenarios where the nominal rate of the second data stream is 425.0 Gbits per second (b / s).

[0016] In some possible implementations, the second data processing includes FEC encoding and inserting padding bits. In the data stream preceding the padding bits, 16 × N padding bits are inserted after every H FEC-encoded FEC codewords, where H is a positive integer multiple of 16. These 16 × N bits comprise 16 bit sequences, each of which consists of N bits. N = 128. The values ​​of the x-th to 127th bits in each of the N = 128 bits of the 16 bit sequences are provided below to allow the receiving end to use the frame alignment sequence in the padding bits for internal code synchronization. The x-th bit can also be referred to as bit x.

[0017] The values ​​of bits 127 to bit x in each of the N=128 bits of the 16-bit sequence are as follows:

[0018] In the 0th bit sequence, bits 127 to x = 124 are 0110 respectively;

[0019] In the first bit sequence, bits 127 to x = 124 are 0110 respectively;

[0020] In the second bit sequence, bits 127 to x = 124 are 1011 respectively;

[0021] In the third bit sequence, bits 127 to x = 124 are 0101 respectively;

[0022] In the 4th bit sequence, bits 127 to x = 124 are 0110 respectively;

[0023] In the 5th bit sequence, bits 127 to x = 124 are 0101 respectively;

[0024] In the 6th bit sequence, bits 127 to x = 124 are 0010 respectively;

[0025] In the 7th bit sequence, bits 127 to x = 124 are 1011 respectively;

[0026] In the 8th bit sequence, bits 127 to x = 126 are 0 and 1 respectively;

[0027] In the 9th bit sequence, bits 127 to x = 126 are 10 in sequence;

[0028] In the 10th bit sequence, bits 127 to x = 126 are 0 and 1 respectively;

[0029] In the 11th bit sequence, bits 127 to x = 126 are 00 respectively;

[0030] In the 12th bit sequence, bits 127 to x = 126 are 10 respectively;

[0031] In the 13th bit sequence, bits 127 to x = 126 are 10 respectively;

[0032] In the 14th bit sequence, bits 127 to x = 126 are 0 and 1 respectively;

[0033] In the 15th bit sequence, bits 127 to x = 126 are 10 in sequence.

[0034] In some possible implementations, the second data processing includes cyclic shifting. The following provides a specific method for cyclically shifting the 16 data streams before the 16 cyclic shifts, which can ensure that two bit pairs from the same RS codeword in the interleaved data are at least 8 symbols apart, thereby improving the burst resistance of the concatenated code.

[0035] The number of symbols cyclically shifted to the right for every 12 consecutive symbols in each of the 16 data streams before the cyclic shift is as follows:

[0036] In the fifth data stream of Article 0, every 12 consecutive symbols are cyclically shifted 0 symbols to the right;

[0037] In the fifth data stream of the first line, every 12 consecutive symbols are cyclically shifted 3 symbols to the right;

[0038] In the second data stream, every 12 consecutive symbols are cyclically shifted 6 symbols to the right;

[0039] In the fifth data stream of Article 3, every 12 consecutive symbols are cyclically shifted 9 symbols to the right;

[0040] In the fifth data stream of Article 4, every 12 consecutive symbols are cyclically shifted one symbol to the right;

[0041] Article 5: In the fifth data stream, every 12 consecutive symbols are cyclically shifted 4 symbols to the right;

[0042] In Article 6, every 12 consecutive symbols in the fifth data stream are cyclically shifted 7 symbols to the right;

[0043] In Article 7, the fifth data stream is shifted 10 symbols to the right in a circular shift pattern for every 12 consecutive symbols.

[0044] Article 8: In the fifth data stream, every 12 consecutive symbols are cyclically shifted 0 symbols to the right;

[0045] In Article 9, every 12 consecutive symbols in the fifth data stream are cyclically shifted 3 symbols to the right;

[0046] In the fifth data stream of Article 10, every 12 consecutive symbols are cyclically shifted 6 symbols to the right;

[0047] In Article 11, every 12 consecutive symbols in the fifth data stream are cyclically shifted 9 symbols to the right;

[0048] In the 12th data stream, every 12 consecutive symbols are cyclically shifted one symbol to the right;

[0049] Article 13, in the fifth data stream, every 12 consecutive symbols are cyclically shifted 4 symbols to the right;

[0050] Article 14. In the fifth data stream, every 12 consecutive symbols are cyclically shifted 7 symbols to the right;

[0051] In Article 15, every 12 consecutive symbols in the fifth data stream are cyclically shifted 10 symbols to the right.

[0052] In some possible implementations, the nominal rate of each first data stream is 425 Gbits per second, m = p, and each first data stream is demultiplexed to obtain t data streams, t = 2, 4, or 16. Based on the nominal rate of 425 Gbits per second for each first data stream, the transmission rate of each channel is increased while maintaining good performance of the concatenated code, and the system latency is kept low. Furthermore, multiple possible implementations of demultiplexing are provided to facilitate adaptation to 400GBASE-R, 800GBASE-R, 1.6TBASE-R, and 3.2TBASE-R scenarios, thereby achieving good performance of the concatenated code and low system latency in various transmission scenarios.

[0053] In some possible implementations, p = 1 in the 400GBASE-R scenario and p = 2 in the 800GBASE-R scenario; in either the 400GBASE-R or 800GBASE-R scenario, performing first data processing on p first data streams to obtain m second data streams includes: demultiplexing each of the p first data streams to obtain 16 fourth data streams, for a total of 16p fourth data streams, with the demultiplexing granularity being RS symbol pairs; and performing alignment identifier locking on the 16 fourth data streams to obtain 1 second data stream, for a total of m second data streams.

[0054] In some possible implementations, in a 1.6TBASE-R scenario, p = 4; in a 3.2TBASE-R scenario, p = 8; performing first data processing on p first data streams to obtain m second data streams includes: demultiplexing each of the p first data streams to obtain 4 fourth data streams, for a total of 4p fourth data streams, with the demultiplexing granularity being RS-FEC 4 symbols; and aligning and locking the 4 fourth data streams to obtain 1 second data stream, for a total of 4 second data streams.

[0055] In some possible implementations, in the 3.2TBASE-R scenario, p = 8; performing first data processing on p first data streams to obtain m second data streams includes: demultiplexing each of the 8 first data streams to obtain 2 fourth data streams, resulting in a total of 16 fourth data streams, with the demultiplexing granularity being RS-FEC 4 symbols; and performing alignment identifier locking on the 2 fourth data streams to obtain 1 second data stream, resulting in a total of 4 second data streams.

[0056] In some possible implementations, in a 400GBASE-R scenario, p=1; in an 800GBASE-R scenario, p=2; performing first data processing on any one of the p first data streams includes: demultiplexing any one of the first data streams to obtain 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; aligning and locking the 16 fourth data streams to obtain 16 fifth data streams, each corresponding to one of the 16 physical coding sublayer (PCS) channel data streams; deskewing the 16 fifth data streams to obtain 16 sixth data streams; delaying the sixth data streams whose corresponding PCS channel numbers are odd to obtain 16 seventh data streams; and multiplexing the 16 seventh data streams to obtain one second data stream, with the multiplexing granularity being RS symbol pairs.

[0057] In some possible implementations, in a 1.6TBASE-R scenario, p=4, and in a 3.2TBASE-R scenario, p=8; performing first data processing on any one of the p first data streams includes: demultiplexing any one of the first data streams to obtain four fourth data streams, with the demultiplexing granularity being RS-FEC 4 symbols; performing alignment identifier locking on the four fourth data streams to obtain four fifth data streams; deskewing the four fifth data streams to obtain four sixth data streams; and multiplexing the four sixth data streams to obtain one second data stream, with the multiplexing granularity being RS-FEC 4 symbols.

[0058] In some possible implementations, the nominal rate of each first data stream is 212.5 Gbits per second, and the first data processing also includes multiplexing, where p = 2m. Because the first data processing includes multiplexing, the nominal rate of each second data stream is 425 Gbits per second. Thus, even with the increased transmission rate of each channel, the concatenated code still maintains good performance, while also reducing system latency.

[0059] In some possible implementations, in a 400GBASE-R scenario, p=2, performing first data processing on p first data streams to obtain m second data streams includes: demultiplexing each of the two first data streams to obtain eight fourth data streams, resulting in a total of 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; performing alignment identifier locking on the eight fourth data streams to obtain one fifth data stream, resulting in a total of two fifth data streams, with the RS-FEC 4 symbol boundaries of each of the two fifth data streams already determined; and multiplexing the two fifth data streams to obtain one second data stream, with the multiplexing granularity being a positive integer multiple of the RS-FEC 4 symbols.

[0060] In some possible implementations, in a 400GBASE-R scenario, where p=2, performing first data processing on p first data streams to obtain m second data streams includes: demultiplexing each of the two first data streams to obtain eight fourth data streams, resulting in a total of 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; aligning and locking the eight fourth data streams to obtain eight fifth data streams, resulting in a total of 16 fifth data streams, with each of the 16 fifth data streams corresponding to 16 PCS channel data streams; deskewing the 16 fifth data streams to obtain 16 sixth data streams; delaying the sixth data streams whose corresponding PCS channel numbers are odd among the 16 sixth data streams to obtain 16 seventh data streams; and multiplexing the 16 seventh data streams to obtain one second data stream, with the multiplexing granularity being RS symbol pairs.

[0061] In some possible implementations, in a 400GBASE-R scenario, p=2, performing first data processing on p first data streams to obtain m second data streams includes: demultiplexing each of the p first data streams to obtain 8 fourth data streams, resulting in a total of 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; performing alignment identifier locking on the 8 fourth data streams to obtain 8 fifth data streams, resulting in a total of 16 fifth data streams; deskewing the 16 fifth data streams to obtain 16 sixth data streams; delaying the sixth data streams whose corresponding PCS channel numbers are odd among the 16 sixth data streams to obtain 16 seventh data streams; and performing first multiplexing on every 8 seventh data streams among the 16 seventh data streams to obtain 1 eighth data stream, resulting in a total of 2 eighth data streams, with the first multiplexing granularity being RS symbol pairs, and the RS-FEC of each of the 2 eighth data streams being... The 4-symbol boundary has been determined; the two eighth data streams are multiplexed a second time to obtain one second data stream, and the granularity of the second multiplexing is a positive integer multiple of the RS-FEC 4-symbol.

[0062] In some possible implementations, in an 800GBASE-R scenario, p=4, the four first data streams include two groups of first data streams, and each group of first data streams includes two first data streams. First data processing on any one group of first data streams includes: demultiplexing each first data stream in any one group to obtain eight fourth data streams, resulting in a total of 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; aligning and locking the eight fourth data streams to obtain eight fifth data streams, resulting in a total of 16 fifth data streams; deskewing the 16 fifth data streams to obtain 16 sixth data streams; delaying the sixth data streams whose corresponding PCS channel numbers are odd to obtain 16 seventh data streams; and multiplexing the 16 seventh data streams to obtain one second data stream, with the multiplexing granularity being RS symbol pairs.

[0063] In some possible implementations, in an 800GBASE-R scenario, p=4, the four first data streams comprise two groups of first data streams, each group of first data streams comprises two first data streams, and the first data processing for any one group of first data streams includes: demultiplexing each of the first data streams in any one group to obtain eight fourth data streams, resulting in a total of 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; and performing alignment identifier locking on the eight fourth data streams. Eight fifth data streams are obtained, resulting in a total of 16 fifth data streams. These 16 fifth data streams are de-skewed to obtain 16 sixth data streams. The sixth data streams with odd PCS channel numbers are delayed to obtain 16 seventh data streams. Every eight seventh data streams are multiplexed in the first multiplexing process to obtain one eighth data stream, resulting in a total of two eighth data streams. The granularity of the first multiplexing is RS symbol pairs, and the RS-FEC 4 symbol boundaries of each of the two eighth data streams have been determined. The two eighth data streams are then multiplexed in the second multiplexing process to obtain one second data stream. The granularity of the second multiplexing is a positive integer multiple of the RS-FEC 4 symbols.

[0064] In some possible implementations, in a 1.6TBASE-R scenario, p=8, the 8 first data streams include 4 groups of first data streams, each group of first data streams includes 2 first data streams, and the first data processing for any group of first data streams includes: demultiplexing each first data stream in any group of first data streams to obtain 2 fourth data streams, for a total of 4 fourth data streams, with the demultiplexing granularity being RS-FEC 4 symbols; aligning and locking the 2 fourth data streams to obtain 2 fifth data streams, for a total of 4 fifth data streams, with the RS-FEC 4 symbol boundaries of each of the 4 fifth data streams already determined; deskewing the 4 fifth data streams to obtain 4 sixth data streams; and multiplexing the 4 sixth data streams to obtain 1 second data stream, with the multiplexing granularity being a positive integer multiple of RS-FEC 4 symbols.

[0065] In some possible implementations, in a 3.2TBASE-R scenario, p=16, the 16 first data streams include 8 groups of first data streams, each of the 8 groups of first data streams includes 2 first data streams, and the first data processing for any group of the 8 groups of first data streams includes: demultiplexing each of the first data streams in any group of first data streams to obtain 2 fourth data streams, for a total of 4 fourth data streams, the granularity of demultiplexing being RS-FEC 4 symbols; aligning and locking the 2 fourth data streams to obtain 2 fifth data streams, for a total of 4 fifth data streams, the RS-FEC 4 symbol boundary of each of the 4 fifth data streams has been determined; deskewing the 4 fifth data streams to obtain 4 sixth data streams; and multiplexing the 4 sixth data streams to obtain 1 second data stream, the granularity of multiplexing being a positive integer multiple of RS-FEC 4 symbols.

[0066] In some possible implementations, the second data processing includes FEC encoding, where the FEC-encoded FEC codeword comprises N bits, and the N bits include K information bits, where N = 128 and K = 120.

[0067] In some possible implementations, the K / 10 RS symbols corresponding to the K information bits in the FEC codeword obtained by FEC encoding are respectively derived from K / 10 RS codewords, where K is a positive integer multiple of 10, thereby improving the tolerance of convolutional interleaving to colored noise.

[0068] In some possible implementations, every 12 consecutive RS symbols in the convolutionally interleaved data stream are derived from 12 RS codewords, resulting in better performance for concatenated FEC coding.

[0069] In some possible implementations, the 0th delay line of the three delay lines is used to delay 0 bits, the 1st delay line of the three delay lines is used to delay Q×d bits, and the 2nd delay line of the three delay lines is used to delay 2×Q×d bits. Alternatively, the 0th delay line of the three delay lines is used to delay 2×Q×d bits, the 1st delay line of the three delay lines is used to delay Q×d bits, and the 2nd delay line of the three delay lines is used to delay 0 bits.

[0070] Secondly, embodiments of this application provide a data processing method applied at a transmitting end. Specifically, the transmitting end performs second data processing on m second data streams to obtain m third data streams, wherein the m second data streams are obtained by first data processing on p first data streams encoded by RS. p = m or 2m, where m is an integer greater than or equal to 1. The first data processing includes demultiplexing and alignment identifier locking. The second data processing includes convolutional interleaving; convolutional interleaving is used to delay the bits in one data stream before convolutional interleaving according to the three delay lines. The bits in the one data stream before convolutional interleaving are sequentially input into the three delay lines according to the sequence number of the three delay lines, with d bits input to each delay line at a time and d bits output from each delay line at a time. The three delay lines are used to delay 0 bits, Q×d bits, and 2×Q×d bits, respectively.

[0071] Among them, the Ethernet service rate carried by m second data streams can be 400GEBASE-R, 800GBASE-R, 1.6TBASE-R, 3.2TBASE-R, etc., based on the nominal rate of 425.0 Gbits per second (b / s) for each second data stream. The value range of Q is provided below for different scenarios.

[0072] For example, m=1 means that the Ethernet service carried by m second data streams is at a rate of 400GEBASE-R, or that m second data streams carry 400GEBASE-R Ethernet service, i.e., a 400GBASE-R scenario, where Q≥181.

[0073] For example, m=2 means that the Ethernet service carried by m second data streams is at a rate of 800GBASE-R, or that m second data streams carry 800GEBASE-R Ethernet service, i.e., in the 800GBASE-R scenario, Q≥91.

[0074] For example, m=4, which means that the Ethernet service carried by m second data streams has a rate of 1.6TBASE-R, or that m second data streams carry 1.6TBASE-R Ethernet service, i.e., in the 1.6TBASE-R scenario, Q≥45.

[0075] For example, m=8, which is equivalent to the Ethernet service carried by m second data streams having a rate of 3.2TBASE-R, or equivalent to m second data streams carrying 3.2TBASE-R Ethernet service, i.e., in the 3.2TBASE-R scenario, Q≥23.

[0076] In some possible implementations, the nominal rate of each first data stream is 425 gigabits per second, m = p, and each first data stream is demultiplexed to obtain t data streams, t = 2, 4 or 16.

[0077] In some possible implementations, p = 1 in the 400GBASE-R scenario and p = 2 in the 800GBASE-R scenario. In either the 400GBASE-R or 800GBASE-R scenario, one second data stream is obtained by locking 16 fourth data streams through alignment flags. The 16 fourth data streams are obtained by demultiplexing each of the p first data streams, with the demultiplexing granularity being RS symbol pairs.

[0078] In some possible implementations, p = 4 in the 1.6TBASE-R scenario and p = 8 in the 3.2TBASE-R scenario. One second data stream is obtained by locking four fourth data streams through alignment flags. The four fourth data streams are obtained by demultiplexing each of the p first data streams, with the demultiplexing granularity being RS-FEC 4 symbols.

[0079] In some possible implementations, in the 3.2TBASE-R scenario, p=8, one second data stream is obtained by locking two fourth data streams through alignment identifiers, and the two fourth data streams are obtained by demultiplexing each of the eight first data streams, with the demultiplexing granularity being RS-FEC 4 symbols.

[0080] In some possible implementations, in a 400GBASE-R scenario, p=1; in an 800GBASE-R scenario, p=2; one second data stream is obtained by multiplexing 16 seventh data streams, with the multiplexing granularity being RS symbol pairs; the 16 seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the 16 sixth data streams; the 16 sixth data streams are obtained by de-skewing 16 fifth data streams; the 16 fifth data streams are obtained by locking the alignment flags of 16 fourth data streams; the 16 fifth data streams correspond to 16 PCS channel data streams respectively; the 16 fifth data streams are obtained by locking the alignment flags of 16 fourth data streams; and the 16 fourth data streams are obtained by demultiplexing any one of the p first data streams, with the demultiplexing granularity being RS symbol pairs.

[0081] In some possible implementations, in a 1.6TBASE-R scenario, p=4, and in a 3.2TBASE-R scenario, p=8; one second data stream is obtained by multiplexing four sixth data streams with a multiplexing granularity of RS-FEC 4 symbols; four sixth data streams are obtained by deskewing four fifth data streams; four fifth data streams are obtained by locking four fourth data streams with alignment flags; and four fourth data streams are obtained by demultiplexing any one of the p first data streams with a demultiplexing granularity of RS-FEC 4 symbols.

[0082] In some possible implementations, the nominal rate of each first data stream is 212.5 gigabits per second, and the first data processing also includes multiplexing, p = 2m.

[0083] In some possible implementations, in a 400GBASE-R scenario, p=2, one second data stream is obtained by multiplexing two fifth data streams, with the multiplexing granularity being a positive integer multiple of RS-FEC 4 symbols. Any one fifth data stream is obtained by locking eight fourth data streams through alignment flags. The eight fourth data streams are obtained by demultiplexing each of the two first data streams, with the demultiplexing granularity being RS symbol pairs.

[0084] In some possible implementations, in a 400GBASE-R scenario, p=2, one second data stream is obtained by multiplexing 16 seventh data streams, with the multiplexing granularity being RS symbol pairs; the 16 seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the 16 sixth data streams; the 16 sixth data streams are obtained by de-skewing 16 fifth data streams; eight of the 16 fifth data streams are obtained by locking the alignment flags of eight fourth data streams; and the eight fourth data streams are obtained by demultiplexing each of the two first data streams, with the demultiplexing granularity being RS symbol pairs.

[0085] In some possible implementations, in a 400GBASE-R scenario, p=2, one second data stream is obtained by second multiplexing of two eighth data streams, the granularity of the second multiplexing being a positive integer multiple of RS-FEC 4 symbols; one of the two eighth data streams is obtained by first multiplexing of every eight of the sixteen seventh data streams, the granularity of the first multiplexing being RS symbol pairs; the sixteen seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the sixteen sixth data streams; the sixteen sixth data streams are obtained by de-skewing the sixteen fifth data streams; eight of the sixteen fifth data streams are obtained by alignment flag locking of eight fourth data streams; and the eight fourth data streams are obtained by demultiplexing each of the first data streams in p first data streams, the granularity of the demultiplexing being RS symbol pairs.

[0086] In some possible implementations, in an 800GBASE-R scenario, p=4, the four first data streams comprise two groups of first data streams, and each group of first data streams comprises two first data streams. One second data stream is obtained by multiplexing 16 seventh data streams, with the multiplexing granularity being RS symbol pairs. The 16 seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the 16 sixth data streams. The 16 sixth data streams are obtained by de-skewing 16 fifth data streams. Eight of the 16 fifth data streams are obtained by locking the alignment flags of eight fourth data streams. The eight fourth data streams are obtained by demultiplexing each first data stream in any group of first data streams, with the demultiplexing granularity being RS symbol pairs.

[0087] In some possible implementations, in an 800GBASE-R scenario, p=4, the four first data streams comprise two groups of first data streams, and each group of first data streams comprises two first data streams. One second data stream is obtained by second multiplexing two eighth data streams, with the granularity of the second multiplexing being a positive integer multiple of RS-FEC 4 symbols. One of the two eighth data streams is obtained by first multiplexing eight of the sixteen seventh data streams, with the granularity of the first multiplexing being RS symbol pairs. The sixteen seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the sixteen sixth data streams. The sixteen sixth data streams are obtained by de-skewing the sixteen fifth data streams. Eight of the sixteen sixth data streams are obtained by aligning and locking eight fourth data streams. The eight fourth data streams are obtained by demultiplexing each of the first data streams in any group of first data streams, with the granularity of the demultiplexing being RS symbol pairs.

[0088] In some possible implementations, in a 1.6TBASE-R scenario, p=8, the 8 first data streams comprise 4 groups of first data streams, and each of the 4 groups comprises 2 first data streams. One second data stream is obtained by multiplexing 4 sixth data streams, with the multiplexing granularity being a positive integer multiple of RS-FEC 4 symbols. The 4 sixth data streams are obtained by de-skewing 4 fifth data streams. Two of the 4 fifth data streams are obtained by alignment and locking 2 fourth data streams. The two fourth data streams are obtained by demultiplexing each of the first data streams in any group, with the demultiplexing granularity being RS-FEC 4 symbols.

[0089] In some possible implementations, in a 3.2TBASE-R scenario, p=16, the 16 first data streams comprise 8 groups of first data streams, and each of the 8 groups of first data streams comprises 2 first data streams. One second data stream is obtained by multiplexing 4 sixth data streams, with the multiplexing granularity being a positive integer multiple of RS-FEC 4 symbols. The 4 sixth data streams are obtained by de-skewing 4 fifth data streams. Two of the 4 fifth data streams are obtained by aligning and locking 2 fourth data streams. The 2 fourth data streams are obtained by demultiplexing each of the first data streams in any group of first data streams, with the demultiplexing granularity being RS-FEC 4 symbols.

[0090] Thirdly, embodiments of this application provide a data processing method applied at a receiving end. Specifically, the receiving end receives m third data streams. The m third data streams are obtained by processing m second data streams through second data processing. The m second data streams are obtained by processing p first data streams encoded by RS through first data processing, where p = m or 2m, and m is an integer greater than or equal to 1. The first data processing includes demultiplexing and alignment identifier locking. The second data processing includes convolutional interleaving and FEC encoding. Convolutional interleaving is used to delay the bits in one data stream before convolutional interleaving according to the three delay lines. The bits in the one data stream before convolutional interleaving are sequentially input into the three delay lines according to the sequence number of the three delay lines, with d bits input to each delay line at a time and d bits output from each delay line at a time. The three delay lines are used to delay 0 bits, Q×d bits, and 2×Q×d bits, respectively.

[0091] Among them, the Ethernet service rate carried by m second data streams can be 400GEBASE-R, 800GBASE-R, 1.6TBASE-R, 3.2TBASE-R, etc., based on the nominal rate of 425.0 Gbits per second (b / s) for each second data stream. The value range of Q is provided below for different scenarios.

[0092] For example, m=1 means that the Ethernet service carried by m second data streams is at a rate of 400GEBASE-R, or that m second data streams carry 400GEBASE-R Ethernet service, i.e., a 400GBASE-R scenario, where Q≥181.

[0093] For example, m=2 means that the Ethernet service carried by m second data streams is at a rate of 800GBASE-R, or that m second data streams carry 800GEBASE-R Ethernet service, i.e., in the 800GBASE-R scenario, Q≥91.

[0094] For example, m=4, which means that the Ethernet service carried by m second data streams has a rate of 1.6TBASE-R, or that m second data streams carry 1.6TBASE-R Ethernet service, i.e., in the 1.6TBASE-R scenario, Q≥45.

[0095] For example, m=8, which is equivalent to the Ethernet service carried by m second data streams having a rate of 3.2TBASE-R, or equivalent to m second data streams carrying 3.2TBASE-R Ethernet service, i.e., in the 3.2TBASE-R scenario, Q≥23.

[0096] In some possible implementations, the nominal rate of each first data stream is 425 gigabits per second, where m = p.

[0097] In some possible implementations, the nominal rate of each first data stream is 212.5 gigabits per second, and the first data processing also includes multiplexing, p = 2m.

[0098] Fourthly, embodiments of this application provide a data processing apparatus. The data processing apparatus includes a first processing unit and a second processing unit. The first processing unit is used to: perform first data processing on p first data streams encoded by Reed-Solomon RS to obtain m second data streams, where p = m or 2m, and m is an integer greater than or equal to 1. The first data processing includes demultiplexing and alignment identifier locking. The second processing unit is used to: perform second data processing on the m second data streams respectively to obtain m third data streams. The second data processing includes convolutional interleaving; the convolutional interleaving is used to delay bits in one data stream before convolutional interleaving according to three delay lines. Bits in the one data stream before convolutional interleaving are sequentially input to the three delay lines according to their sequence numbers, with d bits input to each delay line at a time and d bits output from each delay line at a time. The three delay lines are used to delay 0 bits, Q×d bits, and 2×Q×d bits, respectively.

[0099] Among them, the Ethernet service rate carried by m second data streams can be 400GEBASE-R, 800GBASE-R, 1.6TBASE-R, 3.2TBASE-R, etc., based on the nominal rate of 425.0 Gbits per second (b / s) for each second data stream. The value range of Q is provided below for different scenarios.

[0100] For example, m=1 means that the Ethernet service carried by m second data streams is at a rate of 400GEBASE-R, or that m second data streams carry 400GEBASE-R Ethernet service, i.e., a 400GBASE-R scenario, where Q≥181.

[0101] For example, m=2 means that the Ethernet service carried by m second data streams is at a rate of 800GBASE-R, or that m second data streams carry 800GEBASE-R Ethernet service, i.e., in the 800GBASE-R scenario, Q≥91.

[0102] For example, m=4, which means that the Ethernet service carried by m second data streams has a rate of 1.6TBASE-R, or that m second data streams carry 1.6TBASE-R Ethernet service, i.e., in the 1.6TBASE-R scenario, Q≥45.

[0103] For example, m=8, which is equivalent to the Ethernet service carried by m second data streams having a rate of 3.2TBASE-R, or equivalent to m second data streams carrying 3.2TBASE-R Ethernet service, i.e., in the 3.2TBASE-R scenario, Q≥23.

[0104] In some possible implementations, d = 40.

[0105] In some possible implementations, the second data processing includes distribution, wherein one data stream prior to distribution is processed to obtain 16 distributed data streams.

[0106] In some possible implementations, the second data processing includes FEC encoding and inserting padding bits, wherein 16×N padding bits are inserted after every H FEC codewords encoded by the FEC in one data stream before the insertion of padding bits, where H is a positive integer multiple of 16, and the 16×N bits include 16 bit sequences, each of the 16 bit sequences including N bits.

[0107] The values ​​of bits 127 to bit x in each of the N=128 bits of the 16-bit sequence are as follows:

[0108] In the 0th bit sequence, bits 127 to x = 124 are 0110 respectively;

[0109] In the first bit sequence, bits 127 to x = 124 are 0110 respectively;

[0110] In the second bit sequence, bits 127 to x = 124 are 1011 respectively;

[0111] In the third bit sequence, bits 127 to x = 124 are 0101 respectively;

[0112] In the 4th bit sequence, bits 127 to x = 124 are 0110 respectively;

[0113] In the 5th bit sequence, bits 127 to x = 124 are 0101 respectively;

[0114] In the 6th bit sequence, bits 127 to x = 124 are 0010 respectively;

[0115] In the 7th bit sequence, bits 127 to x = 124 are 1011 respectively;

[0116] In the 8th bit sequence, bits 127 to x = 126 are 0 and 1 respectively;

[0117] In the 9th bit sequence, bits 127 to x = 126 are 10 in sequence;

[0118] In the 10th bit sequence, bits 127 to x = 126 are 0 and 1 respectively;

[0119] In the 11th bit sequence, bits 127 to x = 126 are 00 respectively;

[0120] In the 12th bit sequence, bits 127 to x = 126 are 10 respectively;

[0121] In the 13th bit sequence, bits 127 to x = 126 are 10 respectively;

[0122] In the 14th bit sequence, bits 127 to x = 126 are 0 and 1 respectively;

[0123] In the 15th bit sequence, bits 127 to x = 126 are 10 in sequence.

[0124] In some possible implementations, the second data processing includes cyclic shifting, wherein the number of symbols cyclically shifted to the right for every 12 consecutive symbols in each of the 16 data streams preceding the cyclic shift is as follows:

[0125] In the fifth data stream of Article 0, every 12 consecutive symbols are cyclically shifted 0 symbols to the right;

[0126] In the fifth data stream of the first line, every 12 consecutive symbols are cyclically shifted 3 symbols to the right;

[0127] In the second data stream, every 12 consecutive symbols are cyclically shifted 6 symbols to the right;

[0128] In the fifth data stream of Article 3, every 12 consecutive symbols are cyclically shifted 9 symbols to the right;

[0129] In the fifth data stream of Article 4, every 12 consecutive symbols are cyclically shifted one symbol to the right;

[0130] Article 5: In the fifth data stream, every 12 consecutive symbols are cyclically shifted 4 symbols to the right;

[0131] In Article 6, every 12 consecutive symbols in the fifth data stream are cyclically shifted 7 symbols to the right;

[0132] In Article 7, the fifth data stream is shifted 10 symbols to the right in a circular shift pattern for every 12 consecutive symbols.

[0133] Article 8: In the fifth data stream, every 12 consecutive symbols are cyclically shifted 0 symbols to the right;

[0134] In Article 9, every 12 consecutive symbols in the fifth data stream are cyclically shifted 3 symbols to the right;

[0135] In the fifth data stream of Article 10, every 12 consecutive symbols are cyclically shifted 6 symbols to the right;

[0136] In Article 11, every 12 consecutive symbols in the fifth data stream are cyclically shifted 9 symbols to the right;

[0137] In the 12th data stream, every 12 consecutive symbols are cyclically shifted one symbol to the right;

[0138] Article 13, in the fifth data stream, every 12 consecutive symbols are cyclically shifted 4 symbols to the right;

[0139] Article 14. In the fifth data stream, every 12 consecutive symbols are cyclically shifted 7 symbols to the right;

[0140] In Article 15, every 12 consecutive symbols in the fifth data stream are cyclically shifted 10 symbols to the right.

[0141] In some possible implementations, the nominal rate of each first data stream is 425 gigabits per second, m = p, and each first data stream is demultiplexed to obtain t data streams, t = 2, 4 or 16.

[0142] In some possible implementations, p = 1 in the 400GBASE-R scenario and p = 2 in the 800GBASE-R scenario. In either the 400GBASE-R or 800GBASE-R scenario, the first processing unit is specifically used to: demultiplex each of the p first data streams to obtain 16 fourth data streams, for a total of 16p fourth data streams, with the demultiplexing granularity being RS symbol pairs; and to perform alignment identifier locking on the 16 fourth data streams to obtain 1 second data stream, for a total of m second data streams.

[0143] In some possible implementations, in a 1.6TBASE-R scenario, p = 4; in a 3.2TBASE-R scenario, p = 8; the first processing unit is specifically used to: demultiplex each of the p first data streams to obtain 4 fourth data streams, for a total of 4p fourth data streams, with the demultiplexing granularity being RS-FEC 4 symbols; and perform alignment identifier locking on the 4 fourth data streams to obtain 1 second data stream, for a total of 4 second data streams.

[0144] In some possible implementations, in the 3.2TBASE-R scenario, p=8; the first processing unit is specifically used to: demultiplex each of the 8 first data streams to obtain 2 fourth data streams, for a total of 16 fourth data streams, with the demultiplexing granularity being RS-FEC 4 symbols; and to perform alignment identifier locking on the 2 fourth data streams to obtain 1 second data stream, for a total of 4 second data streams.

[0145] In some possible implementations, p=1 in a 400GBASE-R scenario and p=2 in an 800GBASE-R scenario; the first processing unit is specifically used to: demultiplex any first data stream to obtain 16 fourth data streams, the demultiplexing granularity being RS symbol pairs; perform alignment identifier locking on the 16 fourth data streams to obtain 16 fifth data streams, the 16 fifth data streams corresponding to 16 PCS channel data streams respectively; deskew the 16 fifth data streams to obtain 16 sixth data streams; delay the sixth data streams whose corresponding PCS channel numbers are odd to obtain 16 seventh data streams; and multiplex the 16 seventh data streams to obtain 1 second data stream, the multiplexing granularity being RS symbol pairs.

[0146] In some possible implementations, p=4 in a 1.6TBASE-R scenario and p=8 in a 3.2TBASE-R scenario; the first processing unit is specifically used to: demultiplex any first data stream to obtain four fourth data streams, the granularity of demultiplexing being RS-FEC 4 symbols; perform alignment identifier locking on the four fourth data streams to obtain four fifth data streams; perform deskewing on the four fifth data streams to obtain four sixth data streams; and multiplex the four sixth data streams to obtain one second data stream, the granularity of multiplexing being RS-FEC 4 symbols.

[0147] In some possible implementations, the nominal rate of each first data stream is 212.5 gigabits per second, and the first data processing also includes multiplexing, p = 2m.

[0148] In some possible implementations, in a 400GBASE-R scenario, p=2, the first processing unit is specifically used to: demultiplex each of the two first data streams to obtain eight fourth data streams, resulting in a total of 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; perform alignment identifier locking on the eight fourth data streams to obtain one fifth data stream, resulting in a total of two fifth data streams, with the RS-FEC 4 symbol boundary of each of the two fifth data streams already determined; and multiplex the two fifth data streams to obtain one second data stream, with the multiplexing granularity being a positive integer multiple of the RS-FEC 4 symbols.

[0149] In some possible implementations, in a 400GBASE-R scenario, p=2, the first processing unit is specifically used to: demultiplex each of the two first data streams to obtain eight fourth data streams, for a total of 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; perform alignment identifier locking on the eight fourth data streams to obtain eight fifth data streams, for a total of 16 fifth data streams, with each of the 16 fifth data streams corresponding to 16 PCS channel data streams; deskew the 16 fifth data streams to obtain 16 sixth data streams; delay the sixth data streams whose corresponding PCS channel numbers are odd to obtain 16 seventh data streams; and multiplex the 16 seventh data streams to obtain one second data stream, with the multiplexing granularity being RS symbol pairs.

[0150] In some possible implementations, in a 400GBASE-R scenario, p=2, the first processing unit is specifically used to: demultiplex each of the p first data streams to obtain 8 fourth data streams, resulting in a total of 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; perform alignment identifier locking on the 8 fourth data streams to obtain 8 fifth data streams, resulting in a total of 16 fifth data streams; deskew the 16 fifth data streams to obtain 16 sixth data streams; delay the sixth data streams whose corresponding PCS channel numbers are odd among the 16 sixth data streams to obtain 16 seventh data streams; perform first multiplexing on every 8 seventh data streams among the 16 seventh data streams to obtain 1 eighth data stream, resulting in a total of 2 eighth data streams, with the first multiplexing granularity being RS symbol pairs, and the RS-FEC 4 symbol boundary of each of the 2 eighth data streams being determined; and perform second multiplexing on the 2 eighth data streams to obtain 1 second data stream, with the second multiplexing granularity being RS-FEC. A positive integer multiple of the sign 4.

[0151] In some possible implementations, in an 800GBASE-R scenario, p=4, the four first data streams include two groups of first data streams, and each group of first data streams includes two first data streams. The first processing unit is specifically used to: demultiplex each first data stream in any group of first data streams to obtain eight fourth data streams, for a total of 16 fourth data streams, with the demultiplexing granularity being RS symbol pairs; perform alignment identifier locking on the eight fourth data streams to obtain eight fifth data streams, for a total of 16 fifth data streams; perform deskewing on the 16 fifth data streams to obtain 16 sixth data streams; delay the sixth data streams whose corresponding PCS channel numbers are odd to obtain 16 seventh data streams; and multiplex the 16 seventh data streams to obtain one second data stream, with the multiplexing granularity being RS symbol pairs.

[0152] In some possible implementations, in an 800GBASE-R scenario, p=4, the four first data streams include two groups of first data streams, and each group of first data streams includes two first data streams. The first processing unit is specifically used to: demultiplex each first data stream in any group of first data streams to obtain eight fourth data streams, resulting in a total of 16 fourth data streams. The granularity of demultiplexing is RS symbol pairs. Alignment identifier locking is applied to the eight fourth data streams to obtain eight fifth data streams, resulting in a total of 16 fifth data streams. Deskipation is applied to the 16 fifth data streams to obtain 16 sixth data streams. Delay is applied to the sixth data streams whose corresponding PCS channel number is odd among the 16 sixth data streams to obtain 16 seventh data streams. First multiplexing is applied to every eight seventh data streams among the 16 seventh data streams to obtain one eighth data stream, resulting in a total of two eighth data streams. The granularity of the first multiplexing is RS symbol pairs, and the RS-FEC of each of the two eighth data streams is... The 4-symbol boundary has been determined; the two eighth data streams are multiplexed a second time to obtain one second data stream, and the granularity of the second multiplexing is a positive integer multiple of the RS-FEC 4-symbol.

[0153] In some possible implementations, in a 1.6TBASE-R scenario, p=8, the 8 first data streams include 4 groups of first data streams, and each group of first data streams includes 2 first data streams. The first processing unit is specifically used to: demultiplex each first data stream in any group of first data streams to obtain 2 fourth data streams, for a total of 4 fourth data streams, with the demultiplexing granularity being RS-FEC 4 symbols; perform alignment identifier locking on the 2 fourth data streams to obtain 2 fifth data streams, for a total of 4 fifth data streams, with the RS-FEC 4 symbol boundary of each of the 4 fifth data streams already determined; perform deskewing on the 4 fifth data streams to obtain 4 sixth data streams; and multiplex the 4 sixth data streams to obtain 1 second data stream, with the multiplexing granularity being a positive integer multiple of RS-FEC 4 symbols.

[0154] In some possible implementations, in the 3.2TBASE-R scenario, p=16, the 16 first data streams include 8 groups of first data streams, and each group of first data streams includes 2 first data streams. The first processing unit is specifically used to: demultiplex each first data stream in any group of first data streams to obtain 2 fourth data streams, for a total of 4 fourth data streams, with the demultiplexing granularity being RS-FEC 4 symbols; perform alignment identifier locking on the 2 fourth data streams to obtain 2 fifth data streams, for a total of 4 fifth data streams, with the RS-FEC 4 symbol boundary of each of the 4 fifth data streams already determined; perform deskewing on the 4 fifth data streams to obtain 4 sixth data streams; and multiplex the 4 sixth data streams to obtain 1 second data stream, with the multiplexing granularity being a positive integer multiple of RS-FEC 4 symbols.

[0155] In some possible implementations, the second data processing includes FEC encoding, where the FEC-encoded FEC codeword comprises N bits, and the N bits include K information bits, where N = 128 and K = 120.

[0156] In some possible implementations, the K / 10 RS symbols corresponding to the K information bits in the FEC codeword obtained by FEC encoding are respectively derived from K / 10 RS codewords, where K is a positive integer multiple of 10.

[0157] In some possible implementations, every 12 consecutive RS symbols in the convolutionally interleaved data stream come from 12 RS codewords.

[0158] In some possible implementations, the 0th delay line of the three delay lines is used to delay 0 bits, the 1st delay line of the three delay lines is used to delay Q×d bits, and the 2nd delay line of the three delay lines is used to delay 2×Q×d bits. Alternatively, the 0th delay line of the three delay lines is used to delay 2×Q×d bits, the 1st delay line of the three delay lines is used to delay Q×d bits, and the 2nd delay line of the three delay lines is used to delay 0 bits.

[0159] Fifthly, embodiments of this application provide a data processing apparatus. The data processing apparatus includes a processing unit. The processing unit is configured to: perform second data processing on m second data streams respectively to obtain m third data streams, wherein the m second data streams are obtained by first data processing on p first data streams encoded by RS. p = m or 2m, where m is an integer greater than or equal to 1. The first data processing includes demultiplexing and alignment identifier locking. The second data processing includes convolutional interleaving; convolutional interleaving is used to delay bits in one data stream before convolutional interleaving according to three delay lines. Bits in one data stream before convolutional interleaving are sequentially input to the three delay lines according to their numbers, with d bits input to each delay line at a time and d bits output from each delay line at a time. The three delay lines are used to delay 0 bits, Q×d bits, and 2×Q×d bits respectively.

[0160] Among them, the Ethernet service rate carried by m second data streams can be 400GEBASE-R, 800GBASE-R, 1.6TBASE-R, 3.2TBASE-R, etc., based on the nominal rate of 425.0 Gbits per second (b / s) for each second data stream. The value range of Q is provided below for different scenarios.

[0161] For example, m=1 means that the Ethernet service carried by m second data streams is at a rate of 400GEBASE-R, or that m second data streams carry 400GEBASE-R Ethernet service, i.e., a 400GBASE-R scenario, where Q≥181.

[0162] For example, m=2 means that the Ethernet service carried by m second data streams is at a rate of 800GBASE-R, or that m second data streams carry 800GEBASE-R Ethernet service, i.e., in the 800GBASE-R scenario, Q≥91.

[0163] For example, m=4, which means that the Ethernet service carried by m second data streams has a rate of 1.6TBASE-R, or that m second data streams carry 1.6TBASE-R Ethernet service, i.e., in the 1.6TBASE-R scenario, Q≥45.

[0164] For example, m=8, which is equivalent to the Ethernet service carried by m second data streams having a rate of 3.2TBASE-R, or equivalent to m second data streams carrying 3.2TBASE-R Ethernet service, i.e., in the 3.2TBASE-R scenario, Q≥23.

[0165] In some possible implementations, the nominal rate of each first data stream is 425 gigabits per second, m = p, and each first data stream is demultiplexed to obtain t data streams, t = 2, 4 or 16.

[0166] In some possible implementations, p = 1 in the 400GBASE-R scenario and p = 2 in the 800GBASE-R scenario. In either the 400GBASE-R or 800GBASE-R scenario, one second data stream is obtained by locking 16 fourth data streams through alignment flags. The 16 fourth data streams are obtained by demultiplexing each of the p first data streams, with the demultiplexing granularity being RS symbol pairs.

[0167] In some possible implementations, p = 4 in the 1.6TBASE-R scenario and p = 8 in the 3.2TBASE-R scenario. One second data stream is obtained by locking four fourth data streams through alignment flags. The four fourth data streams are obtained by demultiplexing each of the p first data streams, with the demultiplexing granularity being RS-FEC 4 symbols.

[0168] In some possible implementations, in the 3.2TBASE-R scenario, p=8, one second data stream is obtained by locking two fourth data streams through alignment identifiers, and the two fourth data streams are obtained by demultiplexing each of the eight first data streams, with the demultiplexing granularity being RS-FEC 4 symbols.

[0169] In some possible implementations, in a 400GBASE-R scenario, p=1; in an 800GBASE-R scenario, p=2; one second data stream is obtained by multiplexing 16 seventh data streams, with the multiplexing granularity being RS symbol pairs; the 16 seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the 16 sixth data streams; the 16 sixth data streams are obtained by de-skewing 16 fifth data streams; the 16 fifth data streams are obtained by locking the alignment flags of 16 fourth data streams; the 16 fifth data streams correspond to 16 PCS channel data streams respectively; the 16 fifth data streams are obtained by locking the alignment flags of 16 fourth data streams; and the 16 fourth data streams are obtained by demultiplexing any one of the p first data streams, with the demultiplexing granularity being RS symbol pairs.

[0170] In some possible implementations, in a 1.6TBASE-R scenario, p=4, and in a 3.2TBASE-R scenario, p=8; one second data stream is obtained by multiplexing four sixth data streams with a multiplexing granularity of RS-FEC 4 symbols; four sixth data streams are obtained by deskewing four fifth data streams; four fifth data streams are obtained by locking four fourth data streams with alignment flags; and four fourth data streams are obtained by demultiplexing any one of the p first data streams with a demultiplexing granularity of RS-FEC 4 symbols.

[0171] In some possible implementations, the nominal rate of each first data stream is 212.5 gigabits per second, and the first data processing also includes multiplexing, p = 2m.

[0172] In some possible implementations, in a 400GBASE-R scenario, p=2, one second data stream is obtained by multiplexing two fifth data streams, with the multiplexing granularity being a positive integer multiple of RS-FEC 4 symbols. Any one fifth data stream is obtained by locking eight fourth data streams through alignment flags. The eight fourth data streams are obtained by demultiplexing each of the two first data streams, with the demultiplexing granularity being RS symbol pairs.

[0173] In some possible implementations, in a 400GBASE-R scenario, p=2, one second data stream is obtained by multiplexing 16 seventh data streams, with the multiplexing granularity being RS symbol pairs; the 16 seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the 16 sixth data streams; the 16 sixth data streams are obtained by de-skewing 16 fifth data streams; eight of the 16 fifth data streams are obtained by locking the alignment flags of eight fourth data streams; and the eight fourth data streams are obtained by demultiplexing each of the two first data streams, with the demultiplexing granularity being RS symbol pairs.

[0174] In some possible implementations, in a 400GBASE-R scenario, p=2, one second data stream is obtained by second multiplexing of two eighth data streams, the granularity of the second multiplexing being a positive integer multiple of RS-FEC 4 symbols; one of the two eighth data streams is obtained by first multiplexing of every eight of the sixteen seventh data streams, the granularity of the first multiplexing being RS symbol pairs; the sixteen seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the sixteen sixth data streams; the sixteen sixth data streams are obtained by de-skewing the sixteen fifth data streams; eight of the sixteen fifth data streams are obtained by alignment flag locking of eight fourth data streams; and the eight fourth data streams are obtained by demultiplexing each of the first data streams in p first data streams, the granularity of the demultiplexing being RS symbol pairs.

[0175] In some possible implementations, in an 800GBASE-R scenario, p=4, the four first data streams comprise two groups of first data streams, and each group of first data streams comprises two first data streams. One second data stream is obtained by multiplexing 16 seventh data streams, with the multiplexing granularity being RS symbol pairs. The 16 seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the 16 sixth data streams. The 16 sixth data streams are obtained by de-skewing 16 fifth data streams. Eight of the 16 fifth data streams are obtained by locking the alignment flags of eight fourth data streams. The eight fourth data streams are obtained by demultiplexing each first data stream in any group of first data streams, with the demultiplexing granularity being RS symbol pairs.

[0176] In some possible implementations, in an 800GBASE-R scenario, p=4, the four first data streams comprise two groups of first data streams, and each group of first data streams comprises two first data streams. One second data stream is obtained by second multiplexing two eighth data streams, with the granularity of the second multiplexing being a positive integer multiple of RS-FEC 4 symbols. One of the two eighth data streams is obtained by first multiplexing eight of the sixteen seventh data streams, with the granularity of the first multiplexing being RS symbol pairs. The sixteen seventh data streams are obtained by delaying the sixth data streams with odd PCS channel numbers corresponding to the sixteen sixth data streams. The sixteen sixth data streams are obtained by de-skewing the sixteen fifth data streams. Eight of the sixteen sixth data streams are obtained by aligning and locking eight fourth data streams. The eight fourth data streams are obtained by demultiplexing each of the first data streams in any group of first data streams, with the granularity of the demultiplexing being RS symbol pairs.

[0177] In some possible implementations, in a 1.6TBASE-R scenario, p=8, the 8 first data streams comprise 4 groups of first data streams, and each of the 4 groups comprises 2 first data streams. One second data stream is obtained by multiplexing 4 sixth data streams, with the multiplexing granularity being a positive integer multiple of RS-FEC 4 symbols. The 4 sixth data streams are obtained by de-skewing 4 fifth data streams. Two of the 4 fifth data streams are obtained by alignment and locking 2 fourth data streams. The two fourth data streams are obtained by demultiplexing each of the first data streams in any group, with the demultiplexing granularity being RS-FEC 4 symbols.

[0178] In some possible implementations, in a 3.2TBASE-R scenario, p=16, the 16 first data streams comprise 8 groups of first data streams, and each of the 8 groups of first data streams comprises 2 first data streams. One second data stream is obtained by multiplexing 4 sixth data streams, with the multiplexing granularity being a positive integer multiple of RS-FEC 4 symbols. The 4 sixth data streams are obtained by de-skewing 4 fifth data streams. Two of the 4 fifth data streams are obtained by aligning and locking 2 fourth data streams. The 2 fourth data streams are obtained by demultiplexing each of the first data streams in any group of first data streams, with the demultiplexing granularity being RS-FEC 4 symbols.

[0179] In a sixth aspect, embodiments of this application provide a data processing apparatus, which includes a receiving unit. The receiving unit is configured to: receive m third data streams. The m third data streams are obtained by processing m second data streams through second data processing, and the m second data streams are obtained by processing p first data streams encoded by RS through first data processing, where p = m or 2m, and m is an integer greater than or equal to 1. The first data processing includes demultiplexing and alignment identifier locking, and the second data processing includes convolutional interleaving and FEC encoding. The convolutional interleaving is used to delay the bits in one data stream before convolutional interleaving according to the three delay lines. The bits in the one data stream before convolutional interleaving are sequentially input into the three delay lines according to the sequence number of the three delay lines, with d bits input to each delay line at a time and d bits output from each delay line at a time. The three delay lines are used to delay 0 bits, Q×d bits, and 2×Q×d bits, respectively.

[0180] Among them, the Ethernet service rate carried by m second data streams can be 400GEBASE-R, 800GBASE-R, 1.6TBASE-R, 3.2TBASE-R, etc., based on the nominal rate of 425.0 Gbits per second (b / s) for each second data stream. The value range of Q is provided below for different scenarios.

[0181] For example, m=1 means that the Ethernet service carried by m second data streams is at a rate of 400GEBASE-R, or that m second data streams carry 400GEBASE-R Ethernet service, i.e., a 400GBASE-R scenario, where Q≥181.

[0182] For example, m=2 means that the Ethernet service carried by m second data streams is at a rate of 800GBASE-R, or that m second data streams carry 800GEBASE-R Ethernet service, i.e., in the 800GBASE-R scenario, Q≥91.

[0183] For example, m=4, which means that the Ethernet service carried by m second data streams has a rate of 1.6TBASE-R, or that m second data streams carry 1.6TBASE-R Ethernet service, i.e., in the 1.6TBASE-R scenario, Q≥45.

[0184] For example, m=8, which is equivalent to the Ethernet service carried by m second data streams having a rate of 3.2TBASE-R, or equivalent to m second data streams carrying 3.2TBASE-R Ethernet service, i.e., in the 3.2TBASE-R scenario, Q≥23.

[0185] In some possible implementations, the nominal rate of each first data stream is 425 gigabits per second, where m = p.

[0186] In some possible implementations, the nominal rate of each first data stream is 212.5 gigabits per second, and the first data processing also includes multiplexing, p = 2m.

[0187] In a seventh aspect, embodiments of this application provide a chip for performing the methods described in any of the first, second, or third aspects.

[0188] Eighthly, embodiments of this application provide an optical module including a processor and an interface. The interface is used to transmit and receive signals, and the processor is used to perform the methods described in any of the embodiments of the first, second, or third aspects. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0189] Ninthly, embodiments of this application provide a network device. The transmitting device includes a host-side device and an optical module as described in the seventh aspect. For example, the optical module is used to convert electrical signals from the host-side device into optical signals and transmit the optical signals. As another example, the optical module is used to convert received optical signals into electrical signals and transmit the electrical signals to the host-side device.

[0190] In a tenth aspect, embodiments of this application provide a communication system that includes multiple network devices as described in the ninth aspect, wherein the multiple network devices are used to send optical signals to each other.

[0191] In one aspect, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any of the embodiments of the first, second, or third aspects to be implemented.

[0192] In a twelfth aspect, this application provides a computer program product including program instructions that, when executed, implement the methods described in any of the embodiments of the first, second, or third aspects above. Attached Figure Description

[0193] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0194] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1;

[0195] Figure 3 is a schematic diagram of another communication system applied in the embodiments of this application;

[0196] Figure 4 is a flowchart illustrating a data processing method provided in an embodiment of this application.

[0197] Figure 5(a) is a schematic diagram of one embodiment of the first data processing in this application;

[0198] Figure 5(b) is a schematic diagram of another implementation of the first data processing in the embodiments of this application;

[0199] Figure 5(c) is a schematic diagram of another implementation of the first data processing in the embodiments of this application;

[0200] Figure 5(d) is a schematic diagram of another implementation of the first data processing in the embodiments of this application;

[0201] Figure 6(a) is a schematic diagram of another implementation of the first data processing in the embodiments of this application;

[0202] Figure 6(b) is a schematic diagram of another implementation of the first data processing in the embodiments of this application;

[0203] Figure 6(c) is a schematic diagram of another implementation of the first data processing in the embodiments of this application;

[0204] Figure 6(d) is a schematic diagram of another implementation of the first data processing in the embodiments of this application;

[0205] Figure 7(a) is a schematic diagram of one embodiment of the 2:1 reuse in this application;

[0206] Figure 7(b) is a schematic diagram of another embodiment of the 2:1 reuse in the present application;

[0207] Figure 7(c) is a schematic diagram of one embodiment of the 4:1 reuse in the present application.

[0208] Figure 7(d) is a schematic diagram of another implementation of the 4:1 reuse in the embodiments of this application;

[0209] Figure 8 is a schematic diagram of one embodiment of the second data processing in this application;

[0210] Figure 9(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application;

[0211] Figure 9(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application;

[0212] Figure 10 is a schematic diagram of one implementation of block distribution in this application;

[0213] Figure 11(a) is a schematic diagram of an embodiment of this application that first performs cyclic shift and then internal code encoding;

[0214] Figure 11(b) is a schematic diagram of an embodiment of this application that first performs internal code encoding and then performs cyclic shifting;

[0215] Figure 12 is a schematic diagram of one embodiment of bit pair interleaving in this application;

[0216] Figure 13 is a schematic diagram of one embodiment of inserting padding bits in this application;

[0217] Figure 14 is a schematic diagram of one embodiment of generating padding bits in this application;

[0218] Figure 15 is a schematic diagram of a specific embodiment of cyclic shifting in this application;

[0219] Figure 16 is a schematic diagram of a specific value of the padding bit in an embodiment of this application;

[0220] Figure 17 is a schematic diagram of cyclic shifting according to method 1 in Table 1 of the embodiments of this application;

[0221] Figure 18 is a schematic diagram of another specific value of the padding bit in an embodiment of this application;

[0222] Figure 19 is a schematic diagram of a data processing device in an embodiment of this application;

[0223] Figure 20 is a schematic diagram of another structure of the data processing device in an embodiment of this application;

[0224] Figure 21 is a schematic diagram of a structure of an optical module in an embodiment of this application;

[0225] Figure 22 is a schematic diagram of a network device in an embodiment of this application. Detailed Implementation

[0226] This application provides a data processing method, apparatus, and system that enable concatenated codes to have better performance, which is beneficial for hardware implementation. At the same time, it can reduce system latency and make it applicable to a wide range of transmission scenarios.

[0227] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be interchanged where appropriate so that the embodiments described in this application can be implemented in an order other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. It should be noted that in the embodiments of this application, unless otherwise stated, "a plurality of" refers to two or more. The "or" in the embodiments of this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A or B can be represented as: A existing alone, A and B existing simultaneously, and B existing alone.

[0228] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application. As shown in Figure 1, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers, and the channel transmission medium 03 can be an optical fiber. The connection interface between the transmitting device 01 and the transmitting processing module 02 (or between the receiving device 05 and the receiving processing module 04) can be an attachment unit interface (AUI). The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, or other modules that process data during data transmission. For example, the processing module can be an ER optical module, FR optical module, or LR optical module, such as a 1.6T LR1 coherent optical module (referred to as a 1.6T LR coherent optical module), a 1.6T FR1 coherent optical module (referred to as a 1.6T FR coherent optical module), or a 1.6T ER1 coherent optical module (referred to as a 1.6T ER coherent optical module). ER, FR, or LR optical modules can also be called simplified coherent (coherent-light or coherent-lite, CL) optical modules. Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here.

[0229] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1. As shown in Figure 2, during the data transmission process from the transmitting device 01 to the receiving device 05, the transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to the transmitting processing module 02. The transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits the data with both external and internal code encoding to the channel transmission medium 03. The channel transmission medium 03 transmits the data with both external and internal code encoding to the receiving processing module 04. The receiving processing module 04 performs internal code decoding on the data with both external and internal code encoding and transmits the internally decoded data to the receiving device 05. The receiving device 05 performs external code decoding on the data with internal code decoding.

[0230] It should be understood that the distinction between "internal" in "internal code" and "external" in "external code" is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with the external code, the data encoded by the transmitting processing module 02 is called data encoded with the internal code, the data decoded by the receiving device 05 is called data decoded with the external code, and the data decoded by the receiving processing module 04 is called data decoded with the internal code. In one possible implementation, both the internal and external encoding described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use Reed-Solomon (RS) encoding for external encoding, and the transmitting processing module 02 can use Hamming code for internal encoding. Alternatively, the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal encoding. A BCH code correcting a single error is equivalent to a Hamming code. Again, the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can use Polar code for internal encoding. In some specific application scenarios, the transmitting device 01 can use RS(544,514) code for external code encoding. RS(544,514) code is also called KP4 code.

[0231] Figure 3 is a schematic diagram of another communication system applied in an embodiment of this application. As shown in Figure 3, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs external code encoding and internal code encoding on the data. The data after external code encoding and internal code encoding is sent to the channel transmission medium 03. The receiving device 05 decodes the data received from the channel transmission medium 03 using both internal code decoding and external code decoding. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as routers, switches, servers, or optical transport network equipment, and the channel transmission medium 03 can be an optical fiber. The transmitting device 01, the channel transmission medium 03, and the receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here. That is, the transmitting device 01 shown in Figure 3 also integrates the functions of the transmitting processing module 02 shown in Figure 2, and the receiving device 05 shown in Figure 3 also integrates the functions of the receiving processing module 04 shown in Figure 2. At this time, the transmitting device 01 may also adopt linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0232] The above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art will know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0233] Figure 4 is a schematic flowchart of a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied to the sending end, for example, it can be implemented by the sending end processing module 02 shown in Figure 2 above, or by the sending end device 01 shown in Figure 3 above.

[0234] 101. Perform first data processing on p first data streams that have been RS encoded to obtain m second data streams.

[0235] Specifically, each of the p first data streams is an external code encoded data stream, where p is an integer greater than or equal to 1. For ease of explanation, the following description uses RS encoding as an example of external code encoding. In practical applications, other encoding methods can also be used for external code encoding. The data stream after RS ​​encoding can include multiple RS codewords. In this embodiment, the code length of the RS codeword is counted in units of symbols. The symbols in the RS codeword can be called RS symbols. For example, RS encoding uses RS(544,514) code, also known as KP4 code. The code length of the RS codeword is 544 RS symbols, that is, the RS codeword includes 544 RS symbols, and one RS symbol contains 10 bits. In each first data stream, every a consecutive RS symbols come from a RS codewords, where a is an integer greater than or equal to 4.

[0236] It should be noted that the Ethernet service rate carried by the m second data streams can be 400GEBASE-R, 800GBASE-R, 1.6TBASE-R, 3.2TBASE-R, etc., based on the nominal rate of 425.0 Gbits per second (b / s) of each second data stream. The value of m depends on the rate of the Ethernet service carried.

[0237] For example, m=1 means that the Ethernet service carried by m second data streams is at a rate of 400GEBASE-R, or that m second data streams carry 400GEBASE-R Ethernet service, i.e., a 400GBASE-R scenario.

[0238] For example, m=2 means that the Ethernet service carried by m second data streams is at a rate of 800GBASE-R, or that m second data streams carry 800GEBASE-R Ethernet service, i.e., an 800GBASE-R scenario.

[0239] For example, m=4 means that the Ethernet service carried by m second data streams has a rate of 1.6TBASE-R, or that m second data streams carry 1.6TBASE-R Ethernet service, i.e., a 1.6TBASE-R scenario.

[0240] For example, m=8 means that the Ethernet service carried by m second data streams has a rate of 3.2TBASE-R, or that m second data streams carry 3.2TBASE-R Ethernet service, i.e., a 3.2TBASE-R scenario.

[0241] For ease of description, the following will be referred to as 400GBASE-R scenario, 800GBASE-R scenario, 1.6TBASE-R scenario and 3.2TBASE-R scenario.

[0242] For the 400GBASE-R scenario, also known as the 400GE transmission scenario, in some specific applications, p=2 first data streams are obtained by processing the two attachment unit interface (AUI) data streams of 400GBASE-R 2:2 SM-PMA. The two AUI data streams of 400GBASE-R are obtained by processing the 16 physical coding sublayer (PCS) lane data streams of 400GBASE-R 16:2 SM-PMA. The PCS (Physical Coding Sublayer) lane data streams can also be simply referred to as PCSL data streams. In each PCSL data stream, every two adjacent RS symbols come from two different RS codewords. After processing by 400GBASE-R 16:2 SM-PMA and 400GBASE-R 2:2 SM-PMA, every four consecutive RS symbols in each first data stream come from four RS codewords. In some other specific applications, p=1 first data stream is obtained by processing one AUI data stream of 400GAUI-1 using 400GBASE-R 1:1 SM-PMA. One AUI data stream of 400GAUI-1 is obtained by processing 16 PCSL data streams using 400GBASE-R 16:1 SM-PMA. In each PCSL data stream, every two adjacent RS symbols come from two different RS codewords. After processing with 400GBASE-R 16:1 SM-PMA and 400GBASE-R 1:1 SM-PMA, every four consecutive RS symbols in each first data stream come from four RS codewords.

[0243] In the 800GBASE-R scenario, also known as the 800GE transmission scenario, in some specific applications, p=4 first data streams are obtained by processing 4 AUI data streams from 800GAUI-4 using 800GBASE-R 4:4 SM-PMA. The 4 AUI data streams from 800GAUI-4 are obtained by processing 32 PCSL data streams using 800GBASE-R 32:4 SM-PMA. In each PCSL data stream, every two adjacent RS symbols come from two different RS codewords. After 800GBASE-R 32:4 SM-PMA and 800GBASE-R 4:4 SM-PMA processing, every four consecutive RS symbols in each first data stream come from four RS codewords. In other specific applications, p=2 first data streams are obtained by processing 2 AUI data streams from 800GAUI-2 using 800GBASE-R 2:2 SM-PMA. The two AUI data streams of 800GAUI-2 are obtained by processing 32 PCSL data streams using 800GBASE-R 32:2 SM-PMA. In each PCSL data stream, every two adjacent RS symbols come from two different RS codewords. After processing with 800GBASE-R 32:2 SM-PMA and 800GBASE-R 2:2 SM-PMA, every four consecutive RS symbols in each first data stream come from four RS codewords.

[0244] For the 1.6TBASE-R scenario, also known as the 1.6TE transmission scenario, in some specific applications, p=8 first data streams are obtained by processing 8 AUI data streams of 1.6TAUI-8 using 1.6TBASE-R 8:8 SM-PMA. The 8 AUI data streams of 1.6TAUI-8 are obtained by processing 16 PCSL data streams using 1.6TBASE-R 16:8 SM-PMA. In each PCSL data stream, every 4 consecutive RS symbols come from 4 different RS codewords. After 1.6TBASE-R 16:8 SM-PMA and 1.6TBASE-R 8:8 SM-PMA processing, every 4 consecutive RS symbols in each first data stream come from 4 RS codewords. In other specific applications, p=4 first data streams are obtained by processing 4 AUI data streams of 1.6TAUI-4 using 1.6TBASE-R 4:4 SM-PMA. The four AUI data streams of 1.6TAUI-4 are obtained by processing 16 PCSL data streams using 1.6TBASE-R 16:4 SM-PMA. In each PCSL data stream, every four consecutive RS symbols come from four different RS codewords. After processing with 1.6TBASE-R 16:4 SM-PMA and 1.6TBASE-R 4:4 SM-PMA, every four consecutive RS symbols in each first data stream come from four RS codewords.

[0245] For the 3.2TBASE-R scenario, also known as the 3.2TE transmission scenario, in some specific applications, p=16 first data streams are obtained by processing 16 AUI data streams from 3.2TAUI-16 using 3.2TBASE-R W:16 SM-PMA. The 16 AUI data streams from 3.2TAUI-16 are obtained by processing W PCSL data streams using 3.2TBASE-R W:16 SM-PMA. In each PCSL data stream, every four consecutive RS symbols come from four different RS codewords. After 3.2TBASE-R W:16 SM-PMA and 3.2TBASE-R 16:16 SM-PMA processing, every four consecutive RS symbols in each first data stream come from four RS codewords. In other specific applications, p=8 first data streams are obtained by processing eight AUI data streams from 3.2TAUI-8 using 3.2TBASE-R 8:8 SM-PMA. The 8 AUI data streams of 3.2TAUI-8 are obtained by processing W PCSL data streams using 3.2BASE-R W:8 SM-PMA. In each PCSL data stream, every four consecutive RS symbols come from four different RS codewords. After processing with 3.2BASE-R W:8 SM-PMA and 3.2BASE-R 8:8 SM-PMA, every four consecutive RS symbols in each first data stream come from four RS codewords. Where W = 16 or W = 32.

[0246] It should be noted that the nominal rate of each of the p first data streams is either 212.5 Gbits per second (b / s) or 425.0 Gbits per second (b / s). Different first data processing schemes will be provided below for different nominal rates of the first data streams. Furthermore, for each nominal rate of the first data stream, specific first data processing schemes adapted to 400GBASE-R, 800GBASE-R, 1.6TBASE-R, and 3.2TBASE-R scenarios will be provided. The value of p will also differ for these scenarios. The p first data streams can also be referred to as p physical medium attachment (PMA) data streams.

[0247] The nominal rate of the first data stream is 425.0 Gbits per second (b / s), which can also be referred to as a 400G / lane transmission scenario. Compared to the first data processing in the 200G / lane transmission scenario, the difference in the first data processing provided in this application embodiment for the 400G / lane transmission scenario includes different demultiplexing parameters. Furthermore, in the 400G / lane transmission scenario, p first data streams undergo first data processing to obtain m = p second data streams.

[0248] The nominal rate of the first data stream is 212.5 Gbits per second (b / s), which can also be referred to as a 200G / lane transmission scenario. Since the second data processing provided in this application embodiment is aimed at a 400G / lane transmission scenario, the first data processing includes multiplexing operations. p first data streams undergo the first data processing to obtain m = p / 2 second data streams, which is equivalent to the nominal rate of each second data stream being 425.0 Gbits per second (b / s).

[0249] Regardless of whether the nominal rate of the first data stream is 212.5 Gbits per second (b / s) or 425.0 Gbits per second (b / s), the second data processing described below is designed for a second data stream with a nominal rate of 425.0 Gbits per second (b / s). In other words, the implementation methods of the second data processing provided in this application are adapted to each implementation method of the first data processing provided in this application. The specific implementation methods of the first data processing in different scenarios will be described below.

[0250] It should be noted that the multiplexing and demultiplexing operations in the various implementations of the first data processing will be described below with reference to the granularity of multiplexing and demultiplexing. Multiplexing refers to multiplexing multiple data streams before multiplexing by outputting v bits or symbols in a round-robin manner; the granularity of multiplexing is v bits or symbols. Demultiplexing refers to demultiplexing the data stream before demultiplexing by distributing v bits or symbols each time; the granularity of demultiplexing is also v bits or symbols.

[0251] For a scenario where the nominal rate of the first data stream is 425.0 Gbits per second (b / s), the first data processing includes at least demultiplexing and alignment marker locking operations. The alignment marker locking is also simply referred to as alignment lock.

[0252] Figure 5(a) is a schematic diagram of one implementation of the first data processing in this application. As shown in Figure 5(a), p first data streams are demultiplexed p:q to obtain q demultiplexed data streams, where q = t × p, t = 2, t = 4, or t = 16. That is, p:q demultiplexing includes p 1:t demultiplexings, and each first data stream undergoes one corresponding 1:t demultiplexing to obtain t demultiplexed data streams, resulting in a total of q demultiplexed data streams. Then, alignment marker locking is performed on the q demultiplexed data streams to obtain m = p second data streams. The alignment marker locking utilizes the known alignment marker (AM) in the PCSL data stream to determine the boundary of four consecutive RS symbols in the second data stream. The boundary of four consecutive RS symbols is also called the 4-symbol boundary or RS-FEC symbol-quartet boundary, and the four consecutive RS symbols come from four RS codewords.

[0253] Figure 5(b) is a schematic diagram of another implementation of the first data processing in this application. Based on Figure 5(b), the implementation methods of the first data processing adapted for 400GBASE-R, 800GBASE-R, 1.6TBASE-R, and 3.2TBASE-R scenarios will be described below. In the 400GBASE-R scenario, p = 1. In the 800GBASE-R scenario, p = 2. In the 1.6TBASE-R scenario, p = 4. In the 3.2TBASE-R scenario, p = 8.

[0254] For both 400GBASE-R and 800GBASE-R scenarios, each of the p first data streams is demultiplexed 1:t to obtain 16 demultiplexed data streams, resulting in a total of 16p demultiplexed data streams. That is, t = 16, and the demultiplexing granularity is RS symbol pairs. Specifically, a round-robin method is used, distributing 20 bits at a time to demultiplex one first data stream into 16 demultiplexed data streams. Alignment flag locking is achieved when all 16 demultiplexed data streams are successfully locked. Here, achieving alignment flag locking means that the alignment flag is correctly locked; the boundary of the 20 bits distributed at this point is the boundary of an RS FEC symbol pair. This is equivalent to taking two consecutive RS symbols from one first data stream and distributing them to one demultiplexed data stream each time; two consecutive RS symbols in one first data stream represent one RS symbol pair. Then, alignment flag locking is applied to the 16 demultiplexed data streams to obtain one second data stream, resulting in a total of p second data streams. All 16 demultiplexed data streams achieve alignment flag locking, meaning the alignment flags are correctly locked.

[0255] It should be understood that each first data stream has its own RS FEC symbol pair boundary. Based on the RS FEC symbol pair boundary, and in conjunction with the processing of 400GBASE-R 16:1 SM-PMA or 800GBASE-R 32:2 SM-PMA, the four symbols (two consecutive RS FEC symbol pairs) in each first data stream originate from four RS codewords. These four RS FEC symbols constitute an RS FEC 4 symbol (RS FEC symbol-quartet), and the boundary between the two RS FEC symbol pairs is the RS FEC 4 symbol boundary. Therefore, by demultiplexing and aligning identifier locking the first data stream to determine the boundary of the RS FEC symbol pairs, the RS FEC 4 symbol boundary of the first data stream is also determined, thereby allowing the determination of the RS FEC 4 symbol boundary of the second data stream.

[0256] It should be noted that if the alignment identifier is not locked within a certain time interval after the 16 demultiplexed data streams, the 20-bit boundary distributed in the above 1:16 demultiplexing is shifted. This shifting is also called slipping. The time interval can also be called the threshold time interval or the bit interval (e.g., 222, 822, 400 bits). In some specific applications, the 20-bit boundary is shifted by 1 bit. In other specific applications, the 20-bit boundary is shifted by a bit greater than 1. In this case, all possible boundaries must be evaluated. A shift of 20 × z + 1 bits can be used, where z is a positive integer, such as 21 bits or 41 bits. When the shift interval matches the specific hardware implementation's bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until all 16 demultiplexed data streams achieve alignment flag locking.

[0257] For the 1.6TBASE-R scenario, each of the four first data streams (p=4) is demultiplexed 1:t to obtain four demultiplexed data streams, resulting in a total of 16 demultiplexed data streams. That is, when t=4, the demultiplexing granularity is RS-FEC 4 symbols. This means that a round-robin method is used, distributing 40 bits at a time to demultiplex one first data stream into four demultiplexed data streams. When all four demultiplexed data streams achieve alignment identifier locking, the boundary of the 40 bits distributed at this point is an RS-FEC 4 symbol boundary. Here, achieving alignment identifier locking means that the alignment identifier is correctly locked, and each first data stream has its own RS-FEC 4 symbol boundary. This is equivalent to taking four consecutive RS symbols from one first data stream and distributing them to one demultiplexed data stream each time. Four consecutive RS symbols in one first data stream represent one RS FEC 4 symbol. Then, alignment flag locking is performed on the four demultiplexed data streams to obtain one second data stream, resulting in a total of four second data streams. All four demultiplexed data streams achieve alignment flag locking; achieving alignment flag locking means that the alignment flag is correctly locked.

[0258] It should be noted that if the alignment identifier is not locked within a certain time interval, the 40-bit boundary distributed in the above 1:4 demultiplexing is shifted (also called slip). This time interval can also be called the threshold time interval or the bit interval (e.g., 222, 822, 400 bits). In some specific applications, the 40-bit boundary is shifted by 1 bit. In other specific applications, the 40-bit boundary is shifted by a bit greater than 1. In this case, all possible boundaries must be evaluated, and a shift of 40 × z + 1 bits can be performed, where z is a positive integer, such as 41 bits or 81 bits. When the shift interval matches the specific hardware implementation's bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until all four demultiplexed data streams achieve alignment flag locking.

[0259] For the 3.2TBASE-R scenario, each of the 8 first data streams is demultiplexed in a 1:t manner to obtain 2 or 4 demultiplexed data streams, resulting in a total of 16 or 32 demultiplexed data streams. That is, t = 2 or 4, the demultiplexing granularity is RS-FEC 4 symbols. This means that a round-robin method is used, distributing 40 bits at a time to demultiplex one first data stream into t demultiplexed data streams. When all t demultiplexed data streams achieve alignment identifier locking, the boundary of the 40 bits distributed at this point is the boundary of one RS-FEC 4 symbol. Here, achieving alignment identifier locking means that the alignment identifier is correctly locked. This is equivalent to taking 4 consecutive RS symbols from one first data stream and distributing them to one demultiplexed data stream each time; 4 consecutive RS symbols in one first data stream represent one RS FEC 4 symbol. Then, alignment flag locking is applied to the four demultiplexed data streams to obtain one second data stream, resulting in a total of four second data streams. All four demultiplexed data streams achieve alignment flag locking, meaning the alignment flag is correctly locked.

[0260] It should be noted that if the alignment identifier is not locked within a certain time interval, the 40-bit boundary distributed in the above 1:4 demultiplexing is shifted (also called slip). This time interval can also be called the threshold time interval or the bit interval (e.g., 222, 822, 400 bits). In some specific applications, the 40-bit boundary is shifted by 1 bit. In other specific applications, the 40-bit boundary is shifted by a bit greater than 1. In this case, all possible boundaries must be evaluated, and a shift of 40 × z + 1 bits can be performed, where z is a positive integer, such as 41 bits or 81 bits. When the shift interval matches the specific hardware implementation's bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until all four demultiplexed data streams achieve alignment flag locking.

[0261] It should be noted that, in the implementation of the first data processing shown in Figure 5(b), p first data streams are processed by the first data processing to obtain p second data streams. The p first data streams and p second data streams correspond one-to-one. The only difference is that the 4-symbol boundary of each first data stream is determined by the alignment identifier. The second data streams do not have any other changes compared to the first data streams.

[0262] Because skew exists between PCSL data streams involved in 1:16 demultiplexing during 800GBASE-R 32:2 SM-PMA processing, it may prevent the K information bits of the inner codeword from originating from K / 10 RS codewords after convolutional interleaving in subsequent second data processing, thus affecting the performance of the concatenated code. Therefore, for the 800GBASE-R scenario, the first data processing also includes skew removal, delaying odd-numbered PCSL data streams, and symbol pair multiplexing operations.

[0263] Figure 5(c) is a schematic diagram of another implementation of the first data processing in this application. As shown in Figure 5(c), for the 800GBASE-R scenario, p = 2. Any one of the first data streams is first demultiplexed with a 1:16 symbol pair to obtain 16 demultiplexed data streams, that is, t = 16, the demultiplexing granularity is RS symbol pairs, and then alignment identifier locking is performed on the 16 demultiplexed data streams. After all 16 demultiplexed data streams have achieved alignment identifier locking, the 16 alignment identifier-locked data streams correspond to 16 PCSL data streams respectively. The 16 PCSL data streams are deskewed; specifically, the skew between the 16 PCSL data streams can be eliminated according to the alignment identifier (AM), so that there is no skew between the starting positions of the alignment identifier (AM) of the 16 PCSL data streams. Then, based on the unique marker (UM) field in the alignment identifier, the PCSL data streams with odd channel numbers among the 16 PCSL data streams are delayed by one RS symbol. This operation can also be called the odd PCSL delay. It should be noted that for the 800GBASE-R scenario, the physical coding sublayer defines 32 PCSLs, represented as PCSL0 to PCSL31, where PCSL1, PCSL3, PCSL7, ..., PCSL29, and PCSL31 are odd PCSLs. Different sequences are defined for the unique marker (UM) field of the alignment identifier for each of the 32 PCSLs. Therefore, the PCSL sequence number can be determined based on the specific sequence in the unique marker (UM) field of the alignment identifier in the PCSL. For example, if the unique marker (UM) field sequence of the alignment identifier in a PCSL is the same as the unique marker (UM) field sequence of the alignment identifier in PCSL1, then this PCSL is PCSL1, and also an odd PCSL. Then, the 16 PCSL data streams with odd PCSL delays are multiplexed into 16:1 symbol pairs in a polling manner according to RS symbol pairs to output a second data stream with a defined 4-symbol boundary. That is, the granularity of 16:1 multiplexing is RS symbol pairs.

[0264] Because skew may exist between PCSL data streams participating in 1:4 4-symbol multiplexing during 1.6TBASE-R 16:4 SM-PMA processing, it may cause issues in the subsequent second data processing, where convolutional interleaving may not guarantee that the K information bits of the inner codeword come from K / 10 RS codewords, thus affecting the performance of the concatenated code. Therefore, for the 1.6TBASE-R scenario, the first data processing also includes skew removal and 4-symbol multiplexing operations.

[0265] Figure 5(d) is a schematic diagram of another implementation of the first data processing in this application. As shown in Figure 5(d), for the 1.6TBASE-R scenario, p = 4. Any one of the first data streams is first demultiplexed in a 1:4 ratio to obtain four demultiplexed data streams. That is, t = 4, and the demultiplexing granularity is RS-FEC 4 symbols. Then, alignment identifier locking is performed on the four demultiplexed data streams. After all four demultiplexed data streams have achieved alignment identifier locking, the four aligned identifier locked data streams correspond to four PCSL data streams respectively. The four PCSL data streams are deskewed so that there is no skew between the starting positions of the alignment identifiers (AM) of the four PCSL data streams. Then, the four PCSL data streams are multiplexed in a 4:1 ratio according to the RS 4-symbol polling output method to obtain one second data stream with a determined 4-symbol boundary, that is, the multiplexing granularity is RS-FEC 4 symbols.

[0266] Because skew may exist between PCSL data streams participating in 1:t 4-symbol multiplexing during 3.2TBASE-R W:4 SM-PMA processing, it may prevent the K information bits of the inner codeword from coming from K / 10 RS codewords after convolutional interleaving in the subsequent second data processing, thus affecting the performance of the concatenated code. Therefore, for the 3.2TBASE-R scenario, the first data processing also includes skew removal and 4-symbol multiplexing operations.

[0267] Figure 5(d) is a schematic diagram of another implementation of the first data processing in this application. As shown in Figure 5(d), for the 3.2TBASE-R scenario, p = 8. Any one of the first data streams is first demultiplexed with a 1:t 4-symbol demultiplexing to obtain t demultiplexed data streams. The granularity of the demultiplexing is RS-FEC 4 symbols. Then, alignment identifier locking is performed on the t demultiplexed data streams. After all four demultiplexed data streams have achieved alignment identifier locking, the t aligned identifier locked data streams correspond to t PCSL data streams respectively. The t PCSL data streams are deskewed so that there is no skew between the starting positions of the alignment identifiers (AM) of the t PCSL data streams. Then, the t PCSL data streams are multiplexed with a 4:1 4-symbol according to the RS 4-symbol polling output method to obtain one second data stream with a determined 4-symbol boundary, i.e., the granularity of the multiplexing is RS-FEC 4 symbols. Where W = 32, t = 4, or W = 16, t = 2.

[0268] For a scenario where the nominal rate of the first data stream is 212.5 Gbits per second (b / s), the first data processing includes at least demultiplexing, alignment marker locking, and multiplexing operations, where m = p / 2. The alignment marker locking is also simply referred to as alignment lock.

[0269] Figure 6(a) is a schematic diagram of another implementation of the first data processing in this application. As shown in Figure 6(a), for the 400GBASE-R scenario, p = 2. Any one of the first data streams is first demultiplexed with 1:8 symbol pairs to obtain 8 demultiplexed data streams. The granularity of demultiplexing is RS symbol pairs. Then, alignment identifier locking is performed on the 8 demultiplexed data streams. After all 8 demultiplexed data streams have achieved alignment identifier locking, one data stream with a determined 4-symbol boundary is obtained, thus obtaining a total of 2 data streams with determined 4-symbol boundaries. Then, the 2 data streams with determined 4-symbol boundaries are multiplexed 2:1. Specifically, H groups of RS-FEC 4 symbols are sequentially read from each data stream with determined 4-symbol boundaries into the second data stream, thus obtaining one second data stream with determined 4-symbol boundaries. Here, H is an integer greater than or equal to 1, which is equivalent to the granularity of the above 2:1 multiplexing being a positive integer multiple of RS-FEC 4 symbols.

[0270] Figure 7(a) is a schematic diagram of one embodiment of 2:1 multiplexing in this application. As shown in Figure 7(a), H = 1, that is, the granularity of the above 2:1 multiplexing is one set of RS-FEC 4 symbols. Figure 7(b) is a schematic diagram of another embodiment of 2:1 multiplexing in this application. As shown in Figure 7(b), H = 2, that is, the granularity of the above 2:1 multiplexing is two sets of RS-FEC 4 symbols.

[0271] Considering the possible deviation between the two first data streams, obtaining the second data stream in the manner shown in Figure 6(a) requires a convolutional interleaver with a larger delay to achieve greater performance for the concatenated code. However, the concatenated code can achieve better performance using a convolutional interleaver with a smaller delay, as shown in Figure 6(b) below.

[0272] Figure 6(b) is a schematic diagram of another implementation of the first data processing in this application. For the 400GBASE-R scenario, p=2, as shown in Figure 6(b), any one of the first data streams is first demultiplexed with 1:8 symbol pairs to obtain 8 demultiplexed data streams. The granularity of demultiplexing is RS symbol pairs. Then, alignment identifier locking is performed on the 8 demultiplexed data streams. After all 8 demultiplexed data streams have achieved alignment identifier locking, 8 corresponding PCSL data streams with alignment identifier locking are obtained, thus obtaining a total of 16 PCSL data streams with alignment identifier locking. Then, the 16 PCSL data streams are deskewed as a whole. This is equivalent to treating the 16 PCSL data streams as a whole and deskewing any possible skew between the 16 PCSL data streams, so that the starting position of AM in any two PCSL data streams differs by N×136 RS symbols, where N is an integer greater than or equal to 0. Then, based on the unique flag UM field in the alignment identifier, the PCSL data streams with odd channel numbers are delayed by 69 RS symbols. The 16 PCSL data streams are then multiplexed 16:1 according to a symbol pair polling output method to obtain a second data stream with a defined 4-symbol boundary. That is, the granularity of the 16:1 multiplexing is RS symbol pairs. For example, 16:1 multiplexing requires polling one symbol pair from the PCSL data streams with even channel numbers and those with odd channel numbers, such as sequentially reading one symbol pair from each of PCSL data streams 0 to 15 into the second data stream.

[0273] For the 800GBASE-R scenario, p=4, the 4 first data streams include 2 groups of first data streams, and each group of first data streams includes 2 first data streams. Figure 6(b) shows the process of first data processing for one of the groups of first data streams. Specifically, as shown in Figure 6(b), any one of the first data streams in the same group of first data streams is first demultiplexed with 1:8 symbol pairs to obtain 8 demultiplexed data streams. The granularity of demultiplexing is RS symbol pairs. Then, alignment flag locking is performed on the 8 demultiplexed data streams. After all 8 demultiplexed data streams have achieved alignment flag locking, 8 corresponding PCSL data streams with alignment flag locking are obtained, thus obtaining a total of 16 PCSL data streams with alignment flag locking. Then, the 16 PCSL data streams are de-skewed as a whole. This is equivalent to treating the 16 PCSL data streams as a single entity and de-skewing any potential skew between them, ensuring that the start positions of AM in any two PCSL data streams are aligned. Next, based on the unique flag UM field in the alignment identifier, the PCSL data streams with odd channel numbers are delayed by one RS symbol. Finally, the 16 PCSL data streams are multiplexed 16:1 according to a symbol pair polling output method to obtain a second data stream with a defined 4-symbol boundary. That is, the granularity of the 16:1 multiplexing is RS symbol pairs.

[0274] It should be noted that in the 800GBASE-R scenario, there are 32 PCSL data streams, from PCSL data stream 0 to PCSL data stream 31. Of the aforementioned 16 PCSL data streams, 8 originate from 8 PCSL data streams from PCSL data stream 0 to PCSL data stream 15, and the remaining 8 originate from 8 PCSL data streams from PCSL data stream 16 to PCSL data stream 31. When multiplexing a symbol pair by polling from these 16 PCSL data streams, a symbol pair must be read alternately from PCSL data streams 0 to PCSL data stream 15, and then from PCSL data streams 16 to PCSL data stream 31, so that the four consecutive RS symbols in the output second data stream originate from four RS codewords. For example, if there are 16 PCSL data streams, PCSL data stream 0, PCSL data stream 1, PCSL data stream 2, PCSL data stream 3, PCSL data stream 4, PCSL data stream 5, PCSL data stream 6, PCSL data stream 7, PCSL data stream 16, PCSL data stream 17, PCSL data stream 18, PCSL data stream 19, PCSL data stream 20, PCSL data stream 21, PCSL data stream 22, and PCSL data stream 23, then one RS symbol pair can be read from each PCSL data stream in a round-robin fashion to the second data stream.

[0275] Figure 6(c) is a schematic diagram of another implementation of the first data processing in this application. As shown in Figure 6(c), for the 400GBASE-R scenario, p=2, the difference between the implementation shown in Figure 6(c) and the implementation shown in Figure 6(b) is that the implementation shown in Figure 6(c) adjusts the 16:1 multiplexing in the implementation shown in Figure 6(b) to level 2 multiplexing. Other similar operations will not be described here. Specifically, the 16 PCSL data streams with an odd PCSL delay can be divided into two groups, each group including 8 PCSL data streams. The 8 PCSL data streams in any one group are multiplexed 8:1 according to the symbol pair polling output to obtain 1 multiplexed data stream, thus obtaining a total of 2 multiplexed data streams. The granularity of 8:1 multiplexing is RS symbol pairs, and the 4-symbol boundary of each multiplexed data stream has been determined. Furthermore, the two multiplexed data streams are multiplexed 2:1 to obtain a second data stream. Specifically, H groups of RS-FEC 4 symbols are sequentially read from each multiplexed data stream into the second data stream, thus obtaining a second data stream with a defined 4-symbol boundary. Here, H is an integer greater than or equal to 1, which means that the granularity of the 2:1 multiplexing is a positive integer multiple of the RS-FEC 4 symbols. For example, Figure 7(a) shows one implementation of 2:1 multiplexing with H=1. As another example, Figure 7(b) shows another implementation of 2:1 multiplexing with H=2.

[0276] For the 800GBASE-R scenario, as shown in Figure 6(c), p=4. The difference between the implementation shown in Figure 6(c) and the implementation shown in Figure 6(b) is that the implementation shown in Figure 6(c) adjusts the 16:1 multiplexing in the implementation shown in Figure 6(b) to level 2 multiplexing. Other similar operations will not be described here. Specifically, the 16 PCSL data streams with an odd PCSL delay can be divided into two groups, each group including 8 PCSL data streams. The 8 PCSL data streams in any one group are multiplexed 8:1 according to the symbol pair polling output to obtain 1 multiplexed data stream, thus obtaining a total of 2 multiplexed data streams. The granularity of 8:1 multiplexing is RS symbol pairs, and the 4-symbol boundary of each multiplexed data stream has been determined. Furthermore, the two multiplexed data streams are multiplexed 2:1 to obtain a second data stream. Specifically, H groups of RS-FEC 4 symbols are sequentially read from each multiplexed data stream into the second data stream, thus obtaining a second data stream with a defined 4-symbol boundary. Here, H is an integer greater than or equal to 1, which means that the granularity of the 2:1 multiplexing is a positive integer multiple of the RS-FEC 4 symbols. For example, Figure 7(a) shows one implementation of 2:1 multiplexing with H=1. As another example, Figure 7(b) shows another implementation of 2:1 multiplexing with H=2.

[0277] It should be noted that the eight PCSL data streams involved in the above 8:1 multiplexing are obtained from one first data stream through demultiplexing and other processing. Four of the eight PCSL data streams come from four PCSL data streams from PCSL data stream 0 to PCSL data stream 15, and the other four come from four PCSL data streams from PCSL data stream 16 to PCSL data stream 31. When multiplexing a symbol pair by polling from the eight PCSL data streams, a symbol pair needs to be read alternately from PCSL data streams from PCSL data stream 0 to PCSL data stream 15, and then from PCSL data streams from PCSL data stream 16 to PCSL data stream 31.

[0278] Figure 6(d) is a schematic diagram of another implementation of the first data processing in this application. As shown in Figure 6(d), for the 1.6TBASE-R scenario, p=8, the 8 first data streams include 4 groups of first data streams, and each group of first data streams includes 2 first data streams. Figure 6(d) shows the process of performing first data processing on one of the groups of first data streams. Specifically, as shown in Figure 6(d), t=2, any one of the first data streams in the same group of first data streams is first demultiplexed with a 1:2 ratio of 4-symbols to obtain 2 demultiplexed data streams. The granularity of demultiplexing is RS-FEC 4 symbols. Then, the 2 demultiplexed data streams are aligned and locked with alignment identifiers to obtain 2 corresponding PCSL data streams that have achieved alignment identifier locking, thus obtaining a total of 4 PCSL data streams that have achieved alignment identifier locking. Then, the four PCSL data streams are de-skewed as a whole. This is equivalent to treating the four PCSL data streams as a single entity and de-skewing any potential skew between them, ensuring that the start positions of AM in any two of the four PCSL data streams are aligned. Next, the four PCSL data streams are multiplexed 4:1 to obtain a second data stream. Specifically, H groups of RS-FEC 4 symbols are sequentially read from each PCSL data stream and added to the second data stream, resulting in a second data stream with defined 4-symbol boundaries. Here, H is an integer greater than or equal to 1, meaning the granularity of the 4:1 multiplexing is a positive integer multiple of the RS-FEC 4 symbols.

[0279] Figure 7(c) is a schematic diagram of one embodiment of 4:1 multiplexing in this application. As shown in Figure 7(c), H = 1, that is, the granularity of the above 4:1 multiplexing is one set of RS-FEC 4 symbols. Figure 7(d) is a schematic diagram of another embodiment of 4:1 multiplexing in this application. As shown in Figure 7(d), H = 2, that is, the granularity of the above 4:1 multiplexing is two sets of RS-FEC 4 symbols.

[0280] For the 3.2TBASE-R scenario, p=16, the 16 first data streams include 8 groups of first data streams, and each group of first data streams includes 2 first data streams. Figure 6(d) shows the process of first data processing for one group of first data streams. Specifically, as shown in Figure 6(d), any one of the first data streams in the same group is first demultiplexed with a 1:2 ratio of 4-symbols to obtain 2 demultiplexed data streams. The granularity of demultiplexing is RS-FEC 4 symbols. Then, alignment flag locking is performed on the 2 demultiplexed data streams to obtain 2 corresponding PCSL data streams that have achieved alignment flag locking, thus obtaining a total of 4 PCSL data streams that have achieved alignment flag locking. Then, the 4 PCSL data streams are deskewed as a whole. This is equivalent to treating the 4 PCSL data streams as a whole and deskewing any possible skew between the 4 PCSL data streams, so that the starting positions of AM in any 2 PCSL data streams are aligned. Then, the four PCSL data streams are multiplexed 2t:1 to obtain one second data stream. Specifically, H groups of RS-FEC 4 symbols are sequentially read from each PCSL data stream into the second data stream, thus obtaining one second data stream with a defined 4-symbol boundary. Here, H is an integer greater than or equal to 1, which means that the granularity of the above 2t:1 multiplexing is a positive integer multiple of the RS-FEC 4 symbols.

[0281] 102. Perform second data processing on each of the m second data streams to obtain m third data streams.

[0282] Specifically, the second data processing includes the following operations: convolutional interleaving, block distribution, circular shifting, internal code encoding, bit pair interleaving, and padding bit insertion.

[0283] Considering that the number of information bits in the internal code is K, that is, K information bits in the second data stream are internally encoded to generate P parity bits, thus obtaining an internal codeword containing N = K + P bits, where 1 < K < N, P > 0, K > 0. Considering that the external code generally uses RS(544, 514), to achieve optimal performance for concatenated FEC coding, K is generally set to an integer multiple of 10, that is, K is an integer multiple of the number of RS symbols included in the RS codeword. By adding convolutional interleaving before the internal code encoding, the K information bits in each internal codeword correspond to K / 10 RS symbols, that is, one RS symbol is taken from each of the K / 10 RS codewords to form the K information bits in an internal codeword. For example, if the internal code encoding uses BCH(126, 110), the K = 110 information bits in each internal codeword correspond to K / 10 = 11 RS symbols, and the corresponding K / 10 = 11 RS symbols come from K / 10 = 11 RS codewords. For example, the internal code encoding uses a linear block code with N=128 and K=120. Each internal codeword contains K=120 information bits corresponding to K / 10=12 RS symbols, and these K / 10=12 RS symbols come from K / 10=12 different RS codewords. In other words, the second data processing provided in this application embodiment achieves that the K information bits in each internal codeword come from K / 10 different RS codewords, and improves the tolerance of convolutional interleaving to colored noise.

[0284] Figure 8 is a schematic diagram of one embodiment of the second data processing in this application. As shown in Figure 8, an embodiment of the second data processing for one of the second data streams is illustrated. Specifically, the second data stream is convolved and interleaved, and then distributed in a 1:f block ratio to obtain f distributed data streams. Next, the f distributed data streams are cyclically shifted and encoded, and then the f cyclically shifted and encoded data streams are interleaved in an f:1 bit-pair ratio to obtain one bit-pair interleaved data stream. Furthermore, padding bits are inserted into the one bit-pair interleaved data stream to obtain one third data stream. Each step in the second data processing is described in detail below.

[0285] The convolutional interleaver used to implement convolutional interleaving includes r delay lines, each with a different number of storage units. The delay line with the fewest storage units has 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, where r is an integer greater than 1 and Q is an integer greater than or equal to 1. Each storage unit stores d bits, where d is an integer greater than or equal to 1. Bits from the input data stream of the convolutional interleaver are sequentially input into the r delay lines according to their indices. Each input consists of d bits to and from each delay line at a time. In some specific applications, d bits are input into the convolutional interleaver at a time, and these d bits are input into one delay line of the convolutional interleaver. In other specific applications, r × d bits are input into the convolutional interleaver at a time, and these r × d bits are input into the r delay lines of the convolutional interleaver. The data input to each delay line consists of d consecutive bits from the r × d bits. The continuous r×d bits in the data stream output by the convolutional interleaver include the d bits output by each delay line.

[0286] It should be understood that the r delay lines each comprise 0, Q, 2×Q, ..., (r-1)×Q storage units, with each storage unit storing d bits. The r delay lines correspond to r delay values, which include 0 bits, Q×d bits, 2×Q×d bits, ..., (r-1)×Q×d bits. The more bits a delay line includes in its delay values, the longer the delay (also called latency) to the data stream. It should be understood that when a delay line contains no storage units, its delay is 0 bits, which is called zero-latency pass-through. It should be understood that the aforementioned storage units are also called delay elements.

[0287] Figure 9(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application. As shown in Figure 9(a), the number of storage units in the r delay lines decreases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)×Q storage units, each delay line decreases by Q storage units sequentially, and delay line r-1 has 0 storage units. Figure 9(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application. As shown in Figure 9(b), the number of storage units in the r delay lines increases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line r-1 has (r-1)×Q storage units.

[0288] It should be understood that in the convolutional interleaver shown in Figure 9(a), delay line 0 delays the input data by (r-1)×Q×d bits, delay line 1 delays the input data by (r-2)×Q×d bits, and so on, with delay line r-2 delaying the input data by Q×d bits, while delay line r-1 does not delay the input data. Similarly, in the convolutional interleaver shown in Figure 9(b), delay line 0 does not delay the input data, delay line 1 delays the input data by Q×d bits, and so on, with delay line r-2 delaying the input data by (r-1)×Q×d bits, and delay line r-1 delaying the input data by (r-1)×Q×d bits.

[0289] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line receives and outputs d bits in a single input, the switch is switched to the next delay line. This ensures that the bits in the input data stream are sequentially input to the r delay lines according to their sequence numbers, and that the consecutive r×d bits in the output data stream include the d bits output from each delay line. The specific data read / write operations are as follows: d bits are read from the memory cell closest to the output port of the current delay line; the d bits stored in each memory cell of the current delay line are transferred to the next memory cell; then, d bits are written to the memory cell closest to the input port of the current delay line. Afterward, the switch is moved to the next delay line, and the above operations are repeated, and so on.

[0290] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving processing in Figure 9(a) and the convolutional interleaving processing in Figure 9(b) are the inverse operations of each other. That is, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 9(a), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 9(b). Similarly, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 9(b), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 9(a).

[0291] Typically, r = 3, and the number of bits stored in each storage unit is d = a × 10 = 40. Based on the obtained 4-symbol boundary, the 40 bits stored in each storage unit come from 40 consecutive bits in a second data stream, corresponding to 4 RS symbols, i.e., one RS FEC 4 symbol (RS-FEC-symbol-quartet). By configuring an appropriate Q value, every 12 consecutive symbols in the convolutionally interleaved data stream can come from 12 RS codewords.

[0292] Figure 10 is a schematic diagram of one implementation of block distribution in this application. As shown in Figure 10, each convolutionally interleaved data stream is distributed in a 1:f block ratio to obtain f distributed data streams. Specifically, a round-robin method is used to distribute 3 RS-FEC symbol quartets at a time. In Figure 10, A i B i C i This refers to three consecutive RS FEC 4 symbols in the convolutionally interleaved data stream. These three RS FEC 4 symbols are output from the three delay lines of the convolutional interleaver. During block distribution, these three RS FEC 4 symbols, totaling 12 RS symbols, are distributed to one data stream. As shown in Figure 10, A0, B0, and C0 are distributed to data stream 0; A1, B1, and C1 are distributed to data stream 1; A2, B2, and C2 are distributed to data stream 2, and so on. f-1 B f-1 C f-1 Distribute the data to data stream f-1. Where f = 8 or f = 16, i ≥ 0.

[0293] In Figure 8, one implementation of cyclic shifting and internal code encoding involves performing cyclic shifting first, followed by internal code encoding. Specifically, for each distributed data stream, every K / 10 consecutive RS symbols are cyclically shifted left by δ RS symbols or right by Δ RS symbols. Then, the shifted K / 10 RS symbols are internally encoded to add NK parity bits to obtain an internal codeword with a code length of N bits. Taking K=120 and N=128 as an example, one implementation method of performing cyclic shifting first and then internal code encoding is given below.

[0294] Figure 11(a) is a schematic diagram of an embodiment of this application that performs cyclic shifting before internal code encoding. As shown in Figure 11(a), the 12 RS symbols are cyclically shifted right by Δ RS symbols, that is, the i-th RS symbol is cyclically shifted right to the (i+Δ)%12th RS symbol. Alternatively, the 12 RS symbols are cyclically shifted left by δ RS symbols, that is, the i-th RS symbol is cyclically shifted left to the (i+12-δ)%12th RS symbol, where 0≤i<12, 0≤δ<12, 0≤Δ<12. Taking Figure 11(a) as an example, it represents a right cyclic shift of Δ = 4 RS symbols, or a left cyclic shift of δ = 8 RS symbols. It should be noted that the 12 symbols before the cyclic shift in Figure 11(a) are from left to right the 0th to the 11th symbols, where the 0th symbol can also be represented as symbol 0, and the 11th symbol can also be represented as symbol 11.

[0295] Another implementation of the cyclic shift and internal code encoding processing in Figure 8 is to perform internal code encoding first and then cyclic shift. Specifically, for each distributed data stream, internal code encoding is performed on every K / 10 consecutive RS symbols, and NK parity bits are added to obtain an internal codeword with a code length of N bits. Then, the K / 10 RS symbols corresponding to the K information bits in the internal codeword are cyclically shifted while the parity bits in the internal codeword remain in their original positions. For example, the K / 10 RS symbols corresponding to the K information bits are cyclically shifted left by δ symbols or right by Δ symbols. Taking K=120 and N=128 as an example, one implementation method of performing internal code encoding first and then cyclic shift is given below.

[0296] Figure 11(b) is a schematic diagram of an embodiment of this application that first performs internal code encoding and then performs cyclic shift. As shown in Figure 11(b), the 12 RS symbols are cyclically shifted to the right by Δ RS symbols, that is, the i-th RS symbol is cyclically shifted to the right to the (i+Δ)%12th RS symbol. Alternatively, the 12 RS symbols are cyclically shifted to the left by δ RS symbols, that is, the i-th RS symbol is cyclically shifted to the left to the (i+12-δ)%12th RS symbol, where 0≤i<12, 0≤δ<12, 0≤Δ<12. Taking Figure 11(b) as an example, it represents a right cyclic shift of Δ = 4 RS symbols, or a left cyclic shift of δ = 8 RS symbols. It should be noted that the 12 symbols before the cyclic shift in Figure 11(b) are from left to right the 0th to the 11th symbols, where the 0th symbol can also be represented as symbol 0, and the 11th symbol can also be represented as symbol 11.

[0297] It should be noted that, in order to improve the burst resistance of concatenated codes, the number of symbols δ and Δ of the cyclic shift corresponding to each distributed data stream may be different. After bit pair interleaving, multiple consecutive PAM4 burst errors introduced into the channel can be distributed to different inner code codes and different outer code codes, so that concatenated codes have better burst resistance.

[0298] The bit-pair interleaving in Figure 8 can also be called bit-pair multiplexing. Specifically, one codeword is obtained from each data stream that has undergone cyclic shifting and internal code encoding, and then... This represents a bit pair consisting of the 2i-th bit and the (2i+1)-th bit of the inner code codeword in data stream j. Then, following the order of data stream 0 to data stream f-1, one bit pair is read from each inner code codeword and added to the interleaved data stream, where 0 ≤ j <f,0≤i<N / 2。

[0299] Figure 12 is a schematic diagram of one implementation of bit pair interleaving in this application. As shown in Figure 12, bit pairs are first read from data stream 0. Then read bit pairs from data stream 1 …and then read bit pairs from data stream f-1 Then, read bit pairs from data stream 0. Then read bit pairs from data stream 1 …and then read bit pairs from data stream f-1 This polling continues.

[0300] Figure 13 is a schematic diagram of one embodiment of the insertion of padding bits in this application. As shown in Figure 13, f×N padding bits are inserted after every H internal codewords in the bit-pair interleaved data stream, where H is an integer multiple of f. The first group of f×N padding bits is inserted before all internal codewords. Specifically, the f×N padding bits are obtained by processing f×K bits of data padding through the aforementioned internal code encoding and bit-pair interleaving. The f×K bits of data padding do not come from the bits in the second data stream; they are only used to generate the f×N padding bits.

[0301] Figure 14 is a schematic diagram of one embodiment of generating padding bits in this application. As shown in Figure 14, the f×K bit data pad is divided into f bit sequences, each bit sequence including K bits, using m i <k-1:0>Let represent the i-th bit sequence. Each bit sequence is encoded using an internal code to obtain NK parity bits, resulting in a bit sequence containing N bits. This N-bit bit sequence can also be called a pad codeword, denoted as pad_cw_i. <n-1:0>Where 0 ≤ i ≤ f. Then, the f pad codewords are interleaved bit pairs as shown in Figure 12 to obtain f × N pad bits, denoted as pad.<f×N-1:0> Among them, pad in f×N padding bits<f×N-1:f×N-L> The total number of bits is the frame alignment sequence. Typically, f=8, H=8704, L=48; or f=16, H=17408, L=48.

[0302] It should be noted that the embodiment shown in Figure 4 above describes a data processing method applied to the sending end, which includes performing a first data processing step followed by a second data processing step. Correspondingly, the receiving end uses a method matching the data processing method of the sending end to process the received data. In one possible implementation, the data processing method applied to the receiving end performs the inverse processing of the second data processing step followed by the inverse processing of the first data processing step. It should be understood that the inverse processing performed by the receiving end on the data stream is used to restore the data stream before the sending end performed the corresponding processing. For example, the inverse processing of internal code encoding performed by the sending end is internal code decoding; the receiving end performs internal code decoding on the data stream to restore the data stream before the sending end performed internal code encoding. As another example, the inverse processing of convolutional interleaving performed by the sending end is deconvolutional interleaving; the receiving end performs deconvolutional interleaving on the data stream to restore the data stream before the sending end performed convolutional interleaving. Therefore, the specific operations performed by the receiving end can refer to the specific operations performed by the sending end in the embodiment shown in Figure 4 above, and will not be elaborated further here.

[0303] The following provides several possible implementation methods for different scenarios.

[0304] Example 1: For a 1.6TBASE-R scenario, the nominal rate of the first data stream is 425.0Gbps, corresponding to p=4 and q=4×p=16.

[0305] The transmitting processing module 02 receives four AUI data streams of 1.6TAUI-4 and performs four-level pulse amplitude modulation (PAM4) decoding on them to obtain p = four first data streams. Following the scheme shown in Figure 5(b) or Figure 5(d), the four first data streams undergo first data processing to obtain four RS FEC 4-symbol delimited second data streams. Then, each second data stream undergoes second data processing according to the scheme shown in Figure 8 to obtain one third data stream, resulting in a total of four third data streams output.

[0306] In the second data processing step, one implementation of the convolutional interleaver is shown in Figure 9(a), where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 45, and based on the obtained 4-symbol boundary, each storage unit stores d = 40 bits. Each storage unit stores 40 bits corresponding to 4 RS symbols, i.e., one RS FEC 4 symbol (RS-FEC-symbol-quartet). After convolutional interleaving, the output data stream contains 12 consecutive (adjacent) RS symbols from 12 RS codewords, ensuring that the 120 information bits of each inner codeword come from 12 RS codewords, resulting in better performance of the concatenated code. Furthermore, Q = 46 or 48 can be set, which is beneficial for hardware implementation and reduces system latency, making it suitable for a wider range of transmission scenarios.

[0307] Another implementation of the convolutional interleaver in the second data processing is shown in Figure 9(b), where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 46, and based on the obtained 4-symbol boundary, each storage unit stores d = 40 bits. Each storage unit stores 40 bits corresponding to 4 RS symbols, i.e., one RS FEC 4 symbol (RS-FEC-symbol-quartet). In the output data stream after convolutional interleaving, 12 consecutive (adjacent) RS symbols come from 12 RS codewords, allowing each inner codeword's 120 information bits to come from 12 RS codewords, thus giving the concatenated code superior signal performance. Furthermore, Q = 46 or 48 can be set, which is beneficial for hardware implementation and also reduces system latency, making it suitable for a wider range of transmission scenarios.

[0308] In the second data processing, the block distribution uses a 1:8 120-bit distribution, resulting in a total of 8 distributed data streams. Then, for each distributed data stream, every 3 consecutive RS FEC 4-symbols (a total of 12 RS symbols) are first cyclically shifted, and then FEC(128,120) internal code encoding is performed to obtain an internal codeword with a code length of 128 bits, thus obtaining 8 internal code encoded data streams.

[0309] Figure 15 is a schematic diagram of a specific embodiment of cyclic shifting in this application. As shown in Figure 15, the cyclic shifting used in data streams 0 to 7 after distribution is different, where CS(a) represents a right cyclic shift of a RS symbols. The embodiment shown in Figure 15 enables the concatenated code to have better resistance to colored noise.

[0310] In the second data processing, the bit pair interleaving adopts an 8:1 bit pair multiplexing method, which multiplexes the data stream after the 8 internal codes are encoded into 1 data stream, that is, f=8 in Figure 12.

[0311] In the interleaved data stream, 1024 padding bits are inserted at intervals of H = 8074 internal codewords, with the first group of 1024 padding bits inserted before all internal codewords. The pad data length is 960 bits, corresponding to m_i<119:114> in Figure 14.

[0312] Figure 16 is a schematic diagram of a specific value of the padding bits in an embodiment of this application. In the scenario where f = 8, the specific values ​​of m_i<119:114> are shown in Figure 16, where m_i<113:0> is the sequence after the all-zero sequence is scrambled by PRBS13, and 0 ≤ i < 8. The FAS sequence in the padding bits is 01011001 01010010 01100100 10100110 10101101 10011011, where the leftmost bit is the first bit transmitted and the rightmost bit is the last bit transmitted. It should be understood that m_i<119:0> is used to represent 120 bits, of which bit 0 is the last bit transmitted, represented as m_i <0> Of these 120 bits, bit 119 is the first bit transmitted, denoted as m_i. <119> Correspondingly, the 128 bits obtained after encoding these 120 bits with the internal code are equivalent to the specific values ​​of pad_cw_i<127:122>, as shown in Figure 16. Bit 0 in these 128 bits is the last bit transmitted, represented as pad_cw_i. <0> Of these 128 bits, bit 127 is the first bit transmitted, represented as pad_cw_i. <127> It should be noted that in Figure 16, pad_cw_0<127:122> is "010110", which means that bits 127 to 122 of pad_cw_0 are 0, 1, 0, 1, 1, 0 respectively.

[0313] Example 2: Considering the limited bandwidth of future 400G / lane transmission devices and the further increase in colored noise, to enhance the concatenated code's ability to resist colored noise, the block distribution in Example 1 is changed to a 1:16 120-bit distribution, resulting in a total of 16 distributed data streams. Then, for each distributed data stream, every 3 consecutive RS FEC 4-symbols (a total of 12 RS symbols) are cyclically shifted, and then FEC(128,120) internal code encoding is performed to obtain an internal codeword with a code length of 128 bits, thus obtaining 16 internal code encoded data streams.

[0314] Table 1 shows 17 possible implementation schemes for cyclic shifting in this application. Here, the distributed data stream *m* represents the *m*th data stream among 16 distributed data streams, where *m* = {0, 1, 2, ..., 15}. Each row of 16 data points corresponding to each cyclic shifting method provided in Table 1 represents a right cyclic shift of *c* symbols for every consecutive 12 symbols in each of the 16 distributed data streams. Alternatively, each row of 16 data points corresponding to each cyclic shifting method provided in Table 1 represents a left cyclic shift of 12-*c* symbols for every consecutive 12 symbols in each of the 16 distributed data streams.

[0315] Taking Method 1 in Table 1 as an example, it means: every 12 consecutive symbols in data stream 0 is right-circularly shifted by 0 symbols; every 12 consecutive symbols in data stream 1 is right-circularly shifted by 3 symbols; every 12 consecutive symbols in data stream 2 is right-circularly shifted by 6 symbols; every 12 consecutive symbols in data stream 3 is right-circularly shifted by 9 symbols; every 12 consecutive symbols in data stream 4 is right-circularly shifted by 1 symbol; every 12 consecutive symbols in data stream 5 is right-circularly shifted by 4 symbols; every 12 consecutive symbols in data stream 6 is right-circularly shifted by 7 symbols; and every 12 consecutive symbols in data stream 7 is right-circularly shifted by 1 symbol. 0 symbols; every 12 consecutive symbols in data stream 8 are right-circularly shifted by 0 symbols; every 12 consecutive symbols in data stream 9 are right-circularly shifted by 3 symbols; every 10 consecutive symbols in data stream 1 are right-circularly shifted by 6 symbols; every 12 consecutive symbols in data stream 11 are right-circularly shifted by 9 symbols; every 12 consecutive symbols in data stream 12 are right-circularly shifted by 1 symbol; every 12 consecutive symbols in data stream 13 are right-circularly shifted by 4 symbols; every 12 consecutive symbols in data stream 14 are right-circularly shifted by 7 symbols; every 12 consecutive symbols in data stream 15 are right-circularly shifted by 10 symbols.

[0316] By using the cyclic shifting method provided in Table 1 above, the two bit pairs from the same RS codeword in the interleaved data can be spaced at least 8 symbols apart, thus improving the burst resistance of the concatenated code.

[0317] Figure 17 is a schematic diagram of cyclic shifting according to Method 1 in Table 1 of the embodiments of this application. Here, CS(a) represents a right cyclic shift of a RS symbols or a left cyclic shift of 12-a symbols for every consecutive 12 RS symbols in the corresponding distributed data stream.

[0318] Table 1

[0319] In the second data processing, bit pair interleaving adopts a 16:1 bit pair multiplexing method, which multiplexes the data stream after 16 internal codes to obtain 1 data stream, which corresponds to f=16 in Figure 12.

[0320] In the interleaved data stream, 2048 padding bits are inserted at intervals of H = 17408 internal codewords, with the first group of 2048 padding bits inserted before all internal codewords. The pad data length is 1920 bits, corresponding to m_i<119:x> in Figure 14.

[0321] Figure 18 is a schematic diagram of another specific value of the padding bit in an embodiment of this application. In the scenario of f=16, the specific value of m_i<119:x> is shown in Figure 18, m_i <x-1:0>The sequence is the result of scrambling an all-zero sequence with PRBS13, where 0 ≤ i < 16. When 0 ≤ i < 8, x = 116; when 9 ≤ i < 16, x = 118. After bit-pair interleaving of the 8 pad codewords, the FAS sequence in the padding bits becomes 01011001 01010010 01100100 10100110 10101101 1001101, which allows the receiving end to use the FAS sequence for internal code synchronization. The leftmost bit is the first bit transmitted, and the rightmost bit is the last bit transmitted. It should be understood that m_i<119:0> is used to represent 120 bits, of which bit 0 is the last bit transmitted, represented as m_i <0> Of these 120 bits, bit 119 is the first bit transmitted, denoted as m_i. <119> Correspondingly, the 128 bits obtained after encoding these 120 bits with the internal code are equivalent to the specific values ​​of pad_cw_i<127:x+8>, as shown in Figure 18. Bit 0 in these 128 bits is the last bit transmitted, represented as m_i. <0> Of these 128 bits, bit 127 is the first bit transmitted, denoted as m_i. <127> .

[0322] Example 3: In a 1.6TBASE-R scenario, the nominal rate of the first data stream is 212.5Gbps, corresponding to p=8 and q=2×p=16.

[0323] The transmitting processing module 02 receives eight AUI data streams of 1.6TAUI-8 and performs PAM4 decoding on them to obtain p = eight first data streams. Following the scheme shown in Figure 6(c), each pair of the eight first data streams undergoes first data processing to obtain one RS FEC 4-symbol delimited second data stream, resulting in a total of m = four second data streams. Then, each second data stream is processed according to the second data processing scheme in Embodiment 1 or Embodiment 2 to obtain one third data stream.

[0324] Example 4: In the 800GBASE-R scenario, the nominal rate of the first data stream is 425.0Gbps, corresponding to p=2 and q=16×p=32.

[0325] The transmitting processing module 02 receives two AUI data streams from 800GAUI-2 and performs PAM4 decoding on them to obtain p = 2 first data streams. Following the scheme shown in Figure 5(b) or Figure 5(c), the two first data streams undergo first data processing to obtain two RS FEC 4-symbol delimited second data streams. Then, each second data stream undergoes second data processing according to the scheme shown in Figure 8 to obtain one third data stream, resulting in a total of two third data streams output.

[0326] In the second data processing, the convolutional interleaver is implemented as shown in Figure 9(a) or Figure 9(b), where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 91, and based on the obtained 4-symbol boundary, each storage unit stores d = 40 bits. Each storage unit stores 40 bits corresponding to 4 RS symbols, i.e., one RS FEC 4 symbol (RS-FEC-symbol-quartet). After convolutional interleaving, the output data stream contains 12 consecutive (adjacent) RS symbols from 12 RS codewords, ensuring that the 120 information bits of each inner codeword come from 12 RS codewords, resulting in better performance of the concatenated code. Furthermore, Q = 92, 94, or 96 can be set, which is beneficial for hardware implementation and reduces system latency, making it suitable for a wider range of transmission scenarios. The block distribution, cyclic shift, inner code encoding, and padding bit insertion in the second data processing can adopt the schemes in Embodiment 1 or Embodiment 2, which will not be elaborated here.

[0327] Example 5: In the 800GBASE-R scenario, the nominal rate of the first data stream is 212.5Gbps, corresponding to p=4 and q=8×p=32.

[0328] The transmitting processing module 02 receives two AUI data streams from 800GAUI-2 and performs PAM4 decoding on them to obtain p = 2 first data streams. Following the scheme shown in Figure 6(b) or Figure 6(c), each pair of the four first data streams undergoes first data processing to obtain one RS FEC 4-symbol delimited second data stream, resulting in a total of two RS FEC 4-symbol delimited second data streams. Then, each second data stream undergoes second data processing according to the scheme shown in Figure 8 to obtain one third data stream, resulting in a total of two third data streams output. The second data processing scheme can adopt the scheme in Embodiment 4, which will not be elaborated here.

[0329] Example 6: In a 400GBASE-R scenario, the nominal rate of the first data stream is 425.0Gbps, corresponding to p=1 and q=16×p=16.

[0330] The transmitting processing module 02 receives one AUI data stream of 400GAUI-1 and performs PAM4 decoding on it to obtain a first data stream of p=1. Following the scheme shown in Figure 5(b), the first data stream undergoes first data processing to obtain a second data stream with RS FEC 4-symbol delimitation. Then, the second data stream undergoes second data processing according to the scheme shown in Figure 8 to obtain a third data stream.

[0331] In the second data processing, the convolutional interleaver is implemented as shown in Figure 9(a) or Figure 9(b), where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 181, and based on the obtained 4-symbol boundary, each storage unit stores d = 40 bits. Each storage unit stores 40 bits corresponding to 4 RS symbols, i.e., one RS FEC 4 symbol (RS-FEC-symbol-quartet). After convolutional interleaving, the output data stream contains 12 consecutive (adjacent) RS symbols from 12 RS codewords, ensuring that the 120 information bits of each inner codeword come from 12 RS codewords, resulting in better performance of the concatenated code. Furthermore, Q can be set to 182, 184, 186, 188, 190, 192, which is beneficial for hardware implementation and reduces system latency, making it suitable for a wider range of transmission scenarios. The block distribution, cyclic shift, inner code encoding, and padding bit insertion in the second data processing can adopt the schemes in Embodiment 1 or Embodiment 2, which will not be elaborated here.

[0332] Example 7: In a 400GBASE-R scenario, the nominal rate of the first data stream is 212.5Gbps, corresponding to p=2 and q=8×p=16.

[0333] The transmitting processing module 02 receives two AUI data streams from 400GAUI-2 and performs PAM4 decoding on them to obtain p = 2 first data streams. Following the scheme shown in Figure 6(a) or Figure 6(b), the two first data streams undergo first data processing to obtain one RS FEC 4-symbol delimited second data stream. Then, each second data stream undergoes second data processing according to the scheme shown in Figure 8 to obtain one third data stream. The second data processing scheme can adopt the scheme in Embodiment 6, which will not be elaborated here.

[0334] Example 8: In a future 3.2TBASE-R scenario, the nominal rate of the first data stream is 425.0Gbps, corresponding to p=8 and q=4×p=32, or q=2×p=16.

[0335] The transmitting processing module 02 receives eight AUI data streams of 3.2TAUI-8 and performs PAM4 decoding on them to obtain p = eight first data streams. Following the scheme shown in Figure 5(d), each first data stream undergoes first data processing to obtain one RS FEC 4-symbol delimited second data stream, resulting in a total of eight second data streams. Then, each second data stream undergoes second data processing according to the scheme shown in Figure 8 to obtain one third data stream, resulting in a total of eight second data streams.

[0336] In the second data processing, the convolutional interleaver is implemented as shown in Figure 9(a) or Figure 9(b), where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 23, and based on the obtained 4-symbol boundary, each storage unit stores d = 40 bits, with each storage unit storing 40 bits corresponding to 4 RS symbols, i.e., one RS FEC 4 symbol (RS-FEC-symbol-quartet). After convolutional interleaving, the output data stream contains 12 consecutive (adjacent) RS symbols from 12 RS codewords, ensuring that the 120 information bits of each inner codeword come from 12 RS codewords, resulting in better performance of the concatenated code. Furthermore, Q can be set to 24, 26, 28, 30, or 32, which is beneficial for hardware implementation and reduces system latency, making it suitable for a wider range of transmission scenarios. The block distribution, cyclic shift, inner code encoding, and padding bit insertion in the second data processing can adopt the schemes in Embodiment 1 or Embodiment 2, which will not be elaborated here.

[0337] Example 9: In a future 3.2TBASE-R scenario, the nominal rate of the first data stream is 212.5Gbps, corresponding to p=16 and q=2×p=32.

[0338] The transmitting processing module 02 receives 16 AUI data streams of 3.2TAUI-16 and performs PAM4 decoding on them to obtain p = 16 first data streams. Following the scheme shown in Figure 6(d), two of the first data streams undergo first data processing to obtain one second data stream with RS FEC 4-symbol delimitation. Then, each second data stream undergoes second data processing according to the scheme shown in Figure 8 to obtain one third data stream. The second data processing scheme can adopt the scheme in Embodiment 8, which will not be elaborated here.

[0339] Figure 19 is a schematic diagram of a data processing device according to an embodiment of this application. This data processing device is applied at the transmitting end. As shown in Figure 19, the data processing device includes a processing unit 201 and a processing unit 202. The processing unit 201 is used to execute the operation of step 101 in the above embodiment, and the processing unit 202 is used to execute the operation of step 102 in the above embodiment.

[0340] Figure 20 is a schematic diagram of another structure of the data processing device in an embodiment of this application. This data processing device is applied at the receiving end. As shown in Figure 20, the data processing device includes a receiving unit 301 and a processing unit 302. The receiving unit 301 is used to receive signals from the transmitting end, and the processing unit 302 is used to perform corresponding processing on the received signals. For example, the processing unit 302 is used to perform operations such as FEC decoding and deconvolution interleaving.

[0341] It should be understood that the data processing apparatus provided in Figures 19 and 20 can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0342] Figure 21 is a schematic diagram of an optical module structure according to an embodiment of this application. As shown in Figure 21, the optical module includes a processor 401 and an interface 402. The interface 402 can be a transceiver or an input / output interface, and is used to receive signals from other devices and transmit them to the processor 401 or to send signals from the processor 401 to other devices. Optionally, the optical module may also include a memory 403, wherein the memory 403 is used to store program instructions and data.

[0343] In one possible scenario, the optical module is used at the transmitting end, and the processor 401 is used to execute the operations of steps 101 and 102 in the above embodiments. For example, the processor 401 includes processing unit 201 and processing unit 202 as shown in FIG19. As an example, after executing the operations of steps 101 and 102 in the above embodiments, the processor 401 obtains a data stream and sends the data stream through interface 402. In this example, interface 402 can specifically refer to an electrical interface. As another example, the processor 401 executes the operations of steps 101 and 102 in the above embodiments to obtain a data stream. The modulator in the optical module performs signal processing such as electro-optic conversion according to the data stream to obtain an optical signal, and then sends the optical signal through interface 402. In this example, interface 402 can specifically refer to an optical interface.

[0344] In another possible scenario, the optical module is used at the receiving end, and the processor 401 is used to process the received signal, such as performing FEC decoding and deconvolution interleaving operations. For example, the processor 401 includes the processing unit 302 shown in FIG20. As an example, the interface receives the optical signal transmitted through the channel, the demodulator in the optical module performs signal processing such as photoelectric conversion on the optical signal to obtain a data stream, and the processor 401 performs corresponding processing operations on the data stream. In this example, the interface 402 can specifically refer to an optical interface. As another example, the demodulator in the optical module performs signal processing such as photoelectric conversion on the received optical signal to obtain a data stream, and transmits the data stream to the processor 401 through the interface 402. The processor 401 performs corresponding processing operations on the data stream. In this example, the interface 402 can specifically refer to an electrical interface.

[0345] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0346] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules connect to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0347] Figure 22 is a schematic diagram of a network device according to an embodiment of this application. As shown in Figure 22, the network device includes a host-side device 501 and an optical module 502. In one possible scenario, the network device acts as a data transmitter, with the host-side device 501 sending electrical signals to the optical module 502, which converts the electrical signals into optical signals and transmits them through a channel. In another possible scenario, the network device acts as a data receiver, with the optical module 502 converting the received optical signals into electrical signals and sending them to the host-side device 501. For example, the host-side device 501 may specifically be a switch, router, or server. It should be understood that the network device in this embodiment of the application has both transmitting and receiving functions.

[0348] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. In one possible scenario, the OTN device is used at the transmitting end, and the processor is used to execute steps 101 and 102 in the above embodiments. In another possible scenario, the OTN device is used at the receiving end, and the processor is used to execute the inverse operations of steps 101 and 102 in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices besides the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices besides the line-side equipment.

[0349] This application also provides a chip. The chip integrates circuitry for implementing the functions of the processor 401 described above, and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the processing and transmission device in the foregoing embodiments based on program code stored in the memory.

[0350] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0351] This application also provides a computer-readable storage medium including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0352] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0353] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0354] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0355] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof.

[0356] When implemented in hardware, the data transmission method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0357] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0358] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: The p first data streams encoded by Reed-Solomon RS are subjected to first data processing to obtain m second data streams, where p = m or 2m, and m is an integer greater than or equal to 1. The first data processing includes demultiplexing and alignment identifier locking. The m second data streams are subjected to second data processing to obtain m third data streams. The second data processing includes convolutional interleaving. The convolutional interleaving is used to delay the bits in the data stream before convolutional interleaving according to the three delay lines. The bits in the data stream before convolutional interleaving are sequentially input into the three delay lines according to the sequence number of the three delay lines. d bits are input into each delay line at a time and d bits are output from each delay line at a time. The three delay lines are used to delay 0 bits, Q×d bits, and 2×Q×d bits, respectively. m = 1, Q ≥ 181; Alternatively, m = 2, Q ≥ 91; Alternatively, m = 4, Q ≥ 45; Alternatively, m = 8, Q ≥ 23.

2. The method according to claim 1, characterized in that, The nominal rate of each of the m second data streams is 425 gigabits per second.

3. The method according to claim 1 or 2, characterized in that, d＝40。 4. The method according to any one of claims 1 to 3, characterized in that, The second data processing includes distribution, wherein one data stream before distribution is processed to obtain 16 distributed data streams.

5. The method according to any one of claims 1 to 4, characterized in that, The second data processing includes forward error correction (FEC) encoding and padding bit insertion. In the data stream before the padding bit insertion, 16×N padding bits are inserted after every H FEC codewords encoded by the FEC, where H is a positive integer multiple of 16. The 16×N bits include 16 bit sequences, and each bit sequence in the 16 bit sequences includes N bits. N = 128, and the values ​​of bits 127 to bit x in each of the N = 128 bits of the 16 bit sequences are as follows: In the 0th bit sequence, bits 127 to x = 124 are 0110 respectively; In the first bit sequence, bits 127 to x = 124 are 0110 respectively; In the second bit sequence, bits 127 to x = 124 are 1011 respectively; In the third bit sequence, bits 127 to x = 124 are 0101 respectively; In the 4th bit sequence, bits 127 to x = 124 are 0110 respectively; In the 5th bit sequence, bits 127 to x = 124 are 0101 respectively; In the 6th bit sequence, bits 127 to x = 124 are 0010 respectively; In the 7th bit sequence, bits 127 to x = 124 are 1011 respectively; In the 8th bit sequence, bits 127 to x = 126 are 0 and 1 respectively; In the 9th bit sequence, bits 127 to x = 126 are 10 in sequence; In the 10th bit sequence, bits 127 to x = 126 are 0 and 1 respectively; In the 11th bit sequence, bits 127 to x = 126 are 00 respectively; In the 12th bit sequence, bits 127 to x = 126 are 10 respectively; In the 13th bit sequence, bits 127 to x = 126 are 10 respectively; In the 14th bit sequence, bits 127 to x = 126 are 0 and 1 respectively; In the 15th bit sequence, bits 127 to x = 126 are 10 in sequence.

6. The method according to any one of claims 1 to 5, characterized in that, The second data processing includes cyclic shifting, wherein the number of symbols cyclically shifted to the right for every 12 consecutive symbols in each of the 16 data streams preceding the cyclic shift is as follows: In Article 0, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 0 symbols to the right; In the data stream prior to the cyclic shift described in Article 1, every 12 consecutive symbols are cyclically shifted 3 symbols to the right; In Article 2, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 6 symbols to the right; In Article 3, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted to the right by 9 symbols; In Article 4, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted to the right by 1 symbol; In Article 5, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 4 symbols to the right; In Article 6, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 7 symbols to the right; In Article 7, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 10 symbols to the right; In Article 8, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 0 symbols to the right; In Article 9, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 3 symbols to the right; In Article 10, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 6 symbols to the right; In Article 11, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 9 symbols to the right; In Article 12, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted to the right by 1 symbol; In Article 13, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 4 symbols to the right; In Article 14, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 7 symbols to the right; In Article 15, every 12 consecutive symbols in the data stream prior to the cyclic shift are cyclically shifted 10 symbols to the right.

7. The method according to any one of claims 1 to 6, characterized in that, The nominal rate of each first data stream is 425 gigabits per second, m = p, and each first data stream is demultiplexed to obtain t data streams, where t = 2, 4 or 16.

8. The method according to claim 7, characterized in that, p = 1 or 2; performing first data processing on the p first data streams to obtain m second data streams includes: Each of the p first data streams is demultiplexed to obtain 16 fourth data streams, resulting in a total of 16p fourth data streams; Alignment identifier locking is performed on the 16 fourth data streams to obtain 1 second data stream, resulting in a total of m second data streams.

9. The method according to claim 7, characterized in that, p = 4 or 8; performing first data processing on the p first data streams to obtain m second data streams includes: Each of the p first data streams is demultiplexed to obtain 4 fourth data streams, resulting in a total of 4p fourth data streams; Alignment identifier locking is performed on the four fourth data streams to obtain one second data stream, resulting in a total of four second data streams.

10. The method according to claim 7, characterized in that, p = 8; Performing first data processing on the p first data streams to obtain m second data streams includes: Each of the eight first data streams is demultiplexed to obtain two fourth data streams, resulting in a total of 16 fourth data streams; Alignment identifier locking is performed on the two fourth data streams to obtain one second data stream, resulting in a total of four second data streams.

11. The method according to claim 7, characterized in that, p = 1 or 2; performing first data processing on any of the p first data streams includes: Demultiplexing any of the first data streams yields 16 fourth data streams; Alignment identifiers are locked on the 16 fourth data streams to obtain 16 fifth data streams, and the 16 fifth data streams correspond to 16 physical coding sublayer PCS channel data streams respectively; The 16 fifth data streams are de-skewed to obtain 16 sixth data streams; The sixth data streams with odd PCS channel numbers in the 16 sixth data streams are delayed to obtain 16 seventh data streams; The 16 seventh data streams are multiplexed to obtain one second data stream.

12. The method according to claim 7, characterized in that, p = 4 or 8; performing first data processing on any one of the p first data streams includes: Demultiplex any of the first data streams to obtain four fourth data streams; Alignment identifiers are locked on the four fourth data streams to obtain four fifth data streams; The four fifth data streams are de-skewed to obtain four sixth data streams; The four sixth data streams are multiplexed to obtain one second data stream.

13. The method according to any one of claims 1 to 6, characterized in that, The nominal rate of each first data stream is 212.5 Gbits per second, and the first data processing also includes multiplexing, p = 2m.

14. The method according to claim 13, characterized in that, When p = 2, performing first data processing on the p first data streams to obtain m second data streams includes: Each of the two first data streams is demultiplexed to obtain eight fourth data streams, resulting in a total of 16 fourth data streams; Alignment identifier locking is performed on the eight fourth data streams to obtain one fifth data stream, resulting in a total of two fifth data streams; The two fifth data streams are multiplexed to obtain one second data stream.

15. The method according to claim 13, characterized in that, When p = 2, performing first data processing on the p first data streams to obtain m second data streams includes: Each of the two first data streams is demultiplexed to obtain eight fourth data streams, resulting in a total of 16 fourth data streams; Alignment identifiers are locked on the eight fourth data streams to obtain eight fifth data streams, resulting in a total of 16 fifth data streams. Each of the 16 fifth data streams corresponds to one of the 16 PCS channel data streams. The 16 fifth data streams are de-skewed to obtain 16 sixth data streams; The sixth data streams with odd PCS channel numbers in the 16 sixth data streams are delayed to obtain 16 seventh data streams; The 16 seventh data streams are multiplexed to obtain one second data stream.

16. The method according to claim 13, characterized in that, When p = 2, performing first data processing on the p first data streams to obtain m second data streams includes: Each first data stream in the first data stream is demultiplexed to obtain 8 fourth data streams, resulting in a total of 16 fourth data streams; Alignment identifier locking is applied to the eight fourth data streams to obtain eight fifth data streams, resulting in a total of 16 fifth data streams; The 16 fifth data streams are de-skewed to obtain 16 sixth data streams; The sixth data streams with odd PCS channel numbers in the 16 sixth data streams are delayed to obtain 16 seventh data streams; The first multiplexing is performed on every 8 seventh data streams out of the 16 seventh data streams to obtain 1 eighth data stream, resulting in a total of 2 eighth data streams. The granularity of the first multiplexing is RS symbol pairs. The two eighth data streams are multiplexed a second time to obtain a second data stream, wherein the granularity of the second multiplexing is a positive integer multiple of RS-FEC 4 symbols.

17. The method according to claim 13, characterized in that, p=4, the 4 first data streams include 2 groups of first data streams, each of the 2 groups of first data streams includes 2 first data streams, and performing first data processing on any one of the 2 groups of first data streams includes: Each of the first data streams in any group of first data streams is demultiplexed to obtain 8 fourth data streams, resulting in a total of 16 fourth data streams; Alignment identifier locking is applied to the eight fourth data streams to obtain eight fifth data streams, resulting in a total of 16 fifth data streams; The 16 fifth data streams are de-skewed to obtain 16 sixth data streams; The sixth data streams with odd PCS channel numbers in the 16 sixth data streams are delayed to obtain 16 seventh data streams; The 16 seventh data streams are multiplexed to obtain one second data stream.

18. The method according to claim 13, characterized in that, p=4, the 4 first data streams include 2 groups of first data streams, each of the 2 groups of first data streams includes 2 first data streams, and performing first data processing on any one of the 2 groups of first data streams includes: Each of the first data streams in any group of first data streams is demultiplexed to obtain 8 fourth data streams, resulting in a total of 16 fourth data streams. The granularity of the demultiplexing is RS symbol pairs. Alignment identifier locking is applied to the eight fourth data streams to obtain eight fifth data streams, resulting in a total of 16 fifth data streams; The 16 fifth data streams are de-skewed to obtain 16 sixth data streams; The sixth data streams with odd PCS channel numbers in the 16 sixth data streams are delayed to obtain 16 seventh data streams; The first multiplexing is performed on every 8 seventh data streams out of the 16 seventh data streams to obtain 1 eighth data stream, resulting in a total of 2 eighth data streams. The granularity of the first multiplexing is RS symbol pairs. The two eighth data streams are multiplexed a second time to obtain a second data stream, wherein the granularity of the second multiplexing is a positive integer multiple of RS-FEC 4 symbols.

19. The method according to claim 13, characterized in that, p=8, the 8 first data streams include 4 groups of first data streams, each of the 4 groups of first data streams includes 2 first data streams, and the first data processing for any one of the 4 groups of first data streams includes: Each first data stream in any set of first data streams is demultiplexed to obtain two fourth data streams, resulting in a total of four fourth data streams; Alignment identifier locking is applied to the two fourth data streams to obtain two fifth data streams, resulting in a total of four fifth data streams; The four fifth data streams are de-skewed to obtain four sixth data streams; The four sixth data streams are multiplexed to obtain one second data stream.

20. The method according to claim 13, characterized in that, p=16, the 16 first data streams include 8 groups of first data streams, each of the 8 groups of first data streams includes 2 first data streams, and the first data processing for any one of the 8 groups of first data streams includes: Each first data stream in any set of first data streams is demultiplexed to obtain two fourth data streams, resulting in a total of four fourth data streams; Alignment identifier locking is applied to the two fourth data streams to obtain two fifth data streams, resulting in a total of four fifth data streams; The four fifth data streams are de-skewed to obtain four sixth data streams; The four sixth data streams are multiplexed to obtain one second data stream.

21. The method according to claim 14, 19 or 20, characterized in that, The granularity of the reuse is a positive integer multiple of the RS-FEC 4 symbol.

22. The method according to claim 15 or 17, characterized in that, The granularity of the reuse is RS symbol pairs.

23. A data processing method, characterized in that, include: Receive m third data streams, which are obtained from m second data streams through second data processing. The m second data streams are obtained from p first data streams encoded by Reed-Solomon RS through first data processing, where p = m or 2m, and m is an integer greater than or equal to 1. The first data processing includes demultiplexing and alignment identifier locking. The second data processing includes convolutional interleaving. The convolutional interleaving is used to delay the bits in the data stream before convolutional interleaving according to the three delay lines. The bits in the data stream before convolutional interleaving are input to the three delay lines in sequence according to the sequence number of the three delay lines, with d bits input to each delay line at a time and d bits output from each delay line at a time. The three delay lines are used to delay 0 bits, Q×d bits, and 2×Q×d bits, respectively. m = 1, Q ≥ 181; Alternatively, m = 2, Q ≥ 91; Alternatively, m = 4, Q ≥ 45; Alternatively, m = 8, Q ≥ 23.

24. The method according to claim 23, characterized in that, The nominal rate of each first data stream is 425 gigabits per second, where m = p.

25. The method according to claim 23, characterized in that, The nominal rate of each first data stream is 212.5 Gbits per second, and the first data processing also includes multiplexing, p = 2m.

26. A data processing apparatus, characterized in that, The data processing device includes: a first processing unit and a second processing unit; The first processing unit is configured to: perform first data processing on p first data streams encoded by Reed-Solomon RS to obtain m second data streams, where p = m or 2m, and m is an integer greater than or equal to 1; the first data processing includes demultiplexing and alignment identifier locking. The second processing unit is used to: perform second data processing on the m second data streams respectively to obtain m third data streams, wherein the second data processing includes convolutional interleaving; the convolutional interleaving is used to delay the bits in the data stream before convolutional interleaving according to the three delay lines, wherein the bits in the data stream before convolutional interleaving are sequentially input into the three delay lines according to the sequence number of the three delay lines, d bits are input into each delay line at a time and d bits are output from each delay line at a time, wherein the three delay lines are used to delay 0 bits, Q×d bits and 2×Q×d bits respectively; m = 1, Q ≥ 181; Alternatively, m = 2, Q ≥ 91; Alternatively, m = 4, Q ≥ 45; Alternatively, m = 8, Q ≥ 23.

27. The data processing apparatus according to claim 26, characterized in that, The nominal rate of each of the m second data streams is 425 gigabits per second.

28. The data processing apparatus according to claim 26 or 27, characterized in that, d＝40。 29. The data processing apparatus according to any one of claims 26 to 28, characterized in that, The second data processing includes distribution, wherein one data stream before distribution is processed to obtain 16 distributed data streams.

30. The data processing apparatus according to any one of claims 26 to 29, characterized in that, The second data processing includes forward error correction (FEC) encoding and padding bit insertion. In the data stream before the padding bit insertion, 16×N padding bits are inserted after every H FEC codewords encoded by the FEC, where H is a positive integer multiple of 16. The 16×N bits include 16 bit sequences, and each bit sequence in the 16 bit sequences includes N bits. N = 128, and the values ​​of bits 127 to bit x in each of the N = 128 bits of the 16 bit sequences are as follows: In the 0th bit sequence, bits 127 to x = 124 are 0110 respectively; In the first bit sequence, bits 127 to x = 124 are 0110 respectively; In the second bit sequence, bits 127 to x = 124 are 1011 respectively; In the third bit sequence, bits 127 to x = 124 are 0101 respectively; In the 4th bit sequence, bits 127 to x = 124 are 0110 respectively; In the 5th bit sequence, bits 127 to x = 124 are 0101 respectively; In the 6th bit sequence, bits 127 to x = 124 are 0010 respectively; In the 7th bit sequence, bits 127 to x = 124 are 1011 respectively; In the 8th bit sequence, bits 127 to x = 126 are 0 and 1 respectively; In the 9th bit sequence, bits 127 to x = 126 are 10 in sequence; In the 10th bit sequence, bits 127 to x = 126 are 0 and 1 respectively; In the 11th bit sequence, bits 127 to x = 126 are 00 respectively; In the 12th bit sequence, bits 127 to x = 126 are 10 respectively; In the 13th bit sequence, bits 127 to x = 126 are 10 respectively; In the 14th bit sequence, bits 127 to x = 126 are 0 and 1 respectively; In the 15th bit sequence, bits 127 to x = 126 are 10 in sequence.

31. The data processing apparatus according to any one of claims 26 to 30, characterized in that, The second data processing includes cyclic shifting, wherein the number of symbols cyclically shifted to the right for every 12 consecutive symbols in each of the 16 data streams preceding the cyclic shift is as follows: In Article 0, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 0 symbols to the right; In the data stream prior to the cyclic shift described in Article 1, every 12 consecutive symbols are cyclically shifted 3 symbols to the right; In Article 2, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 6 symbols to the right; In Article 3, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted to the right by 9 symbols; In Article 4, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted to the right by 1 symbol; In Article 5, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 4 symbols to the right; In Article 6, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 7 symbols to the right; In Article 7, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 10 symbols to the right; In Article 8, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 0 symbols to the right; In Article 9, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 3 symbols to the right; In Article 10, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 6 symbols to the right; In Article 11, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 9 symbols to the right; In Article 12, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted to the right by 1 symbol; In Article 13, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 4 symbols to the right; In Article 14, every 12 consecutive symbols in the data stream before the cyclic shift are cyclically shifted 7 symbols to the right; In Article 15, every 12 consecutive symbols in the data stream prior to the cyclic shift are cyclically shifted 10 symbols to the right.

32. The data processing apparatus according to any one of claims 26 to 31, characterized in that, The nominal rate of each first data stream is 425 gigabits per second, m = p, and each first data stream is demultiplexed to obtain t data streams, where t = 2, 4 or 16.

33. The data processing apparatus according to any one of claims 26 to 31, characterized in that, The nominal rate of each first data stream is 212.5 Gbits per second, and the first data processing also includes multiplexing, p = 2m.

34. A data processing apparatus, characterized in that, The data processing device includes: a receiving unit; The receiving unit is configured to: receive m third data streams, wherein the m third data streams are obtained by processing m second data streams through second data processing; the m second data streams are obtained by processing p first data streams encoded by Reed-Solomon RS through first data processing, where p = m or 2m, and m is an integer greater than or equal to 1; the first data processing includes demultiplexing and alignment identifier locking; the second data processing includes convolutional interleaving; the convolutional interleaving is used to delay the bits in the data stream before convolutional interleaving according to the three delay lines; the bits in the data stream before convolutional interleaving are sequentially input into the three delay lines according to the sequence number of the three delay lines, with d bits input into each delay line at a time and d bits output from each delay line at a time; the three delay lines are respectively used to delay 0 bits, Q×d bits, and 2×Q×d bits; m = 1, Q ≥ 181; Alternatively, m = 2, Q ≥ 91; Alternatively, m = 4, Q ≥ 45; Alternatively, m = 8, Q ≥ 23.

35. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 25.

36. An optical module, characterized in that, The optical module includes a processor and an interface, the interface being used for transmitting and receiving signals, and the processor being used for performing the method as described in any one of claims 1 to 25.

37. A network device, characterized in that, The network device includes a host-side device and an optical module as described in claim 36; the optical module is used to convert electrical signals from the host-side device into optical signals and transmit the optical signals, or the optical module is used to convert received optical signals into electrical signals and transmit the electrical signals to the host-side device.

38. A communication system, characterized in that, It includes a plurality of network devices as described in claim 37, wherein the plurality of network devices are used to send optical signals to each other.

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