Non-volatile memory rapid recovery method based on metadata priority and on-demand loading

Abstract

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

Description

Technical Field

[0001] This invention relates to the field of computer system architecture and storage technology, and in particular to a fast recovery method for non-volatile memory based on metadata priority and on-demand loading. Background Technology

[0002] Existing NVDIMM systems generally employ a "full blocking recovery" strategy. This means that during system power-on initialization, the controller only releases bus control to the processor after all business data on non-volatile media has been completely migrated to volatile memory. This mechanism results in a linear positive correlation between system recovery time (RTO) and memory capacity. In scenarios with terabyte-level memory, system startup delays can reach several minutes or even tens of minutes, failing to meet the rapid deployment requirements of critical services. During this lengthy full data migration process, processor cores are forced into a suspended or idling state, unable to execute any valid instructions. This leads to valuable computing resources being completely idle during the recovery window, reducing the overall energy efficiency of the system and severely delaying the availability of system services. Traditional recovery methods lack awareness and grading mechanisms for data importance, employing a "blind" linear sequential recovery model that fails to distinguish between critical control data required to maintain the system's operational architecture and ordinary cold data. This undifferentiated processing means that even if critical system services only require a small amount of data to start, they must wait for irrelevant data to be recovered, severely impacting the timely response of core services.

[0003] In summary, existing technologies suffer from problems such as strong coupling between data recovery volume and system startup time, low utilization of computing resources, and lack of priority guarantee mechanisms for critical business operations, which urgently need to be addressed. Summary of the Invention

[0004] Therefore, it is necessary to provide a fast recovery method for non-volatile memory based on metadata priority and on-demand loading to solve at least one of the above-mentioned technical problems.

[0005] To achieve the above objectives, a fast non-volatile memory recovery method based on metadata priority and on-demand loading includes the following steps:

[0006] Step S1: In response to the system fault signal detected by the voltage monitoring unit, freeze the processor context and traverse the page table structure to extract system configuration information; encode the system configuration information and the service data in volatile memory and write them into the non-volatile medium to generate a persistent state image;

[0007] Step S2: Parse the persistent state image, extract address translation metadata, and reconstruct the mapping relationship between virtual addresses and physical page frames in volatile memory; generate an address mapping table, in which the physical page frames pointed to by the address mapping table are set to exist but not associated with valid business data;

[0008] Step S3: Mark the status of physical page frames based on the address mapping table; configure the logic of the hardware interception circuit to generate an interception status bitmap to indicate the validity of physical page frame data;

[0009] Step S4: Monitor bus transactions using the intercepted state bitmap, suspend access to physical page frames in invalid data states through hardware interception circuitry and generate page fault load requests; control the direct memory access engine to load data from the persistent state image to volatile memory based on the page fault load requests; update the intercepted state bitmap to the valid data state and resume the suspended transactions.

[0010] This invention achieves timing decoupling between control flow startup and data flow recovery by prioritizing the reconstruction of processor context and address mapping metadata during the initial stage of system reset and constructing a "virtual ready" state of the memory subsystem in conjunction with a hardware intercept bitmap. This completely breaks the strong linear coupling between system recovery time (RTO) and memory capacity, improving the startup time of TB-level large-capacity memory systems. At the same time, by utilizing the granular on-demand loading mechanism of bus suspend and direct memory access engine, idle and wasted processor computing resources are eliminated while ensuring data consistency. This enables critical business data to achieve immediate response and transparent recovery according to the instruction execution flow, significantly improving system availability and energy efficiency. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the steps of a fast non-volatile memory recovery method based on metadata priority and on-demand loading.

[0012] Figure 2 This is a schematic diagram of the non-volatile memory recovery system architecture in this invention;

[0013] Figure 3 This is a schematic diagram of the hardware interception process in this invention. Detailed Implementation

[0014] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0015] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0016] It should be understood that the term “and / or” as used herein includes any and all combinations of one or more of the associated items listed.

[0017] To achieve the above objectives, please refer to Figures 1 to 3 This invention provides a fast non-volatile memory recovery method based on metadata priority and on-demand loading, comprising the following steps:

[0018] Step S1: In response to the system fault signal detected by the voltage monitoring unit, freeze the processor context and traverse the page table structure to extract system configuration information; encode the system configuration information and the service data in volatile memory and write them into the non-volatile medium to generate a persistent state image;

[0019] In this embodiment of the invention, the non-volatile memory controller monitors the main power supply voltage in real time through its internal analog-to-digital converter. When the continuously sampled value falls below a preset threshold, an emergency mode flag is triggered. The controller then suspends processor instruction execution via a non-maskable interrupt and quickly transfers context data, such as general-purpose registers and status registers, to an internal buffer using the direct memory access channel. Simultaneously, the controller's traversal engine starts from the page table base address register and performs a deep traversal of the multi-level page table structure to extract valid page table entries and generate an address translation table set. Subsequently, the controller starts the multi-channel direct memory access engine, reads physical memory data in parallel, calculates checksums, and finally writes the processor context, address translation table, and all business data sequentially into the non-volatile medium according to a predetermined format, constructing a persistent state image including a header index and a tail checksum.

[0020] Step S2: Parse the persistent state image, extract address translation metadata, and reconstruct the mapping relationship between virtual addresses and physical page frames in volatile memory; generate an address mapping table, in which the physical page frames pointed to by the address mapping table are set to exist but not associated with valid business data;

[0021] In this embodiment of the invention, after the system powers on and resets, the controller first verifies the global checksum of the persistent state image and parses the image header descriptor to locate the metadata storage offset. Based on this, the controller reads the processor context data into the shadow register and performs zeroing and permission locking initialization on a specific reserved area in volatile memory. Subsequently, the controller extracts the top-level page table pointer from the image, reconstructs the page table hierarchy, and writes the separated page table control data into the reserved area. During this process, the controller relocates and corrects the physical address field in the page table entries and forcibly sets the valid bit flag of the leaf nodes, thereby establishing a complete logical address mapping table in volatile memory, even if the physical page frame has not yet loaded any valid service data.

[0022] Step S3: Mark the status of physical page frames based on the address mapping table; configure the logic of the hardware interception circuit to generate an interception status bitmap to indicate the validity of physical page frame data;

[0023] In this embodiment of the invention, the controller initializes a bitmap array covering the entire physical memory in its internal memory and identifies critical system regions and ordinary service regions based on an address mapping table. The controller directly marks the bitmap status bits corresponding to the critical regions as ready, while marking the ordinary service regions as pending backfilling, forming a differentiated status table. Subsequently, this status table is compressed using hardware run-length encoding and loaded into a tightly coupled on-chip cache. The controller also configures the comparison logic of the hardware interception circuit to perform real-time logical binding between the bus address and the status bits in the cache, and enables the interception function, thereby generating an active interception status bitmap used to indicate the data validity of each physical page frame in real time.

[0024] Step S4: Monitor bus transactions using the intercepted state bitmap, suspend access to physical page frames in invalid data states through hardware interception circuitry and generate page fault load requests; control the direct memory access engine to load data from the persistent state image to volatile memory based on the page fault load requests; update the intercepted state bitmap to the valid data state and resume the suspended transactions;

[0025] In this embodiment of the invention, the controller captures read and write transactions in real time through the front-side bus interface and uses a hardware comparator to perform a single-cycle comparison between the target physical address and the intercepted status bitmap. If the status is "pending backfill," the controller immediately sends a retry or wait signal to the bus to suspend the transaction and pushes the request into the direct memory access scheduling queue. The scheduling logic merges consecutive requests and calculates the physical offset of the source data in the non-volatile medium to generate an optimized loading task. The direct memory access engine then starts a bypass transmission channel, bypassing the processor cache to write the data block to volatile memory and perform verification. After successful verification, the controller uses atomic operations to flip the bitmap status to "ready" and notifies the bus controller to restart the suspended transaction, realizing transparent on-demand loading of business data.

[0026] Preferably, step S1 includes:

[0027] The voltage monitoring unit detects the main power rail voltage and generates an emergency mode control flag when the voltage is abnormal.

[0028] In response to the emergency mode control flag, the processor is controlled to complete the current instruction cycle and stop instruction fetching, and the register state is transferred to the buffer of the non-volatile memory controller to generate a processor status data packet;

[0029] Read the base address register of the system memory management unit and traverse multiple levels of page tables to generate a set of address translation tables;

[0030] Based on the address translation table set, scan volatile memory and mark allocated page frames to construct a memory persistence task table;

[0031] Start the direct memory access engine, transfer data according to the memory persistence task table and calculate the checksum to generate a data block check set;

[0032] The processor state data packet, address translation table set, and data block check set are encapsulated and written into a non-volatile medium to generate a persistent state image.

[0033] In one embodiment, the operation of detecting the main power rail voltage using a voltage monitoring unit is specifically implemented through an analog-to-digital converter integrated within the non-volatile memory controller. This converter samples the 12-volt power rail voltage of the motherboard in real time. The controller has a preset voltage drop threshold of 10.8 volts. When the sampled voltage value is below 10.8 volts for three consecutive cycles, the hardware comparator circuit outputs a low-level trigger signal, directly setting the emergency mode bit in the controller's status register and generating an emergency mode control flag.

[0034] In another embodiment, the operation of controlling the processor to complete the current instruction cycle and stop instruction fetching in response to the emergency mode control flag, and transferring the register state to the buffer of the non-volatile memory controller includes: the controller sending a non-maskable interrupt request to the processor via a system bus sideband signal line. The processor responds to the interrupt, completes the current instruction pipeline operation, and then pauses instruction fetching. Subsequently, the processor executes a preset microcode sequence, sequentially packaging the current values ​​of the general-purpose registers, program counter, and status register, and writing them to the controller's internal 4KB dedicated static random access memory buffer in burst transfer mode via the direct memory access channel, generating a processor status data packet.

[0035] In one embodiment, the operation of reading the base address register of the system memory management unit and traversing multiple levels of page tables is performed by the page table traversal engine inside the controller. The engine reads the physical address from the processor's page table base address register CR3 to locate the top-level page table PML4 in volatile memory. Using a depth-first search algorithm, based on the presence of bit flags in the page table entries, it accesses the page directory pointer table PDPT, page directory PD, and page table PT level by level. During the traversal, the physical page frame number and read / write permission bits of each valid page table entry are extracted, and an address translation table set is generated according to the hierarchical structure.

[0036] In another embodiment, the operation of scanning volatile memory and marking allocated page frames based on the address translation table set is implemented by establishing a physical page frame bitmap. The controller initializes a bitmap region covering the entire system's physical memory in internal memory, with each bit corresponding to a 4KB physical page. All valid physical page frame numbers recorded in the address translation table set are parsed, and the corresponding index bit position in the bitmap is set to 1. The total number of bits set to 1 in the bitmap is counted, and adjacent page frames are merged into a start address plus length descriptor format according to physical address continuity to construct a memory persistence task table.

[0037] In one embodiment, the Direct Memory Access Engine (DME) is activated, and the operation of transmitting data and calculating checksums based on the persistent memory task table employs a multi-channel parallel transmission mechanism. The DME is configured with four independent channels, each reading tasks from different address segments in the persistent memory task table. While each channel reads data from volatile memory, it simultaneously calculates a 32-bit cyclic redundancy check (CRC32) code for the data block in real time using hardware CRC32 logic. The read data stream and the calculated checksum are pipelined and merged within the controller to generate a data block checksum set.

[0038] In another embodiment, the operation of encapsulating and writing the processor status data packet, address translation table set, and data block checksum to the non-volatile medium follows a specific image file format. The controller first writes a file header containing the current timestamp and version number to a reserved sector of the non-volatile medium. Then, the processor status data packet and address translation table set are written sequentially, and their offsets in the medium are recorded. Finally, the data block checksum is written to the medium's data area at full speed in a sequential write manner. After writing is complete, the controller calculates the global checksum of the entire image file and writes it to the end of the file, generating a persistent state image.

[0039] Preferably, step S2 includes:

[0040] Verify the integrity of the persistent state image and extract the image file descriptor containing the file offset;

[0041] Parse the index area in the image file descriptor to locate the storage location of system configuration information and generate a metadata index table;

[0042] The processor context is read from the metadata index table, the processor runtime environment is parsed and restored, and a processor recovery state set is generated.

[0043] Perform zeroing and permission settings on a specific physical address range of volatile memory, and initialize the metadata reservation area used to store the recovery control structure.

[0044] In one embodiment, verifying the integrity of the persistent state image specifically includes: during the initialization phase after system power-on reset, the non-volatile memory controller reads 64 bytes of data from a predefined starting sector of the non-volatile medium via a serial peripheral interface. This data contains the persistent state image file header signature and a global checksum. The controller uses its internal hardware hash engine to calculate the CRC32 value of the read data and compares it with the stored global checksum. If the comparison matches, the image is deemed valid, and the length and offset information of each data segment recorded in the file header are parsed to extract the image file descriptor.

[0045] In another embodiment, parsing the index area in the image file descriptor is specifically achieved by directly reading the index segment of the non-volatile medium. The controller initiates a 4KB read operation based on the metadata segment offset address specified in the image file descriptor. The read data is loaded into the controller's internal cache, and the controller parses the data block to identify the starting offset of the processor status data packet. ,length and the starting offset of the address translation table set ,length These specific address location information are combined and stored in the controller register group, generating a metadata index table.

[0046] In one embodiment, the process of reading the processor context based on the metadata index table is performed as follows: the controller, based on... and The parameters initiate the direct memory access engine to read processor status data packets from non-volatile media into the internal SRAM buffer. The controller's parsing logic separates the values ​​of general-purpose registers R0 to R15, the program counter (PC), and the status register (CPSR) from the data packets according to a predetermined format. These values ​​are mapped to the controller's shadow register set, preparing for subsequent steps to write back to the processor core via the system bus to generate the processor recovery state set.

[0047] In another embodiment, the operation of clearing and setting permissions for a specific physical address range of volatile memory is as follows: The controller selects a 1MB contiguous space from physical addresses 0x10000000 to 0x10100000 as a reserved area. The controller sends a fast clear instruction through the memory interface to reset all data bits in this area to 0. Subsequently, the controller modifies the internal memory protection unit configuration table to set the access attribute of this 1MB address range to be writable only in privileged mode and not cacheable, preventing metadata from being tampered with or polluted by the processor data cache during subsequent recovery, thus completing the initialization of the metadata reserved area.

[0048] Preferably, step S2, before generating the address mapping table, further includes:

[0049] Based on the metadata index table, locate the storage offset of the top-level page table in the non-volatile medium and obtain the top-level page table pointer set;

[0050] Using the top-level page table pointer set as the root node, traverse multiple levels of page table hierarchy to construct a page table structure link tree;

[0051] Extract control bits and address fields from page table entries in batches from the page table structure link tree, strip the business data content they point to, and generate a separate page table entry stream;

[0052] Perform a relocation calculation based on the current memory layout on the physical address field in the split page table entry stream to generate corrected virtual-physical address mapping data.

[0053] In one embodiment, locating the storage offset of the top-level page table in the non-volatile medium based on the metadata index table specifically involves the following steps: The controller reads the description entry for the address translation table set in the metadata index table and parses out the physical storage location of the top-level page table (PML4) recorded therein. This location information exists in the form of a byte offset relative to the starting sector of the non-volatile medium. The controller extracts this offset value and stores it in an internal dedicated pointer register, which serves as the root node index for subsequent page table tree reconstruction to obtain the top-level page table pointer set.

[0054] In another embodiment, traversing the multi-level page table hierarchy with the top-level page table pointer set as the root node specifically involves: the controller initiating an internal page table reconstruction state machine, using the top-level page table pointer set as the entry address, and launching a read request to the non-volatile media. The state machine first reads the contents of the PML4 page table, and for each valid entry PML4E, extracts its storage offset pointing to the next-level page directory pointer table PDPT. Subsequently, the state machine recursively reads PDPT, page directory PD, and page table PT, establishing parent-child links between page table nodes at each level in the controller's internal temporary buffer, recording the physical location and hierarchy depth of each level of page table in the non-volatile media, and constructing a page table structure link tree.

[0055] In one embodiment, the batch extraction of control bits and address fields from page table entries in the page table structure link tree specifically includes: the controller traverses the page table structure link tree in the buffer and performs bit field parsing on each page table entry (PTE). The controller uses a mask operation to extract the 0th bit (Presence P), the 1st bit (Read / Write permission RW), the 2nd bit (User / Superuser US), and bits 12 to 51 (Physical Page Frame Number PFN) from the PTE. Simultaneously, the controller ignores the actual 4KB physical page data pointed to by the PFN, retaining only the 64-bit descriptor data of the PTE itself. All extracted PTEs are arranged sequentially in the virtual address space to generate a split page table entry stream.

[0056] In another embodiment, performing a relocation calculation based on the current memory layout on the physical address field in the split page table entry stream specifically involves the controller calculating the starting physical address of the metadata reservation area. This involves correcting the pointers to the next-level page table in the split page table entry stream. Let the relative offset of the pointer to the next-level page table in the original page table entry be... Then the corrected physical address The calculation formula is The controller uses its internal arithmetic logic unit (ALU) to perform this addition operation on the physical address field of each non-leaf node page table entry, ensuring that the reconstructed page table structure accurately points to the new location within the reserved area, and generating the corrected virtual-physical address mapping data.

[0057] Preferably, generating the address mapping table in step S2 specifically includes:

[0058] Based on the starting physical address of the metadata reservation area, the virtual and physical address mapping data is written into volatile memory, and physically residing discrete page table entries are deployed.

[0059] Modify the physical address field pointing to the next level page table in the discrete page table entries to the absolute physical address in the metadata reservation area, and construct a structurally connected page table tree;

[0060] Set the valid bit flag of the leaf node in the page table tree and retain the original access permission attributes to construct a complete attribute mapping network that presents a valid state to the memory management unit;

[0061] The computational attributes fully map the root directory base address of the network and publish it to the processor's control register, generating an address mapping table.

[0062] In one embodiment, the operation of writing virtual-physical address mapping data into volatile memory, based on the starting physical address of the metadata reservation area, specifically includes: the controller activating the direct memory access channel, using the predefined starting physical address of the metadata reservation area (0x10000000) as the base address register value. The controller reads the virtual-physical address mapping data from the internal buffer and writes it into the reservation area of ​​volatile memory in a 4KB page alignment manner. The writing process strictly follows the x86 architecture page table storage specification, ensuring that each page table entry occupies 8 bytes and each page table occupies 4096 bytes, thereby deploying physically residing discrete page table entries within the reservation area.

[0063] In another embodiment, modifying the physical address field pointing to the next-level page table in a discrete page table entry to an absolute physical address within the metadata reservation area involves the following steps: The controller traverses each page directory entry (PDE) written to the reservation area. For each PDE, it reads the physical page frame number field from bits 12 to 51, whose original value points to the old physical address before the fault. The controller uses a preset address mapping table to replace this old physical page frame number with the current absolute physical page frame number of the corresponding next-level page table within the reservation area. For example, if the next-level page table is stored at offset 0x2000 in the reservation area, the physical address field in the PDE is corrected to 0x10002000, constructing a structurally connected page table tree.

[0064] In one embodiment, the operation of setting the valid bit flag of the leaf node in the page table tree and preserving the original access permission attributes includes: the controller locates all last-level page table entries (PTEs) in the page table tree. The controller uses bit manipulation instructions to force the 0th bit (Present Bit) of each PTE to be 1, even if the 4KB physical page pointed to by the PTE is not currently loaded with valid data. At the same time, the controller keeps the original values ​​of the 1st bit (R / W) and the 2nd bit (U / S) unchanged, ensuring that the restored memory access permissions are consistent with those before the failure. This operation deceives the memory management unit into believing that all virtual pages are physically ready, constructing a complete attribute mapping network that presents a valid state to the memory management unit.

[0065] In another embodiment, calculating the root directory base address of the complete attribute mapping network and publishing it to the processor's control register specifically involves: the controller obtaining the physical start address of the top-level page table PML4 stored in the metadata reservation area. This address value is then written into the mirror value of the processor's page table base address register CR3. Subsequently, the controller triggers a system reset end signal, and the processor reads this CR3 mirror value in the first instruction cycle after the reset is released, thereby loading a completely new page table structure, establishing the logical addressing capability of the entire system, and generating an address mapping table.

[0066] Preferably, the step S3 of generating the interception status bitmap for indicating the validity of physical page frame data specifically includes:

[0067] Initialize a memory page state array covering the entire physical memory range in the internal memory of the non-volatile memory controller;

[0068] Traverse the address mapping table to identify the physical page frame distribution of critical system areas and ordinary business areas, and generate a page frame classification list;

[0069] Update the memory page status array based on the page frame classification list, mark the page frames in the key area as ready, mark the page frames in the ordinary business area as pending backfilling, and generate a differentiated status page frame table.

[0070] Configure the hardware interception circuit to set address matching rules and suspend actions, and generate an interception control parameter set;

[0071] Spatial compression encoding is performed on the differentiated state page frame table to generate an optimized state bitmap;

[0072] The optimized state bitmap is loaded into the on-chip cache and associated with the interception control parameter set to generate the interception state bitmap.

[0073] In one embodiment, initializing a memory page state array covering the entire physical memory range in the internal memory of the non-volatile memory controller specifically involves the controller allocating a contiguous bit field space in the internal static random access memory based on the quotient of the total system physical memory capacity and the 4KB page size. For example, for 16GB of memory, 4,194,304 bits are allocated. The controller uses hardware setting logic to initialize all bits in this bit field space to binary 0, representing the default not-ready state, and establishes the memory page state array.

[0074] In another embodiment, traversing the address mapping table to identify the physical page frame distribution of critical system regions and ordinary service regions specifically includes: the controller reads the physical page frame numbers recorded in the address mapping table and compares them with a preset system address mapping rule register. Lower memory regions with physical addresses ranging from 0x00000000 to 0x04000000 are identified as critical system regions storing interrupt vector tables and kernel code, while physical addresses above this range are identified as ordinary service regions. The controller records the starting physical page frame numbers and the number of consecutive pages for each type of region, generating a page frame classification list.

[0075] In one embodiment, updating the memory page status array based on the page frame classification list involves the controller calculating the corresponding bit index in the memory page status array based on the key region address range recorded in the page frame classification list. The controller drives the write circuit to flip the bits at these specific index positions to binary 1, indicating a ready state; the bits corresponding to ordinary service regions are kept at binary 0, indicating a pending backfill state. This operation creates a logical distinction of the physical residency state in the bitmap, generating a differentiated status page frame table.

[0076] In another embodiment, configuring the hardware interception circuit to set address matching rules and suspend actions specifically involves the controller writing a control word to the configuration register of the bus interface unit. The matching rule is set as follows: a successful match occurs when the status bit corresponding to the bus access address is 0. The suspend action is set as follows: a RETRY retry signal is sent to the system bus or a READY ready signal is pulled low, forcing the processor to suspend the current bus transaction. These register configuration values ​​combine to form the interception control parameter set.

[0077] In one embodiment, spatial compression encoding of the differentiated state page frame table specifically employs hardware run-length encoding logic. The controller scans the differentiated state page frame table, detecting consecutive sequences of 0 or 1 states. The consecutive states to be backfilled are converted into a (starting index, length) tuple format, retaining only the boundary information where state bits transition. This encoding method significantly reduces the storage space occupied by the bitmap, generating an optimized state bitmap suitable for fast retrieval.

[0078] In another embodiment, loading the optimized state bitmap into the on-chip cache and associating it with the interception control parameter set specifically involves the following steps: The controller transfers the data from the optimized state bitmap to the on-chip high-speed SRAM tightly coupled to this hardware interception circuit via a direct memory access channel. Simultaneously, the enable pin of the interception circuit is activated, and the output of the high-speed SRAM is physically connected to the comparator input of the interception circuit. At this point, any bus physical address can be indexed into the SRAM and an enable or intercept signal can be output in real time, forming an active interception state bitmap.

[0079] Preferably, updating the memory page state array based on the page frame classification list further includes:

[0080] Calculate the recovery priority of the physical address range based on the page frame classification list, and construct the page frame priority matrix;

[0081] Physical page frames are divided into immediate load queues and lazy load queues based on the page frame priority matrix;

[0082] For page frames in the immediate load queue, data is read from the persistent state image and written to volatile memory to generate critical page frame recovery records;

[0083] For page frames in the lazy loading queue, establish an index association with the persistent state image data to generate a lazy loading index table;

[0084] Merge the status information of the critical page frame recovery record and the lazy-loaded index table, and update the memory page status array.

[0085] In one embodiment, the specific operation of calculating the recovery priority of the physical address range based on the page frame classification list is as follows: The controller parses the attribute field of each item in the page frame classification list. For address ranges identified as kernel code segments, page tables, and interrupt descriptor tables, the highest priority value of 0 is assigned. For I / O buffers and driver data segments, the second highest priority value of 1 is assigned. For ordinary user space data pages, the lowest priority value of 2 is assigned. The controller associates and stores the starting address of each physical page frame with its corresponding priority value to construct a page frame priority matrix.

[0086] In another embodiment, dividing physical page frames into an immediate load queue and a delayed load queue based on the page frame priority matrix specifically involves: the controller setting a priority threshold of 1; traversing the page frame priority matrix and adding all physical page frames with a priority value less than or equal to 1 to the immediate load queue; and adding all physical page frames with a priority value greater than 1 to the delayed load queue. This operation ensures that the most critical data necessary for system startup is processed with priority.

[0087] In one embodiment, the operation of reading data from the persistent state image and writing it to volatile memory for page frames in the immediate load queue is blocking. The controller activates the direct memory access engine and reads the address of each page frame in the immediate load queue sequentially. Based on the address mapping, the controller extracts the corresponding 4KB data block from the image file of the non-volatile medium and writes it to the corresponding physical location in volatile memory. Upon successful writing of a page frame, the controller records the physical address and completion status of the page frame in an internal register, generating a critical page frame recovery record.

[0088] In another embodiment, establishing an index association with persistent state image data for page frames in the lazy-load queue specifically involves the controller not performing actual data transfer, but instead creating an index entry for each page frame in the lazy-load queue. This entry contains the page frame's volatile memory physical address and its source data offset in the non-volatile media image file. The controller organizes these index entries into a linear list or hash table structure and stores it in the controller's metadata area, generating a lazy-load index table.

[0089] In one embodiment, the specific operation of merging the status information of the critical page frame recovery record and the lazy loading index table to update the memory page status array is as follows: The controller reads the critical page frame recovery record and sets the bit position of the corresponding physical address in the memory page status array to 1, marking it as physically ready. Simultaneously, the controller reads the lazy loading index table and confirms that the bit position of the corresponding physical address remains 0, marking it as logically mapped but physically not ready. This merging operation ensures that the status array accurately reflects the complete physical memory landscape of the current hybrid recovery phase.

[0090] Preferably, the logic for configuring the hardware interception circuit in step S3 further includes:

[0091] The optimized state bitmap is moved to the on-chip bypass cache of the non-volatile memory controller to establish a state lookup table;

[0092] Logically bind the interception control parameter set with the output port of the status lookup table to construct an address comparison logic circuit;

[0093] Send a bus interface ready signal to the processor via the bus interface;

[0094] In response to the processor's reset and release operation, an interception status bitmap is enabled to make real-time judgments on memory access.

[0095] In one embodiment, the specific operation of moving the optimized state bitmap to the on-chip bypass cache of the non-volatile memory controller is as follows: the controller initiates an internal high-speed bus transfer to copy the optimized state bitmap from the low-speed SRAM to a dedicated on-chip cache (TCM) adjacent to the bus interface unit in a 128-bit wide burst mode. This cache adopts a dual-port SRAM design, allowing single-cycle reads at the bus clock frequency. After copying, the controller verifies data integrity, ensuring that the bitmap data in the cache is consistent with the source data, and establishes a state lookup table for real-time hardware indexing.

[0096] In another embodiment, logically binding the interception control parameter set to the output port of the status lookup table specifically involves: configuring an internal programmable logic array in the controller; directly connecting the data output of the status lookup table to the reference input of the comparator; and connecting the enable bit, polarity selection bit, and suspend mode control bit from the interception control parameter set to the control input of the comparator. The hardware circuit is configured such that when the status bit indexed by the bus address is 0 (to be backfilled) and the enable bit is valid, the comparator outputs a high-level intercept signal, thereby constructing an address comparison logic circuit at the physical layer.

[0097] In one embodiment, sending a bus interface ready signal to the processor via the bus interface involves the following steps: The controller drives the physical layer interface circuitry of the DDR bus or CXL bus. The controller pulls the READY or ACK signal line to an active level and maintains this state for at least two clock cycles. This signal informs the system bus master that the memory subsystem has completed initialization and is ready to respond to read / write requests, even though most of the physical memory has not yet been loaded with data.

[0098] In another embodiment, in response to a processor reset release operation, enabling real-time decision-making on memory access using an interception state bitmap specifically involves: the system reset controller revoking the RESET signal to the processor core. The processor then begins executing its first instruction. Simultaneously, the state machine within the non-volatile memory controller switches from "configuration mode" to "monitoring mode." At this point, the target physical address of each read / write request arriving at the controller is indexed in a state lookup table, and the hardware logic determines in real-time whether to allow the request to proceed to physical memory or trigger an interception mechanism based on the lookup result.

[0099] Preferably, step S4, which involves monitoring bus transactions using an interception status bitmap, specifically includes:

[0100] Capture read / write transaction signals on the system bus, decode to obtain the target physical address, and generate a memory access request descriptor;

[0101] The target physical address is compared with the interception status bitmap using a hardware comparator to query the data validity status of the current address;

[0102] If the data validity status is pending, a transaction suspension command is sent to the bus controller, and a paused transaction record is generated.

[0103] If the data validity status is ready, then bus transactions are allowed to execute;

[0104] For suspended transactions, check if the requested range crosses the physical page boundary and generate a page fault load request containing the aligned address and data length.

[0105] In one embodiment, capturing read / write transaction signals on the system bus specifically involves the memory controller's front-side bus interface unit monitoring the address bus and control signal lines in real time. When a valid read / write command strobe signal is detected, the 34-bit physical address, transaction ID, burst length, and read / write direction bits on the address bus are latched. The decoding logic converts these raw signals into an internally unified data structure to generate a memory access request descriptor.

[0106] In another embodiment, the comparison of the target physical address with the interception status bitmap using a hardware comparator is specifically as follows: The controller extracts the high 22 bits of the memory access request descriptor as an index key (assuming a page size of 4KB). This index key is sent to the address port of the on-chip cache. The cache controller outputs a 1-bit status value corresponding to the index position within a single clock cycle. This status value is directly input to the A terminal of the hardware comparator and subjected to a logical XOR operation with the preset "ready" level at the B terminal to query the data validity status of the current address.

[0107] In one embodiment, if the data validity status is pending backfilling, a transaction suspension instruction is sent to the bus controller. The specific operation is as follows: When the comparator outputs a logical true value (i.e., a state mismatch), an intercept state machine is triggered. The state machine immediately drives the bus response channel, sending a specific RETRY or WAIT protocol packet to the bus controller, forcing the processor to suspend the current transaction. Simultaneously, the controller copies the complete content of the current memory access request descriptor to its internal suspended transaction queue (FIFO), appends a timestamp, and generates a suspended transaction record.

[0108] In another embodiment, if the data validity state is ready, bus transaction execution is permitted specifically as follows: when the comparator outputs a logical false (i.e., the state matches), the interception logic remains silent. The standard read / write path of the memory controller is activated, and the request is forwarded directly to the DRAM physical layer interface to perform regular charge / discharge read / write operations, completing data transmission as if it were a normal memory access.

[0109] In one embodiment, for a suspended transaction, checking whether the request range crosses the physical page boundary specifically involves the controller calculating the access start address. and end address . judge and If the high 22 bits of the page frame number are the same, it indicates a page fault and needs to be split into two requests. If they are the same, the base address corresponding to the page frame number is taken (the low 12 bits are cleared), and the data length is set to the standard 4KB. This normalization process ensures that all load operations are page-aligned, generating a page fault load request.

[0110] Preferably, step S4, loading data from the persistent state image according to the page fault load request, specifically includes:

[0111] Page fault load requests are pushed into the scheduling queue of the direct memory access engine to generate optimized loading tasks;

[0112] Based on the persistent state image of the optimized loading task query, calculate the physical offset of the data block in the non-volatile medium, and generate a data transfer mapping table;

[0113] Configure a bypass transfer channel that bypasses the processor cache to load data blocks from non-volatile media into volatile memory, generating memory data blocks;

[0114] Integrity verification is performed on memory data blocks using the check bits in the persistent state image, and a verification-completed data page is generated.

[0115] In response to the generation of the verification completion data page, the status bit at the corresponding address in the intercept status bitmap is modified to the ready state using atomic instructions, and a recovery signal is sent to the bus controller to restart the suspended transaction.

[0116] In one embodiment, pushing a page fault load request into the scheduling queue of the direct memory access engine specifically involves the controller writing a control word containing the physical page frame number and request priority into a dedicated hardware first-in-first-out buffer of the direct memory access engine. The scheduling logic unit scans the buffer in real time and executes a request merging strategy. When multiple load requests for consecutive physical addresses are detected in the buffer, the logic unit merges them into a single burst transfer descriptor. Simultaneously, the scheduling unit, based on the priority field, prioritizes blocking read requests from the processor core before background prefetch requests, generating an optimized load task.

[0117] In another embodiment, querying the persistent state image based on the optimized loading task specifically involves the controller reading the starting sector address of the image data area stored in the register. Extract the target physical page frame number from the optimized loading task. The controller uses a hardware multiply-accumulator to calculate the physical byte offset in the non-volatile medium. The calculation formula is: The controller will calculate the source address. Enter the target volatile memory address and transmission length into the transmission control table entry to generate a data transmission mapping table.

[0118] In one embodiment, configuring a bypass transfer channel that bypasses the processor cache involves the following steps: The controller sets the attribute field of the direct memory access transaction, setting the "No Snoopy" or "Inconsistent Access" flag. This flag indicates that the system interconnect bus does not send a listen signal to the processor cache during transmission. The direct memory access engine initiates the transfer, reads a 4KB data block via the non-volatile memory interface protocol, and writes it directly to the dynamic random access memory physical stack via the memory controller's back-end interface, without passing through the processor cache hierarchy, thus generating the memory data block.

[0119] In another embodiment, performing integrity verification on memory data blocks using check bits in the persistent state image specifically involves: at the end of the data transmission pipeline, the internal verification logic of the controller synchronously calculates the cyclic redundancy check code of the data flowing through it. Simultaneously, the controller extracts the original checksum corresponding to the data page from the metadata field prefetched in the data transmission mapping table. Hardware comparator comparison and If the two are equal, the hardware logic outputs a verification pass signal and generates a verification complete data page.

[0120] In one embodiment, modifying the status bit of the corresponding address in the intercepted status bitmap to the ready state using atomic instructions specifically involves the following steps: The controller performs a hardware-locked read-modify-write operation. It locks the status word of the corresponding physical address in the on-chip cache, flips the status bit to "ready," and then releases the lock, ensuring the atomicity of the update operation at the clock cycle level. Next, the controller sends a transaction completion signal or releases a bus wait signal to the bus controller. The bus controller responds to the signal, notifying the processor core to re-initiate the previously suspended memory access transaction.

[0121] Please see Figure 2 The diagram illustrates the core hardware connections of this invention: the processor communicates with the non-volatile memory controller via the system bus. The controller integrates three core modules: a direct memory access engine (responsible for data transmission), a voltage monitoring unit (triggers backup in case of failure), and a hardware interception circuit (enables on-demand loading access monitoring). Simultaneously, the controller connects to volatile memory (runtime data storage) and non-volatile media (persistent state image storage), forming a hardware support architecture for the entire process of "fault backup - metadata recovery - on-demand loading".

[0122] Please see Figure 3 The diagram illustrates the core execution logic of "on-demand loading": When the processor initiates a memory access, the hardware interception circuit first captures the request and queries the interception status bitmap (to determine if the target page data is ready); if the data is not ready, the system suspends the bus transaction, loads the corresponding data from non-volatile media via DMA, atomically updates the status bit to "ready," and then restarts the transaction; if the data is ready, the transaction is completed normally. The entire process achieves transparent data recovery with "access as loading," without requiring any awareness or modification from the business application.

[0123] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0124] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for fast recovery of non-volatile memory based on metadata priority and on-demand loading, characterized in that, A power failure recovery process applied to a computer system, the computer system comprising a processor and a non-volatile memory controller connected through a system bus, wherein the non-volatile memory controller is connected with a volatile memory and a non-volatile medium respectively, and the non-volatile memory controller is internally integrated with a direct memory access engine, a voltage monitoring unit and a hardware interception circuit for monitoring bus transactions; The method is executed by the non-volatile memory controller and comprises the following steps: Step S1: in response to a system failure signal detected by the voltage monitoring unit, freezing the processor context and traversing the page table structure to extract system configuration information; encoding and writing the system configuration information and the service data in the volatile memory into the non-volatile medium to generate a persistent state mirror; Step S2: parsing the persistent state mirror, extracting address translation metadata and reconstructing the mapping relationship of virtual addresses to physical page frames in the volatile memory; generating an address mapping table, wherein the physical page frames pointed by the address mapping table are set to an existing state but are not associated with valid service data; Step S3: marking the state of the physical page frames based on the address mapping table; configuring the logic of the hardware interception circuit to generate an interception state bitmap for indicating the data validity of the physical page frames; Step S4: monitoring the bus transactions by using the interception state bitmap, suspending the access to the physical page frames in the data invalid state by the hardware interception circuit and generating a page fault loading request; controlling the direct memory access engine to load data from the persistent state mirror to the volatile memory according to the page fault loading request; updating the interception state bitmap to the data valid state and resuming the suspended transactions.

2. The method of claim 1, wherein, Step S1 comprises: Detecting the voltage of the main power rail by using the voltage monitoring unit, and generating an emergency mode control flag when the voltage is abnormal; In response to the emergency mode control flag, controlling the processor to complete the current instruction cycle and stop instruction fetching, and transmitting the register state to the buffer of the non-volatile memory controller to generate a processor state data packet; Reading the base address register of the system memory management unit and traversing the multi-level page table to generate a set of address translation tables; Scanning the volatile memory based on the set of address translation tables and marking the allocated page frames to construct a memory persistence task table; Starting the direct memory access engine, transmitting data according to the memory persistence task table and calculating a checksum to generate a data block checksum set; Packaging and writing the processor state data packet, the set of address translation tables and the data block checksum set into the non-volatile medium to generate a persistent state mirror.

3. The method of claim 1, wherein the metadata-based pre- and on-demand loading of the non-volatile memory fast recovery is based on, Step S2 comprises: Verifying the integrity of the persistent state mirror, and extracting an image file descriptor containing a file offset; Parsing the index area in the image file descriptor, locating the storage position of the system configuration information, and generating a metadata index table; Reading the processor context according to the metadata index table, parsing and restoring the processor running environment, and generating a processor recovery state set; Performing zero clearing and permission setting on a specific physical address range of the volatile memory to initialize a metadata reserved area for storing a recovery control structure.

4. The method of claim 3, wherein the metadata-based pre- and on-demand loading of the non-volatile memory fast recovery method is characterized by, Before generating the address mapping table in step S2, it further comprises: Locating the storage offset of the top-level page table in the non-volatile medium according to the metadata index table to obtain a set of top-level page table pointers; Traverse the multi-level page table hierarchy with the top-level page table pointer set as the root node to construct a page table structure link tree; Batch extract the control bits and address fields in the page table entries from the page table structure link tree, strip the service data content pointed to by them, and generate a separated page table entry stream; Perform a relocation calculation based on the current memory layout on the physical address field in the separated page table entry stream to generate corrected virtual-real address mapping data.

5. The metadata-priority-based and on-demand load-based nonvolatile memory fast recovery method according to claim 4, wherein, The address mapping table generated in step S2 specifically includes: Take the starting physical address of the metadata reserved area as a reference, write the virtual-real address mapping data into the volatile memory, and deploy the physically resident discrete page table entries; Modify the physical address field pointing to the next level page table in the discrete page table entries to the absolute physical address in the metadata reserved area, and construct a structurally connected page table tree; Set the valid bit flag of the leaf node in the page table tree and retain the original access permission attribute, and construct an attribute complete mapping network that presents an effective state to the memory management unit; Calculate the root directory base address of the attribute complete mapping network and publish it to the control register of the processor to generate the address mapping table.

6. The metadata-priority-based and on-demand load-based nonvolatile memory fast recovery method according to claim 1, wherein, The interception state bitmap generated in step S3 for indicating the validity of the physical page frame data specifically includes: Initialize a memory page state array covering the entire physical memory range in the internal memory of the non-volatile memory controller; Traverse the address mapping table to identify the physical page frame distribution of the system critical area and the ordinary service area, and generate a page frame classification list; Update the memory page state array according to the page frame classification list, mark the critical area page frames as ready state, and mark the ordinary service area page frames as pending state, and generate a differential state page frame table; Configure the hardware interception circuit to set the address matching rule and the suspension action, and generate the interception control parameter set; Perform spatial compression encoding on the differential state page frame table to generate an optimized state bitmap; Load the optimized state bitmap into the on-chip cache and associate it with the interception control parameter set to generate the interception state bitmap.

7. The metadata-priority-based and on-demand load-based nonvolatile memory fast recovery method according to claim 6, wherein, Updating the memory page state array according to the page frame classification list further includes: Calculate the recovery priority of the physical address range according to the page frame classification list to construct a page frame priority matrix; Divide the physical page frames into an immediate loading queue and a delayed loading queue according to the page frame priority matrix; For the page frames in the immediate loading queue, read the data from the persistent state image and write it into the volatile memory to generate a critical page frame recovery record; For the page frames in the delayed loading queue, establish an index association with the persistent state image data to generate a delayed loading index table; Merge the state information of the critical page frame recovery record and the delayed loading index table to update the memory page state array.

8. The metadata-priority-based and on-demand load-based nonvolatile memory fast recovery method according to claim 6, wherein, The logic of configuring the hardware interception circuit in step S3 further includes: Carry the optimized state bitmap to the on-chip bypass cache of the non-volatile memory controller to establish a state query table; Logically bind the interception control parameter set with the output port of the state query table to construct an address comparison logic circuit; Send a bus interface ready signal to the processor through the bus interface; In response to the reset release operation of the processor, enable the interception state bitmap to make real-time judgments on memory access.

9. The metadata-priority-based and on-demand load-based nonvolatile memory fast recovery method according to claim 1, wherein, The step S4 of monitoring the bus transaction by using the interception state bitmap specifically includes: The read-write transaction signals on the bus are captured, the target physical address is decoded to obtain a target physical address, and a memory access request descriptor is generated; The target physical address is compared with the interception state bitmap by using a hardware comparator to query the data validity state of the current address; If the data validity state is to be backfilled, a transaction suspension instruction is sent to the bus controller, and a transaction suspension record is generated; If the data validity state is ready, the bus transaction is allowed to execute; For the suspended transaction, it is checked whether the request range crosses the physical page boundary, and a page fault loading request containing the aligned address and the data length is generated.

10. The metadata-priority-based and on-demand load-based nonvolatile memory fast recovery method according to claim 1, wherein, The data is loaded from the persistent state image according to the page fault loading request in step S4, specifically including: The page fault loading request is pushed into the scheduling queue of the direct memory access engine to generate an optimized loading task; According to the optimized loading task, the persistent state image is queried, the physical offset of the data block in the non-volatile medium is calculated, and a data transmission mapping table is generated; A bypass transmission channel bypassing the processor cache is configured, the data block is loaded from the non-volatile medium to the volatile memory, and a memory data block is generated; The integrity of the memory data block is verified by using the check bit in the persistent state image to generate a verified data page; In response to generating the verified data page, the state bit of the corresponding address in the interception state bitmap is modified to the ready state by using an atomic instruction, and a resume signal is sent to the bus controller to restart the suspended transaction.

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