Semiconductor device and method of manufacturing such semiconductor device
Patent Information
- Application Number
- PCT/EP2026/054513
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-19
- Filing Date
- 2026-02-19
- Publication Date
- 2026-08-27
Smart Images
Figure EP2026054513_27082026_PF_FP_ABST
Abstract
Description
[0001] TITLE
[0002] Semiconductor device and method of manufacturing such semiconductor device.
[0003] TECHNICAL FIELD
[0004] The present disclosure relates to a semiconductor device and method of manufacturing a semiconductor device. The present disclosure relates to power MOSFET performance.
[0005] BACKGROUND OF THE DISCLOSURE
[0006] Part of a process of making a prior art power trench metal-oxide-semiconductor field-effect transistors, MOSFETs, is to etch a contact in doped region bellow the inter-layer dielectric, ILD. Accordingly, it is a goal of the present disclosure to provide a connection with the doped region such that the connection will have a lower resistance.
[0007] SUMMARY OF THE DISCLOSURE
[0008] According to a first example of the disclosure a semiconductor device is disclosed. The semiconductor device comprising a mesa, two gate oxide regions and two liner-oxide regions forming two oxide regions, where each of the oxide regions comprising a first side and a second side where the gate oxide region is adjacent to the second side of the oxide region and where the liner-oxide region is closer to the first side of the oxide region, wherein each of the two oxides regions comprising a field plate electrode, located in proximity of the first side of the oxide region, in the liner-oxide region, and a gate electrode located in proximity of the second side of the oxide region, in the gate oxide region, wherein the two gate oxide regions and the liner oxide regions are located in the mesa, an inter-layer dielectric, ILD, layer with a first side and a second side, wherein the first side of each of the ILD layers is adjacent to the mesa, and the second side of the gate oxide region, a P-body with a first side and a second side, N+ regions each with a first side and a second side, wherein the second side comprises a N+ top exposed area, a N+ buried area, and a N+ lateral sides, wherein each N+ region is adjacent the gate oxide region and, with its N+ buried area,to the first side of the ILD layer, wherein the first side of each N+ region is further adjacent to the second side of the P-body, wherein the P-body is adjacent to the two gate oxide regions and, with its first side, to the mesa, an etched contact area defined by ILD lateral sides, N+ top exposed areas, N+ lateral sides and a BF2-implantated contact bottom region, wherein the BF2-implantated contact bottom region is located in the P-body region.
[0009] Preferably the length of the N+ top exposed areas is at least 1 nm. Preferably the semiconductor device further comprises a metal barrier deposition layer adjacent to the mesa, the top side of the ILD layer, the ILD lateral sides, the N+ top exposed areas, the N+ side exposed area and the BF2-implantated contact bottom region. Even more preferably the metal barrier deposition layer is made of Ti / TiN.
[0010] Preferably the semiconductor device further comprises a metal-plug deposition adjacent to the metal barrier deposition layer, located in the etched contact area. Even more preferably the metal-plug deposition is made of tungsten.
[0011] Preferably the semiconductor device further comprises a power metal deposition adjacent to the metal barrier deposition layer, and the metal-plug deposition. Even more preferably the power metal deposition is made of AICu.
[0012] According to a second example of the disclosure a method of manufacturing a semiconductor device is disclosed. The method is performed on a semifinished semiconductor device comprising a mesa, two gate oxide regions and two liner-oxide regions forming two oxide regions, where each of the oxide regions comprising a first side and a second side where the gate oxide region is adjacent to the second side of the oxide region and where the liner-oxide region is closer to the first side of the oxide region, wherein each of the two oxides regions comprising a field plate electrode, located in proximity of the first side of the oxide region, in the liner-oxide region, and a gate electrode located in proximity of the second side of the oxide region, in the gate oxide region, wherein the two gate oxide regions and the liner oxide regions are located in the mesa, two an inter-layer dielectric, ILD, layer with a first side and a second side, wherein the first side of each of the ILD layers is adjacent to the mesa, and the second side of the gate oxide region, a P-body with a first side and a second side, N+ region with a first side and a second side, wherein N+ region is adjacent the gate oxide region and to the first side of the ILD layer, wherein the first side of N+ region is further adjacent to the second side of the P-body, wherein the P-body is adjacent to the two gate oxide regions and, with its first side, to the mesa. The method comprises steps of:
[0013] a) Etching the ILD layer part of an etched contact area,
[0014] b) Forming a BF2-implantated contact bottom region by etching N+ region, P-body region and implanting BF2 in etched part of the P-body region,
[0015] c) Creating a N+ top exposed area of the N+ region.
[0016] In an further detail the step c) is performed by etching, preferably with a buffered HF-acid, BHF.
[0017] Preferably after step a) step of depositing a spacer layer is performed such that the spacer layer is adjacent to the first side of the ILD layer, a ILD layer lateral side and the first side of the N+ region, after that, prior to step b), a next step of spacer layer etching is performed such that after this step the spacer layer remains only on the ILD layer lateral side, and step c) is performed such that the spacer layer is removed partially or completely such that after this step a direct contact to the N+ region is enabled.
[0018] Preferably the spacer layer width is at least 1 nm.
[0019] Preferably the spacer layer is made of undoped oxide, nitride, oxidenitride, or tetraethyl orthosilicate.
[0020] Preferably in step a) the etched contact area in the ILD has a width of at least 10 nm, and step c) is performed such that the spacer layer is removed partially or completely such that after this step a direct contact to the N+ region is enabled.
[0021] Preferably the method further comprises step of depositing of a barrier metal which creates the metal barrier deposition layer adjacent to the mesa, the top side of the ILD layer, the ILD lateral sides, the N+ top exposed areas, the N+ side exposed areas and the BF2-implantated contact bottom region, wherein preferably the metal barrier deposition layer is made of Ti / TiN.
[0022] Preferably the method further comprises step of depositing of a metalplug which creates the metal-plug deposition adjacent to the metal barrier deposition layer, located in the etched contact area, wherein preferably the metal-plug deposition is made of tungsten.
[0023] Preferably the method further comprises step of depositing of a power metal layer which creates the power metal deposition adjacent to the metal barrier deposition layer, and the metal-plug deposition, wherein preferably the power metal deposition is made of AICu.BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The disclosure will now be discussed with reference to the drawings, which show in:
[0025] Figure 1 shows a trench MOSFET transistor prior to etching of the ILD, Figure 2 shows the trench MOSFET transistor after etching of the ILD, Figure 3 shows the trench MOSFET transistor with spacer deposited, Figure 4 shows the trench MOSFET transistor with excess spacer removed,
[0026] Figure 5 shows the trench MOSFET transistor after etching P-body and implanting BF2,
[0027] Figure 6 shows the trench MOSFET transistor after ILD shaping, Figure 7 shows the enlarged part of the MOSFET contact illustrating details of ILD pull-back,
[0028] Figure 8 shows the trench MOSFET transistor after deposition of a barrier,
[0029] Figure 9 shows the trench MOSFET transistor after deposition of a plug, Figure 10 shows the trench MOSFET transistor with a power metal, Figure 11 shows the trench MOSFET transistor according to the disclosure,
[0030] Figure 12 shows a simulation of a prior-art trench MOSFET transistor, Figure 13 shows a simulation of the trench MOSFET transistor according to the disclosure,
[0031] Figure 14 shows an alternative method of manufacturing the trench MOSFET transistor according to the disclosure,
[0032] Figures 15 and 16 show a measured values of resistance in the trench MOSFET transistor according to the disclosure and the prior-art trench MOSFET transistor.
[0033] DETAILED DESCRIPTION OF THE DISCLOSURE
[0034] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.This disclosure is provided for semiconductor devices known in the prior art. Due to this, for clarity, some standard parts of said semiconductor devices are not shown on figures and are not mentioned in the text since it will be obvious for the person skilled in the art that those parts are missing and must be implemented for a device to work. It is the intention to fully disclose a part of a semiconductor device which directly results in a performance improvement.
[0035] It should be also noted that the present disclosure is shown and illustrated with a specific technology node based on a power MOSFET using the RESURF principle, however the present disclosure may also be used in other technologies and will work in silicon, SiC, GaN and any other semiconductor technology that uses contacts.
[0036] This disclosure provides a method of manufacturing a semiconductor device. It starts with the semiconductor device known in the prior art and made in a typical way. This starting semiconductor device is shown on fig. 1 and comprises a mesa 1, two gate oxide regions 2a and two liner-oxide regions 2b forming two oxide regions 2, where each of the oxide regions 2 comprising a first side and a second side where the gate oxide region 2a is adjacent to the second side of the oxide region 2 and where the liner-oxide region 2b is closer to the first side of the oxide region 2, wherein each of the two oxides regions 2 comprising a field plate electrode 3, located in proximity of the first side of the oxide region 2, in the liner-oxide region 2b, and a gate electrode 4 located in proximity of the second side of the oxide region 2, in the gate oxide region 2a, wherein the two gate oxide regions 2a and the liner oxide regions 2b are located in the mesa 1; two an inter-layer dielectric, ILD, layer 5 with a first side and a second side, wherein the first side of each of the ILD layers 5 is adjacent to the mesa 1, and the second side of the gate oxide region 2a; a P-body 6 with a first side and a second side;
[0037] N+ region 7 with a first side and a second side, wherein N+ region 7 is adjacent the gate oxide region 2a and to the first side of the ILD layer 5, wherein the first side of N+ region 7 is further adjacent to the second side of the P-body 6, wherein the P-body 6 is adjacent to the two gate oxide regions 2a and, with its first side, to the mesa 1;
[0038] In a next step etching of the ILD layer 5 part of an etched contact area 8 is performed, as it may be seen in fig. 2. This step has two variants, where the first one is shown on figs. 3-5, and other variant is shown on fig. 14. In the first variant after step of etching of the ILD layer 5 step of depositing of spacer layer 9 is performed such that spacer layer 9 is adjacent to the first side of the ILD layer 5, a ILD layerlateral side 5a and the first side of the N+ region 7. This is shown in fig. 3. Next step of spacer layer 9 etching is performed such that after this step spacer layer 9 remains only on the ILD layer lateral side 5a - this is shown on fig. 4. Preferably the spacer layer 9 is made of undoped oxide, nitride, oxide-nitride, tetraethyl orthosilicate or any other dielectric that can be deposited and etched back as described hereinbelow. In both cases the dimension of the etched contact area 8 is approx. 120 nm in the provided example, however other dimensions may also be used and this one is used as an example only.
[0039] In a next step forming a BF2-implantated contact bottom region 10 by etching N+ region 7, P-body region 6 and implanting BF2 in etched part of the P-body region 6. In a second variant etching is done such that the etched contact area 8 reaches the P-body 6 in the same process in which the ILD layer 5 is etched. The first variant is shown on fig. 5, while the second one is shown on fig. 14 - the only difference is that in the first variant the spacer layer 9 is present inside the etched contact area 8, more precisely on the ILD layer lateral side 5a and the first side of the N+ region 7.
[0040] In a next step shown in fig. 6 a N+ top exposed areas 7a of the N+ region 7 is created, wherein step c is preferably performed after step b. Step c is performed such that the spacer layer 9 is removed partially or completely such that after this step a direct contact to the N+ region 7 is enabled, in the N+ top exposed areas 7a and N+ side exposed area 7c. Step c is preferably performed by etching, preferably with a buffered HF-acid, BHF. After this step the N+ top exposed region 7a is enabled to being direct contact, by the metal, to the most highly doped part of the N+ region 7, which in turn reduces the overall resistance of the etched contact area 8 in the semiconductor device.
[0041] The spacer layer 9 will typically have a thickness of 20 nm with a range spanning 1 nm to 1000 nm. The optimal spacer layer 9 thickness depends on the contact width and can vary enormously from technology to technology. For modern power devices with a typical contact width 100-200 nm the oxide spacer deposited thickness would be around 20 nm. A working thickness of the N+ top exposed areas 7a would be at least 1 nm or more. The desired thickness of the N+ top exposed areas 7a would be ideally the same as the spacer layer 9 thickness - in a further step of complete removal it will leave a space for the N+ top exposed areas 7a.
[0042] Both variants use the same chemical-etch step to expose the top part of the N+ region7, namely the N+ top exposed area 7a. The difference is this: for smallcontact widths below 200 nm and / or in cases where contact width must be reduced beyond lithography capability, the preferred method of manufacturing the N+ top exposed areas 7a is to use the oxide spacer described in as a first variant. Generally speaking, for contact widths above 200 nm, the more direct and simpler method of manufacturing the N+ top exposed areas 7a, as presented in the second variant, is preferred. In the final semiconductor device, there is no way to tell through reverse engineering which manufacturing method was used first or second variant - the end result is identical in terms of the benefit to device performance.
[0043] Fig. 7 shows in greater detail the etched back ILD of the semiconductor device. Especially parts of the N+ region 7 are clearly visible in this figure and, for clarity reasons, are not shown in all figures.
[0044] In fig. 8 step of depositing of a metal barrier which creates the metal barrier deposition layer 11 is shown. The metal barrier deposition layer 11, after forming, is adjacent to the mesa 1, the second side of the ILD layer 5, the ILD lateral sides 5a, the N+ top exposed areas 7a, the N+ region lateral sides 7c and the BF2-implantated contact bottom region 10. The metal barrier deposition layer 11 is preferably made of Ti / TiN.
[0045] In fig. 9 step of depositing of a metal-plug which creates the metal-plug deposition 12 is shown. The metal-plug deposition 12, after forming, is adjacent to the metal barrier deposition layer 11, located in the etched contact area 8. Preferably the metal-plug deposition 12 is made of tungsten.
[0046] In fig. 10 step of depositing of a power metal layer which creates a power metal deposition 13, after forming, is adjacent to the metal barrier deposition layer 11 , and the metal-plug deposition 12. Preferably the power metal deposition 13 is made of AICu.
[0047] In fig. 11 shows the same area as fig. 7 as the semiconductor device has been created and observed in real life. It should be noticed that N+ top exposed area 7a is visible in this figure.
[0048] In figs. 12 and 13 a computer simulation of the semiconductor device is shown. The gray scale shows an implant concentration in N+ region 7 - it should be noted that black part is a part with the highest implant concentration. As may be seen in fig. 12 almost no black part of the N+ region 7 is in contact with the metal barrier deposition layer 11. Fig. 13 shows that when the N+ top exposed area 7a is introduced much more of the highest implant concentration part of the N+ region 7 is in contact with the metal barrier deposition layer 11.Fig. 15 and 16 shows a resistance measured with and without implementation of the method according to the disclosure. Prior-art semiconductor devices 14 tends to have higher contact resistance than semiconductor devices 15 according to the disclosure. In the prior-art semiconductor devices 14 resistance keeps a value of approx. 40 ohms and in the semiconductor devices 15 according to the disclosure the resistance value is lowered to 35 ohms.LIST OF REFERENCE NUMERALS USED
[0049] 1 Mesa
[0050] 2 Oxide region
[0051] 2a Gate oxide region
[0052] 2b Liner-oxide region
[0053] 3 Field plate electrode
[0054] 4 Gate electrode
[0055] 5 Inter-layer dielectric, ILD, layer
[0056] 5a ILD lateral side
[0057] 6 P-body region
[0058] 7 N+ region
[0059] 7a N+ top exposed area
[0060] 7b N+ buried area
[0061] 7c N+ side exposed area
[0062] 8 Etched contact area
[0063] 9 spacer layer
[0064] 10 BF2-implantated contact bottom region
[0065] 11 Metal barrier deposition layer
[0066] 12 Metal-plug deposition
[0067] 13 Power metal deposition
[0068] 14 prior-art semiconductor device
[0069] 15 semiconductor device according to the disclosure
Claims
CLAIMS1. A semiconductor device comprising:a mesa,two gate oxide regions and two liner-oxide regions forming two oxide regions, where each of the oxide regions comprising a first side and a second side where the gate oxide region is adjacent to the second side of the oxide region and where the liner-oxide region is closer to the first side of the oxide region, wherein each of the two oxides regions comprising a field plate electrode, located in proximity of the first side of the oxide region, in the liner-oxide region, and a gate electrode located in proximity of the second side of the oxide region, in the gate oxide region, wherein the two gate oxide regions and the liner oxide regions are located in the mesa;an inter-layer dielectric, ILD, layer with a first side and a second side, wherein the first side of each of the ILD layers is adjacent to the mesa, and the second side of the gate oxide region;a P-body with a first side and a second side;N+ regions each with a first side and a second side, wherein the second side comprises a N+ top exposed area, a N+ buried area, and a N+ lateral sides;wherein each N+ region is adjacent the gate oxide region and, with its N+ buried area, to the first side of the I LD layer, wherein the first side of each N+ region is further adjacent to the second side of the P-body, wherein the P-body is adjacent to the two gate oxide regions and, with its first side, to the mesa;an etched contact area defined by ILD lateral sides, N+ top exposed areas, N+ lateral sides and a BF2-implantated contact bottom region, wherein the BF2-implantated contact bottom region is located in the P-body region.
2. The semiconductor device according to claim 1, wherein the length of the N+ top exposed areas is at least 1 nm.
3. The semiconductor device according to claim 1 or 2, further comprising a metal barrier deposition layer adjacent to the mesa, the top side of the ILD layer, the ILD lateral sides, the N+ top exposed areas, the N+ side exposed area and the BF2-implantated contact bottom region, wherein preferably the metal barrier deposition layer is made of Ti / TiN.
4. The semiconductor device according to claim 3, wherein it further comprises a metal-plug deposition adjacent to the metal barrier deposition layer, located in the etched contact area, wherein preferably the metal-plug deposition is made of tungsten.
5. The semiconductor device according to claim 4, wherein it further comprises a power metal deposition adjacent to the metal barrier deposition layer, and the metalplug deposition, wherein preferably the power metal deposition is made of AICu.
6. A method of manufacturing a semiconductor device as defined in claims 1-5, wherein the method is performed on a semifinished semiconductor device comprising:a mesa,two gate oxide regions and two liner-oxide regions forming two oxide regions, where each of the oxide regions comprising a first side and a second side where the gate oxide region is adjacent to the second side of the oxide region and where the liner-oxide region is closer to the first side of the oxide region, wherein each of the two oxides regions comprising a field plate electrode, located in proximity of the first side of the oxide region, in the liner-oxide region, and a gate electrode located in proximity of the second side of the oxide region, in the gate oxide region, wherein the two gate oxide regions and the liner oxide regions are located in the mesa;two inter-layer dielectric, ILD, layers with a first side and a second side, wherein the first side of each of the ILD layers is adjacent to the mesa, and the second side of the gate oxide region;a P-body with a first side and a second side;N+ region with a first side and a second side,wherein N+ region is adjacent the gate oxide region and to the first side of the ILD layer, wherein the first side of N+ region is further adjacent to the second side of the P-body, wherein the P-body is adjacent to the two gate oxide regions and, with its first side, to the mesa;wherein the method comprises steps of:a) etching the ILD layer part of an etched contact area,b) forming a BF2-implantated contact bottom region by etching N+ region, P-body region and implanting BF2 in etched part of the P-body region,c) creating a N+ top exposed area of the N+ region.
7. The method according to claim 6, wherein the step c) is performed by etching, preferably with a buffered HF-acid, BHF.
8. The method according to anyone of claims 6 or 7, wherein after step a) step of depositing a spacer layer is performed such that the spacer layer is adjacent to the first side of the ILD layer, a ILD layer lateral side and the first side of the N+ region, after that, prior to step b), a next step of spacer layer etching is performed such that after this step the spacer layer remains only on the ILD layer lateral side, and step c)is performed such that the spacer layer is removed partially or completely such that after this step a direct contact to the N+ region is enabled.
9. The method according to anyone of claim 8, wherein the spacer layer width is at least 1 nm.
10. The method according to anyone of claim 8 or 9, wherein the spacer layer is made of undoped oxide, nitride, oxide-nitride, or tetraethyl orthosilicate.
11. The method according to anyone of claims 6 or 7, wherein in step a) the etched contact area in the ILD has a width of at least 10 nm, and step c) is performed such that the spacer layer is removed partially or completely such that after this step a direct contact to the N+ region is enabled.
12. The method according to anyone of claims 6-10, wherein it further comprises step of depositing of a barrier metal which creates the metal barrier deposition layer adjacent to the mesa, the top side of the ILD layer, the ILD lateral sides, the N+ top exposed areas, the N+ side exposed areas and the BF2-implantated contact bottom region, wherein preferably the metal barrier deposition layer is made of Ti / TiN.
13. The method according to anyone of claims 1-12, wherein it further comprises step of depositing of a metal-plug which creates the metal-plug deposition adjacent to the metal barrier deposition layer, located in the etched contact area, wherein preferably the metal-plug deposition is made of tungsten.
14. The method according to anyone of claims 1-13, wherein it further comprises step of depositing of a power metal layer which creates the power metal deposition adjacent to the metal barrier deposition layer, and the metal-plug deposition, wherein preferably the power metal deposition is made of AICu.