Imaging device

Abstract

The present invention makes it possible to change resolution at the time of binning of a pixel signal read from a pixel while shortening wiring which is used for binning.　This imaging device comprises: a plurality of pixels respectively provided with photoelectric conversion units; a plurality of floating diffusions to which charges photoelectrically converted by the photoelectric conversion units are transferred; switching transistors that each switch the connection of a plurality of floating diffusions within a pixel; and binning transistors that each switch the connection of a plurality of floating diffusions between a plurality of pixels.

Description

Imaging device

[0001] This technology relates to an imaging device. Specifically, this technology relates to an imaging device capable of changing the resolution during binning.

[0002] In an imaging device, a process of reducing the resolution by binning a plurality of pixel signals may be performed during motion detection or illuminance detection. For example, in a solid-state imaging device that performs binning of pixel signals, a technique of providing a switch for changing the resolution during binning has been disclosed (see, for example, Patent Document 1).

[0003] Japanese Unexamined Patent Application Publication No. 2018-7035

[0004] However, in the above-mentioned conventional technology, since pixel signals are binned in the column direction through a reset transistor that resets the floating diffusion, the wiring used for binning may become long.

[0005] This technology was created in view of such a situation, and aims to enable shortening of the wiring used for binning while enabling the resolution during binning of pixel signals read from pixels to be changed.

[0006] This technology was made to solve the above-mentioned problems. A first aspect thereof is an imaging device including a plurality of pixels each provided with a photoelectric conversion unit, a plurality of floating diffusions to which charges photoelectrically converted by the photoelectric conversion unit are transferred, a switching transistor that switches the connection of the plurality of floating diffusions within the pixel, and a binning transistor that switches the connection of the plurality of floating diffusions between the plurality of pixels. Thereby, based on the switching of the connection of the floating diffusions between a plurality of pixels via the binning transistor, an effect is brought about that the resolution during binning of pixel signals read from pixels is changed.

[0007] Furthermore, in the first aspect, a Lateral Overflow Integration Capacitor (LOFIC) may be provided to store the charge that overflows from the photoelectric conversion unit. This results in the binning resolution of the pixel signal read from the pixel equipped with the LOFIC being changed based on the switching of the floating diffusion connection between multiple pixels.

[0008] Furthermore, in the first aspect, the device may include a pixel array portion in which the pixels are arranged in a matrix in the row direction and the column direction, and the binning transistor may include a first binning transistor that switches the connection of the floating diffusion of adjacent pixels in the column direction, and a second binning transistor that switches the connection of the floating diffusion of adjacent pixels in the row direction. This results in a change in the resolution of the pixel signal read from the pixel during binning in the row direction and the column direction.

[0009] Furthermore, in the first aspect, the first binning transistor may be shared by a plurality of pixels adjacent in the row direction. This reduces the number of first binning transistors while changing the resolution of the pixel signal read from the pixel during row-direction binning.

[0010] Furthermore, in the first aspect, a third binning transistor may be provided for switching the connection of floating diffusion of non-adjacent pixels located in the same row. This results in the effect of making the resolution change during row-direction binning of the pixel signal read from the pixel variable.

[0011] Furthermore, in the first aspect, the second binning transistor may be provided for each pixel. This results in the effect that the resolution of the row-direction binning of the pixel signal read from the pixel is changed based on the switching of the second binning transistor.

[0012] Furthermore, in the first aspect, the floating diffusion may include a first floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred, and a second floating diffusion connected to the first floating diffusion via the switching transistor. This results in an expansion of the low-sensitivity dynamic range based on the charge overflowing into the LOFIC.

[0013] Furthermore, in the first aspect, the binning transistor may switch the connection of the first floating diffusion between the plurality of pixels. This results in a change in the resolution of the pixel signal read from the pixel during binning.

[0014] Furthermore, in the first aspect, the binning transistor may switch the connection of the second floating diffusion between the plurality of pixels. This has the effect of changing the resolution of the pixel signal read out from the pixel during binning, while suppressing a decrease in conversion efficiency at low light levels.

[0015] Furthermore, in the first aspect, the floating diffusion comprises a first floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred, a second floating diffusion connected to the first floating diffusion, and a third floating diffusion connected to the second floating diffusion. The switching transistor may also comprise a first switching transistor that switches the connection between the first floating diffusion and the second floating diffusion, and a second switching transistor that switches the connection between the second floating diffusion and the third floating diffusion. This enables switching of the conversion efficiency while expanding the low-sensitivity dynamic range based on the charge overflowing into the LOFIC.

[0016] Furthermore, in the first aspect, the binning transistor may switch the connection of the first floating diffusion between the plurality of pixels. This results in a change in the resolution of the pixel signal read from the pixel during binning.

[0017] Furthermore, in the first aspect, the binning transistor may switch the connection of the second floating diffusion between the plurality of pixels. This suppresses a decrease in conversion efficiency at low light levels while changing the resolution of the pixel signal read out from the pixel equipped with LOFIC during binning.

[0018] Furthermore, in the first aspect, the binning transistor may switch the connection of the third floating diffusion between the plurality of pixels. This has the effect of changing the resolution of the pixel signal read out from the pixel provided with LOFIC during binning, while suppressing a decrease in conversion efficiency at low light levels.

[0019] Furthermore, in the first aspect, a reset transistor for resetting the floating diffusion may be provided. This allows for shortening of the wiring used for binning, while also changing the resolution of the pixel signals read from the pixels during binning.

[0020] Furthermore, in the first aspect, the reset transistor may be shared by the plurality of pixels. This has the effect of reducing the area occupied by the reset transistor.

[0021] Furthermore, in the first aspect, the device may include a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to the floating diffusion, an amplification transistor that outputs a pixel signal based on the potential of the floating diffusion, and a selection transistor that selects the output of the amplification transistor. This results in the operation of reading out a pixel signal from a pixel.

[0022] Furthermore, in the first aspect, an overflow control transistor may be provided to control the overflow of charge from the photoelectric conversion unit to the floating diffusion. This results in an increase in the amount of charge that can be transferred from the photoelectric conversion unit to the LOFIC.

[0023] Furthermore, the second aspect is an imaging device comprising a pixel array section in which pixels are arranged in a matrix in the row direction and column direction, a reset transistor provided for each pixel for resetting the floating diffusion of the pixel, and a first binning transistor for switching the connection of the floating diffusion of adjacent pixels in the column direction. This results in the effect that the resolution of the pixel signal read from the pixel is changed during binning in the column direction based on the switching of the connection of the floating diffusion between multiple pixels via the first binning transistor.

[0024] Furthermore, in a second aspect, a second binning transistor may be provided for each pixel, which switches the connection of the floating diffusion between adjacent pixels in the row direction. This results in a change in the resolution of the pixel signal read from the pixel during row-direction binning, based on the switching of the connection of the floating diffusion between multiple pixels via the first binning transistor.

[0025] This is a block diagram showing an example configuration of an imaging device according to the first embodiment. This is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment. This is a block diagram showing an example configuration of a pixel array according to the first embodiment. This is a diagram showing an example of a first circuit configuration of a pixel provided in a solid-state imaging device according to the first embodiment. This is a diagram showing an example of a second circuit configuration of a pixel provided in a solid-state imaging device according to the first embodiment. This is a diagram showing an example of a third circuit configuration of a pixel provided in a solid-state imaging device according to the first embodiment. This is a plan view showing an example of a layout of a pixel provided in a solid-state imaging device according to the first embodiment. This is a timing chart showing the waveforms of each part when reading out the pixel signal from each pixel of the pixel array according to the first embodiment. This is a block diagram showing an example configuration of a pixel array according to the second embodiment. This is a block diagram showing an example configuration of a pixel array according to the third embodiment. This is a diagram showing an example of a first circuit configuration of a pixel provided in a solid-state imaging device according to the third embodiment. This is a diagram showing an example of a second circuit configuration of a pixel provided in a solid-state imaging device according to the third embodiment. This is a diagram showing an example of a third circuit configuration of a pixel provided in a solid-state imaging device according to the third embodiment. This is a timing chart showing the waveforms of each part when reading out the pixel signal from each pixel of the pixel array according to the third embodiment without binning. This is a timing chart showing the waveforms of each part during binning readout of the pixel signal from each pixel of the pixel array according to the third embodiment. This is a block diagram showing an example of the configuration of a pixel array according to the fourth embodiment. This is a block diagram showing an example of the configuration of a pixel array according to the fifth embodiment. This is a diagram showing a first circuit configuration example of a pixel provided in a solid-state imaging device according to the sixth embodiment. This is a diagram showing a second circuit configuration example of a pixel provided in a solid-state imaging device according to the sixth embodiment. This is a diagram showing a third circuit configuration example of a pixel provided in a solid-state imaging device according to the sixth embodiment. This is a timing chart showing the waveforms of each part during readout of the pixel signal from each pixel of the pixel array according to the sixth embodiment. This is a diagram showing a first circuit configuration example of a pixel provided in a solid-state imaging device according to the seventh embodiment. This is a diagram showing a second circuit configuration example of a pixel provided in a solid-state imaging device according to the seventh embodiment. This is a diagram showing a third circuit configuration example of a pixel provided in a solid-state imaging device according to the seventh embodiment.This figure shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the eighth embodiment. This figure shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the ninth embodiment. This figure shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the tenth embodiment. This is a perspective view showing a first stacking example of a solid-state imaging device according to the eleventh embodiment. This is a perspective view showing a second stacking example of a solid-state imaging device according to the eleventh embodiment. This is a perspective view showing a third stacking example of a solid-state imaging device according to the eleventh embodiment. This figure shows an example of motion detection of a solid-state imaging device according to the twelfth embodiment. This figure shows an example of decimation processing of a solid-state imaging device according to the thirteenth embodiment. This figure shows a first example of interlacing processing of a solid-state imaging device according to the fourteenth embodiment. This figure shows a second example of interlacing processing of a solid-state imaging device according to the fourteenth embodiment. This is a block diagram showing an example of a camera configuration according to the fifteenth embodiment. This is a block diagram showing an example of connection of a solid-state imaging device according to the fifteenth embodiment. This is a block diagram showing a first pixel division example according to the sixteenth embodiment. This is a block diagram showing a second pixel division example according to the sixteenth embodiment. This is a block diagram showing a third pixel division example according to the sixteenth embodiment. This is a block diagram showing a fourth example of pixel division according to the 16th embodiment. This is a block diagram showing a fifth example of pixel division according to the 16th embodiment. This is a block diagram showing a sixth example of pixel division according to the 16th embodiment. This is a perspective view showing an example of stacking of a solid-state imaging device according to the 17th embodiment. This is a block diagram showing a schematic example of the configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of the imaging unit.

[0026] The following describes embodiments for implementing this technology (hereinafter referred to as "embodiments"). The description will proceed in the following order: 1. First embodiment (an example of switching the connection of floating diffusion between multiple pixels in the row direction and the column direction) 2. Second embodiment (an example of switching the connection of floating diffusion between multiple pixels in the row direction) 3. Third embodiment (an example in which the connection of floating diffusion between multiple pixels is switched in the row direction and the column direction, and a reset transistor is shared between adjacent pixels in the row direction) 4. Fourth embodiment (an example in which the connection of floating diffusion between multiple pixels is switched in the row direction and the column direction, and a reset transistor is shared between adjacent pixels in the row direction and the column direction) 5. Fifth embodiment (an example in which the connection of floating diffusion between multiple pixels is switched in the row direction and the column direction, and the number of binning pixels is varied in the row direction and the column direction) 6. Sixth embodiment (an example in which the connection of floating diffusion for pixels where overflow is controlled is switchable) 7. 7th Embodiment (Example in which the connection of the floating diffusion of a pixel with controlled overflow is switchable, and a reset transistor is shared by multiple pixels) 8. 8th Embodiment (Example in which a floating diffusion is shared by multiple pixels) 9. 9th Embodiment (Example in which a floating diffusion is shared by multiple pixels with controlled overflow) 10. 10th Embodiment (Example in which a capacitance reset transistor is provided to reset the capacitance of a pixel whose floating diffusion connection can be switched) 11. 11th Embodiment (Example in which a pixel chip and a logic chip are stacked) 12. 12th Embodiment (Example in which an imaging device equipped with a pixel whose floating diffusion connection can be switched is applied to motion detection) 13. 13th Embodiment (Example in which an imaging device equipped with a pixel whose floating diffusion connection can be switched is applied to decimation) 14. 14th Embodiment (Example in which an imaging device equipped with a pixel whose floating diffusion connection can be switched is applied to interlacing)15. Fifteenth Embodiment (Example of applying an imaging device equipped with a pixel that can switch the connection of floating diffusion to a camera) 16. Sixteenth Embodiment (Example of applying Cu-Cu bonding to a pixel that can switch the connection of floating diffusion) 17. Seventeenth Embodiment (Example of stacking pixel arrays) 18. Application examples to mobile devices

[0027] <1. First Embodiment> Figure 1 is a block diagram showing an example of the configuration of an imaging device according to the first embodiment.

[0028] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging device 100 also includes a drive control unit 109. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, operation unit 107, and drive control unit 109 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into a vehicle or drone.

[0029] The optical system 101 directs light from the subject into the solid-state imaging device 102 and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0030] The solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, and outputs the electrical signal digitized. At this time, the solid-state imaging device 102 can binn the pixel signals read from the pixels and digitize them. Here, the solid-state imaging device 102 can change the resolution in the row direction and column direction when binning the pixel signals. The solid-state imaging device 102 can also output the pixel signal by switching the conversion efficiency of the pixels. For example, the solid-state imaging device 102 may switch the conversion efficiency of the pixels in two stages or in three stages. The solid-state imaging device 102 may also be equipped with multiple floating diffusions to which charge is transferred from the pixels. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.

[0031] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging timing of the solid-state imaging device 102.

[0032] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing. The image processing unit 104 may also include a processor that performs processing based on software. The image processing unit 104 includes an HDR processing unit 104A.

[0033] The HDR processing unit 104A performs HDR processing based on the pixel signals read from the solid-state imaging device 102. For example, the HDR processing unit 104A can generate an HDR image by combining the pixel signals read from low-light pixels, pixel signals read from medium-light pixels, and pixel signals read from high-light pixels.

[0034] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0035] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display, an organic EL (Electro Luminescence) display, or a micro LED display.

[0036] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0037] The drive control unit 109 controls the drive of the optical system 101 based on the pixel signals read from the solid-state imaging device 102 and the operation information operated by the operation unit 107. For example, the drive control unit 109 can perform manual focusing or control the zoom magnification based on the operation information operated by the operation unit 107.

[0038] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may be omitted, or conversely, it may have additional functions that are not disclosed.

[0039] Figure 2 is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment.

[0040] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116.

[0041] The pixel array unit 111 includes a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when reading a signal. Each pixel PX is connected to the horizontal drive line HCL for each row and to the vertical signal line VSL for each column. The horizontal drive line HCL drives each pixel PX row by row when reading a signal from each pixel PX. The vertical signal line VSL transmits the pixel signal read from the pixel PX column by column to the column signal processing unit 114.

[0042] Each pixel PX may be an HDR (High Dynamic Rang) pixel capable of switching the conversion efficiency for output. Each pixel PX may be provided with a plurality of floating diffusions whose connections can be switched. At this time, based on the switching of the connection of the floating diffusion, the conversion efficiency of each pixel PX can be changed. Each pixel PX may be provided with a LOFI C. Each pixel PX may be a single pixel, or may share two pixels, or may share four pixels, or may share eight pixels. Also, the pixels PX may form a Bayer array or may form a quad Bayer array. The light received by each pixel PX may be visible light, or may be near-infrared light (NIR: Near InfraRed), short-wavelength infrared light (SWIR: Short Wavelength InfraRed), ultraviolet light, or X-rays, etc.

[0043] The vertical scanning circuit 112 scans the pixels PX to be read in the column direction. The vertical scanning circuit 112 may be configured to include a vertical register. Here, the vertical scanning circuit 112 can drive each pixel PX row by row via the horizontal drive line HCL when reading a signal from each pixel PX.

[0044] The column readout circuit 113 can form a source follower with each pixel PX when reading a signal from each pixel PX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL column by column based on the charge held in each pixel PX.

[0045] The column signal processing unit 114 processes the signals transmitted in the column direction from each pixel PX. For example, the column signal processing unit 114 can perform CDS (Correllated Double Sampling) processing or DDS (Double Data Sampling) based on the signals transmitted in the column direction from each pixel PX. Also, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel PX and output the imaging signal Gout. The column signal processing unit 114 includes a column ADC unit 114A.

[0046] The column ADC unit 114A can perform the AD conversion processing of pixel signals in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF. This AD conversion may be single-slope AD conversion, SAR (Successive Approximation Register) AD conversion, ΣAD conversion, dual-integration type AD conversion, or pipeline AD conversion. Also, the AD conversion may be column-parallel ADC or pixel-parallel ADC.

[0047] The horizontal scanning circuit 115 scans the pixels PX to be read in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0048] The control circuit 116 controls the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column reading circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can cooperate the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0049] Figure 3 is a block diagram showing an example of the configuration of a pixel array according to the first embodiment. In this figure, an example of the arrangement of pixels PX1 to PX4 in a 2x2 grid is shown, but it may also be applied to a pixel arrangement of X rows (where X is an integer of 2 or more) and Y columns (where Y is an integer of 2 or more).

[0050] In the figure, vertical signal lines VSL1 and VSL2 are provided in the column direction, and horizontal drive lines HCL1 and HCL2 are provided in the row direction. Pixels PX1 to PX4 are arranged adjacent to each other in the row and column directions. Pixel PX1 is connected to the vertical signal line VSL1 and the horizontal drive line HCL1. Pixel PX2 is connected to the vertical signal line VSL1 and the horizontal drive line HCL2. Pixel PX3 is connected to the vertical signal line VSL2 and the horizontal drive line HCL1. Pixel PX4 is connected to the vertical signal line VSL2 and the horizontal drive line HCL2.

[0051] Furthermore, binning transistors WV1 to WV3 and WD1 to WD4 are provided in the pixel array in which pixels PX1 to PX4 are arranged. Binning transistors WV1 to WV3 and WD1 to WD4 switch the connection of multiple floating diffusions between multiple pixels PX1 to PX4. Binning transistors WV1 to WV3 binn the pixel signals output from each pixel PX1 to PX4 in the column direction. Binning transistors WD1 and WD3 binn the pixel signals output from each pixel PX1 and PX3 in the row direction. Binning transistors WD2 and WD4 binn the pixel signals output from each pixel PX2 and PX4 in the row direction. Each binning transistor WV1 to WV3 is shared by multiple adjacent pixels PX1 to PX4 in the row direction. Each binning transistor WD1 to WD4 is provided for each pixel PX1 to PX4.

[0052] Binning transistors WD1 and WD3 are connected in series with each other. The series circuit of binning transistors WD1 and WD3 is connected between the floating diffusions of each pixel PX1 and PX3. Binning transistors WD2 and WD4 are connected in series with each other. The series circuit of binning transistors WD2 and WD4 is connected between the floating diffusions of each pixel PX2 and PX4. Binning transistor WV1 is connected to the connection point of binning transistors WD1 and WD3. Binning transistor WV2 is connected between the connection point of binning transistors WD1 and WD3 and the connection point of binning transistors WD2 and WD4. Binning transistor WV3 is connected to the connection point of binning transistors WD2 and WD4. MOS (Metal Oxide Semiconductor) transistors may be used as binning transistors WV1 to WV3 and WD1 to WD4.

[0053] The binning signal GD1 is applied to the gates of binning transistors WD1 and WD3. The binning signal GD2 is applied to the gates of binning transistors WD2 and WD4. The binning signal GV1 is applied to the gate of binning transistor WV1. The binning signal GV2 is applied to the gate of binning transistor WV2. The binning signal GV3 is applied to the gate of binning transistor WV3. The transmission lines for each binning signal GD1 and GD2 may be wired in the row direction or in the column direction. Each binning signal GV1 to GV3 may be wired in the row direction.

[0054] Here, by turning on binning transistors WD1 and WD3, the pixel signals read from each pixel PX1 and PX3 can be binned. By turning on binning transistors WD2 and WD4, the pixel signals read from each pixel PX2 and PX4 can be binned. By turning on binning transistors WD1, WD2, and WV2, the pixel signals read from each pixel PX1 and PX2 can be binned. By turning on binning transistors WD3, WD4, and WV2, the pixel signals read from each pixel PX3 and PX4 can be binned. By turning on binning transistors WD1, WD4, and WV2, the pixel signals read from each pixel PX1 and PX4 can be binned. By turning on binning transistors WD2, WD3, and WV2, the pixel signals read from each pixel PX2 and PX3 can be binned. Here, by binning the pixel signals read from each pixel PX2 and PX3, the pixel signals read from the green pixels in the Bayer array can be binned. By turning on the binning transistors WD1 to WD4 and WV2, the pixel signals read from each pixel PX1 to PX4 can be binned.

[0055] Furthermore, by providing binning transistors WV1 to WV3, which binn the pixel signals in the column direction, separately from the reset transistor 123, it becomes unnecessary to use the reset transistor 123 for binning the pixel signals in the column direction. As a result, the length of the wiring used for binning can be shortened, and a decrease in conversion efficiency can be suppressed.

[0056] Figure 4 shows a first example of the circuit configuration of a pixel provided in a solid-state imaging device according to the first embodiment. The pixel in the first embodiment is used in a transfer-gate type LOFIC.

[0057] In the figure, pixel PX11 can be used for each pixel PX1 to PX4. Pixel PX11 includes a photodiode PD, a transfer transistor TG, a reset transistor 123, an amplification transistor 124, a selection transistor 125, switching transistors 126 and 127, and floating diffusion transistors FD1 to FD3. Pixel PX11 also includes capacitors C1 and C2. Capacitor C2 can be used as a LOFIC. Capacitors C1 and C2 may be MIM (Metal-Insulator-Metal) capacitors or MOS capacitors. MOS transistors can be used as the transfer transistor TG, reset transistor 123, amplification transistor 124, selection transistor 125, and switching transistors 126 and 127.

[0058] The photodiode PD stores the charge converted by photoelectricity. The transfer transistor TG transfers the charge stored in the photodiode PD to the floating diffusion FD1. The reset transistor 123 resets FD3 from the floating diffusion FD1. The amplification transistor 124 outputs a pixel signal based on the potential of the floating diffusion FD1. The selection transistor 125 selects the output of the amplification transistor 124.

[0059] Switching transistors 126 and 127 switch the connections between multiple floating diffusion FD1 and FD3 within the pixel PX11. Switching transistor 126 switches the connection between floating diffusion FD1 and FD2. Switching transistor 127 switches the connection between floating diffusion FD2 and FD3.

[0060] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD1 via the transfer transistor TG. The floating diffusion FD1 is connected to the floating diffusion FD2 via the switching transistor 126. The floating diffusion FD1 is also connected to the gate of the amplification transistor 124. The floating diffusion FD1 is also connected to the binning transistor WD. The binning transistor WD can be either the binning transistor WD3 or WD4 in Figure 3. The binning transistor WD is connected to the binning transistor WV. The binning transistor WV can be either the binning transistor WV1 or WV2 in Figure 3. The floating diffusion FD2 is connected to the floating diffusion FD3 via the switching transistor 127. The floating diffusion FD2 is also connected to the capacitor C1. The floating diffusion FD3 is connected to the power supply potential VDD via the reset transistor 123. Additionally, the floating diffusion FD3 is connected to capacitance C2.

[0061] A transfer signal TGL is applied to the gate of the transfer transistor TG. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. A switching signal S0 is applied to the gate of the switching transistor 126. A switching signal S1 is applied to the gate of the switching transistor 127. The transfer signal TGL, the reset signal RST, the selection signal SEL, and the switching signals S0 and S1 can be transmitted to the pixel PX11 via the horizontal drive line HCL shown in Figure 2.

[0062] In a transfer-gate type LOFIC, the charge overflowing from the photodiode PD flows into the capacitor C2 via the transfer transistor TG. At this time, the charge overflowing from the photodiode PD also flows into the floating diffusion transistors FD1 and FD2.

[0063] Figure 5 shows a second example of a pixel circuit configuration provided in a solid-state imaging device according to the first embodiment.

[0064] In the same figure, the connection position of the binning transistor WD in pixel PX12 is different from that of pixel PX11 in Figure 4. In pixel PX12, the binning transistor WD is connected to the floating diffusion FD2. The other configurations of pixel PX12 are the same as those of pixel PX11 in Figure 4. Here, by connecting the binning transistor WD to the floating diffusion FD2, the decrease in conversion efficiency due to the potential of the floating diffusion FD1 can be suppressed.

[0065] Figure 6 shows a third example of a pixel circuit configuration provided in a solid-state imaging device according to the first embodiment.

[0066] In the same figure, the connection position of the binning transistor WD in pixel PX13 differs from that of pixel PX11 in Figure 4. In pixel PX13, the binning transistor WD is connected to the floating diffusion FD3. The other configurations of pixel PX13 are the same as those of pixel PX11 in Figure 4. Here, by connecting the binning transistor WD to the floating diffusion FD3, the decrease in conversion efficiency due to the potential of the floating diffusion FD1 can be suppressed.

[0067] Figure 7 is a plan view showing an example of a pixel layout in a solid-state imaging device according to the first embodiment. The layout shown in the figure is an example of a back-illuminated image sensor.

[0068] In the figure, an element isolation region ISA is formed on the semiconductor substrate SUB to isolate the active region AK from the element. The material of the semiconductor substrate SUB may be Si, GaAs, SiC, GaN, InGaAs, or InP, etc. The element isolation region ISA may be STI (Shallow Trench Isolation). The active region AK can be used to form the channel region, source / drain layers, and contacts of a photodiode PD or pixel transistor. In this case, the photodiode PD is placed on the back side of the semiconductor substrate SUB.

[0069] On the semiconductor substrate SUB, gate electrodes GT, G3 to G7, GB, GV, and a dummy electrode GA are formed at positions that cross the active region AK. The gate electrode GT can be used for the transfer transistor TG. The gate electrode G3 can be used for the reset transistor 123. The gate electrode G4 can be used for the amplification transistor 124. The gate electrode G5 can be used for the selection transistor 125. The gate electrode G6 can be used for the switching transistor 126. The gate electrode G7 can be used for the switching transistor 127. The gate electrode GB can be used for the binning transistor WD. The gate electrode GV can be used for the binning transistor WV. The dummy electrode GA can be used as a dummy for the gate electrode GV. In pixels PX where the dummy electrode GA is provided, the gate electrode GV is removed. Pixels PX where the dummy electrode GA is provided and pixels PX where the gate electrode GV is provided can be arranged adjacent to each other in the row direction.

[0070] The gate electrode GT can be placed adjacent to the photodiode PD. Each gate electrode G7, G3, G4, G5 can be placed sequentially adjacent to each other in the row direction. Each gate electrode GV, GB, G6 can be placed sequentially adjacent to each other in the column direction. The dummy electrode GA and each gate electrode GB, G6 can be placed sequentially adjacent to each other in the column direction.

[0071] Figure 8 is a timing chart showing the waveforms of each part when reading out the pixel signal from each pixel of the pixel array according to the first embodiment.

[0072] In the figure, the reading of pixel signals from each pixel of this pixel array includes a reset period H11, an LCG (Low Conversion Gain) P-phase reading period H12, an HCG (High Conversion Gain) P-phase reading period H13, an HCGD-phase reading period H14, an LCGD-phase reading period H15, an LOFICP-phase reading period H16, and an LOFICD-phase reading period H17.

[0073] During the reset period H11, the photodiode PD is reset. During the LCGP phase readout period H12, the P-phase level (also called the reset level) is read based on the potentials of the floating diffusion FD1 and FD2. During the HCGP phase readout period H13, the P-phase level is read based on the potential of the floating diffusion FD1. During the HCGD phase readout period H14, the D-phase level (also called the signal level) is read based on the potential of the floating diffusion FD1. During the LCGD phase readout period H15, the D-phase level is read based on the potentials of the floating diffusion FD1 and FD2. During the LOFICP phase readout period H16, the P-phase level is read based on the potentials of the floating diffusion FD1 to FD3 and the capacitance C2. During the LOFICD phase readout period H17, the D-phase level is read based on the potentials of the floating diffusion FD1 to FD3 and the capacitance C2.

[0074] During the reset period H11, the transfer signal TGL, switching signals S0 and S1, and reset signal RST rise, and the transfer transistor TG, switching transistors 126 and 127, and reset transistor 123 turn on. At this time, the photodiode PD and floating diffusion transistors FD1 through FD3 are reset. After the reset period H11 has elapsed, the transfer signal TGL, switching signals S0 and S1, and reset signal RST fall, and the transfer transistor TG, switching transistors 126 and 127, and reset transistor 123 turn off.

[0075] Next, during the LCGP phase readout period H12, the selection signal SEL rises, and the selection transistor 125 turns on. Also, the switching signal S0 rises, and the switching transistor 126 turns on. At this time, the floating diffusions FD1 and FD2 are connected via the switching transistor 126. Then, the potential of the vertical signal line VSL is set based on the source follower operation when the P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 124.

[0076] Then, the potential of the vertical signal line VSL corresponding to the LCGP phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line VSL is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line VSL, the LCGP phase levels read from the pixels are AD converted column by column.

[0077] Next, during the HCGP phase readout period H13, the switching signal S0 falls, and the switching transistor 126 turns off. At this time, the floating diffusions FD1 and FD2 are interrupted via the switching transistor 126. Then, the potential of the vertical signal line VSL is set based on the source follower operation when the P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 124.

[0078] Then, the potential of the vertical signal line VSL corresponding to the HCGP phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line VSL is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line VSL, the HCGP phase levels read from the pixels are AD converted column by column.

[0079] Next, before the HCGD phase readout period H14, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD1.

[0080] Next, during the HCGD phase readout period H14, when the transfer signal TGL falls, the transfer transistor 122 turns off. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the D phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 124.

[0081] Then, the potential of the vertical signal line VSL corresponding to the HCGD phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line VSL is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line VSL, the HCGD phase levels read from the pixels are AD converted column by column.

[0082] Next, the switching signal S0 rises before the LCGD phase readout period H15, and the switching transistor 126 turns on. At this time, the floating diffusion diodes FD1 and FD2 are connected via the switching transistor 126. Also, the transfer signal TGL rises, and the transfer transistor TG turns on, transferring the charge accumulated in the photodiode 121 to the floating diffusion diode FD1.

[0083] Next, during the LCGD phase readout period H15, when the transfer signal TGL falls, the transfer transistor 122 turns off. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the D phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplification transistor 124.

[0084] Then, the potential of the vertical signal line VSL corresponding to the LCGD phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line VSL is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line VSL, the LCGD phase levels read from the pixels are AD converted column by column.

[0085] Next, during the LOFICP phase readout period H16, the switching signal S1 rises, and the switching transistor 127 turns on. At this time, the floating diffusions FD2 and FD3 are connected via the switching transistor 127. Then, the potential of the vertical signal line VSL is set based on the source follower operation when the D-phase levels of the floating diffusions FD1 to FD3 are applied to the gate of the amplification transistor 124.

[0086] Then, the potential of the vertical signal line VSL corresponding to the LOFICD phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line VSL is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line VSL, the LOFICD phase level read from the pixel is AD converted column by column.

[0087] Next, before the LOFICD phase readout period H17, the reset signal RST rises, and the reset transistor 123 turns on. At this time, the floating diffusions FD1 to FD3 and capacitors C1 and C2 are reset.

[0088] Next, during the LOFICD phase readout period H17, the reset signal RST falls, and the reset transistor 123 turns off. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the P-phase levels of the floating diffusion FD1 to FD3 are applied to the gate of the amplification transistor 124.

[0089] Then, the potential of the vertical signal line VSL corresponding to the LOFICP phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line VSL is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line VSL, the LOFICP phase levels read from the pixels are AD converted column by column.

[0090] As described above, in the first embodiment, the connection of any of the floating diffusion FD1 to FD3 is switched between the row direction and the column direction between multiple pixels PX1 to PX4. This makes it possible to change the row direction and column direction resolution during binning of the pixel signals read from multiple pixels PX1 to PX4 based on the switching of any of the connections of the floating diffusion FD1 to FD3 between multiple pixels PX1 to PX4. Therefore, the resolution, frame rate, image quality, and dynamic range can be changed according to the application, such as imaging, illumination detection, and motion detection, and the performance of the imaging device can be improved according to the application. Furthermore, by binning and reading out the pixel signals, it is possible to reduce power consumption compared to digital summation, and the S / N ratio can be improved while avoiding reading from defective pixels compared to inter-pixel decimation.

[0091] <2. Second Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this second embodiment, the connection of any of the floating diffusion FD1 to FD3 is switched between the row direction between multiple pixels PX1 to PX4.

[0092] Figure 9 is a block diagram showing an example of the configuration of a pixel array according to the second embodiment.

[0093] In the figure, the imaging device is modified by removing binning transistors WV1 through WV3 from the pixel array of the first embodiment described above. At this time, the connection points of binning transistors WD1 and WD3 and the connection points of binning transistors WD2 and WD4 are directly connected. The other configurations of this imaging device are the same as those of the imaging device of the first embodiment described above.

[0094] Thus, in the second embodiment described above, one of the connections between floating diffusion FD1 and FD3 is switched in the row direction between multiple pixels PX1 and PX4. This makes it possible to change the row resolution during binning of the pixel signals read from multiple pixels PX1 to PX4 based on the switching of one of the connections between floating diffusion FD1 and FD3 between multiple pixels PX1 to PX4.

[0095] <3. Third Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this third embodiment, the connection of any of the floating diffusion FD1 to FD3 is switched between the row direction and the column direction between multiple pixels, and a reset transistor is shared between adjacent pixels in the row direction.

[0096] Figure 10 is a block diagram showing an example of the configuration of a pixel array according to the third embodiment. The pixels of the third embodiment are used in a transfer gate type LOFIC.

[0097] In the figure, this imaging device includes pixels PXS1 to PXS4 instead of pixels PX1 to PX4 of the first embodiment described above. Furthermore, reset transistors RS1 to RS3 are added to the pixel array of the first embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the first embodiment described above.

[0098] Each pixel PXS1 to PXS4 has the reset transistor 123 removed from each pixel PX1 to PX4 in the first embodiment described above. The other configurations of each pixel PXS1 to PXS4 are the same as those of each pixel PX1 to PX4 in the first embodiment described above.

[0099] Each reset transistor RS1 to RS3 is shared by pixels adjacent to each other in the row direction. For example, reset transistor RS1 is shared by pixels PXS1 and PXS3, and reset transistor RS2 is shared by pixels PXS2 and PXS4. In this case, reset transistor RS1 resets the floating diffusion FD1 to FD3 of pixels PXS1 and PXS3, and reset transistor RS2 resets the floating diffusion FD1 to FD3 of pixels PXS2 and PXS4. Each reset transistor RS1 to RS3 is connected in parallel to each binning transistor WV1 to WV3. Reset signals RST1 to RST3 are applied to the gates of each reset transistor RS1 to RS3, respectively.

[0100] Figure 11 shows a first example of a pixel circuit configuration provided in a solid-state imaging device according to the third embodiment.

[0101] In the same figure, pixel PX21 is the same as pixel PX11 in Figure 4 but without the reset transistor 123. The other configurations of pixel PX21 are the same as those of pixel PX11 in Figure 4. In this case, pixel PX21 can use any of the reset transistors RS1 to RS3 instead of reset transistor 123.

[0102] Figure 12 shows a second example of a pixel circuit configuration provided in a solid-state imaging device according to the third embodiment.

[0103] In this figure, the connection position of the binning transistor WD in pixel PX22 is different from that of pixel PX21 in Figure 11. In pixel PX22, the binning transistor WD is connected to the floating diffusion FD2. The other configurations of pixel PX22 are the same as those of pixel PX21 in Figure 11.

[0104] Figure 13 shows a third example of a pixel circuit configuration provided in a solid-state imaging device according to the third embodiment.

[0105] In this figure, the connection position of the binning transistor WD in pixel PX23 differs from that of pixel PX21 in Figure 11. In pixel PX23, the binning transistor WD is connected to the floating diffusion FD3. The other configurations of pixel PX23 are the same as those of pixel PX21 in Figure 11.

[0106] Figure 14 is a timing chart showing the waveforms of each part during non-binning readout of the pixel signal from each pixel of the pixel array according to the third embodiment. Note that the reset signal RST in the figure is assigned to one of the reset signals RST1 to RST3 in Figure 10.

[0107] In the figure, during non-binning readout of the pixel signal, the reset signal RST is always maintained at a high level. At this time, by setting the level of the switching signal GV to a low level and setting the level of the switching signal GD to the same level as the reset signal RST in Figure 8, each pixel of the pixel array is reset. The waveforms of the other parts of the non-binning readout of the pixel signal in the third embodiment are the same as the waveforms of the other parts of the readout of the pixel signal in the first embodiment.

[0108] Figure 15 is a timing chart showing the waveforms of each part during binning readout of pixel signals from each pixel of a pixel array according to the third embodiment.

[0109] In the figure, during pixel signal binning readout, binning readout is performed during the LCGP phase readout period H12, the LCGD phase readout period H15, the LOFICP phase readout period H16, and the LOFICD phase readout period H17.

[0110] Specifically, during the LCGP phase readout period H12, the binning signals GD and GV are set to high levels, and the binning transistors WD and WV are turned on. At this time, the floating diffusion FD1 and FD2 of adjacent pixels in the row and column directions are connected, and LCGP phase-level binning readout is performed.

[0111] During the LCGD phase readout period H15, the binning signals GD and GV are set to high levels, and the binning transistors WD and WV are turned on. At this time, the floating diffusion FD1 and FD2 of adjacent pixels in the row and column directions are connected, and binning readout of the LCGD phase level is performed.

[0112] During the LOFICP phase readout period H16, the binning signals GD and GV are set to high levels, and the binning transistors WD and WV are turned on. At this time, the floating diffusion FD1 to FD3 of adjacent pixels in the row and column directions are connected, and LOFICD phase-level binning readout is performed.

[0113] During the LOFICD phase readout period H17, the binning signals GD and GV are set to high levels, and the binning transistors WD and WV are turned on. At this time, the floating diffusion FD1 to FD3 of adjacent pixels in the row and column directions are connected, and LOFICP phase-level binning readout is performed. The waveforms of the other parts of the pixel signal binning readout in the third embodiment are the same as the waveforms of the pixel signal readout in the first embodiment.

[0114] Thus, in the third embodiment described above, the connection of any of the floating diffusion FD1 to FD3 is switched between the row direction and the column direction between multiple pixels PXS1 to PXS4, and any of the reset transistors RS1 to RS3 are shared between adjacent pixels in the row direction. This makes it possible to change the row direction and column direction resolution during binning of pixel signals read from multiple pixels PXS1 to PXS4 while reducing the circuit size of each pixel PXS1 to PXS4.

[0115] <4. Fourth Embodiment> In the third embodiment described above, the connection of any of the floating diffusion FD1 to FD3 is switched between the row direction and the column direction between multiple pixels PXS1 to PXS4, and one of the reset transistors RS1 to RS3 is shared by adjacent pixels in the row direction. In this fourth embodiment, the connection of any of the floating diffusion FD1 to FD3 is switched between the row direction and the column direction between multiple pixels PXS1 to PXS4, and the reset transistor is shared by adjacent pixels in the row direction and the column direction.

[0116] Figure 16 is a block diagram showing an example of the configuration of a pixel array according to the fourth embodiment.

[0117] In the figure, the reset transistors RS1 and RS3 and the binning transistors WV2 and WV3 are removed from the pixel array of the third embodiment described above. The other configurations of this pixel array are the same as those of the imaging device of the third embodiment described above.

[0118] The reset transistor RS2 is shared by pixels adjacent to each other in the row and column directions. For example, the reset transistor RS2 is shared by each pixel PXS1 to PXS4. In this case, the reset transistor RS2 resets the floating diffusion FD1 to FD3 of each pixel PXS1 to PXS4.

[0119] The binning transistor WV1 is shared by pixels adjacent to each other in the row and column directions. For example, the binning transistor WV1 is shared by each pixel PXS1 through PXS4.

[0120] Thus, in the fourth embodiment described above, the connection of any of the floating diffusion FD1 to FD3 is switched between the row direction and the column direction between multiple pixels PXS1 to PXS4, and the reset transistor RS2 is shared between adjacent pixels in the row direction and the column direction. This makes it possible to change the row direction and column direction resolution during binning of pixel signals read from multiple pixels PXS1 to PXS4 while reducing the circuit size of each pixel PXS1 to PXS4.

[0121] <5. Fifth Embodiment> In the third embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PXS1 to PXS4. In this fifth embodiment, the connection of any of the floating diffusion FD1 to FD3 is switched between the row direction and the column direction between multiple pixels PXS1 to PXS4, and the number of binning pixels is changed in the row direction and the column direction.

[0122] Figure 17 is a block diagram showing an example of the configuration of a pixel array according to the fifth embodiment.

[0123] In the figure, this imaging device has a binning transistor WH1 added to the pixel array of the third embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the third embodiment described above.

[0124] The binning transistor WH1 switches the connection of floating diffusion of non-adjacent pixels located in the same row. For example, one end of the binning transistor WH1 is connected to the connection points of binning transistors WD1 and WD3 and binning transistors WD2 and WD4. The other end of the binning transistor WH1 is connected to the connection points of binning transistors WD1 and WD3 and binning transistors WD2 and WD4 of pixels PXS1 to PXS4 and pixels PXS1 to PXS4 in different columns. A binning signal GH1 is applied to the gate of the binning transistor WH1. The transmission line of the binning signal GH1 can be routed in the column direction.

[0125] Thus, in the fifth embodiment described above, the connection of any of the floating diffusion FD1 to FD3 is switched between the row direction and the column direction between multiple pixels PXS1 to PXS4, and the number of binned pixels can be changed in the row direction and the column direction. This makes it possible to vary the resolution during row-direction binning of the pixel signals read from pixels PXS1 to PXS4.

[0126] <6. Sixth Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this sixth embodiment, the connection of any of the floating diffusion FD1 to FD3 of the pixel whose overflow is controlled is made switchable.

[0127] Figure 18 shows a first circuit configuration example of a pixel provided in a solid-state imaging device according to the sixth embodiment. The pixel in the sixth embodiment is used in an OFG (Over Flow Gate) type LOFIC.

[0128] In the same figure, pixel PX31 has an overflow control transistor 128 added to pixel PX11 in Figure 4. The other configurations of pixel PX31 are the same as those of pixel PX11 in Figure 4.

[0129] The overflow control transistor 128 controls the overflow of charge from the photodiode PD to the capacitor C2. The overflow control transistor 128 is connected between the cathode of the photodiode PD and the connection point between the capacitor C2 and the switching transistor 127. The reset transistor 123 is connected to the floating diffusion FD2. An overflow control signal OFG is applied to the gate of the overflow control transistor 128. The overflow control signal OFG may be set to a fixed potential.

[0130] In the OFG-type LOFIC, the charge overflowing from the photodiode PD flows into the capacitor C2 via the overflow control transistor 128. At this time, the charge overflowing from the photodiode PD does not flow into the floating diffusion transistors FD1 and FD2.

[0131] Figure 19 shows a second example of a pixel circuit configuration provided in a solid-state imaging device according to the sixth embodiment.

[0132] In this figure, the connection position of the binning transistor WD in pixel PX32 is different from that of pixel PX31 in Figure 18. In pixel PX32, the binning transistor WD is connected to the floating diffusion FD2. The other configurations of pixel PX32 are the same as those of pixel PX31 in Figure 18.

[0133] Figure 20 shows a third example of a pixel circuit configuration provided in a solid-state imaging device according to the sixth embodiment.

[0134] In this figure, the connection position of the binning transistor WD in pixel PX33 differs from that of pixel PX31 in Figure 18. In pixel PX33, the binning transistor WD is connected to the floating diffusion FD3. The other configurations of pixel PX33 are the same as those of pixel PX31 in Figure 18.

[0135] Furthermore, pixels PX31 to PX33 of the sixth embodiment described above can be used as pixels PX1 to PX4 of the pixel array of the first or second embodiment described above.

[0136] Figure 21 is a timing chart showing the waveforms of each part when reading out the pixel signal from each pixel of the pixel array according to the sixth embodiment.

[0137] In the figure, when reading the pixel signal from each pixel where overflow is controlled, a reset period H11' is added to the timing chart of the first embodiment described above. The waveforms of the other parts of the pixel signal reading in the sixth embodiment are the same as the waveforms of the other parts of the pixel signal reading in the first embodiment.

[0138] The reset period H11' is provided immediately before the LCGP phase readout period H12. During the reset period H11', the transfer signal TGL, switching signals S0 and S1, and reset signal RST rise, and switching transistors 126 and 127 and reset transistor 123 turn on. At this time, floating diffusions FD1 and FD2 are reset. Then, after switching signal S1 falls, the reset signal RST falls, and the system transitions to the LCGP phase readout period H12. By resetting floating diffusions FD1 and FD2 before the LCGP phase readout period H12, the amount of charge that can be transferred from the photodiode PD to the LOFIC can be increased.

[0139] Thus, in the sixth embodiment described above, the connection of any of the floating diffusion FD1 to FD3 of pixels PX31 to PX33, where overflow is controlled, can be switched. This makes it possible to increase the amount of charge that can be transferred from the photodiode PD to the LOFIC, while changing the row-direction and column-direction resolution during binning of the pixel signals read from multiple pixels PX1 to PX4.

[0140] <7. Seventh Embodiment> In the first embodiment described above, the connection of any of the floating diffusions FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this seventh embodiment, the connection of the floating diffusion of the pixel whose overflow is controlled is made switchable, and the reset transistor is shared among multiple pixels.

[0141] Figure 22 shows a first circuit configuration example of a pixel provided in a solid-state imaging device according to the seventh embodiment. The pixel in the seventh embodiment is used in an OFG type LOFIC.

[0142] In the same figure, pixel PX41 is the same as pixel PX31 in Figure 18 but without the reset transistor 123. The other configurations of pixel PX41 are the same as those of pixel PX31 in Figure 18. In this case, pixel PX41 can use any of the reset transistors RS1 to RS3 instead of reset transistor 123.

[0143] Figure 23 shows a second example of a pixel circuit configuration provided in a solid-state imaging device according to the seventh embodiment.

[0144] In the same figure, the connection position of the binning transistor WD in pixel PX42 is different from that of pixel PX41 in Figure 22. In pixel PX42, the binning transistor WD is connected to the floating diffusion FD2. The other configurations of pixel PX42 are the same as those of pixel PX41 in Figure 22.

[0145] Figure 24 shows a third example of a pixel circuit configuration provided in a solid-state imaging device according to the seventh embodiment.

[0146] In this figure, the connection position of the binning transistor WD in pixel PX43 differs from that of pixel PX41 in Figure 22. In pixel PX43, the binning transistor WD is connected to the floating diffusion FD3. The other configurations of pixel PX43 are the same as those of pixel PX41 in Figure 22.

[0147] Furthermore, pixels PX41 to PX43 of the seventh embodiment described above can be used as pixels PXS1 to PXS4 of any of the pixel arrays of the third to fifth embodiments described above.

[0148] Thus, in the seventh embodiment described above, the connection of the floating diffusion FD1 to FD3 of pixels PX41 to PX43, where overflow is controlled, can be switched, and one of the reset transistors RS1 to RS3 is shared among multiple pixels. This makes it possible to increase the amount of charge that can be transferred from the photodiode PD to the LOFIC, change the row-direction and column-direction resolution during binning of the pixel signals read from multiple pixels PXS1 to PXS4, and reduce the circuit size of each pixel PXS1 to PXS4.

[0149] <8. Eighth Embodiment> In the first embodiment described above, the connection of any of the floating diffusions FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this eighth embodiment, multiple pixels share a floating diffusion.

[0150] Figure 25 shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the eighth embodiment.

[0151] In the figure, this imaging device includes a cell CEL1 instead of the pixel PX of the first embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the first embodiment described above.

[0152] Cell CEL1 includes multiple pixels. In this case, each pixel may include, for example, photodiodes PD1 to PD4 and transfer transistors TG1 to TG4.

[0153] Cell CEL1 shares a reset transistor 123, an amplification transistor 124, a selection transistor 125, switching transistors 126 and 127, floating diffusion transistors FD1 to FD3, and capacitors C1 and C2 among multiple pixels.

[0154] The cathodes of each photodiode PD1 to PD4 are connected to the floating diffusion FD1 via transfer transistors TG1 to TG4, respectively. Transfer signals TGL1 to TGL4 are applied to the gates of each transfer transistor TG1 to TG4, respectively. The rest of the configuration of cell CEL1 is the same as that of any of the pixels PX11 to PX13 in the first embodiment described above.

[0155] Furthermore, the cell CEL1 of the eighth embodiment described above can be used for pixels PX1 to PX4 of the pixel array of either the first or second embodiment described above.

[0156] Thus, in the eighth embodiment described above, the floating diffusion FD1 is shared by multiple pixels included in cell CEL1. This reduces the circuit size of each pixel included in cell CEL1, while allowing the connection of either the floating diffusion FD1 to FD3 to be switched between the row direction and the column direction among multiple pixels.

[0157] <9. Ninth Embodiment> In the first embodiment described above, the connection of any of the floating diffusions FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this ninth embodiment, the floating diffusion is shared by multiple pixels whose overflow is controlled.

[0158] Figure 26 shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the ninth embodiment.

[0159] In the figure, cell CEL2 includes multiple pixels. In this case, each pixel may include, for example, photodiodes PD1 to PD4 and transfer transistors TG1 to TG4.

[0160] Cell CEL2 shares a reset transistor 123, an amplification transistor 124, a selection transistor 125, switching transistors 126 and 127, floating diffusion transistors FD1 to FD3, and capacitors C1 and C2 among multiple pixels.

[0161] The cathodes of each photodiode PD1 to PD4 are connected to the floating diffusion FD1 via transfer transistors TG1 to TG4, respectively. The cathodes of each photodiode PD1 to PD4 are also connected to the floating diffusion FD3 via overflow control transistors FG1 to FG4, respectively. Overflow control signals OFG1 to OFG4 are applied to the gates of each overflow control transistor FG1 to FG4, respectively. The rest of the configuration of cell CEL2 is the same as that of any of the pixels PX31 to PX33 in the sixth embodiment described above.

[0162] Furthermore, the cell CEL2 of the ninth embodiment described above can be used for pixels PX1 to PX4 of the pixel array of either the first or second embodiment described above.

[0163] Thus, in the ninth embodiment described above, the floating diffusion FD1 is shared by multiple pixels in the cell CEL2, where overflow is controlled. This reduces the circuit size of each pixel in the cell CEL2, while allowing the connection of either the floating diffusion FD1 to FD3 to be switched between the row direction and the column direction among multiple pixels.

[0164] <10. Tenth Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between multiple pixels PX1 to PX4 in the row direction and the column direction. In this tenth embodiment, a capacitance reset transistor is provided to reset the capacitance of the pixel whose floating diffusion connection can be switched.

[0165] Figure 27 shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the tenth embodiment.

[0166] In the same figure, pixel PX51 has a capacitive reset transistor 129 added to pixel PX11 in Figure 4. The other configurations of pixel PX51 are the same as those of pixel PX11 in Figure 4.

[0167] The capacitance reset transistor 129 resets capacitance C2. The capacitance reset transistor 129 is connected between the power supply potential VDD and the ground potential. Capacitor C2 is connected between the source of the capacitance reset transistor 129 and the floating diffusion FD3. A capacitance reset signal MST is applied to the gate of the capacitance reset transistor 129.

[0168] Thus, in the tenth embodiment described above, a capacitance reset transistor 129 is provided to reset the capacitance C2 of the pixel PX51, which can switch the connection between any of the floating diffusion FD1 to FD3. This allows for faster charging and discharging of the capacitance C2, while also enabling switching between the row direction and column direction of any of the floating diffusion FD1 to FD3 connections between multiple pixels.

[0169] In the configuration shown in Figure 27, the reset transistor 123 and the capacitive reset transistor 129 are connected to the power supply potential VDD, but the reset transistor 123 and the capacitive reset transistor 129 may be connected to a separate power supply.

[0170] <11. Eleventh Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this eleventh embodiment, a pixel chip on which pixels are mounted and a logic chip on which logic circuits are mounted are stacked.

[0171] Figure 28 is a perspective view showing a first stacking example of a solid-state imaging device according to the eleventh embodiment.

[0172] In the figure, this imaging device can be used with a back-illuminated image sensor. This imaging device comprises a pixel chip PXB and a logic chip LOB. The logic chip LOB is stacked on the pixel chip PXB. The pixel chip PXB can have the pixels PX and binning transistors WV1 to WV3 and WD1 to WD4 of the first embodiment described above formed on it. The logic chip LOB can have the vertical scanning circuit 112, column reading circuit 113, column signal processing unit 114, horizontal scanning circuit 115, and control circuit 116 of the first embodiment described above formed on it.

[0173] Figure 29 is a perspective view showing a second stacking example of a solid-state imaging device according to the eleventh embodiment.

[0174] In the figure, this imaging device can be used with a back-illuminated image sensor. This imaging device comprises a pixel chip PXB and logic chips LOB1 and LOB2. Logic chip LOB1 is stacked on the pixel chip PXB. Logic chip LOB2 is stacked on logic chip LOB1. The pixel chip PXB can form the pixel PX and binning transistors WV1 to WV3 and WD1 to WD4 of the first embodiment described above. Logic chip LOB1 can form the vertical scanning circuit 112, column reading circuit 113, column signal processing unit 114, horizontal scanning circuit 115, and control circuit 116 of the first embodiment described above. Logic chip LOB1 can also form the imaging control unit 103 and image processing unit 104 of the first embodiment described above.

[0175] Figure 30 is a perspective view showing a third stacking example of a solid-state imaging device according to the eleventh embodiment.

[0176] In the figure, this imaging device can be used in a back-illuminated image sensor. This imaging device comprises pixel chips PXB1 and PXB2 and a logic chip LOB. Pixel chip PXB2 is stacked on pixel chip PXB1. Logic chip LOB is stacked on pixel chip PXB2. Pixel chip PXB1 can form the photodiode PD and some of the pixel transistors and some of the binning transistors WV1 to WV3 and WD1 to WD4 of the first embodiment described above. Pixel chip PXB2 can form the remaining parts of the pixel transistors and the remaining parts of the binning transistors WV1 to WV3 and WD1 to WD4 of the first embodiment described above. The pixel transistors include a transfer transistor TG, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and switching transistors 126 and 127. The logic chip LOB can be configured with the vertical scanning circuit 112, column reading circuit 113, column signal processing unit 114, horizontal scanning circuit 115, and control circuit 116 described in the first embodiment above.

[0177] Thus, in the 11th embodiment described above, logic chips are stacked on the pixel chip. This makes it possible to increase the area of ​​the photodiode PD while suppressing an increase in the mounting area of ​​the solid-state imaging device, and thereby increase the sensitivity of the solid-state imaging device.

[0178] <12. Twelfth Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this twelfth embodiment, an imaging device equipped with LOFIC pixels that can switch the connection of the floating diffusion is applied to motion detection.

[0179] Figure 31 shows an example of motion detection by a solid-state imaging device according to the twelfth embodiment.

[0180] In the figure, the imaging device of the above-described embodiment can be used to detect the motion of a subject. In this case, the imaging device can generate a difference image GZ3 by taking the difference between the image GZ1 of the Nth (where N is a positive integer)th frame and the image GZ2 of the N+1th frame. The imaging device can then detect the motion of the subject based on the difference image GZ3. Here, an imaging device having LOFIC pixels can generate an HDR image based on pixel signals from pixels with different sensitivities. Therefore, the exposure amount can be matched between the image GZ1 of the Nth frame and the image GZ2 of the N+1th frame, eliminating the need for exposure adjustment when detecting the motion of a subject.

[0181] Thus, in the twelfth embodiment described above, an imaging device equipped with a LOFIC pixel that can switch between connections of floating diffusion FD1 to FD3 is applied to motion detection. This makes it possible to detect the movement of a subject without requiring exposure adjustment, and also makes it possible to change the row-direction and column-direction resolution during binning of pixel signals read from multiple pixels.

[0182] <13. Thirteenth Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this thirteenth embodiment, an imaging device equipped with pixels that can switch the connection of the floating diffusion is applied to the decimation process.

[0183] Figure 32 shows an example of the thinning process for a solid-state imaging device according to the thirteenth embodiment.

[0184] In the figure, the imaging device has a pixel array in which pixels PX1 to PX4 in Figure 3 are arranged in an array in the row direction and column direction. At this time, the imaging device can set a thinning area RN using the pixel array in which pixels PX1 to PX4 are arranged as a unit, and perform thinning in the row direction and column direction.

[0185] For example, pixels PX1 to PX4 located in rows A3, A4, A7, and A8, and pixels PX1 to PX4 located in columns B3, B4, B7, and B8 can be set as the decimation area RN. In this case, the imaging device can skip scanning of rows A3, A4, A7, and A8, thereby improving the frame rate, and can also stop the AD conversion processing of columns B3, B4, B7, and B8, thereby reducing power consumption.

[0186] Thus, in the 13th embodiment described above, an imaging device equipped with a pixel that can switch between connections of floating diffusion FD1 to FD3 is applied to the decimation process. This makes it possible to change the row and column resolution during binning of pixel signals read from multiple pixels, while limiting the number of pixels from which the pixel signal is read, thereby reducing power consumption and the amount of transmitted data.

[0187] <14. Fourteenth Embodiment> In the first embodiment described above, the connection of any of the floating diffusions FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this fourteenth embodiment, an imaging device equipped with pixels capable of switching the connection of floating diffusions is applied to interlacing.

[0188] Figures 33 and 34 show an example of interlacing processing for a solid-state imaging device according to the 14th embodiment.

[0189] In Figures 33 and 34, the imaging device has pixel arrays in which pixels PX1 to PX4 from Figure 3 are arranged in an array in the row direction and column direction. In this case, the imaging device can perform interlacing processing on a unit basis, with each pixel array containing pixels PX1 to PX4 being the basis for the processing.

[0190] For example, this imaging device can generate an image by combining the even frames in Figure 33 and the odd frames in Figure 34. In this case, in the even frames of Figure 33, the reading from pixels PX1 to PX4 located in rows A3, A4, A7, and A8 is skipped. In the odd frames of Figure 34, the reading from pixels PX1 to PX4 located in rows A3, A4, A7, and A8 is skipped.

[0191] Thus, in the 14th embodiment described above, an imaging device equipped with pixels that can switch between connections of floating diffusion FD1 to FD3 is applied to interlacing processing. This makes it possible to change the row and column resolution during binning of pixel signals read from multiple pixels, while limiting the number of pixels from which pixel signals are read, thereby reducing power consumption and the amount of data transmitted.

[0192] <15. Fifteenth Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between the row direction and the column direction between multiple pixels PX1 to PX4. In this fifteenth embodiment, an imaging device provided with pixels that can switch the connection of the floating diffusion is applied to a camera.

[0193] Figure 35 is a block diagram showing an example of the camera configuration according to the 15th embodiment.

[0194] In the figure, the camera 1500 comprises a solid-state imaging device 1501, a processor 1502, and a sensor 1503. The solid-state imaging device 1501 comprises a pixel control unit 1511, a pixel array unit 1512, an AD conversion unit 1513, an image processing unit 1514, an interface 1515, and a circuit control unit 1516.

[0195] The solid-state imaging device 1501 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, and outputs the electrical signal digitized. At this time, the solid-state imaging device 1501 can digitize the pixel signals read from the pixels by binning them. Here, the solid-state imaging device 1501 can change the resolution in the row direction and column direction when binning the pixel signals.

[0196] The processor 1502 sets the drive mode of the solid-state imaging device 1501 based on the detection result of the sensor 1503. The processor 1502 may perform image recognition processing based on an application program. The processor 1502 may be a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). The processor 1502 may be a single-core processor or a multi-core processor. The processor 1502 may be equipped with hardware circuits such as accelerators that perform part of the processing (for example, an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit)).

[0197] The sensor 1503 detects the external environment based on the control of the processor 1502 and outputs the detection result to the processor 1502. The sensor 1503 may be an image sensor, a distance measuring sensor, or an illuminance sensor.

[0198] The pixel control unit 1511 controls the accumulation operation, shutter operation, and read operation of each pixel PX in the pixel array unit 1512. For example, the pixel control unit 1511 may perform decimation drive or interlacing drive of the pixel array unit 1512.

[0199] The pixel array section 1512 comprises a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction and the column direction. The pixel array section 1512 may comprise any of the pixel arrays and pixels of the first to tenth embodiments described above.

[0200] The AD conversion unit 1513 performs AD conversion processing of pixel signals in parallel for each column. The AD conversion unit 1513 may also have a function to stop the AD conversion processing of columns in which decimation is performed.

[0201] The image processing unit 1514 performs image processing based on the output from the solid-state imaging device 102. The image processing may include HDR processing, motion detection processing, and frame stacking processing.

[0202] Interface 1515 mediates the transfer of data between the processor 1502 and the circuit control unit 1516.

[0203] The circuit control unit 1516 controls the pixel control unit 1511, the pixel array unit 1512, the AD conversion unit 1513, the image processing unit 1514, and the interface 1515. For example, the circuit control unit 1516 can coordinate the pixel control unit 1511, the pixel array unit 1512, the AD conversion unit 1513, the image processing unit 1514, and the interface 1515 so that an image conforming to the drive mode specified by the processor 1502 is obtained.

[0204] At this time, the processor 1502 can receive an external signal from the sensor 1503 and switch the drive mode of the solid-state imaging device 102 via the circuit control unit 1516. The circuit control unit 1516 then controls the pixel control unit 1511 according to the drive mode, and can reduce power consumption by switching the number of pixels to be binned. For example, the processor 1502 can receive a signal from the sensor 1503 to switch to parking surveillance mode and reduce the power consumption of the camera 1500 by capturing images at the minimum resolution required for parking surveillance.

[0205] Figure 36 is a block diagram showing an example of connection of a solid-state imaging device according to the 15th embodiment.

[0206] In the same figure, the pixel control unit 1511, the pixel array unit 1512, the AD conversion unit 1513, and the image processing unit 1514 can be mounted in the stacked structure of Figure 29. Here, the pixel array unit 1512 may be mounted on the pixel chip PXB, the pixel control unit 1511 and the AD conversion unit 1513 may be mounted on the logic chip LOB1, and the image processing unit 1514 may be mounted on the logic chip LOB2.

[0207] In this case, the pixel array unit 1512 and the pixel control unit 1511 may be joined via bonding electrodes D1 and D2, the pixel array unit 1512 and the AD conversion unit 1513 may be joined via bonding electrodes D3 and D4, and the AD conversion unit 1513 and the image processing unit 1514 may be joined via bonding electrodes D5 and D6. Cu can be used as the material for bonding electrodes D1 to D6. This allows for Cu-Cu bonding of the pixel chip PXB and each logic chip LOB1 and LOB2, and enables miniaturization of the bonding portion of the pixel chip PXB and each logic chip LOB1 and LOB2.

[0208] Thus, in the 15th embodiment described above, a solid-state imaging device 1501 equipped with a pixel that can switch between connections of floating diffusion FD1 to FD3 is applied to the camera 1500. This makes it possible to change the row-direction and column-direction resolution of the pixel signals read from multiple pixels during binning, while adapting to the drive mode according to the external environment of the camera 1500.

[0209] <16. Sixteenth Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched in the row direction and column direction between multiple pixels PX1 to PX4. In this sixteenth embodiment, a Cu-Cu junction is applied to pixels in which the connection of any of the floating diffusion FD1 to FD3 can be switched.

[0210] Figure 37 is a block diagram showing a first example of pixel division according to the sixteenth embodiment.

[0211] In the figure, a series circuit of binning transistors WD1 and WD3 is connected between the floating diffusion FD2 of each pixel PX121 and PX123. The circuit configuration of each pixel PX121 and PX122 is the same as the circuit configuration of each pixel PX12 in Figure 5.

[0212] Here, each pixel PX121 and PX123 is separated between the floating diffusion FD1 and the transfer transistor TG. At this time, the configuration of each pixel PX121 and PX123 on the transfer transistor TG side can be mounted on the pixel chip PXB1 in Figure 30, and the configuration of each pixel PX121 and PX123 on the floating diffusion FD1 side can be mounted on the pixel chip PXB2 in Figure 30. The floating diffusion FD1 and the transfer transistor TG can be joined by a Cu-Cu junction via junction electrodes D11 and D12.

[0213] Figure 38 is a block diagram showing a second example of pixel division according to the sixteenth embodiment.

[0214] In the figure, a series circuit of binning transistors WD1 and WD3 is connected between the floating diffusion FD2 of each pixel PX221 and PX223. The circuit configuration of each pixel PX221 and PX223 is the same as the circuit configuration of each pixel PX12 in Figure 5.

[0215] Here, each pixel PX221 and PX223 is separated between the floating diffusion FD1 and the amplification transistor 124. At this time, the configuration of each pixel PX221 and PX223 on the floating diffusion FD1 side can be mounted on the pixel chip PXB1 in Figure 30, and the configuration of each pixel PX221 and PX223 on the amplification transistor 124 side can be mounted on the pixel chip PXB2 in Figure 30. The floating diffusion FD1 and the amplification transistor 124 can be joined by a Cu-Cu junction via junction electrodes D21 and D22.

[0216] Figure 39 is a block diagram showing a third example of pixel division according to the sixteenth embodiment.

[0217] In the figure, a series circuit of binning transistors WD1 and WD3 is connected between the floating diffusion FD2 of each pixel PX321 and PX323. The circuit configuration of each pixel PX321 and PX323 is the same as the circuit configuration of each pixel PX12 in Figure 5.

[0218] Here, each pixel PX321 and PX323 is separated between the floating diffusion FD2 and each binning transistor WD1 and WD3. At this time, the configuration of each pixel PX321 and PX323 on the floating diffusion FD2 side can be mounted on the pixel chip PXB1 in Figure 30, and the configuration of each pixel PX321 and PX323 on the binning transistor WD1 and WD3 side can be mounted on the pixel chip PXB2 in Figure 30. The floating diffusion FD2 and each binning transistor WD1 and WD3 of each pixel PX321 and PX323 can be joined by a Cu-Cu junction via junction electrodes D31 and D32.

[0219] Figure 40 is a block diagram showing a fourth example of pixel division according to the sixteenth embodiment.

[0220] In the figure, a series circuit of binning transistors WD1 and WD3 is connected between the floating diffusion FD2 of each pixel PX421 and PX423. The circuit configuration of each pixel PX421 and PX423 is the same as the circuit configuration of each pixel PX12 in Figure 5.

[0221] Here, each pixel PX421 and PX423 is separated between the floating diffusion FD3 and the switching transistor 127. At this time, the configuration of each pixel PX421 and PX423 on the switching transistor 127 side can be mounted on the pixel chip PXB1 in Figure 30, and the configuration of each pixel PX421 and PX423 on the floating diffusion FD3 side can be mounted on the pixel chip PXB2 in Figure 30. The floating diffusion FD3 and the switching transistor 127 can be joined by a Cu-Cu junction via junction electrodes D41 and D42.

[0222] Figure 41 is a block diagram showing a fifth example of pixel division according to the sixteenth embodiment.

[0223] In the figure, a series circuit of binning transistors WD1 and WD3 is connected between the floating diffusion FD2 of each pixel PX521 and PX523. The circuit configuration of each pixel PX521 and PX523 is the same as the circuit configuration of each pixel PX12 in Figure 5.

[0224] Here, the image is divided between each pixel PX521, PX5223, the floating diffusion FD2, and the switching transistor 126. At this time, the configuration of each pixel PX521, PX523 on the switching transistor 126 side can be mounted on the pixel chip PXB1 in Figure 30, and the configuration of each pixel PX521, PX523 on the floating diffusion FD2 side can be mounted on the pixel chip PXB2 in Figure 30. The floating diffusion FD2 and the switching transistor 126 can be joined by a Cu-Cu junction via junction electrodes D51 and D52.

[0225] Figure 42 is a block diagram showing a sixth example of pixel division according to the sixteenth embodiment.

[0226] In the figure, a series circuit of binning transistors WD1 and WD3 is connected between the floating diffusion FD2 of each pixel PX621 and PX623. The circuit configuration of each pixel PX621 and PX623 is the same as the circuit configuration of each pixel PX12 in Figure 5.

[0227] Here, each pixel PX621 and PX623 is separated between the floating diffusion FD1 and the switching transistor 126. At this time, the configuration of each pixel PX621 and PX623 on the floating diffusion FD1 side can be mounted on the pixel chip PXB1 in Figure 30, and the configuration of each pixel PX621 and PX623 on the switching transistor 126 side can be mounted on the pixel chip PXB2 in Figure 30. The floating diffusion FD1 and the switching transistor 126 can be joined by a Cu-Cu junction via junction electrodes D61 and D62.

[0228] Thus, in the 16th embodiment described above, a Cu-Cu junction is applied to a pixel that can switch between connections of any of the floating diffusion FD1 to FD3. This makes it possible to miniaturize the junctions of the pixel chips PXB1 and PXB2 while changing the row-direction and column-direction resolution during binning of the pixel signals read from multiple pixels.

[0229] In the above embodiment, binning of LOFIC pixels was used as an example, but it may also be applied to binning of pixels that do not have LOFIC. Furthermore, in the above embodiment, an example was shown in which three floating diffusion FD1 to FD3, whose connections can be switched, are provided for each pixel, but it may also be applied to binning in which two floating diffusion FD1 and FD2, whose connections can be switched, are provided for each pixel. In this case, by connecting floating diffusion FD1 and FD2, it can be set to LCG, and by disconnecting floating diffusion FD1 and FD2, it can be set to HCG. Alternatively, it may also be applied to binning in which one floating diffusion FD1 is provided for each pixel.

[0230] <17. Seventeenth Embodiment> In the first embodiment described above, the connection of any of the floating diffusion FD1 to FD3 was switched between the row direction and the column direction between a plurality of pixels PX1 to PX4. In this seventeenth embodiment, semiconductor chips are stacked, each having a pixel array section in which pixels are arranged in a matrix.

[0231] Figure 43 is a perspective view showing an example of stacking of pixel arrays according to the 17th embodiment.

[0232] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. Semiconductor chip 922 is stacked on semiconductor chip 921.

[0233] A pixel array section 923 is formed on the semiconductor chip 922. Pixels 931 are arranged in a matrix in the row and column directions within the pixel array section 923. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922, enabling electrical connection between the semiconductor chips 921 and 922.

[0234] A peripheral circuit 924 is formed on the semiconductor chip 921. The peripheral circuit 924 includes a column readout circuit 925, a column ADC 926, a communication interface 927, and a control circuit 928. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. The pixel array section 923 may be provided with any of the pixel arrays and pixels of the first to tenth embodiments described above.

[0235] The semiconductor chips 921 and 922 may be directly bonded. Hybrid bonding can be used for the direct bonding of the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu connections. The semiconductor substrate material used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0236] As described above, in the 17th embodiment, the semiconductor chip 922 on which the pixel array 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0237] <18. Examples of Application to Mobile Devices> The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0238] Figure 44 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0239] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 44, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0240] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0241] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0242] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0243] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0244] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0245] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0246] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0247] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0248] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 44, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0249] Figure 45 shows an example of the installation position of the imaging unit 12031.

[0250] In Figure 45, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0251] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0252] Figure 45 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0253] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0254] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0255] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0256] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0257] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, for example, each imaging device of the above embodiment can be applied to the imaging unit 12031. By applying the technology of this disclosure to the vehicle control system 12000, the resolution, frame rate, image quality, and dynamic range can be changed according to the application, such as imaging, illumination detection, and motion detection, and the performance of the imaging unit 12031 can be improved according to the application.

[0258] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0259] Furthermore, this technology can also take the following configurations: (1) An imaging device comprising: a plurality of pixels each provided with a photoelectric conversion unit; a plurality of floating diffusions to which the charge photoelectrically converted by the photoelectric conversion unit is transferred; a switching transistor for switching the connections of the plurality of floating diffusions within the pixel; and a binning transistor for switching the connections of the plurality of floating diffusions between the plurality of pixels. (2) The imaging device according to (1), further comprising a LOFIC (Lateral Overflow Integration Capacitor) for accumulating the charge overflowed from the photoelectric conversion unit. (3) The imaging device according to (1), further comprising a pixel array unit in which the pixels are arranged in a matrix in the row direction and the column direction, wherein the binning transistor comprises a first binning transistor for switching the connections of floating diffusions of adjacent pixels in the column direction and a second binning transistor for switching the connections of floating diffusions of adjacent pixels in the row direction. (4) The imaging device according to (3), wherein the first binning transistor is shared by a plurality of adjacent pixels in the row direction. (5) The imaging apparatus according to (3) or (4), further comprising a third binning transistor for switching the connection of floating diffusions of non-adjacent pixels located in the same row. (6) The imaging apparatus according to any one of (3) to (5), wherein the second binning transistor is provided for each pixel. (7) The imaging apparatus according to any one of (1) to (7), wherein the floating diffusion comprises a first floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred, and a second floating diffusion connected to the first floating diffusion via the switching transistor. (8) The imaging apparatus according to (7), wherein the binning transistor switches the connection of the first floating diffusion between the plurality of pixels. (9) The imaging apparatus according to (7), wherein the binning transistor switches the connection of the second floating diffusion between the plurality of pixels.(10) The imaging apparatus according to any one of (1) to (9), wherein the floating diffusion comprises a first floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred, a second floating diffusion connected to the first floating diffusion, and a third floating diffusion connected to the second floating diffusion, and the switching transistor comprises a first switching transistor for switching the connection between the first floating diffusion and the second floating diffusion, and a second switching transistor for switching the connection between the second floating diffusion and the third floating diffusion. (11) The imaging apparatus according to (10), wherein the binning transistor switches the connection of the first floating diffusion between the plurality of pixels. (12) The imaging apparatus according to (10), wherein the binning transistor switches the connection of the second floating diffusion between the plurality of pixels. (13) The imaging apparatus according to (10), wherein the binning transistor switches the connection of the third floating diffusion between the plurality of pixels. (14) The imaging apparatus according to any one of (1) to (13), further comprising a reset transistor for resetting the floating diffusion. (15) The imaging apparatus according to (14), wherein the reset transistor is shared by the plurality of pixels. (16) The imaging apparatus according to any one of (1) to (15), further comprising a transfer transistor for transferring the charge accumulated in the photoelectric conversion unit to the floating diffusion, an amplification transistor for outputting a pixel signal based on the potential of the floating diffusion, and a selection transistor for selecting the output of the amplification transistor. (17) The imaging apparatus according to any one of (1) to (16), further comprising an overflow control transistor for controlling the overflow of the charge from the photoelectric conversion unit to the floating diffusion.(18) An imaging apparatus comprising: a pixel array portion in which pixels are arranged in a matrix in the row direction and column direction; a reset transistor provided for each pixel for resetting the floating diffusion of the pixel; and a first binning transistor for switching the connection of the floating diffusion of adjacent pixels in the column direction. (19) The imaging apparatus according to (18), wherein the first binning transistor is shared by a plurality of adjacent pixels in the row direction. (20) The imaging apparatus according to (18) or (19), further comprising a second binning transistor provided for each pixel for switching the connection of the floating diffusion of adjacent pixels in the row direction.

[0260] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Storage unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column reading circuit 114 Column signal processing unit 114A Column ADC unit 115 Horizontal scanning circuit 116 Control circuit PX Pixel HCL Horizontal drive line VSL Vertical signal line WV1 to WV3, WD1 to WD4 Binning transistor PD Photodiode FD1 to FD3 Floating diffusion 122 Transfer transistor 123 Reset transistor 124 Amplifier transistor 125 Selection transistor 126, 127 Switching transistor

Claims

1. An imaging device comprising: a plurality of pixels, each provided with a photoelectric conversion unit; a plurality of floating diffusions to which the charge photoelectrically converted by the photoelectric conversion unit is transferred; a switching transistor for switching the connections of the plurality of floating diffusions within the pixel; and a binning transistor for switching the connections of the plurality of floating diffusions between the plurality of pixels.

2. The imaging apparatus according to claim 1, further comprising a LOFIC (Lateral Overflow Integration Capacitor) for accumulating the charge overflowed from the photoelectric conversion unit.

3. The imaging apparatus according to claim 1, comprising a pixel array portion in which the pixels are arranged in a matrix in the row direction and the column direction, wherein the binning transistors include a first binning transistor that switches the connection of floating diffusion between adjacent pixels in the column direction and a second binning transistor that switches the connection of floating diffusion between adjacent pixels in the row direction.

4. The imaging apparatus according to claim 3, wherein the first binning transistor is shared by a plurality of pixels adjacent to each other in the row direction.

5. The imaging apparatus according to claim 3, further comprising a third binning transistor for switching the connection of floating diffusion of non-adjacent pixels located in the same row.

6. The imaging apparatus according to claim 3, wherein the second binning transistor is provided for each pixel.

7. The imaging apparatus according to claim 1, wherein the floating diffusion comprises a first floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred, and a second floating diffusion connected to the first floating diffusion via the switching transistor.

8. The imaging apparatus according to claim 7, wherein the binning transistor switches the connection of the first floating diffusion between the plurality of pixels.

9. The imaging apparatus according to claim 7, wherein the binning transistor switches the connection of the second floating diffusion between the plurality of pixels.

10. The imaging apparatus according to claim 1, wherein the floating diffusion comprises a first floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred, a second floating diffusion connected to the first floating diffusion, and a third floating diffusion connected to the second floating diffusion, and the switching transistor comprises a first switching transistor for switching the connection between the first floating diffusion and the second floating diffusion, and a second switching transistor for switching the connection between the second floating diffusion and the third floating diffusion.

11. The imaging apparatus according to claim 10, wherein the binning transistor switches the connection of the first floating diffusion between the plurality of pixels.

12. The imaging apparatus according to claim 10, wherein the binning transistor switches the connection of the second floating diffusion between the plurality of pixels.

13. The imaging apparatus according to claim 10, wherein the binning transistor switches the connection of the third floating diffusion between the plurality of pixels.

14. The imaging apparatus according to claim 1, further comprising a reset transistor for resetting the floating diffusion.

15. The imaging apparatus according to claim 14, wherein the reset transistor is shared by the plurality of pixels.

16. The imaging apparatus according to claim 1, comprising: a transfer transistor for transferring the charge accumulated in the photoelectric conversion unit to the floating diffusion; an amplification transistor for outputting a pixel signal based on the potential of the floating diffusion; and a selection transistor for selecting the output of the amplification transistor.

17. The imaging apparatus according to claim 1, further comprising an overflow control transistor for controlling the overflow of the charge from the photoelectric conversion unit to the floating diffusion.

18. An imaging apparatus comprising: a pixel array section in which pixels are arranged in a matrix in the row direction and column direction; a reset transistor provided for each pixel for resetting the floating diffusion of the pixel; and a first binning transistor for switching the connection of the floating diffusion of adjacent pixels in the column direction.

19. The imaging apparatus according to claim 18, wherein the first binning transistor is shared by a plurality of pixels adjacent in the row direction.

20. The imaging apparatus according to claim 18, further comprising a second binning transistor provided for each pixel, which switches the connection of the floating diffusion of adjacent pixels in the row direction.

Images