Wireless communication device and method

Abstract

Millimeter wave (mmWave) technologies, devices, and methods related to transceivers, receivers, and antenna structures for wireless communications are described. Various aspects include collocated millimeter wave (mmWave) antennas and near field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication systems with MIMO support and phase noise synchronization on a single coaxial cable, passing RF signals over cable (RFoC) in distributed phased array communication systems, clock noise leakage reduction, IF to RF auxiliary chips for backward and forward compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architectures, and the like.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from the following provisional patent applications:

[0003] U.S. Provisional Patent Application Serial No. 62 / 437,385, entitled “MILLIMETER WAVE ANTENNA STRUCTURES,” filed on December 21, 2016;

[0004] U.S. Provisional Patent Application Serial No. 62 / 511,398, entitled “MILLIMETER WAVE TECHNOLOGY,” filed May 26, 2017;

[0005] U.S. Provisional Patent Application Serial No. 62 / 527,818, entitled “ANTENNA CIRCUITS AND TRANSCEIVERS FOR MILLIMETER WAVE (MMWAVE) COMMUNICATIONS,” filed on June 30, 2017; and

[0006] U.S. Provisional Patent Application Serial No. 62 / 570,680, entitled “RADIO FREQUENCY TECHNOLOGIES FOR WIRELESS COMMUNICATIONS,” filed on October 11, 2017.

[0007] Each of the above-referenced provisional patent applications is incorporated herein by reference in its entirety. Technical Field

[0008] Some aspects of the disclosure pertain to antennas and antenna structures. Some aspects of the disclosure pertain to antennas and antenna structures for millimeter wave communications. Some aspects of the disclosure pertain to wireless communication devices (e.g., mobile devices and base stations) that use antennas and antenna structures to transmit wireless signals. Some aspects of the disclosure pertain to devices that operate according to a 5th generation (5G) wireless system. Some aspects of the disclosure pertain to devices that operate according to a Wireless Gigabit Alliance (WiGig) (e.g., IEEE 802.11ad) protocol. Some aspects of the disclosure pertain to the use of multi-level copper pillar etching. Some aspects of the disclosure pertain to co-located millimeter wave (mmWave) antennas and near field communication (NFC) antennas. Some aspects of the disclosure pertain to a scalable phased array radio transceiver architecture (SPARTA). Some aspects of the disclosure pertain to a phased array distributed communication system with MIMO support and phase noise synchronization on a single coaxial cable. Some aspects of the disclosure pertain to transmitting radio frequency (RF) signals on cables (RFoC) in a distributed phased array communication system. Some aspects of the disclosure pertain to clock noise leakage reduction. Some aspects of the disclosure relate to an intermediate frequency (IF) to RF auxiliary chip for backward and forward compatibility and modularity. Some aspects of the disclosure relate to on-package matching networks. Some aspects of the disclosure relate to a 5G scalable receiver (Rx) architecture. Background Art

[0009] Physical space in mobile devices used for wireless communications is often at a premium due to the amount of functionality included in the form factor of these devices. Challenging problems arise due to the need for spatial coverage of the radiated radio waves, as well as maintaining signal strength as the mobile device moves to different places, or the user may orient the mobile device differently over time. This may result in the need for a large number of antennas, different polarities of the radiated radio waves at different times, radiation directions, different spatial diversity, and related requirements in some aspects. When designing a package that includes antennas that operate at millimeter wave (mmWave or mmW) frequencies, efficient use of space can help address these issues.

[0010] The ubiquity of wireless communications has continued to raise numerous challenging problems. In particular, the challenges have evolved with the advent of mobile communication systems (e.g., 5G communication systems) due to the diversity of devices with different requirements and the spectrum to be used. In particular, the range of frequency bands used in communications has increased, most recently due to carrier aggregation that combines licensed and unlicensed bands and the upcoming use of mmWave bands.

[0011] The challenge in mmWave radio front-end modules (RFEM) is to provide complete or near-complete directional coverage. Millimeter wave systems require high antenna gain to approach the link budget, and phased array antennas can be used to provide beam steering. However, the use of phased array antennas (e.g., planar patch antenna arrays) by themselves provides limited angular coverage. Although beam steering can help direct energy toward the intended receiver (and at the receiver, reciprocally increase gain in the direction of the intended transmitter), simple arrays limit the coverage of the steering angle. In addition, for mmWave, the polarization of the radio frequency (RF) signal is a major issue. There are significant propagation differences between vertical and horizontal polarizations, and in addition, the use of these two polarizations can be used to provide spatial diversity. Considering that the technology is expected to be applied to mobile devices, it will become important to provide selectable polarization in the antenna.

[0012] Another issue of growing concern is atmospheric attenuation losses. Due to high path loss due to atmospheric absorption and high attenuation through solid materials, massive multiple-input multiple-output (MIMO) systems can be used for communications in the mmWave band. The use of beamforming to search for unobstructed directional spatial channels and the differences between line-of-sight (LOS) and non-line-of-sight (NLOS) communications can make mmWave architectures complex compared to architectures used for communications over wireless personal area networks (WPANs) or wireless local area networks (WLANs). BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A An exemplary user device is shown in accordance with some aspects.

[0014] Figure 1B Show that according to some aspects can be combined Figure 1A The devices use the mmWave system.

[0015] Figure 2 An exemplary base station radio head is shown in accordance with some aspects.

[0016] Figure 3A Exemplary millimeter wave communication circuits are shown in accordance with some aspects.

[0017] Figure 3B Showing some aspects Figure 3A Aspects of exemplary transmit circuitry are shown.

[0018] Figure 3C Showing some aspects Figure 3A Aspects of exemplary transmit circuitry are shown.

[0019] Figure 3D Showing some aspects Figure 3A Aspects of exemplary RF circuits are shown.

[0020] Figure 3E Showing some aspects Figure 3A Aspects of an exemplary receive circuit are shown.

[0021] Figure 4 Showing some aspects Figure 3A An exemplary RF circuit that may be used is shown in FIG.

[0022] Figure 5A Aspects of an exemplary radio front end module (RFEM) according to some aspects are shown.

[0023] Figure 5B Alternative aspects of an exemplary radio front end module according to some aspects are shown.

[0024] Figure 6 FIG. 1 or FIG. 2 shows a schematic diagram of a method according to some aspects of the present invention. Figure 2 An exemplary multi-protocol baseband processor that can be used in.

[0025] Figure 7 An exemplary mixed-signal baseband subsystem is shown in accordance with some aspects.

[0026] Fig. 8A An exemplary digital baseband subsystem is shown in accordance with some aspects.

[0027] Figure 8B Alternative aspects of an exemplary baseband processing subsystem in accordance with some aspects are shown.

[0028] Fig. 9 An exemplary digital signal processor subsystem is shown in accordance with some aspects.

[0029] Fig. 10A An example of an accelerator subsystem in accordance with some aspects is shown.

[0030] Fig. 10B An alternative exemplary accelerator subsystem is shown in accordance with some aspects.

[0031] FIG. 11A to FIG. 11E

[0013] An example periodic radio frame structure is shown in accordance with some aspects.

[0032] FIG. 12A to FIG. 12C

[0026] An example of a constellation design for a single carrier modulation scheme that may be transmitted or received in accordance with some aspects is shown.

[0033] Fig.13A and Fig. 13B

[0026] Alternative exemplary constellation designs are shown for single carrier modulation schemes that can be transmitted and received in accordance with some aspects.

[0034] Fig.14

[0013] An example system for generating a multi-carrier baseband signal for transmission according to some aspects is shown.

[0035] Fig.15 Shown are example resource elements depicted in grid form according to some aspects.

[0036] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D An example of encoding according to some aspects is shown.

[0037] Fig.17 are cross-sectional and top views of an exemplary semiconductor die with metal pillars according to some aspects.

[0038] Fig.18A are cross-sectional and top views of an exemplary semiconductor die having metal pillars forming a first type of interconnect structure according to some aspects.

[0039] Fig.18B are cross-sectional and top views of an exemplary semiconductor die having metal pillars forming a second type of interconnect structure according to some aspects.

[0040] Fig.18C are cross-sectional and top views of an exemplary semiconductor die having metal pillars forming a third type of interconnect structure according to some aspects.

[0041] Fig.19 is a cross-sectional view of an exemplary semiconductor die having metallic pillars forming an interconnect structure, wherein the pillars are attached to a package stack, according to some aspects.

[0042] Fig. 20A is a side view of an exemplary user equipment subsystem described in the present disclosure, illustrated in cross-section, in accordance with some aspects.

[0043] Fig. 20B Showing some aspects Fig. 20A An exemplary base portion of a stacked structure.

[0044] Fig.21 Showing some aspects Fig. 20A An exemplary RF feed inside a cavity of a stacked structure.

[0045] Fig. 22 An exemplary RF feed trace is shown passing through an opening in a shielding cage in accordance with some aspects.

[0046] Fig.23 Several views of an exemplary semiconductor package with a juxtaposed millimeter wave (mmWave) antenna and a near field communication (NFC) antenna are shown according to some aspects.

[0047] Fig.24 An exemplary radio frequency front end module (RFEM) with a phased antenna array according to some aspects is shown.

[0048] Fig.25 Shown is an example position of an exemplary RFEM in a mobile device according to some aspects.

[0049] Fig.26 is a block diagram of an exemplary RFEM program according to some aspects.

[0050] Fig. 27 is a block diagram of an example medium access control (MAC) / baseband (BB) subsystem in accordance with some aspects.

[0051] Fig.28 is a diagram of an example NFC antenna implementation according to some aspects.

[0052] Fig.29 Several views of an exemplary semiconductor package with juxtaposed mmWave antennas and near field communication (NFC) antennas on multiple printed circuit board (PCB) substrates are shown in accordance with some aspects.

[0053] Fig.30 is a block diagram of an exemplary RF phased array system that implements beamforming by phase shifting and combining signals at RF in accordance with some aspects.

[0054] Fig.31 is a block diagram of an example phased array system that implements beamforming by phase shifting a local oscillator (LO) and combining analog signals at IF / baseband in accordance with some aspects.

[0055] Fig.32 is a block diagram of an exemplary phased array with digital phase shifting and combining according to some aspects.

[0056] Fig.33 is a block diagram of an exemplary transceiver cell element that may be used in a scalable phased array radio transceiver architecture in accordance with some aspects.

[0057] Fig.34 is a block diagram of an exemplary phased array radio transceiver architecture using multiple transceiver cells according to some aspects.

[0058] Fig.35 An exemplary dicing of a semiconductor die into individual transceiver cells forming a phased array radio transceiver is shown in accordance with some aspects.

[0059] Fig.36is a block diagram of an exemplary phased array radio transceiver architecture packaged with a phased array antenna according to some aspects.

[0060] Fig.37 is a block diagram of an exemplary transceiver small unit with a communication bus according to some aspects.

[0061] Fig.38 is a block diagram of an example phased array transceiver architecture using a single analog-to-digital converter (ADC) in an LO phase-shifted mode of operation for a transceiver tile according to some aspects.

[0062] Fig.39 is a block diagram of an example phased array transceiver architecture using multiple ADCs in a LO phase-shifted mode of operation of a transceiver tile according to some aspects.

[0063] Fig.40 is a block diagram of an exemplary phased array transceiver architecture in which a transceiver tile uses multiple ADCs in a hybrid operating mode (LO and digital phase shifting and combining) to generate multiple digital signals in accordance with some aspects.

[0064] Fig.41 is a block diagram of an exemplary phased array transceiver architecture using a single ADC in an analog IF / baseband phase shift and combining mode of operation for a transceiver tile according to some aspects.

[0065] Fig.42 is a block diagram of an exemplary phased array transceiver architecture in which a transceiver tile uses multiple ADCs to generate multiple digital signals in an analog IF / baseband phase-shifted mode of operation according to some aspects.

[0066] Fig.43 Exemplary operating modes of a phased array transceiver architecture with transceiver tiles according to some aspects are shown.

[0067] Fig.44A A top view of an exemplary substrate of one package of a dual package system is shown according to some aspects.

[0068] Fig.44B Showing some aspects Fig.44A Bottom view of the substrate.

[0069] Fig.44C Showing some aspects Fig.44A and Fig.44B 1 is a bottom view of an exemplary substrate of a second package of a dual package system.

[0070] Fig.44D FIG. 1 shows stacked in a package-on-package implementation according to some aspects. FIG. 44A to FIG. 44CA first package and a second package.

[0071] Fig.45A A top view of another exemplary substrate of one package of another dual package system is shown in accordance with some aspects.

[0072] Fig.45B Showing some aspects Fig.45A Bottom view of the substrate.

[0073] Fig.45C Showing some aspects Fig.45A and Fig.45B 1 is a bottom view of an exemplary substrate of a second package of a dual package system.

[0074] Fig.45D FIG. 1 shows a stacked package in a package-on-package implementation according to some aspects. FIG. 45A to FIG. 45C A first package and a second package.

[0075] Fig.46A A top view of an exemplary substrate of one package of yet another dual package system is shown in accordance with some aspects.

[0076] Fig.46B Showing some aspects Fig.45A Bottom view of the substrate.

[0077] Fig.46C Showing some aspects Fig.45A and Fig.45B A bottom view of an exemplary substrate of a second package of a dual package system;

[0078] Fig.46D FIG. 1 shows a stacked package in a package-on-package implementation according to some aspects. FIG. 46A to FIG. 46C A first package and a second package.

[0079] Fig.47A A top view of an exemplary substrate of one package of yet another dual packaging system is shown according to some aspects.

[0080] Fig.47B Showing some aspects Fig.46A Bottom view of the substrate.

[0081] Fig.47C Showing some aspects Fig.47A and Fig.47B 1 is a bottom view of an exemplary substrate of a second package of a dual package system.

[0082] Fig.47D FIG. 1 shows a stacked package in a package-on-package implementation according to some aspects. FIG. 44A to FIG. 44C A first package and a second package.

[0083] Fig.48A Shown is a top view of two packages of a dual package side-by-side packaging system in accordance with some aspects.

[0084] Fig.48B Showing some aspects Fig.48A Bottom view of the two packages.

[0085] Fig.48C Shown in a side-by-side implementation according to some aspects Fig.48A and Fig.48B Side view of two packages.

[0086] Fig.49 is an exemplary illustration of various sizes of SD flash memory cards.

[0087] Fig.50 A three-dimensional view of an exemplary Micro SD card is shown with content and functionality altered in accordance with certain aspects to modify the card for mmWave wireless communication operations.

[0088] Fig.51A Showing some aspects of the Figure 2 The radiation pattern of a dipole antenna Fig.50 An exemplary MicroSD card is shown.

[0089] Fig.51B FIG. 1 shows a vertically polarized monopole antenna element having a Z-height limited vertically positioned in an exposed area according to some aspects. Fig.50 Micro SD card.

[0090] Fig.51C A device having a folded dipole antenna according to some aspects is shown. Fig.50 Micro SD card.

[0091] Fig.52 Three exemplary MicroSD cards are shown modified as described above to provide multiple cards per motherboard in accordance with some aspects.

[0092] Fig.53A is a side view of an exemplary split ball grid array (BGA) or land grid array (LGA) pattern package PCB subsystem with an attached transceiver subsystem according to some aspects.

[0093] Fig.53B Based on some aspects Fig.53A Side view cross section of a subsystem.

[0094] Fig.53CFIG. 1 is a diagram showing a top view of a shield and also showing a cutaway portion according to some aspects. Fig.53A Top view of the subsystem.

[0095] Fig.53D FIG. 1 is a diagram showing a cutout portion for enabling an antenna to radiate and showing contacts according to some aspects Fig.53A Top view of the subsystem.

[0096] Fig.53E An arrangement of exemplary subsystems arranged in a circular fashion around a pole for radiation coverage in substantially all directions in accordance with some aspects is shown.

[0097] Fig.53F An exemplary subsystem of a corner shape is shown according to some aspects.

[0098] Figure 53G Showing some aspects Figure 3A subsystem.

[0099] Fig.53H A side view of an exemplary antenna subsystem is shown in accordance with some aspects.

[0100] Fig.53I A top view of an exemplary configuration of a dual shield antenna subsystem is shown in accordance with some aspects.

[0101] Fig.53J Showing some aspects Fig.53I Side view of the antenna subsystem.

[0102] Fig.54A An exemplary 60 GHz phased array system-in-package (SIP) is shown in accordance with some aspects.

[0103] Fig.54B A side perspective view of an exemplary 60 GHz phased array SIP is shown in accordance with some aspects.

[0104] Fig.55 A 60 GHz SIP is shown placed on a self-tester in accordance with some aspects.

[0105] Fig.56A A test setup for a first portion of a test for addressing undesired on-die or on-package crosstalk in a SIP is shown in accordance with some aspects.

[0106] Fig.56B An exemplary test setup for a second portion of testing for addressing undesired on-die or on-package crosstalk in a SIP is shown in accordance with some aspects.

[0107] Fig.57An exemplary automated test rig suitable for testing a 60 GHz phased array SIP is shown in accordance with some aspects.

[0108] Fig.58 Showing some aspects to be added to Fig.57 Example components of automated test equipment.

[0109] Fig.59 An exemplary RF front end module (RFEM) of a distributed phased array system is shown in accordance with some aspects.

[0110] Fig.60 An exemplary baseband subsystem (BBS) of a distributed phased array system is shown in accordance with some aspects.

[0111] Fig.61 Shown is an exemplary distributed phased array system with MIMO support and multiple coaxial cables coupled to a single RFEM in accordance with some aspects.

[0112] Fig.62 An exemplary distributed phased array system with MIMO support is shown, wherein each RFEM transceiver is coupled to a separate coaxial cable, according to some aspects.

[0113] Fig.63 An exemplary distributed phased array system with MIMO support and a single coaxial cable coupled to a single RFEM is shown in accordance with some aspects.

[0114] Fig.64 Exemplary spectral content of various signals conveyed over the single coaxial cable of FIG. 3 is shown in accordance with some aspects.

[0115] Fig.65 An exemplary distributed phased array system with a single BBS and multiple RFEMs is shown, supporting MIMO support and having a single coaxial cable between the BBS and each RFEM, according to some aspects.

[0116] Fig.66 An exemplary RF front end module (RFEM) of a distributed phased array system is shown in accordance with some aspects.

[0117] Fig.67 An exemplary baseband subsystem (BBS) of a distributed phased array system is shown in accordance with some aspects.

[0118] Fig.68 An exemplary frequency diagram showing a signal transmitted between RFEM and a BBS according to some aspects.

[0119] Fig.69An exemplary RFEM is shown coupled to an exemplary BBS via a single coaxial cable for communicating RF signals in accordance with some aspects.

[0120] Fig.70 Showing some aspects Fig.69 A more detailed diagram of the BBS.

[0121] Fig.71 An exemplary massive antenna array (MAA) using multiple RFEMs coupled to a single BBS is shown in accordance with some aspects.

[0122] Fig.72 is an exploded view of a laptop computer showing an exemplary waveguide for RF signals to reach a cover of the laptop computer, according to some aspects.

[0123] Fig.73 An illustration of one or more exemplary coaxial cables routed from a laptop computer's radio subsystem, through a cover of the laptop device, and through a hole in a hinge of the laptop device, according to some aspects.

[0124] Fig.74 An illustration of one or more exemplary coaxial cables from a laptop computer's radio subsystem exiting a hole in a hinge of a laptop cover, passing through an antenna or antenna array in the cover, according to some aspects.

[0125] Fig.75 is a schematic diagram of an exemplary transmission line for a signal from a motherboard of a laptop computer to a cover of the laptop device and to a radio front end module (RFEM) according to some aspects.

[0126] Fig.76 is a schematic diagram of an exemplary transmission line for a signal from a laptop computer's motherboard to a cover of the laptop and to a plurality of RFEMs in accordance with some aspects.

[0127] Fig.77A and Fig.77B is an illustration of an exemplary substrate integrated waveguide (SIW) according to some aspects.

[0128] Fig.78 An exemplary RF front end module (RFEM) of a distributed phased array system with reduced clock noise leakage according to some aspects is shown.

[0129] Fig.79 An exemplary baseband subsystem (BBS) of a distributed phased array system with reduced clock noise leakage according to some aspects is shown.

[0130] Fig.80An exemplary frequency diagram showing a signal transmitted between RFEM and a BBS according to some aspects.

[0131] Fig.81 Clock spreader and despreader circuits that may be used in conjunction with clock noise leakage reduction according to some aspects are shown.

[0132] Fig.82 A frequency graph showing a signal transmitted between RFEM and BBS using clock noise leakage reduction according to some aspects.

[0133] Fig.83 An exemplary RF front end module (RFEM) of a distributed phased array system with IF processing according to some aspects is shown.

[0134] Fig.84 Showing some aspects Fig.83 An exemplary baseband subsystem (BBS) for a distributed phased array system.

[0135] Fig.85 Shown is an exemplary multi-band distributed phased array system with IF processing in RFEM according to some aspects.

[0136] Fig.86 An exemplary distributed phased array system is shown having an RFEM coupled to a BBS via a single coaxial cable for communicating RF signals in accordance with some aspects.

[0137] Fig.87 Showing some aspects Fig.86 A more detailed diagram of the BBS.

[0138] Fig.88 An exemplary distributed phased array system supporting multiple operating frequency bands using multiple RFEMs coupled to a single BBS in accordance with some aspects is shown.

[0139] Fig.89 Showing some aspects Fig.88 A more detailed diagram of the BBS.

[0140] Fig.90 An exemplary distributed phased array system including RFEM, a companion chip, and a BBS is shown, wherein IF processing is offloaded to the companion chip, according to some aspects.

[0141] Fig.91 Showing some aspects Fig.90 A more detailed diagram of the auxiliary chip and BBS.

[0142] Fig.92 An exemplary multi-band distributed phased array system with IF processing in a companion chip according to some aspects is shown.

[0143] Fig.93 An exemplary on-chip implementation of a two-way power combiner according to some aspects is shown.

[0144] Fig.94 An exemplary on-chip implementation of a large power combiner according to some aspects is shown.

[0145] Fig.95 An exemplary on-chip implementation of an impedance transformation network according to some aspects is shown.

[0146] Fig.96 An exemplary on-package implementation of a two-way power combiner according to some aspects is shown.

[0147] Fig.97 An exemplary on-package implementation of a large power combiner according to some aspects is shown.

[0148] Fig.98 An exemplary on-package implementation of an impedance transformation network according to some aspects is shown.

[0149] Fig.99 An exemplary on-package implementation of a Doherty power amplifier according to some aspects is shown.

[0150] Fig.100A is a side view of an exemplary moldless stacked package-on-package embedded die radio system using a connector according to some aspects.

[0151] Fig.100B is a side view of an exemplary dual patch antenna using a connector according to some aspects.

[0152] Fig.100C It is based on some aspects as the size of the antenna increases. Fig.100B Simulation graph of the return loss of the dual-patch antenna.

[0153] Fig.101A is a side view of an exemplary moldless stacked package-on-package embedded die radio system using flex interconnects according to some aspects.

[0154] Fig.101B is a side view of a moldless stacked package-on-package embedded die radio system using a flex interconnect, wherein the flex interconnect is shown in a photographic representation, according to some aspects.

[0155] Fig.102 is a side view of an exemplary molded-on-package embedded die radio system according to some aspects.

[0156] Fig.103is a side view of an exemplary molded-on-package embedded die radio system according to some aspects.

[0157] Fig.104 is a side view of a stacked package embedded die radio system using a redistribution layer according to some aspects.

[0158] Fig.105 is a side view of a molded-on-package embedded die radio system having recesses in a molding layer to gain height in the z-direction according to some aspects.

[0159] Fig.106 is a side view of a molded-on-package embedded die radio system including a mechanical shield embedded in a mold for EMI shielding and for heat spreading according to some aspects.

[0160] Fig.107 is a perspective view of an exemplary stacked ultra-thin system in a packaged radio system with a laterally positioned antenna or antenna array according to some aspects.

[0161] Figures 108A to 108C An exemplary embedded die package according to some aspects is shown.

[0162] Fig.109 Block diagram illustrating a side view of an exemplary stacked ring resonator (SRR) antenna package cell for use in accordance with some aspects.

[0163] Fig.110 It is shown that according to some aspects, it can be used in Fig.109 An exemplary ring resonator in one or more layers of an antenna package small unit.

[0164] Fig.111 It is shown that according to some aspects, it can be used in Fig.109 An exemplary ring resonator having multiple feed lines using different polarizations in one or more layers of an antenna package cell.

[0165] Fig.112 Showing some aspects Fig.109 Example electric field lines in the E-plane of the SRR antenna.

[0166] Fig.113 Based on some aspects Fig.109 An exemplary graphical representation of the reflection coefficient and boresight achieved gain of a small element of an SRR antenna package.

[0167] Fig.114 Showing the use according to some aspects Fig.109 Block diagram of an exemplary antenna array of an SRR antenna package small unit.

[0168] Fig.115 Showing the composition according to some aspects Fig.109 An exemplary SRR antenna encapsulates an exemplary set of layers of a small unit.

[0169] Fig.116 Showing some aspects Fig.109 Block diagram of an exemplary stack-up of an SRR antenna package small unit.

[0170] Fig.117 According to some aspects, it is shown that Fig.109 Block diagram of multiple exemplary strip lines of the SRR antenna package small unit feed line.

[0171] Fig.118A An exemplary mobile device utilizing multiple waveguide antennas in accordance with some aspects is shown.

[0172] Fig.118B An exemplary radio frequency front end module (RFEM) having a waveguide transition element according to some aspects is shown.

[0173] Fig.119A and Fig.119B A perspective view of an exemplary waveguide structure for transitioning between a PCB and a waveguide antenna is shown in accordance with some aspects.

[0174] Fig.120A , Fig.120B and Fig.120C Showing some aspects Figure 119A-119B Various cross-sectional views of the waveguide transition structure.

[0175] Fig.121A , Fig.121B and Fig.121C An exemplary impedance matching air cavity is shown according to some aspects. Figure 119A-119B Various perspective views of the waveguide transition structure.

[0176] Fig.122 Showing that according to some aspects Figure 119A-119B Another view of the air cavity when the waveguide transition structure is mounted with the PCB and waveguide.

[0177] Fig.123 A graphical representation of simulation results showing reflection coefficient values ​​as a function of air gap width according to some aspects.

[0178] Fig.124 An exemplary dual polarization antenna structure is shown in accordance with some aspects.

[0179] Figures 125A to 125CAn exemplary dual polarized antenna structure implemented on a multi-layer PCB is shown in accordance with some aspects.

[0180] Fig.126 Showing some aspects Figures 125A to 125C Simulated S-parameters of the antenna structure are shown.

[0181] Fig.127A and Fig.127B Showing some aspects Figures 125A to 125C Example simulated far-field radiation patterns of the antenna structure shown.

[0182] Fig.128A A schematic diagram showing a surface wave hole having surface wave holes drilled in one configuration according to some aspects Figures 125A to 125C Top view of the antenna structure.

[0183] Fig.128B FIG. 1 shows a surface wave hole having been drilled in another configuration according to some aspects. Figures 125A to 125C Top view of the antenna structure.

[0184] Fig.129 Alternative implementations of exemplary dual polarization antenna structures in accordance with some aspects are shown.

[0185] Fig.130A Showing some aspects Fig.129 Top view of the antenna.

[0186] Fig.130B and Fig.130C Based on some aspects Fig.129 Perspective view of the antenna.

[0187] Fig.131A Showing some aspects of FIG. 130A to FIG. 130C Simulation of the relationship between the total radiation efficiency and frequency of the antenna structure.

[0188] Fig.131B Showing some aspects FIG. 130A to FIG. 130C Top view of an exemplary 4x1 antenna array of the type shown.

[0189] Fig.131C Based on some aspects Fig.131B A perspective view of a 4x1 antenna array of the type shown.

[0190] Fig.131D and Fig.131E shows 0° phasing according to some aspects Fig.131B and Fig.131C Example simulated radiation pattern of a 4x1 antenna array.

[0191] Fig.131F and Figure 131G shows 120° phasing according to some aspects Fig.131B and Fig.131C Example simulated radiation pattern of a 4x1 antenna array.

[0192] Fig.132 Showing some aspects Fig.131B and Fig.131C An exemplary simulation of the worst-case coupling between adjacent elements of an antenna array.

[0193] Fig.133 shows a 0° phased image according to some aspects. Fig.131B and Fig.131C Envelope correction for a 4x1 antenna array.

[0194] Fig.134 A coordinate system for polar simulation radiation patterns described below is shown in accordance with some aspects.

[0195] Fig.135 An exemplary wireless electronic system is shown with a die embedded within a main substrate and shielded surface mount devices mounted on the main substrate in accordance with some aspects.

[0196] Fig.136 An exemplary wireless electronic system is shown with a die and surface mount devices placed on a primary substrate within a cavity in a secondary substrate in accordance with some aspects.

[0197] Fig.137 An exemplary radio system package is shown with a die embedded inside a primary substrate and surface mount devices placed above the primary substrate within a cavity in a secondary substrate in accordance with some aspects.

[0198] Fig.138A is a perspective cutaway view of an exemplary radio system package with a die embedded within a primary substrate and surface mount devices placed above the primary substrate within a cavity in a secondary substrate according to some aspects.

[0199] Fig.138B is a diagram showing the bottom side of the main substrate according to some aspects Fig.138A Perspective diagram of a radio system.

[0200] Fig.139 is a diagram showing the interior of the sub-base according to some aspects Fig.138A Perspective diagram of a radio system.

[0201] Fig.140A A solder contact for mechanical or electrical connection is shown according to some aspects Fig.138A Partial perspective top view of a radio system.

[0202] Fig.140B According to some aspects, solder contacts on the secondary substrate are configured to match Fig.140A The soldering contacts Fig.138A A partial perspective view of the radio system.

[0203] Fig.141A An exemplary single-element edge-fire antenna including a surface assembly attached to a PCB according to one aspect is shown.

[0204] Fig.141B According to one aspect, Fig.141A The placement and material details of the single-element antenna.

[0205] Fig.141C According to one aspect, Fig.141A and Fig.141B An end view of a single element antenna is shown.

[0206] Fig.141D According to one aspect, a Fig.141A and Fig.141B An exemplary four-antenna element array of antenna elements of the type shown.

[0207] Fig.142 Two different lengths of an extended dielectric are shown according to one aspect. Fig.141A and Fig.141B The bandwidth of the antenna is shown.

[0208] Fig.143 According to one aspect, Fig.141A and Fig.141B Overall efficiency of the antenna over the frequency range shown.

[0209] Fig.144 According to one aspect, the Fig.143 The frequency range shown is on the frequency range Fig.141A and Fig.141B The overall efficiency of the antenna is shown.

[0210] Fig.145 According to one aspect, a method for Fig.141A and Fig.141B Maximum achievable gain over the frequency range of the antenna shown.

[0211] Fig.146 According to one aspect, a method for Fig.141A and Fig.141B The maximum achieved gain of the antenna over another frequency range is shown.

[0212] Fig.147 According to one aspect, Fig.141DExemplary isolation between two adjacent antenna elements of an antenna array is shown.

[0213] Fig.148A FIG. 1 shows a first extended dielectric length according to one aspect. Fig.141A and Fig.141B An exemplary three-dimensional radiation pattern of an antenna element at a given frequency is shown.

[0214] Fig.148B FIG. 1 shows a second extended dielectric length according to one aspect. Fig.141A and Fig.141B An exemplary three-dimensional radiation pattern of an antenna element at a given frequency is shown.

[0215] Fig.148C According to one aspect, Fig.141D An exemplary three-dimensional radiation pattern at a given frequency for a four-element antenna array is shown, where each antenna element has a first extended dielectric length.

[0216] Fig.148D According to one aspect, Fig.141D An exemplary three-dimensional radiation pattern of four array antenna elements at a given frequency is shown, wherein each antenna element has a second extended dielectric length.

[0217] Fig.149 According to one aspect, Fig.141A and Fig.141B An exemplary E-plane coplanar polarized radiation pattern of an antenna element at a given frequency is shown.

[0218] Fig.150 According to one aspect, Fig.141A and Fig.141B An exemplary E-plane cross-polarized radiation pattern for the antenna shown at a given frequency.

[0219] Fig.151 According to one aspect, Fig.141A and Fig.141B An exemplary H-plane coplanar polarized radiation pattern of the antenna shown at a given frequency.

[0220] Fig.152 According to one aspect, Fig.141A and Fig.141B An exemplary H-plane cross-polarized radiation pattern of the antenna shown at a given frequency.

[0221] Fig.153A According to one aspect, Fig.141A and Fig.141B An exemplary antenna element similar to the antenna shown, in which a portion of the surface assembly is incorporated with the PCB.

[0222] Fig.153B FIG. 1 shows an example of a method for transmitting a signal with additional details showing vertically polarized and horizontally polarized feed points according to an aspect. Fig.153A The antenna elements are shown.

[0223] Fig.154A A method of manufacturing a PCB comprising two surface components on both sides of the PCB according to one aspect is shown. Fig.141A and Fig.141B The antenna shown is similar to the exemplary antenna elements.

[0224] Fig.154B Showing additional details including a close-up view of a feed line according to one aspect Fig.154A The antenna elements are shown.

[0225] Fig.155A It is based on one aspect after soldering the small surface components and the main PCB together. Fig.153B Perspective diagram of a dual polarized antenna.

[0226] Fig.155B 1. A surface assembly according to one aspect of the present invention is shown which is combined with a main PCB. Fig.155A A transparent view of the antenna elements is shown.

[0227] Fig.155C Shown with additional details according to one aspect Fig.155A A front view of the antenna element is shown.

[0228] Fig.155D According to one aspect, Fig.155A A side view of the antenna element is shown.

[0229] Fig.156A According to one aspect, a method for Fig.155A The dual polarization return loss S-parameters of the antenna element are shown.

[0230] Fig.156B According to some aspects, a Fig.155A An exemplary 3D radiation pattern for a vertical feed of the antenna element is shown.

[0231] Fig.156C According to some aspects, a Fig.155A 3D radiation pattern of a horizontally fed antenna element shown.

[0232] Fig.157A According to one aspect, a method for Fig.155A The vertically polarized fed E-plane radiation pattern of the antenna shown.

[0233] Fig.157B According to one aspect, a method for Fig.155AHorizontally polarized fed H-plane radiation pattern of the antenna element shown.

[0234] Fig.158 Showing some aspects of Fig.155A Example achieved gain of the horizontally fed E-plane pattern of the antenna.

[0235] Fig.159A An exemplary antenna element with orthogonal vertical and horizontal excitations is shown in accordance with some aspects.

[0236] Fig.159B An exemplary antenna element with +45 degree and -45 degree excitation is shown in accordance with some aspects.

[0237] Fig.160A According to some aspects, the Fig.159B The two ports of the antenna are excited in phase to obtain vertical (V) polarization.

[0238] Fig.160B According to some aspects, Fig.159B Horizontal (H) polarization is obtained using one hundred eighty degrees out-of-phase excitation at the ports of the antenna.

[0239] Fig.161A FIG. 1 shows a schematic diagram of a device having vertical and horizontal excitation ports according to some aspects. Fig.159A antenna element.

[0240] Fig.161B Showing some aspects of Fig.161A Example simulated radiation pattern results for an antenna element.

[0241] Fig.162A A diagram illustrating an example 4x4 array of antenna elements using orthogonal excitation according to some aspects.

[0242] Fig.162B FIG. 1 shows a method for implementing a dual polarization antenna element according to some aspects. Fig.162A Example simulated radiation pattern results for a 4x4 array of .

[0243] Fig.162C According to some aspects of the invention, Fig.162A Example simulated radiation pattern results for an array excited by a +45 degree scan angle.

[0244] Fig.163A An exemplary dual polarization differential 4-port patch antenna in an anti-phase configuration is shown in accordance with some aspects.

[0245] Fig.163B A side view showing some aspects of the Fig.163A Antenna configuration.

[0246] Fig.163C According to some aspects, a method for Fig.162A and Fig.162B An exemplary layered structure stack of levels L1-L6 of the antenna configuration.

[0247] Fig.163D Exemplary patch antenna polarizations are shown in accordance with some aspects.

[0248] Fig.163E Exemplary suppression of cross-polarization levels according to some aspects is shown.

[0249] Fig.164 Showing some aspects of Figures 163A to 163C Example simulation radiation pattern results for a 4-port antenna configuration.

[0250] Fig.165A An exemplary 4-port excitation antenna topology with feed lines from a feed source to each of the four ports is shown in accordance with some aspects.

[0251] Fig.165B A driven patch having a stacked patch antenna superimposed on a feed line is shown according to some aspects Fig.165A The feeder in a 4-port configuration.

[0252] Fig.165C Show about Fig.165B An exemplary 12-level stack of aspects.

[0253] Fig.166A Schematic diagram showing an example 4x4 antenna array using a 4-port element integrated with a feed network in accordance with some aspects.

[0254] Fig.166B and Fig.166C Showing some aspects of Fig.166A Example simulation radiation pattern results of a 4-port antenna array.

[0255] Fig.167A An exemplary array configuration using a 2-port dual polarized antenna element is shown in accordance with some aspects.

[0256] Fig.167B and Fig.167C Showing some aspects of Fig.167A Example simulated radiation pattern results for an antenna array.

[0257] Fig.168A Another exemplary array configuration using a 2-port dual polarized antenna element in accordance with some aspects is shown.

[0258] Fig.168B and Fig.168C Showing some aspects of Fig.168A Example simulation results of the radiation pattern of .

[0259] Fig.169 An example mast-mounted mmWave antenna block with multiple antenna arrays for vehicle-to-everything (V2X) communications is shown in accordance with some aspects.

[0260] Fig.170 Example beam steering and antenna switching in a millimeter wave antenna array communicating with a single evolved Node B (eNB) in accordance with some aspects are shown.

[0261] Fig.171 Example beam steering and antenna switching in a millimeter wave antenna array communicating with multiple eNBs according to some aspects are shown.

[0262] Fig.172 Example simultaneous millimeter wave communications with multiple devices using an antenna block having multiple antenna arrays according to some aspects are shown.

[0263] Fig.173 A number of example beams are shown that may be used for an antenna block including multiple antenna arrays for millimeter wave communications according to some aspects.

[0264] Fig.174 Based on some aspects of use Fig.169 A block diagram of an exemplary millimeter wave communication device having an antenna block with multiple antenna arrays.

[0265] Figure 175A is an illustration of an exemplary via-hole antenna array configured in a mobile phone according to some aspects.

[0266] Fig.175B is an illustration of an exemplary via-hole antenna array configured in a laptop device according to some aspects.

[0267] Fig.175C is an illustration of an exemplary via antenna array configured on a mainboard PCB according to some aspects.

[0268] Fig.176A is a cross-sectional view of an exemplary via antenna in a multi-layer PCB according to some aspects.

[0269] Fig.176B is a perspective view of an exemplary via-hole antenna according to some aspects.

[0270] Fig.177A is an illustration of an exemplary PCB via antenna as viewed internally from the top of the PCB according to some aspects.

[0271] Fig.177B is an illustration of an exemplary PCB via antenna as viewed from the bottom of the PCB according to some aspects.

[0272] Figure 178A is a top view of an exemplary via-hole antenna array according to some aspects.

[0273] Fig.178B is an illustration of an exemplary vertical feed for a via hole antenna according to some aspects.

[0274] Figure 178C is an illustration of an exemplary horizontal feed for a via hole antenna according to some aspects.

[0275] Fig.179A is a perspective view of an exemplary back-to-back via configured as a dipole via antenna according to some aspects.

[0276] Fig.179B is a perspective view showing an exemplary back-to-back via of a PCB layer stackup configured as a dipole via antenna, according to some aspects.

[0277] Fig.180 Based on some aspects of Fig.179A and Fig.179B A plot of the antenna return loss for a dipole through-hole antenna configuration.

[0278] Fig.181A It is based on some aspects of the Ludwig definition at a frequency of 27.5 GHz. Fig.179A and Fig.179B Simulated far-field coplanar radiation pattern of a dipole through-hole antenna configuration.

[0279] Fig.181B It is based on some aspects of the Ludwig definition at a frequency of 28 GHz. Fig.179A and Fig.179B Example simulated far-field coplanar radiation pattern of a dipole through-hole antenna configuration.

[0280] Fig.181C It is based on some aspects of the Ludwig definition at a frequency of 29.5 GHz. Fig.179A and Fig.179B Example simulated far-field coplanar radiation pattern of a dipole through-hole antenna configuration.

[0281] Fig.182 An exemplary dual-element via-hole antenna array design for operation at 28 GHz for 5G technology according to some aspects.

[0282] Fig.183 Based on some aspects of Fig.182Simulation plot of antenna return loss for a dual-element via-hole antenna array design.

[0283] Fig.184A is based on some aspects of operation at a frequency of 27.5GHz Fig.182 Simulated radiation pattern of a two-element via array.

[0284] Fig.184B is based on some aspects of operation at a frequency of 29.5GHz Fig.182 Simulated radiation pattern of a two-element via array.

[0285] Fig.185 is a perspective view of an exemplary via antenna designed in a PCB according to some aspects.

[0286] Fig.186A Based on some aspects Fig.185 Bottom view of the ground plane of the via-hole antenna.

[0287] Fig.186B Showing some aspects Fig.185 Side view of the via-hole antenna.

[0288] Fig.186C Based on some aspects Fig.185 A perspective view of a via-hole antenna.

[0289] Fig.187 Based on some aspects of Fig.185 A simulation plot of an exemplary via-hole antenna return loss of a via-hole antenna.

[0290] Fig.188 An illustration of air holes drilled in a PCB around an exemplary via antenna to reduce surface wave propagation according to some aspects.

[0291] Figures 189A to 189C An exemplary modified ground plane assembly for a 3D conical antenna is shown in accordance with some aspects.

[0292] Fig.189D Exemplary conical antennas with various imperfect ground planes are shown.

[0293] Figures 190A to 190C An exemplary embodiment of a conical shaped monopole antenna structure with different types of ground planes in accordance with some aspects is shown.

[0294] Fig.191A and Fig.191B Showing some aspects Figures 190A to 190C Radiation pattern comparison between antenna structures.

[0295] Fig.192A and Fig.192BBased on some aspects Figures 190A to 190C A more detailed description of some of the antenna structures.

[0296] Fig.193A and Fig.193B Showing some aspects Figures 190A to 190C Top and bottom views of an exemplary 3D antenna structure.

[0297] Fig.194 Based on some aspects Fig.192A and Fig.192B Comparison of the return loss graphs of the antennas.

[0298] Figures 195A to 195C E-field distribution with respect to the ground structures 190A to 190C is shown according to some aspects.

[0299] Figures 196A to 196C An exemplary five-element conical antenna array is shown without and with a modified ground plane in accordance with some aspects.

[0300] Fig.197A and Fig.197B A comparison of cross-polarized radiation patterns without and with a modified ground plane is shown in accordance with some aspects.

[0301] Fig.198A and Fig.198B The effect of a ground plane on antenna radiation according to some aspects is shown.

[0302] Fig.199 Shown is a return loss comparison and an isolation comparison for an exemplary antenna array with a modified ground plane, according to some aspects.

[0303] Fig.200 Shown is a comparison of return loss and isolation between antenna elements for an exemplary unmodified large antenna array in accordance with some aspects.

[0304] Figures 201A to 201C An exemplary PCB with a slotted modified ground plane that can be used for a 3D antenna according to some aspects is shown.

[0305] Fig.202 A block diagram of an exemplary receiver operating in switch mode and split mode is shown.

[0306] Fig.203 A block diagram of an example receiver using a segmented low noise amplifier (LNA) and a segmented mixer is shown in accordance with some aspects.

[0307] Fig.204A block diagram is shown of an example receiver using a segmented low noise amplifier (LNA) and a segmented mixer operating in a split mode to process contiguous carrier aggregation signals in accordance with some aspects.

[0308] Fig.205 A block diagram of an example receiver using a segmented LNA and a segmented mixer operating in a switch mode with signal splitting at the LNA input according to some aspects is shown.

[0309] Fig.206 A block diagram of an example receiver using a segmented LNA and a segmented mixer operating in a split mode with signal split at an LNA input in accordance with some aspects is shown.

[0310] Fig.207 A block diagram of an exemplary local oscillator (LO) signal generation circuit is shown in accordance with some aspects.

[0311] Fig.208 A block diagram of an example receiver using a segmented output LNA and a segmented mixer operating in a switch mode with signal splitting at the LNA output according to some aspects is shown.

[0312] Fig.209 A block diagram of an example receiver using a segmented output LNA and a segmented mixer operating in a split mode with signal split at the LNA output according to some aspects is shown.

[0313] Fig.210 An exemplary LO distribution scheme for a receiver operating in switch mode according to some aspects is shown.

[0314] Fig.211 An exemplary LO allocation scheme for a receiver operating in split mode is shown in accordance with some aspects.

[0315] Fig.212 is a side view of a moldless stacked package-on-package embedded die radio system using a connector according to some aspects.

[0316] Fig.213 is a side view of an exemplary molded-on-package embedded die radio system according to some aspects.

[0317] Fig.214 is a side view of an exemplary molded-on-package embedded die radio system according to some aspects.

[0318] Fig.215 A cross section of an exemplary computing platform is shown having stand-alone components of an RF front end in accordance with some aspects.

[0319] Fig.216 A cross section of an exemplary computing platform is shown with integrated components of an RF front end in a stack or substrate in accordance with some aspects.

[0320] Fig.217 An exemplary smart device or an exemplary computer system or SoC (system on a chip) partially implemented in a stackup / substrate according to some aspects is shown.

[0321] Fig.218 A side view of an exemplary mold-on-package embedded die radio system using ultra-thin components configured between the die and the antenna is shown in accordance with some aspects.

[0322] Fig.219 is a side view of a molded-on-package embedded die radio system having three packages stacked one on top of another according to some aspects.

[0323] Fig.220 is a high-level block diagram of an exemplary mmWave RF architecture for 5G and WiGig according to some aspects.

[0324] Fig.221A A frequency transition plan for an example mmWave RF architecture for 5G and WiGig is shown in accordance with some aspects.

[0325] Fig.221B is a schematic diagram of frequency allocation for the 5G 40 GHz band according to some aspects.

[0326] Fig.221C An example synthesizer source for offsetting a second of two band streams across an unused 5G band is shown in accordance with some aspects.

[0327] Fig.221D Phase noise power as a function of frequency is shown in accordance with some aspects.

[0328] Fig.222 An exemplary transmitter up-conversion frequency scheme for 5G in the 40 GHZ band is shown in accordance with some aspects.

[0329] Fig.223 An exemplary transmitter up-conversion frequency scheme for 5G in the 30 GHZ band is shown in accordance with some aspects.

[0330] Fig.224A A first section of an exemplary baseband integrated circuit (BBIC) block diagram is shown in accordance with some aspects.

[0331] Fig.224B A second section of an exemplary baseband integrated circuit (BBIC) block diagram is shown in accordance with some aspects.

[0332] Fig.225 is an exemplary detailed radio frequency integrated circuit (RFIC) block diagram according to some aspects.

[0333] Fig.226A and Fig.226B is a block diagram of an exemplary mmWave and 5G communication system according to some aspects.

[0334] Fig.227 Shown are illustrative assignments of radio frequency (RF), intermediate frequency (IF), and oscillator (LO) frequencies for scanning across various channel options in accordance with some aspects.

[0335] Fig.228 An exemplary fixed LO transmitter up-conversion scheme is shown in accordance with some aspects.

[0336] Fig.229 Double frequency conversion in an exemplary radio system including a first frequency conversion with a fixed LO and a second frequency conversion with a varying LO is shown in accordance with some aspects.

[0337] Fig.230 A digital-to-time converter (DTC) structure is shown in accordance with some aspects.

[0338] Fig.231 A DTC architecture for open loop calibration according to some aspects is shown.

[0339] Figure 232A illustrates time interleaving of DTCs for increasing clock frequency according to some aspects; Fig.232B Showing some aspects Figure 232A The clock signal.

[0340] Fig.233 A serial injection locked oscillator with pulse shaping according to some aspects is shown.

[0341] Fig.234 Methods of providing mmWave frequency signals according to some aspects are shown.

[0342] Fig.235 A receiver according to some aspects is shown.

[0343] Fig.236 A basic implementation of a feed-forward equalizer (FFE) according to some aspects is shown.

[0344] Fig.237A and Fig.237B An FFE according to some aspects is shown.

[0345] Fig.238 Methods of providing analog signal equalization according to some aspects are shown.

[0346] Fig.239A and Fig.239B Configuration of a reconfigurable decision feedback equalizer (DFE) according to some aspects is shown.

[0347] Figure 240A and Figure 240B A selector / D flip-flop (DFF) combination configuration of a reconfigurable DFE according to some aspects is shown.

[0348] Fig.241 There are some ways to configure DFE.

[0349] Fig.242 A mmWave architecture according to some aspects is shown.

[0350] Fig.243 A transmitter hybrid beamforming architecture according to some aspects is shown.

[0351] Fig.244 A simulation of communication rates according to some aspects is shown.

[0352] Fig.245 A simulation of a signal-to-noise ratio (SNR) according to some aspects is shown.

[0353] Fig.246 Methods of delivering beamformed mmWave signals according to some aspects are shown.

[0354] Figure 247A and Figure 247B A transceiver structure according to some aspects is shown.

[0355] Figure 248A and Figure 248B A transceiver structure according to some aspects is shown.

[0356] Fig.249 Adaptive resolution analog-to-digital converter (ADC) power consumption is shown in accordance with some aspects.

[0357] Fig.250 Bit error rate (BER) performance according to some aspects is shown.

[0358] Fig.251 Methods of delivering beamformed mmWave signals according to some aspects are shown.

[0359] Figure 252A and Figure 252B A transceiver structure according to some aspects is shown.

[0360] Fig.253 An array structure according to some aspects is shown.

[0361] Fig.254 A simulation of a grating lobe according to some aspects is shown.

[0362] Fig.255 Simulations of optimal phase values ​​according to some aspects are shown.

[0363] Fig.256 Another simulation of optimal phase values ​​according to some aspects is shown.

[0364] Fig.257 A process for a phase shifter according to some aspects is shown.

[0365] Fig.258 Phase value determination according to some aspects is shown.

[0366] Fig.259 Performance comparison according to some aspects is shown.

[0367] Fig.260 Another performance comparison according to some aspects is shown.

[0368] Fig.261 Methods of providing beam steering in a communication device according to some aspects are shown.

[0369] Figure 262A and Fig.262B Aspects of a charge pump according to some aspects are shown.

[0370] Fig.263 Aspects of a charge pump according to some aspects are shown.

[0371] Figure 264A A simplified scheme of an output section of a charge pump according to some aspects is shown. Figure 264B A timing diagram illustrating signals of a charge pump according to some aspects.

[0372] Figures 265A to 265C Operation of a charge pump according to some aspects is shown.

[0373] Figures 266A to 266C An overview of the operation of a charge pump according to some aspects is shown.

[0374] Fig.267 Methods of injecting charge in a charge pump according to some aspects are shown.

[0375] Fig.268 A receiver architecture according to some aspects is shown.

[0376] Fig.269 Filter characteristics of a receiver according to some aspects are shown.

[0377] Fig.270BER performance of a receiver according to some aspects is shown.

[0378] Fig.271 Different receiver architectures according to some aspects are shown.

[0379] Fig.272 Methods of compensating for interferers in a receiver according to some aspects are shown.

[0380] Figure 273A and Figure 273B Interference according to some aspects is shown.

[0381] Fig.274 A receiver architecture according to some aspects is shown.

[0382] Fig.275 An oversampled signal is shown in accordance with some aspects.

[0383] Figure 276A and Figure 276B Filter characteristics of a receiver according to some aspects are shown.

[0384] Fig.277 Beamforming patterns in accordance with some aspects are shown.

[0385] Fig.278 BER performance according to some aspects is shown.

[0386] Fig.279

[0013] Methods of reducing quantizer dynamic range in a receiver according to some aspects are shown.

[0387] Fig.280 An ADC system (ADCS) according to some aspects is shown.

[0388] Figure 281A and Figure 281B Different modes of operation of an ADCS according to some aspects are shown.

[0389] Fig.282 Core ADC averaging according to some aspects is shown.

[0390] Fig.283 Resolution improvements for an averaging system according to some aspects are shown.

[0391] Fig.284 Methods of providing a flexible ADC architecture according to some aspects are shown.

[0392] Fig.285 A receiver architecture according to some aspects is shown.

[0393] Fig.286 A simulation of spatial response according to some aspects is shown.

[0394] Fig.287 A simulation of BER according to some aspects is shown.

[0395] Fig.288 Simulations of interference suppression according to some aspects are shown.

[0396] Fig.289

[0013] Methods of reducing quantizer dynamic range in a receiver according to some aspects are shown.

[0397] Fig.290 is a block diagram of an example of a time-interleaved analog-to-digital converter (TI-ADC) according to some aspects that may be utilized herein and that uses M parallel low-speed ADC channels to achieve high-speed frequency conversion in some aspects.

[0398] Fig.291 is a graph showing how all channels operate at the same sampling frequency F with M evenly spaced phases according to an example TI-ADC S (or its reciprocal T S , shown in Fig.291 (middle) timing diagram 29100.

[0399] Fig.292 is a block diagram illustrating an example of a transceiver 29200 with a loopback design according to examples disclosed herein.

[0400] Fig.293 is a flow chart illustrating a process according to examples disclosed herein.

[0401] Fig.294 is a block diagram of an example TI-ADC according to some aspects.

[0402] Fig.295 is a block diagram of an example of a TI-ADC architecture that implements high-speed frequency conversion according to some aspects.

[0403] Fig.296 is a diagram showing how all channels can operate at the same sampling frequency F with M evenly spaced phases according to some aspects. S (or its reciprocal T S , shown in Fig.296 (middle) timing diagram.

[0404] Fig.297 is a flow diagram illustrating an example implementation of a process for applying gain correction in accordance with some aspects.

[0405] Fig.298 is a graph illustrating an example of a PA characteristic curve of AM / AM (input amplitude to output amplitude) according to some aspects.

[0406] Fig.299is a graph showing an example of a PA characteristic curve of AM / PM (input amplitude to output phase variation) according to some aspects.

[0407] Fig.300 is a block diagram of an example of a gain model for a section of a phased array transmitter according to an exemplary aspect of the present disclosure.

[0408] Fig.301 is a block diagram of an example of a switchable transceiver section that the above-described transmitter model may represent according to an exemplary aspect of the present disclosure.

[0409] Fig.302 Basically according to exemplary aspects of the present disclosure Fig.301 A duplicate transceiver section of the shown transceiver section, but with the switch thrown in the receive configuration.

[0410] Figure 303A and Fig.303B is a portion of a block diagram of an overall transceiver example that may include transceiver sections according to exemplary aspects of the present disclosure.

[0411] Fig.304 is a block diagram illustrating a phased array transceiver communicating with an external phased array transceiver (EPAT) according to an exemplary aspect of the present disclosure.

[0412] Fig.305 is a flow chart illustrating an example of a process that may be used by a transceiver according to exemplary aspects of the present disclosure.

[0413] Fig.306 is a flow chart illustrating another example of a process that may be used by a transceiver according to exemplary aspects of the present disclosure.

[0414] Figure 307A and Fig.307B is a portion of a block diagram of an example of an overall distributed phased array transceiver system in accordance with some aspects.

[0415] Fig.308 is a block diagram of a receiver power amplifier according to some aspects.

[0416] Fig.309 is a graph that plots EVM versus received power for a given automatic gain control (AGC) gain setting according to some aspects.

[0417] Fig.310

[0013] A graph including EVM versus received power for a plurality of AGC gain settings having a degree of overlap with one another according to some aspects.

[0418] Fig.311is a graph illustrating an optimal threshold for activating a particular AGC gain setting according to some aspects.

[0419] Fig.312 is a flow chart illustrating an example process that may be utilized to determine an optimal threshold value in accordance with some aspects.

[0420] Fig.313 is a schematic block diagram of a radio frequency (RF) phased array system according to some aspects.

[0421] Fig.314 is a schematic block diagram illustrating another topology of a phased array radio transceiver referred to as a local oscillator (LO) phased array system in accordance with some aspects.

[0422] Fig.315 is a schematic block diagram illustrating a third alternative for a phased array radio transceiver design in accordance with some aspects and referred to as a digital phased array system.

[0423] Fig.316 is a block diagram of an example small unit cell element of a SPARTA array according to some aspects.

[0424] Fig.317 is a block diagram illustrating a tiled SPARTA cell according to some aspects.

[0425] Fig.318 and Fig.319 It is a physical picture of wafer cutting according to some aspects.

[0426] Fig.320 A physical illustration of a modular SPARTA array that can be wafer processed and combined with an antenna array according to some aspects.

[0427] Fig.321 is a block diagram illustrating a SPARTA celllet that may be an implementation of a SPARTA celllet that may be used for digital phase array tiling according to some aspects.

[0428] Fig.322 is a block diagram illustrating LO phased array pipelining between adjacent cells in LO phase combining mode according to some aspects.

[0429] Fig.323 is a block diagram illustrating SPARTA cell tiling using a LO phase array and illustrating an active data converter ADC, according to some aspects.

[0430] Fig.324 is a block diagram illustrating a SPARTA array in hybrid mode, where each row is tiled in LO phase shift and shares a single ADC, according to some aspects.

[0431] Fig.325 is a block diagram illustrating pipelining of analog phased array combining between adjacent cellets for an analog phased array combining mode of operation, according to some aspects.

[0432] Fig.326 is a schematic diagram of components for an injection locking (IL) based phase modulation circuit that exploits the phase shifting properties of a conventional locked oscillator, according to some aspects.

[0433] Fig.327 is a graph showing how output phase and amplitude change as the center frequency of the oscillator changes relative to the locking frequency while still locked to the injection frequency according to some aspects.

[0434] Fig.328 is a diagram showing a phase controller having a cap-DAC generated by controlling the baseband modulation bits as data input according to some aspects. and Timing plot of two symbols.

[0435] Fig.329 is a block diagram of an IL-based phase modulation circuit with full 360° phase modulation using a cascaded subharmonic injection locking architecture with respect to a carrier frequency, according to some aspects.

[0436] Figure 330 is a combined graph showing real time delay based beamforming with elements 1 and 2 feeding the same baseband data signal ("11", "00") at two different offsets in accordance with some aspects.

[0437] Fig.331 is a schematic block diagram illustrating an example architecture of a four-element phased array transmitter that implements combining harmonic IL-based phase modulation with true time-delay beamforming in accordance with some aspects.

[0438] Fig.332 is a block diagram of a circuit for IL-based phase modulation showing an example of an injection locked oscillator when operating at 1 / 3 of a carrier frequency, according to some aspects.

[0439] Fig.333 is a block diagram for an IL-based phase modulation circuit showing an example of an injection locked oscillator when operating at 1 / 2 of a carrier frequency, according to some aspects.

[0440] Fig.334 is a diagram illustrating a Quadrature Phase Shift Keying (QPSK) (PAM2-wire based) modulation (two bits per symbol) with a diagram mapped as a constellation diagram illustrating possible I / Q values, in accordance with some aspects.

[0441] Fig.335 is a diagram illustrating 16-QAM (PAM4-wired based) modulation (four bits per symbol) with a diagram mapped as a constellation diagram illustrating possible I / Q values, according to some aspects.

[0442] Fig.336 is a diagram of a design for PAM2 (QPSK) modulation according to some aspects.

[0443] Fig.337 is a table of the provided data and error values ​​according to some aspects.

[0444] Fig.338 is a graph showing the equalization of using Z and a first table according to some aspects.

[0445] Fig.339 is a table showing a second concept in which error values ​​are all negative 1 except for values ​​above positive 3 and values ​​below negative 3 according to some aspects.

[0446] Fig.340 is a graph of the Z function using the second table according to some aspects.

[0447] Fig.341 is a schematic block diagram of a typical baud rate CDR loop for wired according to some aspects.

[0448] Figure 342 is a schematic block diagram of a novel wireless CDR loop with both in-phase (I) and quadrature (Q) inputs according to some aspects.

[0449] Fig.343 It is based on some aspects of inclusion that can be used Figure 342 A table of various mode values ​​for the modes in the design.

[0450] Figure 344A is a schematic block diagram of an AGC circuit that may be implemented at a receiver if the amplitude of a received signal varies during operation of the receiver in accordance with some aspects.

[0451] Figure 344B is a flow diagram of an example AGC process that may be implemented at a receiver if the amplitude of a received signal varies during operation of the receiver in accordance with some aspects.

[0452] Fig.345 is a graph showing a method for obtaining a receiver signal having b=log 2 Constellation diagram plot of the orthogonal encoding of the quantization bins of a (2n)-bit low-resolution ADC.

[0453] Fig.346is a constellation diagram plot for illustrating orthogonal encoding of quantization regions for a 3-bit ADC according to some aspects.

[0454] Fig.347 is shown according to some aspects in only r 1 and r 5 Plots of the conditional probability distribution for the monotonically increasing and decreasing cases.

[0455] Fig.348 is a graph showing the derivative of a conditional probability distribution according to some aspects.

[0456] Fig.349 is a graph illustrating an example of the estimated performance of the proposed power estimation algorithm compared to a classical average power determination according to some aspects.

[0457] Fig.350 is a graph showing latency of a novel algorithm according to some aspects.

[0458] Fig.351 It is a plot of the normalized mean square error (MSE) based on some comparisons.

[0459] Figure 352 is a graph illustrating mean square error (MSE) with uniform 45° phase noise according to some aspects.

[0460] Fig.353 is a schematic block diagram illustrating an example of a MIMO receiver with a digital processor according to some aspects.

[0461] Fig.354 is a block diagram illustrating an example of a beamforming circuit with N identical transceiver segments and N antenna elements according to some aspects.

[0462] Figure 355 is a graph that plots SNDR at an antenna versus input power when antenna array gain is held constant in accordance with some aspects.

[0463] Fig.356 is a graph that plots SNDR at an antenna versus input power when the antenna array gain is varied to enable gain control in accordance with some aspects.

[0464] Fig.357 is a graph showing radiated power and relative current drain versus the number of active elements in an antenna array according to some aspects.

[0465] Fig.358 is a graph illustrating tradeoffs in operating conditions with respect to Rx, according to some aspects.

[0466] Fig.359is a graph illustrating tradeoffs in operating conditions for Tx according to some aspects.

[0467] Figure 360 is a flow diagram illustrating an example of a receive process that may be used, according to some aspects.

[0468] Fig.361 is a flow diagram illustrating an example of a transmission process that may be used, according to some aspects.

[0469] Fig.362 is a schematic diagram of a DAC architecture according to some aspects.

[0470] Fig.363 is a hierarchically structured schematic diagram of one implementation of the apparatus described herein.

[0471] Fig.364 is a composite pictorial representation including a pair of graphs showing co-planar polarization and cross polarization when a transmit antenna and a receive antenna are aligned (ie, parallel) in accordance with some aspects.

[0472] Figure 365 is a composite pictorial representation including a pair of graphs illustrating co-planar polarization and cross polarization when a transmit antenna and a receive antenna are misaligned (ie, not parallel) in accordance with some aspects.

[0473] Figure 366 is an example of a receiver designed using MSFFPE according to some aspects.

[0474] Fig.367 is a circuit diagram showing a conventional summer.

[0475] Fig.368 is a circuit diagram illustrating an integrating DFE summer according to some aspects, with relevant differences highlighted.

[0476] Fig.369 is a schematic diagram providing more details on the design of a DFE summer according to some aspects.

[0477] Fig.370 is a graph related to DFE summer design showing clock signals with respect to a summing amplifier output signal and a strong arm-1 signal, according to some aspects.

[0478] Figure 371 is a schematic illustration of a block diagram of an RF device according to some exemplary aspects.

[0479] Figure 372 is a schematic illustration of a block diagram of an RF device according to some exemplary aspects.

[0480] Fig.373is a schematic illustration of a bidirectional amplifier circuit according to some exemplary aspects.

[0481] Figure 374 is a schematic illustration of a bidirectional amplifier circuit according to some exemplary aspects.

[0482] Fig.375 is a schematic illustration of a bidirectional amplifier circuit according to some exemplary aspects.

[0483] Figure 376 is a schematic illustration of a block diagram of a transceiver including a cascaded topology of an active bidirectional splitter and combiner (ABDSC) according to some exemplary aspects.

[0484] Figure 377 is a schematic illustration of a circuit diagram of a common-source topology for an ABDSC according to some exemplary aspects.

[0485] Figure 378 is a schematic illustration of a common-gate topology of an ABDSC according to some exemplary aspects.

[0486] Fig.379 is a schematic illustration of a common-gate / common-source (CS / CG) topology of an ABDSC according to some exemplary aspects.

[0487] Figure 380 is a schematic illustration of a block diagram of an architecture of a transmitter according to some exemplary aspects.

[0488] Figure 381A is a schematic illustration of an electronic circuit for a stacked gate controlled amplifier according to some exemplary aspects.

[0489] Figure 381B is a schematic illustration of an electronic circuit for a stacked gate controlled amplifier according to some exemplary aspects.

[0490] Figure 382 is a schematic illustration of a block diagram of a transmitter including a stacked gate modulated digital power amplifier (PA) according to some exemplary aspects.

[0491] Figure 383A and Figure 383B is a schematic illustration of a dynamic implementation of a multi-level high-speed eye diagram according to some exemplary aspects.

[0492] Figure 384A and Figure 384B Graphs depicting performance improvements corresponding to an input series switching amplifier according to some exemplary aspects ( Figure 384A ) and power reduction graph ( Figure 384B ).

[0493] Figure 385A and Figure 385B A plot of amplitude resolution corresponding to an N-bit digital PA according to some exemplary aspects is depicted. Figure 385A ) and power efficiency graph ( Figure 385B ).

[0494] Figure 386 Drain efficiency versus power saturation for a stacked gate controlled amplifier having a driver amplifier preceding it is described according to some exemplary aspects.

[0495] Fig.387 is a schematic illustration of a block diagram of a transmitter according to some exemplary aspects.

[0496] Fig.388 is a schematic illustration of a block diagram of a two-stage Doherty amplifier that may employ a sub-quarter wavelength (SQWL) balun, according to some exemplary aspects.

[0497] Fig.389 is a schematic illustration of a block diagram of a transceiver according to some exemplary aspects.

[0498] Fig.390 is a schematic illustration of a block diagram of a transmitter according to some exemplary aspects.

[0499] Figure 391 is a schematic illustration of a block diagram of an out-phasing amplifier employing a SQWL balun as a load according to some exemplary aspects.

[0500] Figure 392 is a schematic illustration of a block diagram of a transceiver according to some exemplary aspects.

[0501] Fig.393 is a schematic illustration of an electronic circuit layout of a phase shifting circuit according to some exemplary aspects.

[0502] Fig.394 is a schematic illustration of a first quadrant of a constellation point mapping according to some exemplary aspects.

[0503] Fig.395 is a schematic illustration of a graph depicting gain variation of constellation points versus ideal phase-shifted constellation points according to some exemplary aspects.

[0504] Fig.396 is a schematic illustration of a block diagram of a transceiver according to some exemplary aspects.

[0505] Fig.397 is a schematic illustration of a block diagram of a transceiver according to some exemplary aspects.

[0506] Fig.398is a schematic illustration of a quadrature local oscillator (LO) generator according to some exemplary aspects.

[0507] Fig.399 is a schematic illustration of a passive quadrature LO generator according to some exemplary aspects.

[0508] Figure 400 is a schematic illustration of a block diagram of a transmitter according to some exemplary aspects.

[0509] Figure 401 A schematic illustration of frequency band planning for multiple channels corresponding to multiple channel bandwidths that can be implemented according to some exemplary aspects.

[0510] Figure 402 is a schematic illustration of a graph depicting gain responses of a low-band amplifier and a high-band amplifier according to some exemplary aspects.

[0511] Figure 403 is a schematic illustration of a converter according to some exemplary aspects.

[0512] Figure 404 is a schematic illustration of a block diagram of a wireless communication device according to some demonstrative aspects.

[0513] Figure 405 is a schematic illustration of an impedance matching switch according to some exemplary aspects.

[0514] Figure 406 is a schematic illustration of a block diagram of a transceiver according to some exemplary aspects.

[0515] Fig.407 is a schematic illustration of a block diagram of a half-duplex transceiver according to some exemplary aspects.

[0516] Figure 408 is a schematic illustration of a bidirectional mixer according to some exemplary aspects.

[0517] Figure 409A A phased array transceiver according to some aspects of the present disclosure is shown.

[0518] Figure 409B An antenna array with an original reduced coverage angle is shown in accordance with some aspects of the present disclosure.

[0519] Figure 409C The use of lenses in conjunction with phased array antennas to deflect the radiated beam and expand the coverage angle is shown in accordance with some aspects of the present disclosure.

[0520] Fig.409D The use of concave reflectors in conjunction with phased array antennas to deflect the radiated beam and expand the coverage angle is shown in accordance with some aspects of the present disclosure.

[0521] Figure 410 A plurality of phased arrays are shown for use in conjunction with printed reflectors in a first configuration in accordance with aspects of the present disclosure.

[0522] Figure 411 A plurality of phased arrays are shown for use with Cassegrain antennas in a first configuration in accordance with aspects of the present disclosure.

[0523] Figure 412 A plurality of phased arrays are shown for use in conjunction with printed reflectors in a second configuration in accordance with aspects of the present disclosure.

[0524] Fig.413 A plurality of phased arrays are shown for use with Cassegrain antennas in a second configuration in accordance with aspects of the present disclosure.

[0525] Fig.414 A plurality of phased arrays are shown for use in conjunction with printed reflectors in a third configuration in accordance with aspects of the present disclosure.

[0526] Figure 415 A plurality of phased arrays are shown for use with Cassegrain antennas in a third configuration in accordance with aspects of the present disclosure.

[0527] Figure 416 A top view illustrating sectorization resulting from multiple phased arrays used in conjunction with reflective antennas in accordance with some aspects of the present disclosure.

[0528] Figure 417 A scan in each sector of a sectorized scan area is shown in accordance with some aspects of the present disclosure.

[0529] Figure 418 A package showing that an antenna according to some aspects of the present disclosure may be embedded within a user device.

[0530] Fig.419 According to some aspects of the present disclosure Figure 418 Plot of the achieved gain for a 1x4 dipole array implemented in a 1x4 package.

[0531] Figure 420 Some aspects of the present disclosure are shown. Fig.419 The radiation pattern associated with the plot.

[0532] Fig.421 The use of an integrated circuit (IC) shield as an antenna ground plane and reflector for a stacked patch antenna in accordance with some aspects of the present disclosure is shown.

[0533] Figure 422AFIG. 1 shows an asymmetric via feeding mechanism according to some aspects of the present disclosure. Fig.421 Side view of the monopole antenna shown.

[0534] Figure 422B-Figure 422D According to some aspects of the present disclosure Fig.421 Specific dimensions of the monopole antenna shown.

[0535] Fig.423 FIG. 1 shows an antenna array configuration with a mobile platform according to some aspects of the present disclosure. Fig.421 and Figure 422A Patch element of the monopole antenna.

[0536] Figure 424A A dipole antenna with a surface mount device (SMD) antenna that transitions the dipole antenna through a monopole to a dipole is shown in accordance with some aspects of the present disclosure.

[0537] Figure 424B According to some aspects of the present disclosure Figure 424A A perspective view of the dipole section of the antenna.

[0538] Figure 424C A combined dipole of a monopole antenna according to some aspects of the present disclosure is shown.

[0539] Figure 424D According to some aspects of the present disclosure Figure 424A A perspective view of the monopole portion of the antenna.

[0540] Figure 424E According to some aspects of the present disclosure Figure 424A and Figure 424D Side view of the antenna.

[0541] Fig.425 According to some aspects of the present disclosure Figure 424A The radiation pattern of the antenna.

[0542] Figure 426A Show Figure 424A The elevation cut of the antenna's radiation pattern.

[0543] Figure 426B According to some aspects of the present disclosure Figure 424B The radiation pattern of the antenna.

[0544] Figure 427A Shown is a side view of an SMD L-shaped dipole with an IC shield used as a reflector, according to some aspects of the present disclosure.

[0545] Figure 427B According to some aspects of the present disclosure Figure 427AShown is a perspective view of an SMD L-shaped dipole with an IC shield used as a reflector.

[0546] Fig.428 A perspective view of an array of four SMD L-shaped dipoles is shown according to one aspect.

[0547] Figure 429A FIG. 1 shows a method for vertical polarization with field cancellation according to some aspects of the present disclosure. Fig.428 Array of .

[0548] Figure 429B FIG. 1 shows a method for vertical polarization with field addition according to some aspects of the present disclosure. Fig.428 Array of .

[0549] Figure 430A FIG. 1 shows a method for horizontal polarization with field addition according to some aspects of the present disclosure. Fig.428 Array of .

[0550] Figure 430B FIG. 1 shows a method for horizontal polarization with field cancellation according to some aspects of the present disclosure. Fig.428 Array of .

[0551] Figure 431 A three-dimensional radiation pattern for vertical (theta) polarization is shown in accordance with some aspects of the present disclosure.

[0552] Figure 432 A three-dimensional radiation pattern for horizontal (phi) polarization is shown in accordance with some aspects of the present disclosure.

[0553] Figure 433 A single SMD monopole antenna is shown in accordance with some aspects of the present disclosure.

[0554] Figure 434 A three-dimensional radiation pattern is shown in accordance with some aspects of the present disclosure.

[0555] Figure 435 An impedance plot of a single monopole is shown in accordance with some aspects of the present disclosure.

[0556] Figure 436 The return loss of a single monopole over frequency is shown according to some aspects of the present disclosure.

[0557] Figure 437 The achieved vertical polarization (θ) gain in the XZ plane from a single monopole is shown in accordance with some aspects of the present disclosure.

[0558] Figure 438 The achieved vertical polarization (θ) gain from a single monopole at frequencies greater than 15° endfire is shown in accordance with some aspects of the present disclosure.

[0559] Fig.439 Dual-element monopole and dual-element dipole arrays are shown in accordance with some aspects of the present disclosure.

[0560] Figure 440 60 GHz according to some aspects of the present disclosure Fig.439 Three-dimensional radiation pattern of a double dipole array.

[0561] Figure 441 The distance according to some aspects of the present disclosure is shown Fig.439 Horizontal polarity of a double dipole array in the end-fire direction as a function of frequency Gain.

[0562] Figure 442 60 GHz according to some aspects of the present disclosure Fig.439 Three-dimensional radiation pattern of a dual monopole array.

[0563] Figure 443 The achieved vertical polarity (θ) is shown according to some aspects of the present disclosure.

[0564] Figure 444 A single-patch, dual-fed, dual-polarization vertical SMD patch antenna is shown in accordance with some aspects of the present disclosure.

[0565] Figure 445 A stacked-patch, single-feed, single-polarization vertical SMD patch antenna is shown in accordance with some aspects of the present disclosure.

[0566] Figure 446 A horizontal SMD patch antenna is shown in accordance with some aspects of the present disclosure.

[0567] Figure 447 A vertical SMD patch antenna using a cross-hatching pattern according to the present disclosure is shown.

[0568] Figure 448 An SMD helical antenna with circular polarization according to some aspects of the present disclosure is shown.

[0569] Fig.449 An implementation of a helical antenna within a SMD according to some aspects of the present disclosure is shown.

[0570] Figure 450 A director coupling radiation to a chassis is shown in accordance with some aspects of the present disclosure.

[0571] Figure 451A is a perspective view of an IC shield wall cutout forming an antenna according to some aspects of the present disclosure.

[0572] Figure 451B According to some aspects of the present disclosure, Figure 451A A side view of the wall cutout of the antenna is shown.

[0573] Figure 451C is a perspective view of an IC shield having wall cutouts and a top cutout including antenna elements of an antenna array according to some aspects of the present disclosure.

[0574] Figure 451D is a perspective view of an IC shield having first and second wall cutouts including antenna elements of an antenna array according to aspects of the present disclosure.

[0575] Figure 452A A patch antenna and RF feed line connections including a transmit / receive (TR) switch for a single polarization design are shown in accordance with some aspects of the present disclosure.

[0576] Figure 452B Patch antenna and RF feed line connections including a TR switch for a dual polarization design are shown according to some aspects of the present disclosure.

[0577] Figure 452C A patch antenna in a single polarization design with an antenna feed having a matching point for the RX feed line slightly offset to one side compared to the TX feed line matching point in accordance with some aspects of the present disclosure is shown.

[0578] Figure 452D A patch antenna in a dual polarization design with an antenna feed for both polarizations with an RX feed matching point slightly offset to one side compared to the TX feed matching point is shown in accordance with aspects of the present disclosure.

[0579] Figure 453A A single polarization implementation of the TX feed and the RX feed directly connected to the antenna feed matching points is shown in accordance with some aspects of the present disclosure.

[0580] Figure 453B Dual polarization implementations of horizontally polarized TX and RX feeds and vertically polarized TX and RX feeds directly connected to antenna feed matching points are shown in accordance with some aspects of the present disclosure.

[0581] Figure 454A An IC shield according to some aspects of the present disclosure is shown.

[0582] Figure 454B An IC shield having raised portions or extensions to enhance antenna gain and diversity is shown in accordance with some aspects of the present disclosure.

[0583] Figure 454C The use of a folded extension with an IC shield to improve the gain of an array of dipole antenna elements in accordance with some aspects of the present disclosure is shown.

[0584] Figure 454D A hole created in a shield structure due to a boss is shown in accordance with some aspects of the present disclosure.

[0585] Figure 454E According to some aspects of the present disclosure Figure 454D A close-up perspective view of the protrusions and holes of the .

[0586] Figure 455 is a top view of a combined patch antenna and dipole antenna array with a shield reflector according to some aspects of the present disclosure.

[0587] Figure 456 According to some aspects of the present disclosure Figure 455 Side view of the antenna array.

[0588] Figure 457 is a perspective view of an interposer for use in a patch array to bypass large obstructions in user equipment, according to some aspects of the present disclosure.

[0589] Figure 458A FIG. 1 is a diagram showing an IC shield cover according to some aspects of the present disclosure. Figure 457 A perspective view of an interposer.

[0590] Figure 458B is a method for using an end-fire direction shown at negative ninety (-90) degrees according to some aspects of the present disclosure. Figure 458A Top view of the radiation pattern of the dipole antenna array.

[0591] Figure 459 FIG. 1 shows the height of the interposer in various directions as a function of the height of the interposer according to some aspects of the present disclosure. Figure 457 and Figure 458A The realized gain of the patch antenna array.

[0592] Figure 460A is a perspective view of a combined patch and slot antenna for dual-band, dual-polarization operation according to some aspects of the present disclosure.

[0593] Figure 460B According to some aspects of the present disclosure Figure 460A Side view of the combined patch and slot antenna.

[0594] Figure 461A is an exploded view of an antenna on chip (AOC) according to some aspects of the present disclosure.

[0595] Figure 461B According to some aspects of the present disclosure, Figure 461A Bottom view of the AOC antenna.

[0596] Figure 461C According to some aspects of the present disclosure Figure 461A Side view of the AOC.

[0597] Figure 462 is included for some aspects of the present disclosure. Figure 461A Another bottom view of the AOC.

[0598] Figure 463 According to some aspects of the present disclosure Figure 461A-461C and Figure 462 Radiation pattern of the on-chip antenna.

[0599] Figure 464A Another view showing an AOC for an embedded die in a package-on-package implementation in accordance with some aspects of the present disclosure.

[0600] Figure 464B is an illustration of the radiation efficiency as a function of the height of the silicon divided by the height of the patch in accordance with some aspects of the present disclosure.

[0601] Figure 464C is an illustration of the achieved gain in dBi as a function of the height of the silicon divided by the height of the patch according to some aspects of the present disclosure.

[0602] Figure 465 is another illustration of an AOC symbolically showing a chip overview and including the relationship of antennas and circuits on the chip according to some aspects of the present disclosure.

[0603] Figure 466 A block diagram illustrating an example machine that can perform any one or more of the techniques or methods discussed herein, according to some aspects of the present disclosure.

[0604] Figure 467 Protocol functions that may be implemented in a wireless communication device according to some aspects of the present disclosure are shown.

[0605] Figure 468 Various protocol entities that may be implemented in conjunction with a wireless communication device or a wireless communication system according to some aspects of the present disclosure are shown.

[0606] Figure 469 A medium access control (MAC) entity is shown that may be used to implement medium access control layer functionality according to some aspects of the present disclosure.

[0607] Figure 470A and Figure 470B It is shown that some aspects of the present disclosure can be Figure 469 The format of the PDU encoded and decoded by the MAC entity.

[0608] Figure 470C , Figure 470D and Figure 470EIt shows that some aspects of the present disclosure can be combined Figure 469 Various subheaders used by the MAC entity.

[0609] Figure 471 Functionality included within a radio link control (RLC) layer entity according to some aspects of the present disclosure is shown.

[0610] Figure 472A A TMD PDU is shown in accordance with some aspects of the present disclosure.

[0611] Figure 472B and Figure 472C A UMD PDU is shown in accordance with some aspects of the present disclosure.

[0612] Figure 472D and Figure 472E An AMD PDU is shown in accordance with some aspects of the present disclosure.

[0613] Figure 472F A STATUS PDU is shown in accordance with some aspects of the present disclosure.

[0614] Figure 473 Aspects of functionality that may be included within a Packet Data Convergence Protocol (PDCP) layer entity according to some aspects of the present disclosure are shown.

[0615] Figure 474 PDCP PDUs that may be sent and received by a PDCP entity according to some aspects of the present disclosure are shown.

[0616] Figure 475 Aspects of communications between instances of a radio resource control (RRC) layer according to some aspects of the present disclosure are shown.

[0617] Figure 476 States of RRC that may be implemented in a user equipment (UE) according to some aspects of the present disclosure are shown. DETAILED DESCRIPTION

[0618] As 5G mmWave-based communications progress, several challenges have evolved (e.g., limited communication distance, directivity of antenna systems, achieving desired directivity and beamforming for large antenna arrays, signal attenuation due to atmospheric attenuation losses and high attenuation through solid materials). The techniques described herein may be used in conjunction with digital baseband circuits, transmit circuits, receive circuits, radio frequency circuits, protocol processing circuits, and antenna arrays to address challenges associated with 5G mmWave-based communications.

[0619] Discussions herein utilizing terms such as, for example, "process," "compute," "calculate," "determine," "establish," "analyze," "examine," and the like may refer to operations and / or processing of a computer, computing platform, computing system, or other electronic computing device that manipulates and / or transforms data represented by physical (e.g., electronic) quantities within a computer's registers and / or memory into other data similarly represented by physical quantities within a computer's registers and / or memory or another information storage medium that may store instructions to perform the operations and / or processing.

[0620] As used herein, the terms "plurality" and "number" include, for example, "many" or "two or more." For example, "a plurality of items" includes two or more items.

[0621] References to "one aspect," "an aspect," "example aspects," "some aspects," "exemplary aspects," "various aspects," etc. indicate that the aspects so described may include particular features, structures, or characteristics, but not every aspect must include the particular features, structures, or characteristics. Furthermore, repeated use of the phrase "in one aspect" may refer to the same aspect, but does not necessarily do so.

[0622] As used herein, unless otherwise specified, the use of the ordinal adjectives "first," "second," "third," etc., to describe common objects indicates merely that different instances of the same object are referred to and is not intended to imply that the objects described must be ordered in a given sequence, temporally, spatially, or in any other manner.

[0623] Some aspects may be used in conjunction with various devices and systems, such as user equipment (UE), mobile device (MD), wireless station (STA), personal computer (PC), desktop computer, mobile computer, laptop computer, notebook computer, tablet computer, server computer, handheld computer, sensor device, Internet of Things (IoT) device, wearable device, handheld device, personal digital assistant (PDA) device, handheld PDA device, on-board device, off-board device, hybrid device, on-board device, off-board device, mobile or portable device, consumer device, non-mobile or non-portable device, wireless communication station, wireless communication device, wireless access point (AP), wired or wireless router, wired or wireless modem, video device, audio device, audio-video (A / V) device, wired or wireless network, wireless area network, wireless video area network (WVAN), local area network (LAN), wireless LAN (WLAN), personal area network (PAN), wireless PAN (WPAN), etc.

[0624] It can, for example, be combined with existing IEEE 802.11 standards (including IEEE 802.11-2016, IEEE Standard for Information technology--Telecommunications and information exchange between systems Local and metropolitan area networks--Specific requirements Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, December 7, 2016); IEEE 802.11ay(P802.11ayStandard for Information Technology--Telecommunications andInformationExchange Between Systems Local and Metropolitan Area Networks--SpecificRequirements Part 11:Wireless LAN Medium Access Control(MAC)and PhysicalLayer(PHY)Specifications--Amendment:Enhanced Throughput for Operation inLicense-Exempt Bands Above 45GHz)) and / or its future versions and / or derivatives, and / or devices and / or networks operating according to existing and / or WiFi Alliance (WFA) point-to-point (P2P) specifications (including WiFi P2P technical specification, version 1.5, August 4, 2015) and / or its future versions and / or derivatives, and / or devices and / or networks operating according to existing Wireless Gigabit Alliance (WGA) specifications (including Wireless Gigabit Alliance, Inc WiGig MAC and PHY Specification Version 1.1, April 2011, Final specification) and / or its future versions and / or derivatives, and / or devices and / or networks operating according to existing cellular specifications and / or protocols (e.g., 3rd Generation Partnership Project (3GPP), 3GPP Long Term Evolution (LTE)) and / or its future versions and / or derivatives, units and / or devices as part of the above networks, etc. use some aspects. .

[0625] Some aspects may be used in conjunction with one-way and / or two-way radio communication systems, cellular radiotelephone communication systems, mobile phones, cellular phones, wireless phones, personal communication system (PCS) devices, PDA devices including wireless communication devices, mobile or portable global positioning system (GPS) devices, devices including GPS receivers or transceivers or chips, devices including RFID elements or chips, multiple-input multiple-output (MIMO) transceivers or devices, single-input multiple-output (SIMO) transceivers or devices, multiple-input single-output (MISO) transceivers or devices, devices with one or more internal antennas and / or external antennas, digital video broadcasting (DVB) devices or systems, multi-standard radio devices or systems, wired or wireless handheld devices (e.g., smart phones), wireless application protocol (WAP) devices, etc.

[0626] One or more types of wireless communication signals and / or systems (e.g., radio frequency (RF), infrared (IR), frequency division multiplexing (FDM), orthogonal FDM (OFDM), orthogonal frequency division multiple access (OFDMA), space division multiple access (SDMA), FDM time division multiplexing (TDM), time division multiple access (TDMA), multi-user MIMO (MU-MIMO), extended TDMA (E-TDMA), general packet radio service (GPRS), extended GPRS, code division multiple access (CDMA), wideband CDMA (WCDMA), CDMA Some aspects may be used in various other devices, systems and / or networks.

[0627] As used herein, the term "wireless device" includes, for example, a device with wireless communication capabilities, a communication device with wireless communication capabilities, a communication station with wireless communication capabilities, a portable or non-portable device with wireless communication capabilities, etc. In some exemplary aspects, a wireless device may be or may include a peripheral integrated with a computer or a peripheral attached to a computer. In some exemplary aspects, the term "wireless device" may optionally include a wireless service.

[0628] The term "transmit" used herein with respect to communication signals includes: sending communication signals and / or receiving communication signals. For example, a communication unit capable of transmitting communication signals may include a transmitter for sending communication signals to at least one other communication unit and / or a communication receiver for receiving communication signals from at least one other communication unit. The verb "transmit" may be used to refer to the action of sending and / or the action of receiving. In one example, the phrase "transmitting a signal" may refer to the action of sending a signal by a first device, and may not necessarily include the action of receiving a signal by a second device. In another example, the phrase "transmitting a signal" may refer to the action of receiving a signal by a first device, and may not necessarily include the action of sending a signal by a second device.

[0629] Some exemplary aspects may be used in conjunction with a WLAN (eg, a WiFi network). Other aspects may be used in conjunction with any other suitable wireless communication network (eg, a wireless area network, a "piconet," a WPAN, a WVAN, etc.).

[0630] Some exemplary aspects may be used in conjunction with a wireless communication network that communicates over a frequency band greater than 45 gigahertz (GHz), such as 60 GHz. However, other aspects may be implemented using any other suitable wireless communication frequency band, such as an extremely high frequency (EHF) frequency band, a millimeter wave (mmWave) frequency band (e.g., a frequency band within a frequency band between 20 GHz and 300 GHz, a frequency band greater than 45 GHZ, a frequency band less than 20 GHZ (e.g., a Sub 1 GHz (S1G) frequency band, a 2.4 GHz frequency band, a 5 GHZ frequency band, a WLAN frequency band, a WPAN frequency band, a frequency band according to the WGA specification, etc.)).

[0631] As used herein, the term "circuitry" may refer to, be part of, or include, for example, an application specific integrated circuit ("ASIC"), an integrated circuit, an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, and / or other suitable hardware components that provide the described functionality. In some aspects, the circuit may include logic that is at least partially operable in hardware. In some aspects, the circuit may be implemented as part of and / or in the form of a radio virtual machine (RVM), for example, implemented as part of a radio processor (RP) configured to execute code to configure one or more operations and / or functions of one or more radio components.

[0632] The term "logic" may refer to, for example, computing logic embedded in the circuits of a computing device and / or computing logic stored in the memory of a computing device. For example, the logic may be accessible by a processor of a computing device to execute the computing logic, thereby performing computing functions and / or operations. In one example, the logic may be embedded in various types of memory and / or firmware (e.g., silicon blocks of various chips and / or processors). The logic may be included in various circuits (e.g., radio circuits, receiver circuits, control circuits, transmitter circuits, transceiver circuits, processor circuits, etc.), and / or implemented as part thereof. In one example, the logic may be embedded in volatile memory and / or non-volatile memory (including random access memory, read-only memory, programmable memory, magnetic memory, flash memory, persistent memory, etc.). One or more processors may execute logic using, for example, memory (e.g., registers, buffers, heaps, etc.) coupled to one or more processors necessary for executing the logic.

[0633] As used herein, the term "antenna" may include any suitable configuration, structure, and / or arrangement of one or more antenna elements, components, units, assemblies, and / or arrays. In some aspects, an antenna may implement transmit and receive functions using separate transmit and receive antenna elements. In some aspects, an antenna may implement transmit and receive functions using common and / or integrated transmit / receive elements. Antennas may include, for example, phased array antennas, single element antennas, switched beam antenna assemblies, and the like.

[0634] As used herein, the phrase "point-to-point (PTP or P2P) communication" may relate to device-to-device communication over a wireless link between devices ("point-to-point link"). PTP communication may include, for example, WiFi Direct (WFD) communication (e.g., WFD point-to-point (P2P) communication), wireless communication over a direct link within a Quality of Service (QoS) Basic Service Set (BSS), a Tunneled Direct Link Setup (TDLS) link, STA-to-STA communication in an Independent Basic Service Set (IBSS), and the like.

[0635] Some exemplary aspects are described herein with respect to WiFi communications. However, other aspects may be implemented with respect to any other communication schemes, networks, standards, and / or protocols.

[0636]

[0013] In some demonstrative aspects, a wireless communication device may implement a millimeter wave (mmWave) radio front end module (RFEM), e.g., as described below.

[0637] Millimeter wave can be defined as spanning a frequency range from about 30 GHz to about 300 GHz, and in practice currently covers several discrete licensed and unlicensed frequency bands.

[0638] Currently available unlicensed mmWave bands are in the vicinity of 60 GHz. Licensed bands may include 28 GHz, 39 GHz, 73 GHz, and 120 GHz. The availability of these bands and the specific frequency range of each band vary with regulatory authority, and in some cases (particularly for licensed band operations), there is still significant uncertainty regarding the regulations of some countries. Challenges associated with mmWave-based cellular communications include limited distances, directivity of antennas at distances, signal loss due to the use of conventional cables rather than traces, and challenges with integrating multiple antennas for beamforming. These challenges are addressed in this patent discussed below according to some aspects, and may include the use of polarization innovations, traces and other lines to avoid signal loss, and improved capabilities for use in beamforming.

[0639] Figure 1A An exemplary user device according to some aspects is shown. The user device 100 may include a mobile device in some aspects and include an application processor 105, a baseband processor 110 (also referred to as a baseband subsystem), a radio front end module (RFEM) 115, a memory 120, a connectivity subsystem 125, a near field communication (NFC) controller 130, an audio driver 135, a camera driver 140, a touch screen 145, a display driver 150, a sensor 155, a removable memory 160, a power management integrated circuit (PMIC) 165, and a smart battery 170.

[0640] In some aspects, the application processor 105 may include, for example, one or more central processing unit (CPU) cores and one or more of the following: cache memory, a low dropout regulator (LDO), an interrupt controller, a serial interface (e.g., SPI), I2C or a general programmable serial interface subsystem, a real-time clock (RTC), a timer-counter including interval and watchdog timers, general purpose IO, a memory card controller (e.g., SD / MMC, etc.), a USB interface, a MIPI interface, and / or a Joint Test Access Group (JTAG) test access port.

[0641] In some aspects, baseband processor 110 may be implemented as, for example, a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and / or a multi-chip module including two or more integrated circuits.

[0642] Applications of mmWave technology may include, for example, WiGig and future 5G, but mmWave technology may be applicable to a variety of telecommunication systems. mmWave technology may be particularly attractive for short-range telecommunication systems. WiGig devices operate in the unlicensed 60 GHz band, while 5G mmWave should initially operate in the licensed 28 GHz and 39 GHz bands. Figure 1B A block diagram of an example baseband subsystem 110 and RFEM 115 in a mmWave system is shown in FIG.

[0643] Figure 1B It shows that some aspects of the present disclosure can be combined Figure 1A The device 100 uses a mmWave system 100A. The system 100A includes two components: a baseband subsystem 110 and one or more radio modules (RFEM) 115. The RFEM 115 can be connected to the baseband subsystem 110 via a single coaxial cable 190 that provides a modulated intermediate frequency (IF) signal, DC power, a clock signal, and a control signal.

[0644] Although the baseband subsystem 110 is not shown in its entirety, Figure 1B1 shows an implementation of an analog front end. This includes a transmitter (TX) section 191A with an upconverter 173 for changing to an intermediate frequency (IF) (around 10 GHz in the current implementation), a receiver (RX) section 191B with a downconversion 175 from IF to baseband, a control and multiplexing circuit 177 including a combiner for multiplexing / demultiplexing transmit and receive signals onto a single cable 190. In addition, a power tee circuit 192 (which includes discrete components) is included on the baseband circuit board to provide DC power for the RFEM 115. In some aspects, the combination of the TX section and the RX section can be referred to as a transceiver, to which one or more antennas or antenna arrays of the type described herein can be coupled.

[0645] RFEM 115 may be a small circuit board including multiple printed antennas and one or more RF devices containing multiple radio chains, including up / down conversion 174 to millimeter wave frequencies, power combiner / divider 176, programmable phase shift 178, and power amplifier (PA) 180, low noise amplifier (LNA) 182, and control and power management circuits 184A and 184B. This arrangement may be different from Wi-Fi or cellular implementations that typically have the RF and baseband functions all integrated into a single unit and have only the antennas remotely connected via coaxial cables.

[0646] This architectural difference can be driven by very large power losses in coaxial cables at mmWave frequencies. These power losses can reduce transmit power at the antenna and reduce receive sensitivity. To avoid this problem, in some aspects, the PA 180 and LNA 182 can be moved to the RFEM 115 with an integrated antenna. In addition, the RFEM 115 can include an up / down conversion 174 so that the IF signal on the coaxial cable 190 can be at a lower frequency. Additional system context for mmWave 5G devices, technologies, and features is discussed below.

[0647] Figure 2 An exemplary base station or infrastructure equipment radio head according to some aspects is shown. The base station radio head 200 may include one or more of the following: an application processor 205, a baseband processor 210, one or more radio front-end modules 215, a memory 220, a power management integrated circuit (PMIC) 225, a power tee circuit 230, a network controller 235, a network interface connector 240, a satellite navigation receiver (e.g., a GPS receiver) 245, and a user interface 250.

[0648] In some aspects, the application processor 205 may include, for example, one or more CPU cores and one or more of the following: cache memory, a low dropout regulator (LDO), an interrupt controller, a serial interface (e.g., SPI), an I 2 C or general-purpose programmable serial interface subsystem, real-time clock (RTC), timer-counters including interval and watchdog timers, general-purpose IO, memory card controller (such as SD / MMC, etc.), USB interface, MIPI interface, and Joint Test Access Group (JTAG) test access port.

[0649] In some aspects, baseband processor 210 may be implemented as, for example, a lower soldered substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, or a multi-chip subsystem including two or more integrated circuits.

[0650] In some aspects, the memory 220 may include one or more of the following: volatile memory including dynamic random access memory (DRAM) and / or synchronous DRAM (SDRAM) and non-volatile memory (NVM) including high-speed electrically erasable memory (commonly known as flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM) and / or three-dimensional cross-point memory. The memory 220 may be implemented as one or more of the following: a solder-down packaged integrated circuit, a socketed memory module, and an inserted memory card.

[0651] In some aspects, the power management integrated circuit 225 may include one or more of the following: a voltage regulator, a surge protector, a power alarm detection circuit, and one or more backup power supplies (e.g., a battery or capacitor). The power alarm detection circuit may detect one or more of a blown (undervoltage) and a surge (overvoltage) condition.

[0652] In some aspects, the power tee circuit 230 can provide electrical power drawn from a network cable. The power tee circuit 230 can provide both power supply and data connectivity to the base station radio head 200 using a single cable.

[0653] In some aspects, the network controller 235 can provide connectivity to the network using a standard network interface protocol (e.g., Ethernet). Network connectivity can be provided using a physical connection that is one of electrical (commonly referred to as a copper interconnect), optical, or wireless.

[0654] In some aspects, the satellite navigation receiver 245 may include circuitry for receiving and decoding signals transmitted by one or more navigation satellite constellations, such as the Global Positioning System (GPS), Globalnaya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Galileo, and / or BeiDou. The receiver 245 may provide data, which may include one or more of position data or time data, to the application processor 205. The time data may be used by the application processor 205 to synchronize operations with other radio base stations or infrastructure equipment.

[0655] In some aspects, the user interface 250 may include one or more of the buttons. The buttons may include a reset button. The user interface 250 may also include one or more indicators (eg, LEDs) and a display screen.

[0656] Figure 3A illustrates an exemplary mmWave communication circuit according to some aspects; Figure 3B and Figure 3C Showing some aspects Figure 3A aspects of the transmitting circuit shown; Figure 3D Showing some aspects Figure 3A aspects of the RF circuit shown; Figure 3E Showing some aspects Figure 3A aspects of the receiving circuit shown. Figure 3A The illustrated millimeter wave communication circuit 300 may alternatively be grouped according to function. Figure 3A The components shown are provided here for illustrative purposes and may include Figure 3A Other components not shown.

[0657] The millimeter wave communication circuit 300 may include a protocol processing circuit 305 (or processor) or other components for processing. The protocol processing circuit 305 may implement one or more of medium access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), radio resource control (RRC), and non-access stratum (NAS) functions. The protocol processing circuit 305 may include one or more processing cores for executing instructions and one or more memory structures for storing program and data information.

[0658] The millimeter wave communication circuit 300 may also include a digital baseband circuit 310. The digital baseband circuit 310 may implement physical layer (PHY) functions including one or more of the following: hybrid automatic repeat request (HARQ) functions, scrambling and / or descrambling, encoding and / or decoding, layer mapping and / or demapping, modulation symbol mapping, received symbol and / or bit metric determination, multi-antenna port precoding and / or decoding (which may include one or more of space-time, space-frequency or space coding), reference signal generation and / or detection, preamble sequence generation and / or decoding, synchronization sequence generation and / or detection, control channel signal blind decoding and other related functions.

[0659] The millimeter wave communication circuit 300 may also include a transmit circuit 315, a receive circuit 320, and / or an antenna array circuit 330. The millimeter wave communication circuit 300 may also include an RF circuit 325. In some aspects, the RF circuit 325 may include one or more parallel RF chains for transmitting and / or receiving. Each of the RF chains may be connected to one or more antennas of the antenna array circuit 330.

[0660] In some aspects, protocol processing circuitry 305 may include one or more instances of control circuitry. The control circuitry may provide control functionality for one or more of digital baseband circuitry 310, transmit circuitry 315, receive circuitry 320, and / or RF circuitry 325.

[0661] Figure 3B and Figure 3C Showing some aspects Figure 3A aspects of the transmitting circuit shown. Figure 3B The illustrated transmit circuit 315 may include one or more of a digital-to-analog converter (DAC) 340, an analog baseband circuit 345, an up-conversion circuit 350, and / or a filtering and amplification circuit 355. The DAC 340 may convert a digital signal into an analog signal. The analog baseband circuit 345 may perform a plurality of functions as indicated below. The up-conversion circuit 350 may up-convert a baseband signal from the analog baseband circuit 345 to an RF frequency (e.g., a mmWave frequency). The filtering and amplification circuit 355 may filter and amplify the analog signal. A control signal may be provided between the protocol processing circuit 305 and one or more of the DAC 340, the analog baseband circuit 345, the up-conversion circuit 350, and / or the filtering and amplification circuit 355.

[0662] Figure 3CThe illustrated transmit circuitry 315 may include digital transmit circuitry 365 and RF circuitry 370. In some aspects, signals from filtering and amplification circuitry 355 may be provided to digital transmit circuitry 365. As above, control signals may be provided between protocol processing circuitry 305 and one or more of digital transmit circuitry 365 and RF circuitry 370.

[0663] Figure 3D Showing some aspects Figure 3A Aspects of RF circuitry shown. RF circuitry 325 may include one or more instances of radio chain circuitry 372 (which in some aspects may include one or more filters, power amplifiers, low noise amplifiers, programmable phase shifters, and power supplies).

[0664] The radio frequency circuit 325 may also include a power combining and distribution circuit 374 in some aspects. In some aspects, the power combining and distribution circuit 374 may operate bidirectionally, so that the same physical circuit may be configured to operate as a power divider when the device is transmitting and operate as a power combiner when the device is receiving. In some aspects, the power combining and distribution circuit 374 may include one or more completely or partially separated circuits for performing power distribution when the device is transmitting and performing power combination when the device is receiving. In some aspects, the power combining and distribution circuit 374 may include a passive circuit comprising one or more two-way power dividers / combiners arranged in a tree shape. In some aspects, the power combining and distribution circuit 374 may include an active circuit comprising an amplifier circuit.

[0665] In some aspects, the RF circuit 325 can be connected to Figure 3A RF circuit 325 may be connected to transmit circuit 315 and receive circuit 320 via one or more radio link interfaces 376 and / or combined radio link interface 378. In some aspects, one or more radio interfaces 376 may provide one or more interfaces for one or more receive or transmit signals each associated with a single antenna structure. In some aspects, combined radio link interface 378 may provide a single interface for one or more receive or transmit signals each associated with a group of antenna structures.

[0666] Figure 3E Showing some aspects Figure 3A384. In some aspects, the one or more parallel receiving circuits 382 and the one or more combined receiving circuits 384 may include one or more intermediate frequency (IF) down-conversion circuits 386, IF processing circuits 388, baseband down-conversion circuits 390, baseband processing circuits 392, and analog-to-digital converter (ADC) circuits 394. As used herein, the term "intermediate frequency" refers to the frequency to which the carrier frequency (or frequency signal) is shifted in the intermediate steps of transmission, reception, and / or signal processing. The IF down-conversion circuit 386 may convert the received RF signal to IF. The IF processing circuit 388 may process the IF signal, for example, via filtering and amplification. The baseband down-conversion circuit 390 may convert the signal from the IF processing circuit 388 to baseband. The baseband processing circuit 392 may process the baseband signal, for example, via filtering and amplification. The ADC circuit 394 may convert the processed analog baseband signal into a digital signal.

[0667] Figure 4 Showing some aspects Figure 3A In one aspect, ( Figure 4 425 described in Figure 3A The RF circuit 325 in may include one or more of an IF interface circuit 405, a filtering circuit 410, an up-conversion and down-conversion circuit 415, a synthesizer circuit 420, a filtering and amplification circuit 424, a power combining and distribution circuit 430, and a radio chain circuit 435.

[0668] Figure 5A and Figure 5B Showing some aspects Figure 1A and Figure 2 Aspects of a radio front end module that may be used in the circuits shown. The RFEM 500 includes a millimeter wave RFEM 505 and one or more above-6 GHz radio frequency integrated circuits (RFICs) 515 and / or one or more sub-6 GHz RFICs 522. In this aspect, the one or more above-6 GHz RFICs 515 and / or the one or more sub-6 GHz RFICs 522 may be physically separated from the millimeter wave RFEM 505. The RFICs 515 and 522 may include connections to one or more antennas 520. The RFEM 505 may include multiple antennas 510.

[0669] Figure 5BAn alternative aspect of a radio front end module according to some aspects is shown. In this aspect, both mmWave and sub-6 GHz radio functionality can be implemented in the same physical radio front end module (RFEM) 530. The RFEM 530 can include both a mmWave antenna 535 and a sub-6 GHz antenna 540.

[0670] Figure 6 Showing some aspects Figure 1A or Figure 2 A multi-protocol baseband processor 600 that may be used in the illustrated systems and circuits. In one aspect, the baseband processor may include one or more digital baseband subsystems 640A, 640B, 640C, 640D, also collectively referred to herein as digital baseband subsystems 640.

[0671] In an aspect, the one or more digital baseband subsystems 640A, 640B, 640C, 640D may be coupled to one or more of the CPU subsystem 670, the audio subsystem 675, and the interface subsystem 680 via the interconnect subsystem 665. In an aspect, the one or more digital baseband subsystems 640 may be coupled to one or more of each of the digital baseband interfaces 660A, 660B and the mixed signal baseband subsystems 635A, 635B via the interconnect subsystem 645.

[0672] In one aspect, interconnect subsystems 665 and 645 may each include one or more of each of a bus point-to-point connection and a network-on-chip (NOC) structure. In one aspect, audio subsystem 675 may include one or more of digital signal processing circuits, buffer memory, program memory, voice processing accelerator circuits, data converter circuits (e.g., analog to digital and digital to analog converter circuits), and analog circuits including one or more of amplifiers and filters.

[0673] Figure 7 An exemplary mixed-signal baseband subsystem 700 is shown according to some aspects. In one aspect, the mixed-signal baseband subsystem 700 includes one or more of an IF interface 705, an analog IF subsystem 710, a downconverter and upconverter subsystem 720, an analog baseband subsystem 730, a data converter subsystem 735, a synthesizer 725, and a control subsystem 740.

[0674] Fig. 8A A digital baseband processing subsystem 801 is shown in accordance with some aspects. Figure 8B Alternative aspects of a digital baseband processing subsystem 802 are shown in accordance with some aspects.

[0675] exist Fig. 8AIn one aspect, the digital baseband processing subsystem 801 may include one or more of each of the digital signal processor (DSP) subsystems 805A, 805B, ... 805N, an interconnect subsystem 835, a boot loader subsystem 810, a shared memory subsystem 815, a digital I / O subsystem 820, and a digital baseband interface subsystem 825.

[0676] exist Figure 8B In one aspect, the digital baseband processing subsystem 802 may include one or more of each of the accelerator subsystems 845A, 845B, ... 845N, the buffer memories 850A, 850B, ... 850N, the interconnect subsystem 835, the shared memory subsystem 815, the digital I / O subsystem 820, the controller subsystem 840, and the digital baseband interface subsystem 825.

[0677] In one aspect, the boot loader subsystem 810 may include digital logic circuitry configured to perform configuration of a program memory and an operating state associated with each of the one or more DSP subsystems 805. Configuration of the program memory of each of the one or more DSP subsystems 805 may include loading executable program code from storage external to the digital baseband processing subsystems 801 and 802. Configuration of the operating state associated with each of the one or more DSP subsystems 805 may include one or more of the following steps: setting a state of at least one DSP core that may be incorporated into each of the one or more DSP subsystems 805 to a state in which it is not running, and setting a state of at least one DSP core that may be incorporated into each of the one or more DSP subsystems 805 to a state in which it begins executing program code starting from a predetermined memory location.

[0678] In an aspect, the shared memory subsystem 815 may include one or more of read-only memory (ROM), static random access memory (SRAM), embedded dynamic random access memory (eDRAM), and / or non-volatile random access memory (NVRAM).

[0679] In one aspect, the digital I / O subsystem 820 may include a serial interface (e.g., an inter-integrated circuit (I 2C), a serial peripheral interface (SPI) or other 1, 2, or 3 wire serial interface), a parallel interface (e.g., a general purpose input-output (GPIO), a register access interface, and a direct memory access (DMA). In one aspect, the register access interface implemented in the digital I / O subsystem 820 can allow a microprocessor core external to the digital baseband processing subsystem 801 to read and / or write one or more of the control and data registers and memories. In one aspect, the DMA logic implemented in the digital I / O subsystem 820 can allow contiguous blocks of data to be transferred between memory locations, including memory locations internal and external to the digital baseband processing subsystem 801.

[0680] In one aspect, the digital baseband interface subsystem 825 may provide for the transfer of digital baseband samples between the baseband processing subsystem and a mixed signal baseband or radio frequency circuit external to the digital baseband processing subsystem 801. In one aspect, the digital baseband samples transferred by the digital baseband interface subsystem 825 may include in-phase and quadrature (I / Q) samples.

[0681] In one aspect, the controller subsystem 840 may include one or more of each of the control and status registers and the control state machine. In one aspect, the control and status registers may be accessed via a register interface and may provide one or more of: starting and stopping the operation of the control state machine, resetting the control state machine to a default state, configuring optional processing features, and / or configuring the generation of interrupts and reporting the status of operations. In one aspect, each of the one or more control state machines may control the order of operation of each of the one or more accelerator subsystems 845. There may be multiple accelerator subsystems in the same baseband subsystem. Fig. 8A and Figure 8B Examples of implementations of both.

[0682] Fig. 9 A digital signal processor (DSP) subsystem 900 is shown in accordance with some aspects.

[0683] In one aspect, the DSP subsystem 900 may include one or more of each of a DSP core subsystem 905, a local memory 910, a direct memory access (DMA) subsystem 915, an accelerator subsystem 920A, 920B...920N, an external interface subsystem 925, a power management circuit 930, and an interconnect subsystem 935.

[0684] In an aspect, local memory 910 may include one or more of each of a read-only memory, a static random access memory, or an embedded dynamic random access memory.

[0685] In one aspect, DMA subsystem 915 may provide registers and control state machine circuitry suitable for transferring blocks of data between memory locations, including memory locations external and internal to DSP subsystem 900 .

[0686] In one aspect, the external interface subsystem 925 may provide access by a microprocessor system external to the DSP subsystem 900 to one or more of memory, control registers, and status registers that may be implemented in the DSP subsystem 900. In one aspect, the external interface subsystem 925 may provide for transfer of data between the local memory 910 and storage external to the DSP subsystem 900 under the control of one or more of the DMA subsystem 915 and the DSP core subsystem 905.

[0687] Fig. 10A An example of an accelerator subsystem 1000 is shown in accordance with some aspects. Fig. 10B An example of an accelerator subsystem 1000 is shown in accordance with some aspects.

[0688] In an aspect, the accelerator subsystem 1000 may include one or more of each of a control state machine 1005, control registers 1010, a memory interface 1020, a scratchpad memory 1025, compute engines 1030A...1030N, and data flow interfaces 1035A, 1035B.

[0689] In one aspect, the control registers 1010 may configure and control the operation of the accelerator subsystem 1000, which may include one or more of: enabling or disabling an operation by gating register bits, pausing an ongoing operation by writing to a pause register bit, providing parameters for configuring a computing operation, providing memory address information for identifying the location of one or more control and data structures, configuring the generation of an interrupt, or other control functions.

[0690] In one aspect, the control state machine 1005 may control the sequence of operations of the accelerator subsystem 1000 .

[0691] Figures 11A-11D Frame formats according to some aspects are shown.

[0692] Fig.11A A periodic radio frame structure 1100 is shown according to some aspects. The radio frame structure 1100 has a predetermined duration and repeats in a periodic manner with a repetition interval equal to the predetermined duration. The radio frame structure 1100 is divided into two or more subframes 1105. In an aspect, the subframes 1105 may be of a predetermined duration that may not be equal. In an alternative aspect, the subframes 1105 may be of a duration that is dynamically determined and varies between subsequent repetitions of the radio frame structure 1100.

[0693] Fig. 11B A periodic radio frame structure using frequency division duplexing (FDD) is shown according to some aspects. In an FDD aspect, a downlink radio frame structure 1110 is sent by a base station or infrastructure equipment to one or more mobile devices, and an uplink radio frame structure 1115 is sent by a combination of one or more mobile devices to a base station.

[0694] Fig.11D Another example of a radio frame structure that may be used in some aspects is shown. In this example, the radio frame 1100 has a duration of 10 ms. The radio frame 1100 is divided into time slots 1125, 1135, each of which has a duration of 0.1 ms and is numbered from 0 to 99. Additionally, each pair of adjacent time slots 1125, 1135 numbered 2i and 2i+1 (where i is an integer) is referred to as a subframe.

[0695] In some aspects, T s The unit represents the time interval, where T s Defined as 1 / (75,000×2048) seconds. Fig.11D In the , a radio frame is defined as having a duration of 1,536,600xT s , and a time slot is defined as having a duration of 15,366xT s .

[0696] In use Fig.11D In some aspects of the radio frame format of the present invention, each subframe may include a combination of one or more of downlink control information, downlink data information, uplink control information, and / or uplink data information. The combination of information type and direction may be independently selected for each subframe.

[0697] Fig.11E Showing an example of a radio frame structure that may be used in some aspects, a downlink frame 1150 and an uplink frame 1155 are shown. According to some aspects, the downlink frame 1150 and the uplink frame 1155 may have a duration of 10 ms, and the uplink frame 1155 may be sent with a timing advance 1160 relative to the downlink frame 1150.

[0698] In accordance with some aspects, downlink frame 1150 and uplink frame 1155 can each be divided into two or more subframes 1165, which can be 1 ms in duration. In accordance with some aspects, each subframe 1165 can include one or more time slots 1170.

[0699] In some aspects, according to Fig.11D and Fig.11E For example, you can press Ts The unit represents the time interval.

[0700] according to Fig.11D The example timing shown is some aspects of T s It can be defined as 1 / (30,720×1000) seconds. Fig.11D In some aspects, a radio frame may be defined as having a duration of 30,720.T s , and a time slot can be defined as having a duration of 15,360.T s .

[0701] according to Fig.11E Some aspects of the examples shown, T S It can be defined as Ts=1 / (Δfmax.Nf), where Δfmax=480×103 and Nf=4,096.

[0702] according to Fig.11E Some aspects of the illustrated examples may determine the number of time slots based on a numerology parameter that may be related to the frequency spacing between subcarriers of a multicarrier signal used for transmission.

[0703] FIG. 12A to FIG. 12C An example of a constellation diagram design for a single carrier modulation scheme that may be transmitted or received according to some aspects is shown. Constellation points 1200 are shown on orthogonal in-phase and quadrature axes that respectively represent the amplitude of a sinusoid at the carrier frequency and are separated by up to 90 degrees of phase from each other.

[0704] Fig. 12A The representation of a constellation comprising two points 1200 is called binary phase shift keying (BPSK). Fig. 12B denoted as a constellation comprising four points 1200, known as quadrature phase shift keying (QPSK). Fig. 12C A constellation comprising 16 points 1200 is referred to as quadrature amplitude modulation (QAM) with 16 points (16QAM or QAM16). Higher order modulation constellations comprising, for example, 64, 256 or 1024 points may be similarly constructed.

[0705] exist Figure 12A-12C In the constellation described in , binary codes 1220 are assigned to points 1200 of the constellation using a scheme in which the closest neighboring points 1200 (i.e., pairs of points 1200 that are separated from each other by a minimum Euclidean distance) have assigned binary codes 1220 that differ by only one binary digit. For example, in Fig. 12C , point allocation code 1000 has closest neighboring point allocation codes 1001, 0000, 1100, and 1010, each of which differs from 1000 by only one bit.

[0706] Fig.13A and Fig. 13B Examples of alternative constellation designs for single carrier modulation schemes that may be transmitted and received in accordance with some aspects are shown. Fig.13A The constellation points 1300 and 1315 are shown on orthogonal in-phase and quadrature axes, respectively representing the amplitude of the sinusoid at the carrier frequency and separated in phase by 90 degrees from each other.

[0707] In one aspect, Fig.13A The example constellation points 1300 shown may be arranged in a square grid, and may be arranged such that there is an equal distance on the in-phase and quadrature planes between each pair of closest neighboring constellation points. In one aspect, the constellation points 1300 may be chosen so that there is a predetermined maximum distance from the origin of the in-phase and quadrature planes for any allowed constellation point, represented by circle 1310. In one aspect, the set of allowed constellation points may exclude constellation points that would fall within square regions 1305 at the corners of the square grid.

[0708] Fig. 13B The constellation points 1300 and 1315 are shown on orthogonal in-phase and quadrature axes, respectively representing the amplitude of the sinusoid at the carrier frequency and separated by 90 degrees of phase from each other. In one aspect, the constellation points 1315 are grouped into sets of two or more constellation points, with the points of each set arranged at an equal distance from the origin of the in-phase and quadrature planes and located on one of a set of circles 1320 centered at the origin.

[0709] Fig.14 An example of a system for generating a multi-carrier baseband signal for transmission according to some aspects is shown. In this aspect, data 1430 can be input to an encoder 1400 to generate encoded data 1435. The encoder 1400 can perform a combination of one or more of error detection, error correction, rate matching, and interleaving. The encoder 1400 can also perform a scrambling step.

[0710] In an aspect, the encoded data 1435 may be input to the modulation mapper 1405 to generate complex-valued modulation symbols 1440. The modulation mapper 1405 may map a group of one or more binary digits selected from the encoded data 1435 to complex-valued modulation symbols according to one or more mapping tables.

[0711] In one aspect, the complex-valued modulation symbols 1440 may be input to the layer mapper 1410 to be mapped into one or more layer-mapped modulation symbol streams 1445. The stream of complex-valued modulation symbols 1440 is denoted as d(i), where i represents the sequence number index, and the one or more streams 1445 of layer-mapped symbols are denoted as x (k)(i), where k represents the index of the number of streams and i represents the index of the number of sequences. The layer mapping function for a single layer can be expressed as:

[0712] x (0) (i) = d(i)

[0713] And the layer mapping for two layers can be expressed as:

[0714] x (0) (i) = d(2i)

[0715] x (1) (i) = d(2i+1)

[0716] The layer mapping may be similarly represented for more than two layers.

[0717] In an aspect, one or more of the layer-mapped modulation symbol streams 1445 may be input to a precoder 1415, which generates one or more streams of precoded symbols 1450. The one or more streams 1445 of layer-mapped symbols are represented as blocks of vectors:

[0718] [x (0) (i)…x ( υ- 1) (i)]T

[0719] Among them, i represents the range from 0 to The output is represented as a block of vectors:

[0720] [z (0) (i)…z (P-1) (i)] T

[0721] Among them, i represents the range from 0 to The number of sequences in the index.

[0722] The precoding operation may be configured to include one of: direct mapping using a single antenna port, transmit diversity using space-time block coding, or spatial multiplexing.

[0723] In an aspect, each stream of precoded symbols 1450 may be input to a resource mapper 1420, which generates a stream of resource mapped symbols 1455. The resource mapper 1420 may map the precoded symbols into frequency domain subcarriers and time domain symbols according to a mapping, which may include continuous block mapping, randomized mapping, or sparse mapping depending on a mapping code.

[0724] In one aspect, the resource-mapped symbols 1455 may be input to a multi-carrier generator 1425, which generates time-domain baseband symbols 1460. The multi-carrier generator 1425 may generate the time-domain symbols using, for example, a discrete Fourier transform (DFT), commonly implemented as an inverse fast Fourier transform (FFT), or a filter bank including one or more filters. In one aspect, wherein the resource-mapped symbols 1455 are represented as s k (i), where k is the subcarrier index, i is the symbol number index, and the time domain complex baseband symbol x(t) can be expressed as x(t)=∑ k s k (i)p T (tT sym )exp[j2πf k (tT sym -τ k )], where p T (t) is the prototype filter function, T sym is the start time of the symbol period, τ k is the subcarrier-dependent time offset, f k is the frequency of subcarrier k.

[0725] Prototype function p T (t) can be, for example, a rectangular time-domain pulse, a Gaussian time-domain pulse, or any other suitable function.

[0726] In some aspects, the subcomponents of the transmitted signal comprising subcarriers in the frequency domain and symbol intervals in the time domain may be referred to as resource elements.

[0727] Fig.15 Resource elements 1505 are shown depicted in a grid format according to some aspects. In some aspects, resource elements may be grouped into rectangular blocks including multiple subcarriers (e.g., 12 subcarriers) in the frequency domain and a number P of symbols contained in one slot in the time domain. The number P may be 6, 7, or any other suitable number of symbols. Fig.15 In the description, each resource element 1505 within the resource block 1500 can be indexed as (k, l), where k is the index number of the subcarrier in the range 0 to NxM-1, where N is the number of subcarriers in the resource block and M is the number of resource blocks.

[0728] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D An example of encoding according to some aspects is shown. Fig.16AAn example of an encoding process 1600 that may be used in some aspects is shown. The encoding process 1600 may include one or more physical encoding processes 1605, which may be used to provide encoding for a physical channel that may encode data or control information. The encoding process 1600 may also include multiplexing and interleaving 1635, which generates combined encoded information by combining information from one or more sources that may include one or more of data information and control information and may have been encoded by one or more physical encoding processes 1605. The combined encoded information may be input to a scrambler 1640, which may generate scrambled encoded information.

[0729] The physical coding process 1605 may include one or more of a CRC attachment block 1610, a code block segmentation 1615, a channel coding 1620, a rate matching 1625, and a code block concatenation 1630. The CRC attachment block 1610 may be obtained from the representation {a 0 ,a 1 ,…a A-1 The input bit calculation representation {p 0 ,p 1 ,…,p L-1} to generate the output bit sequence {b 0 ,b 1 ,…,b A+L-1}, thereby using the output sequence bits as coefficients of the polynomial over the finite field GF(2) in the variable D (i.e., the polynomial b 0 D A+L-1 +b 1 D A +L-2 +…+b A+L-2 D 1 +b A+L-1 )) has a predetermined remainder when divided by a predetermined generator polynomial g(D) of order L. In one aspect, the predetermined remainder may be zero, L may be 24, and the predetermined polynomial g(D) may be D 24 +D 23 +D 18 +D 17 +D 14 +D 11 +D 10 +D 7 +D 6 +D 5 +D 4 +D 3 +D+1.

[0730] In some aspects, the processing of code block segmentation 1615 can generate one or more segmented code blocks, each code block including a portion of the data input to code segmentation 1615. Code block segmentation 1615 can have as parameters the minimum and maximum block size constraints determined according to the selected channel coding scheme. Code block segmentation 1615 can add padding bits to one or more output segmented code blocks to ensure that the minimum block size constraint is met. Code block segmentation 1615 can divide the data input to the processing into blocks to ensure that the maximum block size constraint is met. In some aspects, code block segmentation 1615 can append parity bits to each segmented code block. Such appending of parity bits can be determined based on one or more of the selected coding scheme and whether the number of segmented code blocks to be generated is greater than 1.

[0731] In some aspects, the process of channel coding 1620 may generate codewords from the segmented code blocks according to one or more of a plurality of coding schemes. As an example, the channel coding 1620 may use one or more of convolutional coding, tail-biting convolutional coding, parallel concatenated convolutional coding, and polar coding.

[0732] Fig. 16B An encoder 1620 is used that can be used to encode data according to one of a convolutional code and a tail-biting convolutional code in accordance with some aspects.

[0733] According to some aspects, input data 1645 can be sequentially delayed by each of two or more delay elements 1650, generating a data word including elements including the current input data and two or more copies of the current input data, each delayed by a different number of time units. According to some aspects, encoder 1620 can generate one or more outputs 1660, 1665, and 1670, each of which is generated by calculating a linear combination of elements of the data word generated by combining input data 1645 and the outputs of two or more delay elements 1650.

[0734] According to some aspects, the input data may be binary data, and the linear combination may be calculated using one or more XOR functions 1655. According to some aspects, the encoder 1620 may be implemented using software running on a processor, and the delay element 1650 may be implemented by storing the input data 1645 in a memory.

[0735] According to some aspects, a convolutional code may be generated by using convolutional encoder 1620 and initializing delay elements 1650 to predetermined values ​​(which may be all zeros or any other suitable value). According to some aspects, a tail-biting convolutional code may be generated by using convolutional encoder 1620 and initializing delay elements 1650 to the last N bits of a data block (where N is the number of delay elements 1650).

[0736] Fig. 16C , an encoder 16C100 is shown that may be used to encode data according to a parallel concatenated convolutional code (PCCC), which may be referred to as a turbo code, in accordance with some aspects.

[0737] According to some aspects, encoder 16C100 may include interleaver 16C110, upper component encoder 16C115, and lower component encoder 16C117. According to some aspects, upper component encoder 16C115 may generate one or more encoded data streams 16C140 and 16C145 from input data 16C105. According to some aspects, interleaver 16C110 may generate interleaved input data 16C119 from input data 16C105. According to some aspects, lower component encoder 16C117 may generate one or more encoded data streams 16C150 and 16C155 from interleaved input data 16C105.

[0738] According to some aspects, the interleaver 16C110 can output interleaved output data 16C119 having a one-to-one relationship with the data contained in the input data 16C105 but having the data arranged in a different time sequence. According to some aspects, the interleaver 16C110 can be a block interleaver, which can be represented as {c 0 ,c 1 ,…,c K-1 One or more blocks of input data 16C105 of} are taken as input (where each ci is an input data bit and K is the number of bits in each block), and the generated data can be represented as {c Π(1) ,c Π(2) ,…,c Π(K-1)} corresponding to each of one or more of these input blocks. Π(i) is a permutation function, which may be a quadratic form, and which may be expressed as Π(i) = (f 1 i+f 2 i 2 )modK, where f1 and f2 are constants that may depend on the value K of the block size.

[0739] In accordance with some aspects, each of the upper component encoder 16C115 and the lower component encoder 16C117 may include an input bit selector 16C118 that may generate a selected input bit stream 16C119 that may be selected from a linear combination of stored bits during the trellis termination phase and one of the encoder input bit streams during the data encoding phase. In accordance with some aspects, each of the upper component encoder 16C115 and the lower component encoder 16C117 may store bits in two or more delay elements 16C120 arranged to operate as a shift register, the input to the shift register comprising a linear combination of bits from the selected input bit stream 16C119 and previously stored bits, the stored bits being initialized to predetermined values ​​prior to the encoding phase and having predetermined values ​​at the end of the trellis termination phase. In accordance with some aspects, each of the upper component encoder 16C115 and the lower component encoder 16C117 may generate one or more outputs 16C140 and 16C145, each of which may be a linear combination of the stored bits and one of the selected input bitstreams 16C119.

[0740] According to some aspects, each of the upper component encoder 16C115 and the lower component encoder 16C117 can have a transfer function during the encoding stage, which can be expressed as

[0741]

[0742] According to some aspects, encoder 16C100 may be implemented as software instructions running on a processor in combination with a memory for storing data input to interleaver 16C110 and the stored bits of each of upper component encoder 16C115 and lower component encoder 16C117.

[0743] Fig.16D 2 shows an encoder 16D 200 that may be used to encode data bits according to a low density parity check (LDPC) code in accordance with some aspects.

[0744] According to some aspects, data bits 16D230 input to encoder 16D200 may be stored in data bin 16D210 , the stored data bits may be input to parity bit generator 16D220 , and encoded bits 16D240 may be output by parity bit generator 16D220 .

[0745] According to some aspects, the data bits input to the LDPC encoder 16D200 can be represented as c={c 0 ,c 1 ,…,c K-1}, the encoded data bit 16D240 can be expressed as d = {c 0 ,c1 ,…,c k-1 ,p 0 ,p 1 ,…,p D-K-1}, and the parity bit pi can be selected so that Hd T =0, where H is the parity check matrix, K is the number of bits in the block to be encoded, D is the number of encoded bits, and DK is the number of parity check bits.

[0746] According to one aspect, the parity check matrix H can be expressed as:

[0747] in, is a zero matrix or one of the cyclic permutation matrices obtained from the Z×Z identity matrix by cyclically shifting the columns to the right by ai,j, Z is the size of the permutation matrix, the number of bits encoded D is equal to ZM, and the number of bits to be encoded in the block K is equal to ZN.

[0748] Digital polar transmitters (DTx), whose inputs can be amplitude and phase, can be a promising architecture for integrated complementary metal oxide semiconductor (CMOS) radios used in devices for communicating through next-generation systems, because these devices offer potential for, for example, higher efficiency and system-on-chip (SoC) integration. DTx can use amplitude changes and phase changes of the output signal to provide data. However, similar to other transmitters, DTx is limited to lower frequencies (typically <6 GHz) due to the challenges of implementing wideband phase modulators at mmWave frequencies used in next-generation systems and implementing DTx at mmWave speeds. The channel bandwidth for next-generation systems can be on the order of 100 MHz-GHz, and one or both of single-carrier and orthogonal frequency division multiplexing (OFDM)-based modulation are used. That is, while fundamental frequency oscillations can be generated at various channel frequencies, adjusting amplitude and phase at higher frequencies is a concern.

[0749] Additionally, where mmWave frequencies are used, the power efficiency of DTx may be significantly reduced at these frequencies due to the difference in amplitude variation and corresponding peak power efficiency between mmWave frequency signals and lower frequency signals. OFDM may impose additional spectral constraints on the phase modulated signals generated by DTx. In order to meet the link budget at higher mmWave frequencies with higher propagation losses, these links may rely on phased arrays and multi-user multiple input multiple output (MIMO) to optimize the use of spatial channels across multiple users. In practice, the use of phased arrays may mean that multiple transmit and receive chains are used on each device, further increasing the transmit power used in addition to the power inefficiencies encountered above. Therefore, improving the efficiency of DTx at mmWave frequencies may be useful.

[0750] In one aspect, to help improve these issues, a wideband phase modulator architecture is provided that can be suitable for both single carrier and OFDM based mmWave DTx. The wideband phase modulator architecture can include multiple parallel transmission chains for phased arrays and MIMO / MU-MIMO. The phase modulator can include a phase shift for implementing a phased array.

[0751] In one aspect, DTx can use phase and amplitude extraction of low operator-sum representation (OSR) polar decomposition supporting wide bandwidth RF signals. For practical concerns (feasibility, timing margin, power dissipation, etc.), a digital-to-time converter (DTC) based phase modulator clocked in the low GHz band can be used. Time interleaving can be used between multiple DTCs to increase the clock frequency up to about 10 GHz. In addition, sub-harmonic serial injection into the mmWave LC oscillator can be used to up-convert the modulation to RF frequency.

[0752] RF communication systems often utilize subsystems (e.g., voltage controlled oscillators (VCOs), power amplifiers) formed on semiconductor dies. More specifically, the various electronic components of these subsystems (e.g., capacitors and inductors) are printed on the semiconductor die. However, the inherent resistance of the silicon of the semiconductor die significantly reduces the quality (Q) factor (ratio of inductance divided by resistance) of the inductor printed on the die.

[0753] Fig.17 1702 and top view 1704 of an exemplary semiconductor die with metallic pillars according to some aspects. Fig.17 , the semiconductor die 1706 includes a plurality of pillars 1708. The semiconductor die 1706 may include Figure 3A The semiconductor die 1706 is shown in the RF circuit 325 of the mmWave communication circuit 300 , but the semiconductor die 1706 is not limited thereto.

[0754] In one aspect, pillars 1708 can be copper pillars, which can be used for RF connection to the die. More specifically, copper pillars can be used as metallic structures to connect semiconductor die 1706 to a semiconductor die package (not shown). In some aspects, other metallic structures can be used as pillars 1708 (e.g., solder-based bumps and balls). Copper pillars 1708 can be attached to semiconductor die 106 via metallized contact pads (or contacts) 1710. In some aspects, copper pillars 1708 can be generated in a continuous etching process, wherein unwanted copper is etched away, leaving only copper pillars 1708 attached to die metallized contacts 1710.

[0755] Fig.18A A cross-sectional view 1802A and a top view 1804A of a semiconductor die 1806 having a metallic pillar 1808 forming a first type of interconnect structure are provided in accordance with some aspects. Referring to the cross-sectional view 1802A, the metallic pillar 1808 can be formed according to a multi-stage build up and etch process. More specifically, the metallic pillar 1808 can be built up and etched in stages on the die metallization contact 1810, wherein a separate metallization layer is generated during each build up and etch stage. Fig.18A As can be seen in FIG. 1 , during the first etching phase, metallization layer 1812 is generated. During the additional buildup and etching phases, an interconnect structure can be generated between at least two of the pillars. For example, during the etching phase to generate metallization layer 1814, the metallization material used for layer 1814 can form interconnect structure 1822A. During the etching phase, the metallization material used for 1814 is not etched between at least two of the pillars, so that the layer 1814 connecting the at least two pillars forms an interconnect structure.

[0756] During subsequent build-up and etching phases, metallization layer 1816 is disposed on top of layer 1814 (the metallization interconnect structure is not associated with layer 1816). During subsequent build-up and etching phases to generate metallization layer 1818, the metallization material used for layer 1818 may form interconnect structure 1824A. During a final etching phase, metallization layer 1820 is disposed on top of layer 1818, wherein the metallization interconnect structure is not associated with layer 1820.

[0757] In some aspects, interconnect structures 1822A and 1824A can act as high quality (Q) factor inductive elements directly connected to the contacts of semiconductor die 1806 and can serve RF circuits that can benefit from these high Q inductors. Example RF circuits can include oscillators, power amplifiers, low noise amplifiers, and other circuits that can be partially or fully integrated within semiconductor die 1806.

[0758] In some aspects, interconnect structure 1822A can be located at a position 1832 that is away from and separated from interconnect structure 1824A. In another example, interconnect structure 1822A can be located side by side and / or partially overlapping, as can be seen at position 1830. In some aspects, the selection of the interconnect structure at position 1830 or 1832 can be based on the resulting coupling and mutual inductance associated with interconnect structures 1822A and 1824A. In this case, when the two interconnects are located side by side and / or partially overlapping, a coupling zone 1826 is generated between the interconnect structures. The coupling zone can be used in designing a high-Q inductive element that is at least partially implemented by the interconnect structure associated with metallic pillar 1808.

[0759] In some aspects, lateral parallel coupling (eg, 1826) can be achieved when the interconnect structures (eg, 1824A and 1822A) are created using the same pillar layer (or etch phase) or when different pillar layers are used to create the interconnect structures.

[0760] In some aspects, more than two interconnect structures can be formed using one or more of the layers 1812-1820 associated with the pillar 1808. Additionally, the interconnect structures can be separated by air gaps, such as Fig.18A More specifically, interconnect structure 1822A is separated from semiconductor die 1806 by air gap 1807. Interconnect structure 1822A is also separated from interconnect structure 1824A by another gap 1809 formed within layer 1816.

[0761] In some aspects, the last layer 1820 of the pillars 1808 can be used to form an interconnect structure. Here, when the interconnect structure is disposed on the last layer 1820, the interconnect structure will be connected to the package stack (which is connected to the last layer 1820) with the die attached. Fig.19 1902), or the interconnect structure can be isolated from the stack and can close the circuit directly on the tube die.

[0762] Fig.18B 1802B and top view 1804B of semiconductor die 1806 with metallic pillars 1808 forming a second type of interconnect structure according to some aspects. In addition to interconnect structures 1822B and 1824B can have different shapes and locations on semiconductor die 1806 compared to interconnect structures 1822A and 1824A, the generated Fig.18B The process of metallizing the pillars shown can be compared with that of Fig.18A Same as described.

[0763] Reference Fig.18B , interconnect structures 1822B and 1824B can form a winding-like inductive element, which can be used in various inductive implementations including transformer implementations. In some aspects, interconnect structures 1824B and 1822B can be elements within the primary and / or secondary windings of a transformer. Additionally, interconnect structures 1822B and 1824B can partially or completely overlap, such that a coupling zone 1834 is generated.

[0764] Fig. 18C 1802C and top view 1804C of a semiconductor die 1806 with metallic pillars forming third type interconnect structures 1822C and 1824C according to some aspects. More specifically, interconnect structures 1822C and 1824C may be disposed in a manner similar to those of FIG. Fig.18A1814 and 1818. However, interconnect structures 1822C and 1824C may cross through each other.

[0765] Fig.19 1900 is a cross-sectional view of a semiconductor die having metallic pillars forming an interconnect structure, wherein the pillars are attached to a package stack according to some aspects. More specifically, semiconductor die 1906 may include metallic pillars 1808 formed by layers 1912, 1914, 1916, 1918, and 1920. Semiconductor die 1906 may include metallic pillars 1808 formed by layers 1912, 1914, 1916, 1918, and 1920. Fig.18A Interconnect structures 1822A and 1824A are shown formed. Metallic pillars 1808 can be attached to semiconductor die 1906 using connection paths 1910. Additionally, metallic pillars 1808 can be attached to package stack 1902 using connector pads 1904.

[0766] Physical space in mobile devices for wireless communications is at a premium because of the amount of functionality included within the form factor of these devices. Challenging problems arise, among other reasons, because of the need to provide spatial coverage of the radiated radio waves and maintain signal strength as the mobile device moves to different places, and also because a user may orient the mobile device differently over time, resulting in some aspects of the need to vary the polarity of the radiated radio waves at varying times and vary spatial diversity.

[0767] When designing a package that includes an antenna that operates at millimeter wave (mmWave) frequencies, efficient use of space can help address issues such as the number of antennas required, the direction of their radiation, their polarization, and similar needs. By including a cavity inside the stacked structure for placing an RFIC transceiver die and perhaps for placing discrete components of the device, efficient use of a multi-layer stacked structure (e.g., PCB) within the chassis of a wireless communication mobile device can be effectively used. In some aspects, the die can be a flip chip (FC) die. The stacked structure can include a subsystem, wherein the antenna can be embedded in the layer structure and can be implemented on the top, bottom, and side of the subsystem for greater spatial coverage.

[0768] Fig. 20A 2 is a cross-sectional side view of a user equipment subsystem described in the present disclosure according to some aspects. The user equipment subsystem is indicated as 2000. The user equipment subsystem 2000 may include Figure 3A The RF circuit 325 and the antenna array circuit 330 of the mmWave communication circuit 300 are shown, but the user equipment subsystem 2000 is not limited thereto.

[0769] In some aspects, the stacked structure 2001 includes a cavity 2003. By stacking stacked layers with window openings on top of other stacked layers with FC die and discrete components until the desired height clearance above the FC die and discrete components is reached, a cavity can be formed in which the RFIC and auxiliary components can reside. It can then be covered by one or more complete layers to close the cavity, making the cavity a "top cover". Directional terms (such as "top", "bottom", "side" and "top cover") are used herein relative to the orientation of the accompanying drawings. The cavity can be large enough to enable the FC die and any discrete components to fit inside the cavity while also considering manufacturing design rules (such as assembly accuracy). Each assembly housing can have different design rules, which can also be a function of the actual materials involved. For example, the rules for bismaleimide triazine (BT) stacked materials may be very different from the rules for FR4 stacked materials.

[0770] In some aspects, the RFIC die 2006 is implemented in the cavity 2003, and in some aspects, is fastened to the base of the cavity by solder bumps 2005 (which can be reflow solder bumps in some aspects). Other types of bumps (such as thermosonic, thermal compression and adhesive bonding bumps) can be used. In some aspects, they also serve as the electrical interface of the RFIC die 2006 to the stacked printed circuit. In some aspects, face-up wire bonding can also be used to electrically connect the RFIC to the printed circuit in the stack. If appropriate for the implementation, the discrete component 2007 can also be included in the cavity.

[0771] In some aspects, surrounding the die and discrete components is a ground cage 2008 described in additional detail below, which can be used as a shield to protect the circuit from radio frequency interference (RFI) and electromagnetic interference (EMI). The RFIC placed in the cavity will be enclosed in the described ground cage with the help of metallized ground layers, ground planes and vias running between layers to protect from RFI / EMI. Typically, from the perspective of meeting regulatory requirements, RF chips and circuits need to be shielded from RFI / EMI. Here, the implementation takes advantage of the fact that the RF circuit is embedded in a cavity surrounded by metallization, which can appropriately use the layers of the stacked device and the vias, thus forming a Faraday cage (which is a shield).

[0772] In the case where the components are embedded in a shielded cavity, the antennas can be implemented around the outside of the shielded enclosure as described below and thereby take advantage of the fact that these antennas can be embedded / printed or assembled on or within a PCB from multiple sides to enable greater spatial coverage of the antennas. From an antenna point of view, the shielding cage in the stacked structure can act as an antenna ground or reflector to increase antenna gain and generate a more directional radiation pattern. In addition, the cavity acts as a physical protection for the RFIC itself and any other circuits inside the cavity.

[0773] According to some aspects, antenna elements 2011A to 2011G are implemented within the subsystem. Antennas can be of various types. For example, patch antennas can be implemented on the top and bottom of the structure, facing up and down, respectively, relative to the dipole antenna on the side, such as at 2011G. Other antenna types are possible. In some aspects, since the exposed electrical contacts can be on one side, side antennas will be implemented on three sides, as discussed further below.

[0774] In some aspects, antenna elements 2011A-2011C are implemented to face "downward". Antenna elements 2011D-2011F are placed at the top of the structure and face "upward". Each of antennas 2011A-2011G can be multiple antenna elements. For example, in some aspects, 2011A1 to 2011AN can be used to designate antenna element 2011A as N antenna elements (which can be an array). In other words, in some aspects, the antenna shown as, for example, 2011A can also be an N-element antenna array (e.g., 2011A-1, ..., 2011AN). In addition, arrays 2011D1-2011DN can exist. Furthermore, the antenna elements in these arrays can be distributed on both the top and bottom surfaces of the stacked structure 2001 in different forms (e.g., some of antenna elements 2011C1-2011CN and 2011E1-2011EN are in a single array).

[0775] In some aspects, antenna element 2011G can be placed laterally and can be configured for side or end-fire radiation. Nomenclature 2011G1-2011GN can be used to indicate that there can be N antenna elements 2011G that can be arrayed (see "in" page or out page, hidden due to cross-sectioning). Transmission lines 2009A-2009G can be traces that provide RF connections from the RFIC die to / from the antenna. In some aspects, if the fed antenna is actually an antenna array (e.g., 2011A1-2011AN), the RF traces that feed the array can be arrays of RF traces that can be designated as 2009A1, ... 2009AN. The RF traces from the RFIC can be fed laterally along a given layer through a layer structure or through vias for reaching other layers to various antenna elements. The RF traces can be microstrips, strip lines, or other suitable conductors. In some aspects, the RF traces to the antenna can pass through the openings in the shielded cavity 2003. In some aspects, some segments of these RF feeds may be inside the cavity and some outside. Although shown here as running outside the cavity, alternative aspects may have the RF traces run even vertically first inside the cavity 2003 and then penetrate through openings (via holes or lateral traces) in the shielding cage at the top (or side) to reach the antenna elements. Fig. 20B and Fig.21 This situation is discussed in detail additionally.

[0776] According to some aspects, layer 2013 of the multi-layer stack structure can implement a layer of electrical contacts that electrically connect the RFIC to the appropriate part of the system outside the cavity. Fig. 20B Discuss these contacts. In this example, the electrical contacts ( Fig. 20A 2013 (not shown) will enter or leave the page (e.g., hidden behind the cross-section view).

[0777] Fig. 20B Showing some aspects Fig. 20A The base portion of the laminated structure. Fig. 20B The base 2021 discussed briefly above is shown. Fig. 20B The cross section 20A-20A shown is obtained Fig. 20A In some aspects, Fig. 20B The electrical contacts 2023 and Fig. 20A The same electrical contacts discussed above are implemented at layer 2013 in FIG. Other layers may be used for this implementation.

[0778] Cavity 2003 is shown in hidden lines as being disposed within the stack (shown as being disposed within base 2021). The base can act as a surface for electrical contacts and as an attachment method to a main board (MB) to which the stack can be connected. Electrical contacts 2023 can also act as a heat conduit from the subsystem to the MB. According to some aspects, the MB will have a relative Fig. 20A The layers 2013 (as an example) are appropriately complementary contacts placed as discussed above so that the subsystem can be easily attached to the MB and form an appropriate interface to the MB both electrically and thermally. The electrical contacts that will be inserted into the appropriate jacks are in some aspects the only mechanical connection from the RFIC die to the MB. Alternatively, they can be solder directly attached to the MB through appropriate complementary contacts. Typically, in some aspects, heat requires good metal to conduct, and these exposed electrical contacts 2023 can also act as a heat sink path to pull heat from the die inside the cavity in many cases using the multi-layer structure's strata along the way metallization. While there is a certain amount of heat that is also conducted through the PCB material, this type of heat exchange is not as efficient as metallized contacts for heat transfer.

[0779] As briefly discussed above, the RF traces that feed the antenna may pass through openings in the shielded cavity 2003. Some sections of these RF feeds may be inside the cavity and some outside. According to some aspects, although shown here as running outside the cavity, alternative aspects may have the RF traces run first inside the cavity 2003, even vertically, and then penetrate through openings (via holes or lateral traces) in the shielding cage at the top (or side) to reach the antenna element. This can be seen in Fig.21 and Fig. 22 middle. Fig.21 Showing some aspects Fig. 20A The RF feeding inside the cavity of the stacked structure. Fig. 20A The cavity 2003 in the stacked structure of FIG. 21 is similar. The ground plane layer 2113 that can ground the shield 2108 is the ground layer on the top of the structure shown in the figure, which makes contact with the vertical via (not shown for clarity). The ground layer 2108 is shown with dotted lines to indicate its presence in the stacked structure shown.

[0780] In some aspects, vertical vias 2110 are located around the periphery of cavity 2103 and can be part of a Faraday cage as discussed above. RF traces 2109A, 2109B, 2109C, 2109D, and 2109E are configured to electrically connect to RFIC die 2106, which can be below a ground plane on another layer inside cavity 2103. The RF traces include Fig. 20ARF feed for antennas on or within stacked structure 2001. According to some aspects, RF traces 2009A, 2009B, and 2009C may run inside cavity 2003 and laterally break away between vias ( Fig. 20A ) ground cage described in order to feed antenna elements 2011A, 2011B and 2011C.

[0781] Antenna elements 2011A, 2011B, and 2011C may be broadside antenna elements, shown as dipoles in one example. According to some aspects, RF traces 2109D and 2109E penetrate through the ground shield using vias 2112D and 2112E. Fig. 22 This can be seen more clearly in . Fig. 22 RF feed traces are shown transitioning vertically through the ground plane layer in accordance with some aspects. RF traces 2209D and 2209E penetrate through the ground plane layer through holes or openings 2212D2, 2212E2 in the metallization to allow signal vias to pass through (in some aspects through vias 2212D1 and 2212E1) from the die 2206 to the antenna or antenna elements 2211D and 2211E, respectively. In accordance with some aspects, the antenna or antenna elements 2211D and 2211E are shown in dotted lines to indicate that they can be at the appropriate level of the stacked structure 2001. Although the antenna or antenna element 2211D or 2211E is shown as a patch antenna, it can be any suitable antenna or antenna element. Vias 2212D1 , 2212E1 are shown as oversized to indicate that each can be connected to the appropriate level of stack-up structure 2001 to feed antennas 2211D and 2211E either directly or, in some aspects, via additional RF traces connecting the vias to the antennas.

[0782] RF communication systems often utilize subsystems formed on semiconductor dies, such as voltage controlled oscillators (VCOs), power amplifiers, transceivers, modems, etc. Oftentimes, especially in instances when multiple types of signal communication systems are implemented on a single chip, the packaged chip has limited space for positioning antenna elements.

[0783] Fig.23 Multiple views of an exemplary semiconductor package 2300 with a co-located mmWave antenna and a near field communication (NFC) antenna are shown in accordance with some aspects. The semiconductor package 2300 may include Figure 3A The antenna array circuit 330 of the mmWave communication circuit 300 is shown, but the semiconductor package 2300 is not limited thereto.

[0784] Reference Fig.23, semiconductor package 2300 can be implemented on PCB substrate 2302. PCB substrate can include component side 2302A and printed side 2302B. In some aspects, component side 2302A can include one or more circuits (or subsystems) that perform signal processing functions. For example, component side 2302A can include RF front end module (RFEM) 2310 and baseband subsystem (BBS) 2312. Fig.26 and Fig. 27 The RFEM 2310 and BBS 2312 are shown in more detail, respectively. In some aspects, the PCB substrate may also include a near field communication (NFC) subsystem 2318, which may be configured to receive and transmit NFC signals.

[0785] In some aspects, the RFEM 2310 may include suitable circuitry, logic, interfaces and / or code and may be configured to process one or more intermediate frequency (IF) signals generated by the BBS 2312 for transmission using a phased antenna array. The RFEM 2310 may be configured to receive one or more RF signals via the phased antenna array and convert the RF signals to IF signals for further processing by the BBS 2312.

[0786] In some aspects, the RFEM 2310 can be configured to process mmWave signals in one or more mmWave frequency bands. Additionally, the phased antenna array (or a subset of the phased antenna array) can be implemented as an antenna array 2316 on the printed side 2302B of the PCB substrate 2302. Even though four patch antennas are shown as the phased antenna array 2316, the present disclosure is not limited thereto, and other types (and different numbers) of antennas can be used as the phased antenna array 2316. Additionally, the phased antenna array 2316 can be used to send and receive mmWave signals or other types of wireless signals.

[0787] In some aspects, the phased antenna array 2316 can be co-located with the near field communication (NFC) antenna 2314. Fig.23 As can be seen in FIG, NFC antenna 2314 can be implemented as an inductor element disposed around phased antenna array 2316 on printed side 2302B of PCB substrate 2302. In some aspects, NFC antenna 2314 can include multiple inductor elements (e.g., a multilayer inductor) that can be co-located with phased antenna array 2316.

[0788] In some aspects, the RFEM 2310 and BBS 2312 can be used to process wireless signals in conjunction with one or more wireless standards or protocols in one or more communication networks. Example communication networks can include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile phone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., a wireless network called a The Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards, known as IEEE 802.16 family of standards), IEEE802.15.4 family of standards, Long Term Evolution (LTE) family of standards, 5G wireless communication standards or protocols (including communications in 28 GHz, 37 GHz and 39 GHz communication frequency bands), Universal Mobile Communications System (UMTS) family of standards, point-to-point (P2P) networks, etc.

[0789] Fig.24 A radio frequency front end module (RFEM) having a phased antenna array according to some aspects is shown. Fig.24 , shows an RFEM 2310 of an example phased antenna array implemented on both sides of a PCB substrate 2302. More specifically, the phased antenna array 2400 may include a first plurality of antennas 2402-2408, a second plurality of antennas 2410-2414, a third plurality of antennas 2416-2422, a fourth plurality of antennas 2424-2428, a fifth plurality of antennas 2432, and a sixth plurality of antennas 2434.

[0790] In some aspects, antennas 2402-2428 and 2432 can be disposed on one side of PCB substrate 2302. A sixth plurality of antennas 2434 can be disposed on an opposite side of PCB substrate 2302 (eg, opposite to the PCB substrate 2302). Fig.23 In some aspects, the first, second, third, and fourth pluralities of antennas 2402-2428 can be disposed along four corresponding edges of the PCB substrate 2302 (see FIG. Fig.24 ). A fifth plurality of antennas 2432 may be deployed at a block away from the edge of the PCB substrate 2302. The PCB substrate 2302 may also include a connection terminal 2430, which may be used as a feeder for the phased antenna array 2400. Here, the phased antenna array including antennas 2402-2428, 2432, and 2434 may provide signal coverage in the north, south, west, east, upward, and downward directions relative to the PCB substrate 2302.

[0791] In some aspects, the phased antenna array including antennas 2402-2428, 2432, and 2434 can include different types of antennas (e.g., dipole antennas and patch antennas). In some aspects, other types of antennas can also be used to implement the phased antenna array. In some aspects, one or more of the antennas of the phased antenna array 2400 can be implemented as part of the RFEM 2310. Additionally, the PCB substrate 2302 can include an NFC antenna ( Fig.24 For example, the NFC antenna can be co-located with the antenna 2434 on the same side of the PCB substrate 2302.

[0792] Fig.25 An exemplary position of an RFEM in a mobile device according to some aspects is shown. Fig.25 , shows a mobile device 2500 comprising a plurality of RFEMs 2502. Each RFEM 2502 may comprise, for example, Fig.23 The co-located NFC antenna and mmWave phased array antenna are shown. Fig.25 It can be seen that each RFEM 2502 can be located away from the screen area (e.g., in the border area), so that in the example when a person covers one RFEM by hand, antenna coverage can be provided from another RFEM.

[0793] Fig.26 is a block diagram of an exemplary RFEM program according to some aspects. Fig.26 , the RFEM 2310 is coupled to the BBS 2612 via a coaxial cable 2612. The RFEM 2610 may include a phased antenna array 2602, an RF receiver 2604, an RF transmitter 2606, an LO generator 2608, a triplexer 2610, and a switch 2603. The RF receiver 2604 may include a plurality of power amplifiers 2616, a plurality of phase shifters 2618, an adder 2620, an amplifier 2622, an amplifier 2626, and a multiplier 2624. The RF transmitter 2606 may include a multiplier 2638, amplifiers 2636 and 2640, an adder 2634, a plurality of phase shifters 2632, and a plurality of amplifiers 2630. The RFEM 2310 may also include intermediate frequency (IF) amplifiers 2627 and 2641.

[0794] In an example receive operation, switch 2603 may activate receiver chain processing. Phased antenna array 2602 may be used to receive multiple signals 2614. Received signals 2614 may be amplified by amplifier 2616, and phases may be adjusted by corresponding phase shifters 2618. Each of phase shifters 2618 may receive a separate phase adjustment signal ( Fig.262602), where the individual phase adjustment signals can be based on the desired signal directivity when processing signals received via the phased antenna array 2602. The phase adjusted signals at the output of the phase shifters 2618 can be summed by the adder 2620 and then amplified by the amplifier 2622. The LO generator 2608 can generate an LO signal, which can be amplified by the amplifier 2626 and then multiplied by the output of the amplifier 2622 using the multiplier 2624 to generate an IF output signal. The IF output signals can be amplified by the amplifier 2627, and they are passed to the BBS 2312 via the triplexer 2610 and the coaxial cable 2612.

[0795] In an example transmission operation, switch 2603 may activate the transmitter chain processing. RFEM 2310 may receive an IAF signal from BBS 2312 via coaxial cable 2612 and triplexer 2610. The IAF signal may be amplified by amplifier 2641 and then passed to multiplier 2638. Multiplier 2638 may receive an up-converted LO signal from LO generator 2608 and amplifier 2640. The amplified LO signal may be multiplied by the received IF signal by multiplier 2638. The multiplied signal is then amplified by amplifier 2636 and passed to adder 2634. Adder 2634 generates multiple copies of the amplified signal and passes the signal copies to multiple phase shifters 2632. Multiple phase shifters 2632 may apply different phase adjustment signals to generate multiple phase adjusted signals, which may be amplified by multiple amplifiers 2630. Multiple amplifiers 2630 generate multiple signals 2628 for transmission by phased antenna array 2602.

[0796] In some aspects, the LO generator 2608 can be shared between processing of mmWave wireless signals (or other types of signals) by the RFEM 2310 and processing of NFC signals by the NFC subsystem 2318. For example, the NFC subsystem 2318 can use it at the output of the LO generator 2608 (after dividing the LO generated signal) for upconversion or downconversion as needed. In another example, the NFC subsystem 2318 can use the LO generated signal for direct generation of NFC data by using the LO signal (e.g., by multiplying the LO signal by the NFC data).

[0797] In some aspects, other circuits / subsystems within the RFEM 2310 or BBS 2312 may be shared with the NFC subsystem 2318. For example, the RFEM 2310 or BBS 2312 may include a power management unit (PMU) (not shown) that may be shared with the NFC subsystem 2318. In some aspects, the PMU may include a DC to DC subsystem (e.g., a DC regulator), a voltage regulator, a bandgap voltage reference, a current source, etc. that may be shared with the NFC subsystem 2318.

[0798] Even though the RF receiver 2604 and the RF transmitter 2606 are shown as outputting and receiving intermediate frequency (IF) signals, respectively, the present disclosure is not limited thereto. More specifically, the RF receiver 2604 and the RF transmitter 2606 may be configured to output and receive RF signals, respectively (eg, superheterodyne or direct conversion architecture).

[0799] Fig. 27 is a block diagram of a medium access control (MAC) / baseband (BB) subsystem according to some aspects. Fig. 27 , BBS 2312 may include a triplexer 2702, an IF receiver 2704, a modem 2724, a crystal oscillator 2730, a synthesizer 2728, and a divider 2726. The synthesizer 2728 may use a signal from the crystal oscillator 2730 to generate a clock signal, which may be divided by the divider 2726 to generate an output clock signal for delivery to the RFEM 2310. In some aspects, the generated clock signal may have a frequency of 1.32 GHz.

[0800] The IF receiver 2704 may include an amplifier 2708, a mixer 2710, a filter 2712, and an ADC block 2714. The IF transmitter 2706 may include a DAC block 2722, a low pass filter 2720, a mixer 2718, and an IF amplifier 2716.

[0801] In an example receiving operation, an IF signal is received from RFEM 2310 via triplexer 2702 and amplified by amplifier 2708. The amplified IF signal may be down-converted to a baseband signal by mixer 2710, then filtered by low pass filter 2712, and converted to a digital signal by ADC block 2714, and then processed by modem 2724.

[0802] In an example transmission operation, the digital signal output by the modem 2724 may be converted to an analog signal by a DAC block 2722. The analog signal is then filtered by a low pass filter 2720 and then up-converted to an IF signal by a mixer 2718. The IF signal is then amplified by an IF amplifier 2716 and then transmitted to the RFEM 2310 via a triplexer 2702 and a coaxial cable 2612.

[0803] In some aspects, a coaxial cable may be used to transmit IF signals or RF signals (eg, RF over coaxial (RFoC) communications). Here, one or more other subsystems for processing IF or RF signals may be deployed between the RFEM 2310 and the BBS 2312 for additional signal processing.

[0804] In some aspects, the RFEM 2310, BBS 2312, NFC subsystem 2318, phased antenna array 2316, and NFC antenna 2314 may be located within the same package, or a distributed approach may be used in which one or more subsystems may be implemented on separate packages.

[0805] Fig.28 is a diagram of an exemplary NFC antenna implementation according to some aspects. Fig.23 and Fig.28 , the RFEM 2310 implemented with the co-located antenna array 2316 and the NFC antenna 2314 can also include a signal shielding cover 2802. In some aspects, the NFC antenna 2314 can be disposed on the signal shielding cover 2802. Fig.28 As can be seen in FIG. 2 , the NFC antenna 2314 can be implemented as an inductor coil 2808. More specifically, the following stack can be applied to the signal shielding cover 2802: polyester fiber tape 2814, magnetic sheet 2812, and adhesive tape 2810, inductor coil 2808, base film 2806, and adhesive tape 2804. Even if Fig.28 A particular tape stack including coil 2808 is shown, the present disclosure is not limited thereto, and other aspects of the NFC antenna co-located with the mmWave phased antenna array are possible, and other types of layers / sheets and layer orderings may also be used instead. Fig.28 Layers and ordering shown.

[0806] Fig.29 Multiple views of a semiconductor package with co-located mmWave antennas and near field communication (NFC) antennas on multiple PCB substrates are shown according to some aspects. Fig.29, the semiconductor package 2902 may include multiple PCB substrates. For example, the semiconductor package 2902 may include a first substrate 2904 and a second substrate 2906. The first substrate 2904 may include a first side 2904A (e.g., a printed side) and a second side 2904B (e.g., a component side). The component side 2904B may include one or more components 2908 (e.g., an RFEM (e.g., 2310), a BBS (e.g., 2312), and an NFC subsystem (e.g., 2318)). The printed side 2904A may include a phased antenna array 2910. For example, the phased antenna array 2910 may be used by an RFEM implemented on the component side 2904B. In some aspects, the printed side 2904A may include a co-located NFC antenna 2914. The NFC antenna 2914 may be implemented as an NFC antenna 2914A (next to the phased antenna array 2910) or an NFC antenna 2914B deployed around the phased antenna array 2910.

[0807] In some aspects, a subset of the phased antenna array used by RFEM implemented on substrate 2904 can be deployed on a second substrate 2906. For example, Fig.29 As can be seen in the figure, the substrate 2906 can include a phased antenna array 2912. Both the phased antenna array 2910 and the phased antenna array 2912 can include antennas with horizontal and / or vertical polarization. In some aspects, the second substrate 2906 can include a co-located NFC antenna 2914C, which can be deployed next to the phased antenna array 2912. Alternatively, the NFC antenna can be implemented as an antenna 2914D, which is an inductor deployed around the phased antenna array 2912.

[0808] In some aspects, the first substrate 2904 can include solder balls 2916 , which can be used for coupling between the first substrate 2904 and the second substrate 2906 .

[0809] Phased array radio transceivers can be used in millimeter wave radio communication circuits to increase antenna gain, thereby addressing the significant path loss associated with the smaller antenna aperture at these frequencies. However, phased array radio transceivers utilize a recombining point where the sum of all phased array receiver (or transmitter) signals is combined together. In terms of performance and complexity, this combining node is generally a bottleneck in phased array receivers. Additionally, in applications where phased arrays of different sizes are desired, the combining node may need to be redesigned, which significantly increases the design complexity and is an obstacle to the scalability of phased arrays.

[0810] Fig.30 is a block diagram of an RF phased array system that implements beamforming by phase shifting and combining signals at RF according to some aspects. The RF phased array system shown may include Figure 3AThe RF circuit 325 of the mmWave communication circuit 300 is shown, but the RF phased array system is not limited to this.

[0811] Reference Fig.30 , a phased array radio transceiver 3000 is shown. The transceiver operates by modifying the gain and phase of each received element in such a way that the transmitted (or received) signal is formed from the sum of the coherent vectors of several (in terms of amplitude) weaker signals. The transceiver 3000 operates as an RF phased array system. More specifically, the transceiver 3000 includes a number N of receiver / transmitter chains, which include antennas 3002_1-3002_N, amplifiers 3004_1-3004_N, phase shifters 3006_1-3006_N, variable gain amplifiers 3008_1-3008_N, adders (or combiners) 3010, mixers 3012, filters 3016, and analog-to-digital converters (ADCs) 3018. In the instance when the signal is processed for transmission, the block 3018 may be a digital-to-analog converter.

[0812] In operation, phase shifters 3006_1-3006_N and variable gain amplifiers 3008_1-3008_N are used to adjust each transmitted or received signal. Since only one mixer and baseband chain may be required, Fig.30 The advantage of the RF phased array system is its simplicity. Fig.30 Disadvantages of RF phased array systems in can include: lack of scalability (adding several paths at the RF frequency creates a bandwidth bottleneck), added noise figure in the receiver (because noisy phased arrays and variable gain amplifiers are added near the antenna), and added power consumption (phase and gain adjustment blocks operate at millimeter wave frequencies and may add additional signal losses).

[0813] Fig.31 is a block diagram of a phased array system that implements beamforming by phase shifting a local oscillator (LO) and combining analog signals at IF / baseband according to some aspects. Fig.31 , a phased array radio transceiver 3100 is shown, which is configured as a local oscillator (LO) phase-shifted phased array system. The transceiver 3100 includes antennas 3102_1-3102_N, amplifiers 3104_1-3104_N, variable gain amplifiers 3106_1-3106_N, mixers 3108_1-3108_N, phase shifters 3110_1-3110_N, adders (or combiners) 3114, filters 3116, and ADC 3118. Fig.31As can be seen in FIG. 3 , the LO phased array system 3100 uses a variable gain amplifier in the signal path, however, a phase shifter 3110 is used in the local oscillator path to shift the phase of the LO signal 3112. This topology is superior to Fig.30 An advantage of the RF phased array system is the reduced noise profile. However, the LO phased array system 3100 uses more mixers. Additionally, routing the LO signal operating at millimeter wave frequencies can be challenging.

[0814] In some aspects, the LO phased array system 3100 can be configured to perform phase shifting using an all-digital PLL (ADPLL), and the phase shifting can be done digitally within the ADPLL loop. This can eliminate the need for RF phase shifters (which are expensive in terms of power consumption and introduce distortion and insertion loss in the signal path). Phase shifting within the ADPLL also eliminates the need for explicit phase shifters added to the LO signal path.

[0815] Fig.32 is a block diagram of a phased array with digital phase shifting and combining according to some aspects. Fig.32 , showing a digital phased array system 3200. The transceiver 3200 may include antennas 3202A-3202N, amplifiers 3204A-3204N, variable gain amplifiers 3206A-3206N, mixers 3208A-3208N, filters 3212A-3212N, ADCs 3214A-3214N, and an adder 3216.

[0816] exist Fig.32 As can be seen in Figure 3, the entire transceiver chain is repeated for each antenna, including data converters 3214A-3214N. Signal phase adjustment and signal combining can be performed on the digital signal output 3218 after the adder 3216. However, performing phased array combining in the digital domain may result in increased complexity and power consumption. A benefit of the digital phased array system 3200 is its ability to support multiple users simultaneously by generating separate digital streams each generated with a different set of beamforming coefficients (both gain and phase), where each user utilizes the full antenna array gain.

[0817] exist Figure 30-Figure 32 In the example transceiver shown, a recombination point is used where the sum of all phased array receiver (or transmitter) signals are combined together with different amplitude weights and / or phase shifts. Such a combining node may generally be a bottleneck in a phased array receiver in terms of performance and complexity. Additionally, if a different size phased array is desired, the combining node may be redesigned, which may significantly increase the design complexity of the transceiver and substantially limit the array scalability.

[0818] In some aspects, a scalable phased array radio transceiver architecture may be used, as discussed herein, to mitigate the Figure 30-Figure 32 The scalability and complexity issues associated with the transceiver shown. The scalable phased array radio transceiver architecture can use multiple transceiver tiles (or small units), which helps the architecture to be reusable for multiple applications and products and reduces time to market. Additionally, the proposed scalable phased array radio transceiver architecture is self-configurable, making the programmability of the transceiver device easy. The scalable phased array radio transceiver architecture can support multiple operating modes that enable better phased array gain or low power consumption optimized for specific use cases, as discussed below in this article.

[0819] Fig.33 is a block diagram of transceiver small unit components that may be used in a scalable phased array radio transceiver architecture according to some aspects. Fig.33 , the transceiver cell (TRX) 3300 may include a transmitter (TX) circuit 3302, a receiver (RX) circuit 3304, a local oscillator (LO) circuit 3306, a digital circuit (DIG) 3308, an input / output (I / O) circuit 3310, and a phase adjustment circuit 3312. In some aspects, a set of multiplexers and demultiplexers may be tiled on the four edges 3320-3326 of the transceiver cell 3300 to allow communication with neighboring cells. The four edges of the transceiver cell 3300 may be designated as a north (N) edge 3320, an east (E) edge 3322, a south (S) edge 3324, and a west (W) edge 3326. The I / O circuit 3310 may include both analog and digital parallel buses that connect the transceiver cell 3300 to neighboring cells, which allows cells to be tiled into a transceiver array. In some aspects, the TX circuit 3302 and the RX circuit 3304 can have a single or multiple transmitters and receivers, respectively, allowing multiple receiver and transmitter chains to share a single local oscillator signal to save power. In some aspects, the crystal oscillator signal that can be used to generate the local oscillator signal in each transceiver small unit can be buffered and shared between multiple transceiver small units. In some aspects, the loopback can be used to measure and calibrate the delay introduced by the crystal oscillator buffer in each transceiver small unit. The transceiver small unit 3300 can also include a control circuit ( Fig.33 3308 ), which can be used to process control signals connecting the transceiver cell 3300 to other neighbor cells and static global control signals. In some aspects, the control circuit can be included as part of the digital circuit 3308 .

[0820] In some aspects, TX circuitry 3302 and RX circuitry 3304 may include amplifiers, variable gain amplifiers, mixers, baseband filters, analog-to-digital converters, digital-to-analog converters, and other signal processing circuits. In some aspects, digital circuitry 3308 may include circuitry that performs digital signal processing, filtering, and digital signal combining and phase adjustment. In some aspects, phase adjustment and signal combining may be performed by phase adjustment circuitry 3312 in both the analog or digital domain.

[0821] Fig.34 is a block diagram of a phased array radio transceiver architecture using multiple transceiver cells according to some aspects. Fig.34 , the transceiver array 3400 may include multiple transceiver cells tiled together in the array. More specifically, each of the transceiver cells 3402-3412 may be an exact copy of each other, and each of the transceiver cells 3402-3412 may include a reference Fig.33 The communication between the individual transceiver subunits 3402-3412 may include analog and digital buses. In some aspects, the width of the bus may be equal to the number of simultaneous users that the phased array system can support, as further explained herein below. Fig.34 As can be seen in , each transceiver cell can be connected to only adjacent transceiver cells, which ensures the scalability of the transceiver architecture using multiple transceiver tiles.

[0822] In some aspects, a transceiver architecture using multiple transceiver tiles can be implemented on a single semiconductor die, which can enable the semiconductor wafer to be diced into different shapes and array sizes for different applications, such as Fig.35 shown.

[0823] Fig.35 A semiconductor die is shown diced into individual transceiver cells forming a phased array radio transceiver in accordance with some aspects. Fig.35 , semiconductor wafers 3500 and 3502 are shown. Wafers 3500 and 3502 can be manufactured to include multiple transceiver tiles (or small units) connected to each other during the manufacturing process. In conjunction with wafer 3500, different phased array radio transceivers can be cut from wafer 3500 for different applications. For example, a 10x3 array 3510, multiple 1x2 arrays 3512, a single 3x18 array 3514, multiple 3x3 arrays 3516, multiple 3x9 arrays 3518, multiple 1x4 arrays 3520, and a single 2x10 array 3522 can be cut from semiconductor wafer 3500 and used for different low power applications with varying system level requirements.

[0824] In some aspects, in high performance systems (e.g., base station applications), a single semiconductor die 3502 may be diced to obtain a single transceiver array 3530. Here, the same semiconductor wafer may be populated with multiple copies of the same transceiver cell (e.g., 3300), and the semiconductor wafer may then be diced to obtain transceiver arrays having different shapes.

[0825] Fig.36 is a block diagram of a phased array radio transceiver architecture packaged with a phased array antenna according to some aspects. Fig.36 , the phased array radio transceiver architecture package 3600 may include a transceiver array 3610 having tiled transceiver cells disposed on a semiconductor die 3602. The transceiver array 3610 may be combined with an antenna layer 3604 of antennas in an antenna array 3612, which may be integrated with the transceiver array 3610 to form the phased array radio transceiver architecture package 3600. In some aspects, the spacing of individual transceiver cells within the transceiver array 3610 may be equal to the spacing of individual antennas in the antenna array 3612.

[0826] In some aspects, a configurable phased array transceiver system including a plurality of identical transceiver cells (e.g., a transceiver array 3400 having a plurality of transceiver cells (e.g., cells 3300)) may include a self-aware configurable structure for performing self-configuration. More specifically, a processor circuit associated with the transceiver array 3400 (e.g., a processing circuit within one or more of the individual transceiver cells 3300) may perform self-configuration at power-up. For example, an identification number (ID) for each of the transceiver cells within the transceiver array 3400 may be determined at power-up, such as by an ID allocation algorithm. By having an associated ID number for each transceiver cell, the transceiver array 3400 may provide configuration information indicating the number and / or location of the individual transceiver cells activated within the transceiver array 3400, such that each identical cell may be individually addressed with respect to control and configuration.

[0827] The four sides of the transceiver array chip may be referred to as North (N), South (S), West (W), and East (E). At power-up, ID#1 may be assigned to the NW corner cell (e.g., transceiver cell 3402). The NW corner of the transceiver array 3400 may be determined by a positional connection port that may detect whether a port is open or shorted relative to another port.

[0828] For example, the processor circuit can determine that both the N and W ports of the transceiver cell 3402 are open circuits, and therefore, initial ID#1 is assigned to the cell. The transceiver cell 3402 can then initiate a numbering sequence, wherein the ID number can be increased by 1 and passed to the neighbor transceiver cell eastward. If the current cell does not have an E port connection (e.g., cell 3406) and it has received its ID number from the west cell, then it passes the ID number to the south cell. If the current cell does not have an E port connection and it has received its ID number from the north cell, then it passes the ID number to the west cell (if connected, otherwise, it also passes the ID number to the south cell). Similar processing can be used for the west boundary of the array. This operation continues until it arrives at the SE or SW corner cell. At this point, ID numbering is complete. Additionally, when the ID number of the cell is assigned, the cell can experience the local amplitude and phase calibration of sending and receiving amplitude and phase values. Once the self-calibration process is complete and each transceiver cell within the transceiver array has an assigned ID number, the ID number can be used to further configure the array for processing signals associated with a different number of users. Fig.34 In the example array 3400, ID assignment / numbering may begin at cell 3402, then continue to the right to cell 3406, then down and continue to the left to cell 3408, then down and continue to the right, and so on.

[0829] In some aspects, a scalable phased array radio transceiver architecture (e.g., transceiver array 3400) can support multiple operating modes. Examples of operating modes include LO phased array (or beamforming) operating mode, digital phased array (or beamforming) operating mode, analog phased array (or beamforming) operating mode, and hybrid phased array (or beamforming) operating mode. Each of the operating modes can be implemented using the transceiver small units (e.g., 3402 or 3300) discussed above, allowing the array 3400 to be scalable in size and configuration.

[0830] Fig.37 is a block diagram of a transceiver small unit with a communication bus according to some aspects. Fig.37 , the transceiver small unit 3700 can be the same as the above reference Fig.33 The transceiver small unit 3300 discussed is the same.

[0831] During an example digital beamforming mode of operation, transceiver related elements within the transceiver cell 3700 may be used. For example, in receive mode, a receive signal may be converted to a digital signal and then the vector summed within the transceiver cell 3700 with the digital signal received from a neighbor transceiver cell having a previous ID number. To maintain scalability, the summation between each stage may be pipelined to limit the loading on the data bus line. Additionally, to support a total of K users (or equivalently, K independent beams for a phased array), K number of bus lines may be used, one for each user.

[0832] In some aspects, the number of bus lines can be fixed in hardware, and each transceiver cell can therefore be designed with hardware to support the maximum number of users (or beams) during digital phased array operation. Since the data lines are pipelined, the depth N can be maintained. D Internal pipeline registers. Pipeline depth N D The maximum transceiver array size may be limited, where individual transceiver cells are connected with respect to the digital phased array operation mode. A larger array size (or number of identical transceiver cells) requires a larger pipeline register depth N D .

[0833] Fig.37 As can be seen in FIG. 3 , the transceiver cell 3700 is configured to use a digital beamforming operation mode of K digital buses to communicate with neighbor cells. For example, the digital buses 3702, 3704, 3706, and 3708 of K number can be used to communicate with the transceiver cells located to the west, north, east, and south, respectively. The transceiver cell 3700 may include a transmitter block 3722 and a receiver block 3724. The transmitter block 3722 and the receiver block 3724 may be coupled to the digital buses of K number via digital multiplexers 3710-3712, 3714-3716, and 3718-3720 that can be used to select the digital input from a specific neighbor transceiver cell. The received digital signal from the neighbor cell can be added and then passed to the subsequent neighbor cell in a pipelined manner.

[0834] Fig.38 is a block diagram of a phased array transceiver architecture with transceiver tiles in an LO phase-shifted mode of operation using a single analog-to-digital converter (ADC) according to some aspects. Fig.38 , the phased array transceiver 3800 may include a plurality of transceiver small units 3802-3818. The transceiver small units 3802-3818 may be connected to Fig.33 The transceiver subunits 3300 shown are identical.

[0835] In the example LO phased array mode of operation, each transceiver unit 3802-3818 can receive data from the central control unit ( Fig.38 The phase shifted signal is received by a central control unit (not shown). The central control unit can be a processor used by the transceiver array 3800, or it can be one or more processors within a separate transceiver cell. In the receive path, the phase shifted signal can be applied to the local oscillator signal to generate a phase-shifted LO signal. The outputs of all mixer stages can be summed in the analog domain, bypassing any analog-to-digital conversion. More specifically, after down-converting the received wireless signal using the phase-shifted LO signal, the resulting signal can be summed with a signal received from a neighboring cell (e.g., a transceiver cell along the west edge) and then passed to another neighboring transceiver cell (e.g., a transceiver cell along the east edge).

[0836] Reference Fig.38 3800, the analog down-converted signals are summed as they pass between neighboring cells, and the final summed analog signal is passed to the transceiver cell 3806. The analog-to-digital converter 3820 within the transceiver cell 3806 can be used to convert the analog signal to a digital signal, which can then be passed to the baseband circuit 3822 for processing. Here, only a single ADC will take the combined analog signal output of all transceiver cells 3802-3818 and translate the combined analog signal output into a digital signal. The combination of multiple analog signals from each of the transceiver cells 3802-3818 can be performed through an analog bus line that interfaces between adjacent transceiver cells. Since the ADC is one of the largest power consuming blocks in a phase-shifted array system, significant power reduction can be achieved by using a single ADC within the transceiver array 3800.

[0837] Fig.39 is a block diagram of a phased array transceiver architecture with transceiver tiles in an LO phase shifted mode of operation using multiple ADCs according to some aspects. Fig.39 , the transceiver array 3900 may include a plurality of transceiver small units 3902-3918. The transceiver small units 3902-3918 may be connected to Fig.33 The transceiver small unit 3300 shown is the same. In the example LO phased array operation mode with multiple sub-arrays, each transceiver small unit 3902-3918 can be controlled from a central control unit ( Fig.39 The central control unit may be a processor used by the transceiver array 3900, or it may be one or more processors within a separate transceiver cell.

[0838] exist Fig.39As can be seen in FIG, multiple neighboring transceiver cells within a row of transceiver array 3900 can form a subarray. For example, transceiver cells 3902-3906 can form a transceiver subarray. Transceiver cells 3908-3912 and 3914-3918 can form similar subarrays. In the receive path for each of the subarrays, a phase shift signal can be applied to a local oscillator signal to generate a phase-shifted LO signal. The outputs of all mixer stages within the subarray can be summed in the analog domain, bypassing the analog-to-digital conversion and then passed to a single ADC associated with the subarray. More specifically, after down-converting the received wireless signal using the phase-shifted LO signal, the resulting signal can be summed with the signal received from the neighboring cell within the subarray of cells 3902-3906 (e.g., the transceiver cell along the west edge), and then passed to another neighboring transceiver cell within the subarray (e.g., the transceiver cell along the east edge).

[0839] Referring to the transceiver subarray of cells 3902-3906, the analog down-converted signals are summed as they pass between neighbor cells, and the final summed analog signal is passed to transceiver cell 3906. An analog-to-digital converter 3920 within transceiver cell 3906 may be used to convert the analog signal to a digital signal, which may then be passed to baseband circuitry 3926 for processing.

[0840] Referring to the transceiver subarray of cells 3908-3912, the analog down-converted signals are summed as they pass between neighbor cells, and the final summed analog signal is passed to transceiver cell 3912. An analog-to-digital converter 3922 within transceiver cell 3912 may be used to convert the analog signal to a digital signal, which may then be passed to baseband circuitry 3928 for processing.

[0841] Referring to the transceiver subarrays of cells 3914-3918, the analog down-converted signals are summed as they pass between neighboring cells, and the final summed analog signal is passed to transceiver cell 3918. An analog-to-digital converter 3924 within transceiver cell 3918 may be used to convert the analog signal to a digital signal, which may then be passed to baseband circuitry 3930 for processing.

[0842] All transceiver cell elements within the array are used to generate analog signals and a single ADC within the array is used to generate an output digital signal Fig.38 Compared with the transceiver array 3800, Fig.39The transceiver array 3900 in uses one ADC per subarray, which allows the generation of multiple digital signals that serve multiple users (e.g., if the transceiver array 3900 is divided into M subarrays, each with its own digital signal output, then M users can be served). However, each user will be using only a fraction (1 / M) of the total array aperture.

[0843] Fig.40 is a block diagram of a phased array transceiver architecture with transceiver tiles in a hybrid operating mode (LO and digital phase shifting and combining) using multiple ADCs to generate multiple digital signals in accordance with some aspects. Fig.40 , the phased array transceiver 4000 may include a plurality of transceiver small units 4002-4018. The transceiver small units 4002-4018 may be connected to Fig.33 The transceiver small units 3300 shown are identical. In the example hybrid operation mode, each of the transceiver small units 4002-4018 can be powered by a central control unit ( Fig.40 The central control unit may be a processor used by the transceiver array 4000, or it may be one or more processors within a separate transceiver cell.

[0844] exist Fig.40 As can be seen in FIG, multiple neighboring transceiver cells within a row of array 4000 can form a subarray. For example, transceiver cells 4002-4006 can form a transceiver subarray. Transceiver cells 4008-4012 and 4014-4018 can form similar subarrays. In the receive path for each of the subarrays, a phase shift signal can be applied to a local oscillator signal to generate a phase-shifted LO signal. The outputs of all mixer stages within the subarray can be summed in the analog domain, bypassing the analog-to-digital conversion and then passed to a single ADC associated with the subarray. More specifically, after down-converting the received wireless signal using the phase-shifted LO signal, the resulting signal can be summed with a signal received from a neighboring cell within the subarray of cells 4002-1106 (e.g., a transceiver cell along the west edge), and then passed to another neighboring transceiver cell within the subarray (e.g., a transceiver cell along the east edge). Referring to the transceiver subarrays of cells 4002-4006, the analog down-converted signals are summed as they pass between neighboring cells, and the final summed analog signal is passed to transceiver cell 4006. Analog-to-digital converter (ADC) circuitry 4020 within transceiver cell 4006 may be used to convert the analog signals to digital signals, which may then be passed to baseband circuitry 4026 for processing.

[0845] Referring to the transceiver subarrays of small cells 4008-4012, the analog down-converted signals are summed as they pass between neighboring small cells, and the final summed analog signal is passed to transceiver small cell 4012. An analog-to-digital converter 4022 within transceiver small cell 4012 may be used to convert the analog signal to a digital signal, which may then be passed to baseband circuitry 4028 for processing.

[0846] Referring to the transceiver subarrays of cells 4014-4018, the analog down-converted signals are summed as they pass between neighboring cells, and the final summed analog signal is passed to transceiver cell 4018. Analog-to-digital converter (ADC) circuitry 4024 within transceiver cell 4018 may be used to convert the analog signals to digital signals, which may then be passed to baseband circuitry 4030 for processing.

[0847] In an example hybrid mode of operation, each of baseband circuits 4026, 4028, and 4030 may apply one or more weight values ​​(or coefficients) in order to generate a beamformed signal. More specifically, coefficients H 1 , H 2 ,……,H N can be associated with the desired beam 4037. Similarly, the coefficient W 1 , W 2 ,……,W N can be associated with the desired beam 4033. Baseband circuits 4026, 4028, and 4030 can convert coefficients H 1 , H 2 ,……,H N Applied to the digital signals received from ADC circuits 4020, 4022, and 4024. The weighted signals may be summed by adder 4036 to generate desired beam 4037.

[0848] Similarly, baseband circuits 4026, 4028, and 4030 may convert coefficients W 1 , W 2 ,……,W N Applied to the digital signals received from ADC circuits 4020, 4022, and 4024. The weighted signals may be summed by adder 4032 to generate desired beam 4033. Beams 4037 and 4032 may be further processed by baseband circuits 4038 and 4034, respectively.

[0849] even though Fig.40 The two beams are shown to be generated using two adders in the digital domain, but the disclosure is not limited thereto. In some aspects, only a single set of weights may be applied to the digital output of the ADC circuit, and only a single adder may be used to generate a single beam for a single user.

[0850] Fig.41 is a block diagram of a phased array transceiver architecture with analog / IF / baseband phase shifting using a single ADC and transceiver tiles in combined operation mode according to some aspects. Fig.41 , the transceiver array 4100 can be configured to operate in an analog phase shift (beamforming) mode of operation. Fig.41 As can be seen in FIG. 4 , each of the transceiver small units 4102A, 4102B, 4102C, and 4102D includes a local oscillator 4106, a mixer 4104, and a phase shifter 4108. After the received wireless signal is down-converted by the mixer 4104, the phase shifter 4108 can apply a phase shift that can be specified by the control circuitry within the transceiver array 4100. The phase-shifted analog signals can be passed to neighboring transceiver small units, where they can be summed to produce a final combined signal 4110. The combined phase-shifted baseband analog signals can be converted to digital signals by a single ADC within the transceiver array 4100. For example, the combined signal 4110 can be passed to the ADC 4112B within the transceiver small unit 4102B, which can generate a digital signal 4114 for further processing by the baseband circuitry 4116.

[0851] Fig.42 is a block diagram of a phased array transceiver architecture with transceiver tiles in an analog IF / baseband phase-shifted mode of operation using multiple ADCs to generate multiple digital signals in accordance with some aspects. Fig.42 , the transceiver array 4200 may include transceiver small units 4202A, 4202B, 4202C, and 4202D. Each of the transceiver small units 4202 may include a corresponding mixer 4204 (4204A-4204D) and a local oscillator generator 4206 (4206A-4206D).

[0852] In some aspects, the analog baseband signal at the output of mixer 4204 may be used to generate multiple output signals. More specifically, a set of analog coefficients may be applied using analog multipliers and the output of each mixer to generate weighted signals from each transceiver cell, which may be summed and converted to digital signals by the ADC subsystem. Fig.42 As can be seen in FIG. 4 , the first set of analog coefficients A1(S) (4208A-4208D) can be applied to the outputs of mixers 4204A-4204D, respectively. The weighted signals can be summed to generate a combined signal 4214, which can be passed to ADC 4212B within transceiver subunit 4202B. ADC 4212B can generate an output digital signal 4216 for subsequent processing by digital baseband circuit 4218.

[0853] Similarly, a second set of analog coefficients A2(S) (4210A–4210D) may be applied at the outputs of mixers 4204A–4204D, respectively. The weighted signals may be summed to generate a combined signal 4220, which may be passed to an ADC 4212D within transceiver subunit 4202D. ADC 4212D may generate an output digital signal 4222 for subsequent processing by digital baseband circuitry 4224. Thus, by applying two separate parallel sets of analog coefficients to each output of the transceiver subunit mixer, two separate digital output signals corresponding to two separate beams may be used for two separate users. Even though Fig.42 Only two output digital signals are shown in FIG. , the present disclosure is not limited thereto, and a different number of parallel analog coefficient sets may also be used.

[0854] Fig.43 An example operating mode of a phased array transceiver architecture with transceiver tiles according to some aspects is shown. Fig.43 , Table 4300 provides a summary of the number of parallel analog coefficient sets, data convergence, and parallel digital coefficient sets that may be used for various operating modes of a scalable phased array radio transceiver architecture using multiple transceiver cells as described herein.

[0855] Referring to the first row in Table 4300, the full aperture (e.g., full array size) can be used for the LO beamforming mode of operation in the transceiver array. This mode is found in Fig.38 in which the entire array (full aperture) is used, no analog coefficient sets are used (because the phase shift is achieved by LO phase shift and is not in the analog baseband signal after the mixer), and a single ADC is used to generate a single digital output signal without any parallel digital coefficient sets for subsequent processing.

[0856] Referring to the second row in Table 4300, the full transceiver array can be used in a digital beamforming mode of operation. The analog outputs of each transceiver cell can be summed, and the N number of digital frequency converters within the array can be used to generate N digital signals without using any parallel analog coefficient sets. The N digital outputs of the data frequency converters can be used with the M number of parallel digital coefficient sets to generate the final M number of output beams serving the M users. Fig.40 The application of digital coefficient sets is shown in , where two digital coefficient sets are used for the outputs of N digital frequency converters to generate two final output beams serving two users.

[0857] Referring to the third row in Table 4300, 1 / M of the transceiver array aperture is used to serve M users. Fig.39This example is shown in FIG. 39, where subarray processing is used for M number of analog-to-digital converters (assuming array 3900 has M rows). Up to M number of parallel digital coefficient sets can be used for subsequent processing (e.g., see FIG. 39, where subarray processing is used for M number of analog-to-digital converters (assuming array 3900 has M rows). Fig.40 Center) M digital outputs from the analog-to-digital converter.

[0858] Referring to the fourth row in table 4300, the full aperture of the transceiver array can be used to simulate the phased array operation mode. For example and see Fig.42 , and M number of parallel analog coefficient sets can be used together with M number of digital frequency converters to generate M number of output signals. Fig.42 , M equals 2, so that two parallel analog coefficient sets are used per transceiver cell, where two digital frequency converters generate two output beam signals. Up to M parallel digital coefficient sets can then be used for the beam signal outputs of the data frequency converters.

[0859] Previous wireless user equipment antenna array designs have caused at least three problems. One problem is that previous designs include shielded silicon dies that feed the antenna array, where the shielding is a discrete metal shield, and where the array can be on one or more levels or one or more sides of a substrate that includes the shielded silicon die. This requires a relatively large area substrate for the shielded die, discrete circuits, and antenna arrays on one or more levels or one or more sides of the substrate. Designs that require large area substrates imply more expensive substrates. In the above type of design, it is not unusual for the substrate to be nearly as expensive as twice the silicon die that feeds the antenna array. In some aspects, the substrate can be a stacked structure. Although stacked structures will be described herein, other substrates may also be used in other aspects.

[0860] A second problem encountered in designs of the above type is routing long feed lines from the die to some of the antenna elements because of the large areas involved. This results in as much power loss in some instances as a 3 dB loss or nearly half the power in feeding some of the antenna elements.

[0861] Third, while these designs may provide good phased array radiation in some areas of the substrate, in other areas, radiation from the antenna elements or from the entire antenna array may be blocked due to shielding covering the die and discrete components to protect them from radio frequency interference (RFI) and electromagnetic interference (EMI).

[0862] Therefore, it is desirable to find solutions to the above three problems. One solution involves a design using multiple packages (e.g., substrates or stacked structures). According to some aspects, described herein is a package-on-package (POP) implementation using FIG. 44A to FIG. 44DThe two encapsulated solutions described in .

[0863] Fig.44A A top view of a package of a dual package system according to some aspects is shown. A package generally indicated at 4400 and specifically at 4401 can be a substrate having parallel metallization layers with a metallized top layer and a metallized bottom layer in some aspects. Package 4400 can include Figure 3A The RF circuit 325 and the antenna array circuit 330 of the mmWave communication circuit 300 are shown, but the package 4400 is not limited thereto. In some aspects, part or all of one or more of the metallization layers can be processed to be metallization-free as desired.

[0864] In some aspects, substrate 4401 includes an array of six patch antennas 4403, 4404. Reference numeral 4403 represents a patch antenna having a single matching point indicated by a single dot and can be a single patch antenna. Reference numeral 4404 represents a patch element having two matching points indicated by two dots and can be a double stacked patch antenna element. This design is but one of multiple configurations and types of antenna elements that can be used and represents only some aspects. According to some aspects, around the periphery of substrate 4501 are six antenna elements 4505. According to some aspects, they can be printed antenna elements that are situated with respect to end-fire operation. Although a dipole antenna element is shown at 4505, other types of antenna elements can be used. In the description herein, some or all of the antenna arrays may be referred to as smart antenna arrays.

[0865] The term "smart antenna" or "smart antenna array" seeks meaning in the controlled manner of an antenna or antenna array. In some aspects, an antenna array can be implemented with various types of polarities (e.g., vertical, horizontal, and circular polarization). As an example, when an antenna array is implemented with respect to vertical polarity and horizontal polarity, the polarity transmitted at a given time and therefore which antenna or array is transmitting at a given time can be algorithmically controlled based on an indication of the polarity of the received signal with maximum strength at a wireless user device, and therefore is intelligent. In some aspects, this information can be continuously fed back to a wireless transmitter (e.g., a small cell tower transceiver) from a user device. This operation can then be implemented to achieve the transmitted polarization of the polarization at the receiver of a matching user device (which can be a mobile phone). In some aspects, the user device antenna is also controlled algorithmically. In some aspects, similar algorithmic control works for spatial diversity.

[0866] Fig.44B Showing some aspects Fig.44A A bottom view of the substrate 4401. Fig.44B, the structure is generally shown at 4402 and includes a silicon die 4409 and discrete components (one of which is designated 4411). In some aspects, the discrete components can be capacitors, resistors, and / or inductors. Surrounding the die are contacts 4407, which in some aspects can be solder balls.

[0867] Fig.44B Showing some aspects Fig.44A Bottom view of the substrate. Fig.44C Showing some aspects Fig.44A and Fig.44B A bottom view of a substrate of a second package of a dual package system. According to some aspects, Fig.44C The structure 4419 may be a substrate (such as a PCB board), Fig.44A The substrate 4401 may be similar. The structure 4419 is of length L, which is essentially Fig.44B 4407, discussed below. Shown on structure 4419 are four antenna elements 4421, shown here as dual stacked patch antennas each having two matching points indicated by two small dots on each antenna element. As for substrate 4401, the design of the antenna on or within substrate 4401 is one of many configurations and types of antenna elements that can be used and represents only some aspects.

[0868] According to some aspects, Fig.44D Shown mounted to each other Fig.44A and Fig.44C package. As a stacked package implementation, the first package 4401 and the second package 4419 are mounted or stacked one on top of the other. Various mounting processes can be used to complete the mounting. It can be seen from the POP aspect 4406 that the antenna element 4421 is on or in the substrate 4419 on the "top substrate" of the POP aspect or is the "top package" of the POP aspect, and is pointing "upward". According to some aspects, the antennas 4403 and 4404 are on or in the "bottom" of the substrate 4401 of the POP aspect, or are the "bottom package" of the POP aspect, and are pointing "downward". The connector 4417 and the component 4413 can be fastened and made robust by molding or encapsulation 4414, as discussed below. Level 4423 includes metallization layers, which in some aspects can be multiple metallization layers used for antennas and for feed lines.

[0869] Generally speaking, the concept of POP involves vertically stacking packages that cannot be stacked in previous aspects, and covers 3-dimensional (3D) stacking of antennas, tube cores and components in packages. Some factors to be considered in 3-D stacking include antenna volume and antenna size. The previous design is flat, which produces a shielded tube core design, wherein the X dimension and Y dimension (such as width and length) are the dimensions that lead to the large substrate area discussed above, with substrate cost, feeder power loss and loss of available space, and radiation shielding and other discrete components. The previous design is mainly based on the assumption that because of the importance of the Z height dimension of the volume, the volume of the package is more important than the X and Y dimensions of the package, and there is a specific Z height or "headroom" limit for the user equipment package. But this assumption leads to an increasingly larger XY area in order to reduce the Z dimension, bringing the above problems. However, it has been found that stacking laminated packages can lead to solving these problems, producing less expensive substrates, a reduction in power loss through the routing of feeders (for example, in 5G mmWave operations, very important) and less radiation blocking. The aspects described herein focus on volume, as opposed to area. In other words, through stacking it has been discovered that reduced X and Y dimensions are important, and Z height is slightly less critical than previously thought.

[0870] Various aspects may initially appear to increase Z height slightly, as they can actually stack more components one on top of another. But the result is a large reduction in the X and Y dimensions, with the disadvantageous effect of solving or reducing the above problems of substrate cost, power lost through long feed lines, and radiation blocked by shields and other equipment obstructions.

[0871] Furthermore, it is believed that the Z height of the POP stack will actually meet the needs of current and future wireless user devices. Further, according to some aspects, compared to previous designs, Fig.44A and Fig.44C Top view and Fig.44D The net area below or above the silicon for the smart antenna array (e.g., antenna elements 4403, 4404, and 4405) visible in the side view in FIG. 4 takes up significantly less space and requires less overall feed routing. In other words, in FIG. Fig.44D In the aspect of FIG. 4 , antennas 4403, 4404 are "below" and in close proximity to die 4409, and antenna 4421 is "above" the die and in close proximity to it. The closeness is such that the feed lines that transmit the signals have to traverse very small distances, which means less (and in some aspects, significantly less) power loss due to routing of long feed lines in previous designs.

[0872] In addition, some discrete components (one of which is enumerated as 4413 and connector 4417) that are not required in the antenna feed process and can be placed laterally to the antenna (which is in Fig.44B and Fig.44D The substrate 4401 is shown with the antenna and die on the left side of the package, so that in the case of a full POP implementation, the feed lines connecting the die to the antennas on the top and bottom of the package traverse a shorter distance to the antenna. Fig.44B The length of the contacts 4407 are coextensive for the purpose of illustrating the antenna elements, but in Fig.44D As can be seen, the substrate 4401 extends over the entire assembly and connector.

[0873] As described above, in previous designs, the die and discrete components were placed under the metal shield so that the discrete components would be co-located at the die with the metal shield on top of the discrete components and the die. Due to the fact that in a stacked package, the larger discrete components (e.g., 4413) can be offset from the die in some ways and also because some of the volume in the Z dimension that was unused in the previous design becomes usable space, the combination is actually higher in POP than disclosed herein. This is seen in Fig.44D The available space 4425 in the antenna is now available for the placement of smart antennas or smart antenna arrays (such as antennas 4421 and the antenna arrays of which they form part).

[0874] As mentioned above, the die is surrounded by Fig.44B Neutralization Fig.44D The contacts 4407 in the substrate 4401, which in some aspects can be solder balls. These contacts (such as the mentioned solder balls) contact at least one metallization layer of the substrate 4401. This is seen in Fig.44B and Fig.44D .exist Fig.44D In the cutaway view of FIG. 4 , solder balls 4407 are seen to also be contacting the metallization layer of substrate 4401 and the metallization layer of substrate 4419. Thus, in some aspects, if the solder balls surrounding the die are spaced at a high density, the combination of the solder balls and the two metallization layers on the top and bottom act as a Faraday cage, becoming a shield for die 4409 without the bulk and height of a discrete metal shield used in previous designs. In some aspects, the contacts can be metallized vias, and if spaced at a high density, can also contact the upper and lower metallization layers and act as a Faraday cage.

[0875] In some aspects, the vias can be perpendicular to the substrate. In some aspects, the vias can be in a pitched direction relative to the substrate. In either case, the density of the spacing of the contacts (e.g., vias) or the density of the pitch between the contacts is approximately λ / 20 or less, where λ is the wavelength of the operating frequency. In view of the described Faraday cage, mechanical shields of previous designs may be absent in the described aspects, making the Z height even smaller.

[0876] Furthermore, antenna elements 4403, 4404 and antenna element 4421 of packages 4401 and 4419, respectively, need not be in the same transceiver. An important advantage of stacked packages is that multiple radios and multiple systems are allowed to be stacked on top of or along each other. In some aspects, antennas 4403, 4404 can be coupled to a radio in a Wi-Fi system operating in a Wi-Fi band, and antenna 4421 can be coupled to a radio in a mmWave Wireless Gigabit (WiGig) system, wherein, in some aspects, die 4409 has a Wi-Fi system configuration and a mmWave WiGig system configuration.

[0877] In some aspects, die 4409 may actually include multiple dies (e.g., one die connected to antenna groups (e.g., 4403, 4404) configured for Wi-Fi operation and another die connected to another antenna group (e.g., 4421) configured for mmWave WiGig operation). In addition, in some aspects, if the antenna array (e.g., patch elements 4403, 4404, and 4421) is not connected to the antenna group, such as 4403, 4404, and 4421, the antenna array may be configured for Wi-Fi operation. Fig.44D The antenna elements in the POP configuration are laid out so that they are electrically opposite to each other, and if the antennas are controlled to transmit together, the radiation can be laterally, for example, usually in Fig.44D In the side-shooting operation indicated at 4420.

[0878] Still further, in some aspects, the transmissions of the antenna arrays on opposite sides of the package can be algorithmically controlled to transmit in opposite directions even at one hundred eighty degrees (180°) angular opposition; and in some aspects, the transmissions of the antenna arrays on opposite sides of the package can be in the same direction.

[0879] exist FIG. 45A to FIG. 45D and FIG. 46A to FIG. 46DAs can be seen in the Figures, in some aspects, due to stacking, the number of antennas can vary in different aspects. In previous designs, antenna placement was limited to only specific places of the package due to the space occupied by discrete metal shields. However, because of the improvements brought about by the stacking technology described herein, this limitation is generally not present. In addition, as described above, the metal shields of previous designs create radiation barriers, additionally limiting the placement of antennas. This limitation is greatly eliminated in the POP design. Therefore, in some aspects, the number of antennas and the size and shape of the antenna array can be customized according to the needs of the devices that a particular package will include.

[0880] FIG. 45A to FIG. 45D The aspects shown show FIG. 44A to FIG. 44D Variations of the aspects of the present invention, wherein like reference numerals refer to like drawing items in both sets of drawings. Fig.45A A top view of a substrate of one package of another dual package system is shown in accordance with some aspects. Fig.44B Showing some aspects Fig.44A Bottom view of the substrate. Fig.44C Showing some aspects Fig.44A and Fig.44B Bottom view of the substrate of the second package of the dual package system.

[0881] Fig.45A A package 4500 is shown comprising a substrate 4501 and antennas, one of which is identified as 4504. The antenna is shown as a dual patch antenna by the two matching points indicated by two small dots on each antenna element. The substrate 4501 is shown in a top view. Fig.45B yes Fig.45A The bottom side of substrate 4501 is shown. Fig.45B Shown are RFIC die 4509 and discrete components, one of which is indicated as 4511. Contacts 4507, which in some aspects are solder balls, surround the periphery of the die and discrete components and contact at least one layer of substrate 4501. In some aspects, the horizontal dimension L2 of package 4504 is substantially the same horizontal length of contacts 4507 forming a Faraday cage.

[0882] exist FIG. 45A to FIG. 45D, antennas (e.g., patch antennas 4504, which may constitute an antenna array on substrate 4501, and patch antennas 4521, which may constitute an array antenna on substrate 4519) may be symmetrically and vertically placed relative to each other, as may be desired in some aspects. This will enable the antenna elements to be controlled to transmit together and provide radiation (e.g., providing radiation in opposite directions) by an array including antenna elements 4521 in one or more desired directions perpendicular to substrate 4519 and by an array including antenna elements 4504 in one or more desired directions perpendicular to substrate 4501. In some cases, depending on the transmit sequence, the radiation of the two aforementioned arrays may be laterally in broadside operation, as shown at 4520.

[0883] Fig.45D FIG. 1 shows a stacked package in a package-on-package implementation according to some aspects. FIG. 45A to FIG. 45C A first package and a second package. Fig.45D Aspects 4506 and Fig.44D Similar to Fig.44D In the present invention, stacking is not only beneficial for Z height improvement, but also has advantages in being able to use XY area to provide better antenna radiation. These advantages are not available in some previous designs explained above.

[0884] FIG. 46A to FIG. 46D The aspects shown show FIG. 44A to FIG. 44D Another variation of the aspect of the present invention, in which like reference numerals refer to like drawing items in both sets of drawings. Fig.46C The horizontal dimension L3 of package 3604 is as in Fig.45C 4609 is substantially the same horizontal length as the horizontal length of densely packed contacts 4607 that form part of a Faraday cage to shield die 4609. In some aspects, discrete component 4611 has been placed laterally separated from die 4609 and protected by Fig.46D The following is about the encapsulation 4614 protection in the stacked package configuration. Fig.47D The use of encapsulation in a package-in-package or package-on-package aspect is explained in more detail.

[0885] FIG. 47A to FIG. 47D An example of an encapsulated POP implementation in accordance with some aspects is shown. Fig.47A A top view of a substrate of one package of yet another dual package system is shown in accordance with some aspects. Fig.47B Showing some aspects Fig.46A 4704 and 4721 (which are patch antennas in some aspects) are substantially the same as FIG. 44A to FIG. 44DThe number and type of antenna elements are not critical, as several types and numbers of antenna elements may be used depending on the requirements and specifications of the package at hand.

[0886] In some aspects, antenna elements 4704 and 4721 may be placed in different ways on each package to form two arrays, such as Fig.47A and Fig.47C As indicated in . Fig.47C Showing some aspects Fig.47A and Fig.47B 47. Bottom view of the substrate of the second package of the dual package system of FIG. Of note is the fact that antenna elements 4721 are positioned laterally from their positions in the previous figures, again illustrating the versatility in antenna placement afforded by the stacked package technique that was not available in previous designs with discrete metal shields that interfered with placement and radiation of the antenna elements. Fig.47D FIG. 1 shows a stacked package in a package-on-package implementation according to some aspects. FIG. 44A to FIG. 44C A first package and a second package.

[0887] Fig.47D Of note is the encapsulation or mold 4724 covering the tube core 4709 and the discrete components 4711. The encapsulation can be a mold, a resin, an adhesive, etc. The through-hole mold via 4715 connects the antenna element of the substrate 4701 and the antenna element of the substrate 4719 to the tube core 4709, and in some aspects, for example, operates as an antenna feed portion by way of strip lines 4712, 4714. The through-hole mold vias can be of various types (e.g., copper pillars, solder balls, via holes plated with conductive epoxy, or any other suitable conductor). The encapsulation can be a fully definable material (e.g., an epoxy that can be a laser mechanically drillable material). Alternatively, according to some aspects, the mold can be a fluid material that is actually molded around the pillars. As an example, the through-hole mold vias can be vertical pillar-like pillars or pillars, and the encapsulation can be fluid so that it can envelope all the pillars (or pillars). Therefore, the pillar type through-hole mold vias can be placed first, and then the encapsulation can be added thereafter. Alternatively, the encapsulation may be added first, and the through-hole die vias may be added by drilling through the encapsulation, and adding the conductive vias after drilling through the encapsulation. The advantage of the encapsulation is that while the antenna element remains close to the die as discussed above, the die gives significant additional protection to the die, adding increased reliability and robustness without significantly increasing the distance from the antenna element to the die, except for the increased distance due to the placement of the antenna, which may be part of the requirements regarding the packaging solution at hand.

[0888] An additional significant use of both X and Y space, and also Z height, in a mobile device is the use of connectors (typically snap connectors). Thus, maintaining the required electrical connection from the electronics to the outside world but at the same time eliminating the need for connectors would save substantial and valuable XY real estate and Z height in the packaging for a mobile device. Some have considered soldering flexible coaxial cables or other technical cables that provide the electrical connection and thereby avoid the use of connectors. In some aspects, the flexible cable can be soldered in place and molded into the package in much the same way that the assembly is molded using an encapsulation as described above. In some aspects, Fig.47D The coaxial cable 4722 can be welded to the appropriate connection point, for example, at 4720, and in some aspects is also secured by the encapsulation 4724. The encapsulation (e.g., mold, epoxy, or other encapsulation) allows the coaxial cable to be connected to the substrate as a sealed solution, which can then be sputtered with some type of conductive material to shield the entire combination. The coaxial cable welded and molded in this manner should have sufficient strength to maintain electrical connection without the need for ordinary connectors, and the encapsulation makes the coaxial cable connection robust enough in the package to provide a solution for the need for electrical connection from the inside of the package to the outside world without the need for actual connectors. In some aspects, the welding at 4720 may not be required, and the encapsulation will be sufficient for the required robustness. This produces the substantial XYZ space savings briefly discussed above. In some aspects, by using a board-to-board connector, a flexible cable can provide the required connection.

[0889] In some aspects, there is a need to have antennas on both the top and bottom of the substrate including the die, and there is also a need to reduce both the Z height and the Y dimension of the package.A solution that provides the above needs uses two packages side by side. Fig.48A Shown is a top view of two packages of a dual package side-by-side package system in accordance with some aspects. Fig.48A Two different packages 4800, 4802 are shown in a side-by-side configuration according to some aspects. Fig.48A Package 4800 in 4801 includes substrate 4801. Seen in the top view ("TOP") of package 4801 is item 4808, which is a partial top view of a metal shield covering an RFIC die 4809 and related components for RFI / EMI protection. Offset to either side of shield 4808 are discrete components (one of which is designated at 4811) and contacts (e.g., solder balls 4810) of a type that does not require shielding. Fig.48B Showing some aspects Fig.48A4800. On the bottom side of substrate 4801 of package 4800 are antenna elements shown as dual patch antennas, one of which is designated 4804. Also shown is an end-fire antenna (e.g., dipole 4805). While the current aspects show patch antennas and dipole antennas, other aspects may use different antenna types depending on the desired solution.

[0890] The second package is generally shown in Fig.48A 4802. Shown is a top view ("TOP") of package 4819 according to some aspects. Package 4819 includes: contacts 4810', which in some aspects are solder balls; discrete components, one of which is designated as 4813; and soldered and / or encapsulated cables 4817, discussed in further detail below. According to some aspects, Fig.48B The bottom view ("BOTTOM") of package 4819 is shown including dual patch antenna elements arranged in an array, one of which is designated at 4821. According to some aspects, the printed dipole antennas, one of which is designated at 4820, are configured for end-fire operation.

[0891] Fig.48C Packages 4800, 4802 are shown in a side-by-side configuration. Encapsulation 4824 encapsulates cables 4817 and discrete components 4813 of package 4802. Encapsulation 4814 also encapsulates discrete components (one at 4811) and shield 4808 (not shown in the figure to save space) and die 4809. It is worth noting the fact that package 4800 has been "flipped". In other words, although package 4802 is in a state of being "flipped" by its top ("TOP"), Fig.48C at the top and its bottom (“BOTTOM”) is at Fig.48C 4800 resides at the bottom of the package 4802, but the package 4800 is juxtaposed with the package 4802, wherein the package 4800 is at the bottom of the package 4802 through its top ("TOP") Fig.48C and its bottom (“BOTTOM”) is at Fig.48C The two packages are secured by contacts bonded together (e.g., solder balls at 4810-4810'). This creates antenna 4821 facing downward (which is on the BOTTOM side of package 4819) and antenna 4804 facing upward (which is on the BOTTOM side of package 4819) to provide the desired solution, i.e., reduce the Z height of the package and reduce the Y dimension, as described above.

[0892] The reduction in Z height can be seen in the fact that the side-by-side design does not use vertical stacking in the manner of the above POP design. The reduction in Y dimension can be seen in Fig.48C and FIG. 48D. In both figures, the dimensions of antennas 4804 and 4821 are extremely small. Fig.48A In some aspects, these two factors bring about a smaller Y dimension, so that the design can be placed close to the edge of the user device (Y dimension), leaving additional XY space for the display of the mobile user device to almost touch the edge of the mobile device in the Y dimension. Two antenna sets 4821, 4804 are fed by the tube core 4809. Because of the proximity of the antenna 4804 to the tube core, these antennas will have a desired extremely short feed line from the tube core 4809. Due to the offset that is acceptable in this case in order to fit in the specific mechanical design of the mobile device, the antenna 4821 will have a slightly longer feed line, reducing the Y and Z dimensions in the very narrow space between the display screen of the mobile device and the end of the cover in this example.

[0893] In some aspects, at least some of the above-described requirements for varying the polarity of radiated radio waves at varying times and varying spatial diversity can be met by modifying a standard MicroSD form factor card with respect to a wireless communication user device (e.g., a mobile device) to include a mmWave antenna and transceiver device or other die. The advantage of this modification is that the form factor can be used in a mobile device. Because the Micro SD format is of appropriate size to include a number of mmWave antennas from one to a few, and for RIFIC to be placed in an already existing form factor, there is no need to design a new form factor. In addition, the identification of such existing forms can quickly implement solutions accepted in handheld / phone solutions, providing huge cost savings and possible operational advantages. In addition, the fact that the Micro SD form factor card can be inserted into a user device provides a form factor marketing advantage because it can be installed or prohibited from installation at will, as is appropriate for one aspect.

[0894] Micro SD cards can enable the population / de-population of antennas and radio technologies as needed for interchangeable frequency ranges to support different terrains. For example, from a regulatory point of view, different terrains may make different frequency bands available to users. If the Micro SD cards are frequency bands defined, they can be swapped in and out of user devices as needed to operate in the desired frequency bands appropriate for a particular terrain.

[0895] Because these form factor cards can be easily placed near the end of a mobile platform, the antenna faces outward. Form factor cards already have areas that are RF exposed and not covered by the socket metallization often found on substrates. This exposed area can be used for antennas or small arrays to be embedded within the card. Given the ultra-small size of antennas operating at mmWave frequencies, it is very efficient to fit small antennas and / or small antenna arrays in these areas.

[0896] In some aspects, multiple instances of the card can be arranged to form a massive antenna array (MAA). In addition, multiple sockets (placed outside the RF exposed area of ​​the card) can also enable support for different frequency range subsystems. The antenna can be an end-fire type antenna in some aspects, but the exposed section outside the socket metal structure can enable other types of antennas that radiate in other directions. In other words, and as described below with respect to Fig.50 As will be discussed, the Micro SD card has an exposed area that is not covered by the metallization associated with the socket into which the Micro SD card is inserted. Different types of antennas can be placed in this area to enable radiation in different directions. In some aspects, an end-fire antenna can be used because the end-fire radiation pattern direction will be in the horizontal direction relative to the orientation of the Micro SD card. However, other antenna types with other radiation pattern coverage can also be used.

[0897] As used in this disclosure, terms such as “front,” “rear,” “upper,” “lower,” “side,” etc. are used with respect to the orientation of the drawings. Fig.49 is a description of the various sizes of SD flash memory cards. SD flash memory cards can be included in Figure 3A 315, receiving circuit 320, RF circuit 325, and antenna array circuit 330 of mmWave communication circuit 300 are shown, but SD flash memory cards are not limited to this. Various sizes of SD form factors can be generally seen at 4900. A standard SD form factor card can be seen in front view 4901A and rear view 4901B. Electrical contacts can be seen at 4903. The dimensions of the standard SD form factor are shown in millimeters. Mini SD form factors can be seen at 4905, also with dimensions indicated in millimeters in the front and rear views. Micro SD form factors and their dimensions can also be seen at 4907 in the front and rear views.

[0898] In some aspects, the Micro SD card format can be effectively used for mmWave communications by changing the content and functionality to adapt the card to mmWave operations in wireless communication devices. One reason for this is that, as briefly discussed above, the size of the Micro SD card format enables it to be used for mmWave operations, especially because space in wireless communication devices is scarce and the size of the Micro SD format provides space advantages for use in mobile devices when space is scarce. In addition, given that the Micro SD card has electrical contacts at the "back" area 4909, the "front" area 4911A, 4911B is a section of the Micro SD card that is exposed and not covered by the metallization of the socket into which the Micro SD card is inserted. This makes it attractive for millimeter wave frequency subsystems with antennas, because the antenna can be in an exposed area, while other parts (such as a transceiver) can be covered by metallization that acts as a shield. In some aspects, the antenna is placed in the internal area of ​​the card at 4911A and 4911B, discussed in more detail below. The antenna requires a non-metallized area where they can radiate away from the wireless subsystem. Because they are non-metallized, the interior area of ​​the 4911A and 4911B is ideal for antenna placement.

[0899] Fig.50 A three-dimensional view of a Micro SD card having content and functionality that is changed to modify the card for mmWave wireless communication operation according to some aspects is shown. The Micro SD card-shaped digital card includes a card 5001 visible in the three-dimensional view, which has the front 5001 of the card in the full view. The electrical contacts 5003 on the back of the card are shown in the hidden view. As part of the changes in content and functionality implied above, the RFIC 5005 is shown inside the Micro SD card and is therefore also shown in the hidden view. According to some aspects, the internal portion of the card, if viewed along section XX-XX, shows an antenna, which is shown as a dipole antenna 5107A, 5107B in the figure, and is also in the hidden view because they are inside the front of the card at 5009. In other words, the antenna needs to be exposed to radiate outward from the platform on which they are placed.

[0900] The metallized connector for these types of SD cards is at the back 5003 leaving a thick section 5009 of the Micro SD card 5001 without the metal covering it, so that the thick section is ideal for antenna placement. Because it is so small, the card is also well suited for mmWave frequencies because the antenna will be smaller than the available area, and therefore more than one antenna can be included to form an array, and / or antenna diversity can be included. This fact provides additional advantages: the antenna can be used for multiple-input multiple-output (MIMO) operation. In other words, multiple antennas can be used in a radio system in different ways. They can be simply combined, they can be used to steer beams electrically, and they can be used to support MIMO, whereby different antennas support separate radio chains in the solution that can be used to send / receive as separate information streams independent of other antennas, and additional functions can be realized as well.

[0901] According to some aspects, as an example of MIMO operation, antenna 5107A can be used to support one MIMO stream and antenna 5107B can be used to support a second MIMO stream. Antennas with different polarizations can also be used to achieve this purpose. RFIC 5005 will be designed to support these configurations and the number of streams. In this aspect, two antennas 5107A and 5107B are shown, but the solution is not limited to only two.

[0902] According to some aspects, the RFIC 5005 and antennas 5107A, 5107B can be etched, printed, or otherwise configured at 5009 on or within a PCB inside the subsystem, which can be overmolded into the desired Micro SD card shape. The thickness of section 5009 can be used in some aspects to also include taller antenna structures (such as antenna structures required for vertically polarized antennas). The bottom of the PCB will have edge card contacts at the bottom that make contact with the spring contacts in the Micro SD socket. The antennas shown at 5107A, 5107B are dipole antennas as described above and can radiate hemispherical patterns, while other types of antennas can be more fan-shaped in terms of pattern. Dipole antennas can be considered side-firing because even though they also radiate up and down, they radiate in the same plane as the PCB and Micro SD card. Since the exposed portion 5009 of the card 5001 is at the edge, side-firing antennas are more likely to be used in this form factor, such as in Fig.52 , as discussed below. This form factor is also consistent with the type of platform it can be integrated into (e.g., a phone). In other words, Micro SD cards have been the current standard memory module form factor for phones because they are relatively small but have the ability to also support high-capacity memory storage.

[0903] Furthermore, when arranged in an array with multiple instances of these Micro SD cards, then more options come into play and different antenna types that radiate in different directions can be used. Being a very small card means that the card can support antennas of the same order of magnitude equivalent to the magnitude of the size of the frequencies in the mmWave range. Just as an example, there are WiFi wireless solutions in the mini SD card form factor because the size is larger and can support larger antennas that are consistent with the WiFi frequency range (centimeter waves). The Micro SD being smaller can support smaller antennas or a small number of these antennas that can be used at mmWave frequencies, which means that the antennas can be used to form an array when placed at an appropriate distance from each other, the distance being a function of the frequency.

[0904] Fig.51A According to some aspects, the Fig.50 The radiation pattern of a dipole antenna Fig.50 The outward radiation of the dipole 5107A, 5107B is a sort of half-circle, radiating laterally but also up and down. The other half of the radiation pattern may be blocked by the metallization of the phone / handset or Micro SD socket. Fig.51B FIG. 5 shows a vertically polarized monopole antenna element standing vertically in an exposed area 5109B that is limited in Z height according to some aspects. Fig.50 Micro SD card. Other half wraps around vertical polarization elements can also be used. Folded dipoles can also be used. Fig.51C FIG. 1 shows a schematic diagram of a folded dipole antenna 5107AC, 5107BC according to some aspects. Fig.50 Micro SD card. Fig.51A , Fig.51B and Fig.51C Shown are only some of the various types of antenna elements that may be used in various aspects, both individually and in arrays.

[0905] Fig.52 Shown are three Micro SD cards as discussed above modified to provide multiple instances of such a card, each of which may have multiple antennas per card, according to some aspects. Fig.52Generally visible in the figure is the combination of a motherboard 5201 having three Micro SD cards 5203, 5205, 5207 attached thereto, the cards being modified from ordinary flash memory functionality, as discussed above. In some aspects, the antenna in each card may be a dipole antenna 5107A, 5107B, as discussed above, and radiating in the end-fire direction shown by the arrows leading from each card. As shown in other figures herein and as discussed with respect to other figures herein, different types of antennas may be used in some aspects to implement antennas that meet various needs depending on the solution at hand. While three arrays are shown, they may be extended in either direction by adding additional cards along the X axis to increase the array size. In fact, depending on the available volume, they may also be stacked in the Z direction to extend the array in both the X and Z dimensions, as shown in FIG. Fig.50 A coordinate system is shown. By adding many Micro SD cards next to each other or stacked on top of each other with the correct antenna-to-antenna distance and available volume, a massive antenna array (MAA) can be configured. Depending on the operating frequency and therefore the wavelength λ, the number of antennas on each card can be from one antenna to multiple antennas on each card.

[0906] Space in mobile devices for wireless communication is often scarce because of the amount of functionality included in the form factor of these devices. Among other reasons, challenging problems arise because of the need for spatial coverage of the radiated radio waves, and because the signal strength is maintained as the mobile device moves to different places, or because the user may orient the mobile device differently over time. This may lead to the need to change the polarity of the radiated radio waves and change spatial diversity in some aspects at varying times. When designing a package including an antenna operating at millimeter wave (mmWave) frequencies, efficient use of space can help solve problems such as the number of antennas required, the direction of their radiation, their polarization, and similar needs. At least some of these requirements can be met by a ball grid array (BGA) or a surface grid array (LGA) PCB with an area of ​​a specially cleared ball or LGA pad, as the case may be, to enable antenna elements to radiate from all sides of the PCB with an attached millimeter wave (mmWave) transceiver in some aspects.

[0907] Fig.53A is a side view of a separate BGA or LGA pattern package PCB with an attached transceiver subsystem according to some aspects. The separate BGA or LGA pattern package PCB may include Figure 3AIn the RF circuit 325 of the mmWave communication circuit 300 shown, the separate BGA or LGA pattern package PCB is not limited to this. The BGA or LGA PCB has a substantially parallel common layer. Typically, the BGA and LGA packages are spread over the entire subsystem with relatively uniform extension and balls and pads to attach the subsystem to the main board (MB). BGA balls 5305 and 5306 are shown. An area 5303 without balls and / or LGA pads is intentionally generated so that the free area can be used for the antenna section, where, if appropriate openings are made on the MB to which the PCB 5301 is attached, the antenna element can radiate outward. In other words, area 5303 (sometimes referred to as a "gap") should be "contact-free", so that the antenna element is placed so that the antenna can radiate freely. In other words, the gap 5303 in the BGA / LGA attachment point enables the antenna element to be placed in the gap and radiate laterally through the gap or if the antenna element is a side-firing type.

[0908] As used in this patent, the terms "top", "bottom", "upward", "downward", "lateral" are used with reference to the orientation of the drawings and are not intended to limit the direction of radiation when the package is implemented in a mobile or other device, which can be directed in any direction. Therefore, the radiation described herein is actually in the outward direction regardless of the orientation of the package in the user device.

[0909] In one aspect, downward (outward) facing antenna elements 5315, 5316, 5319, and 5321, shown here as patch antennas (which in some aspects can be arrays of patch antennas or other antennas), radiate downward. This is shown in the figures by wave patterns 5316, 5318, 5320, and 5322. In some aspects, the RFIC transceiver 5307 can be attached to the top of the subsystem and protected from radio frequency radiation (RFI) and electromagnetic interference (EMI) by shield 5309. Antenna elements 5311, 5313 facing upward in the figures can radiate in upward (downward) directions 5312, 5314, respectively. The ability to radiate multiple directions from the platform provides advantages.

[0910] For example, radiation is shown in the opposite direction, but the patch antenna shown can be replaced by other antenna types that radiate laterally (e.g., end-fire or broadside antennas) and can be placed at the edges of the subsystem. Thus, the described subsystem can use different types of antennas with different types of advantages including directions of radiation and polarization.

[0911] As an example, the patch antennas shown have the advantage that each can have two orthogonal feed points to generate two polarizations, but their radiation is essentially broadside, so they will work well in the configuration shown. In some aspects, many antenna elements arranged on the module can be used for beam steering in the array. In addition, this type of subsystem arrangement can find use in multiple-input multiple-output (MIMO) antenna arrays and arrays configured for spatial diversity. Spatial diversity can be achieved by having antennas with radiation patterns in different directions. For example, the patch antenna on the top radiates upward, and the patch on the bottom radiates downward. Other antenna types can be introduced to radiate laterally (e.g., broadside antenna types), thus achieving spatial diversity in some aspects.

[0912] Although the side view is shown as Fig.53A The antenna elements 5311 and 5313 in FIG. Fig.53C It will be shown that there can be multiple of these antennas (e.g., 5330, 5331 and 5332, 5333), as discussed below. Although a specific number of antennas are described, it will be understood by those skilled in the art that the number of antenna elements can vary from aspect to aspect. The operating frequency and antenna size determine how many antennas can actually fit in a given area / space to be effective in an array. In addition, the types (monopole or stacked patch antennas, dipole antennas, and other types) and their arrangements, for example, in an array can also vary. In addition, in many small form factor devices, because area / space is so precious, a subsystem that radiates in multiple directions as described above will have a highly efficient use of area / space with a large (in some aspects, or perhaps the largest) coverage.

[0913] Fig.53B Based on some aspects Fig.53A Side view cross section of a subsystem. Fig.53B MB 5323 is shown with a cutout 5304 implemented to enable antenna elements 5315, 5317, 5319, 5321 to be exposed outward for radiation. In other words, the separate pattern 5303 in the package enables the antenna to radiate from the attachment side of the mmWave antenna and transceiver subsystem. Because of the cutout in the area, the antenna elements 5315, 5317, 5319 and 5321 can radiate freely without essentially anything blocking them, and this makes radiation in another direction possible in the limited area / volume of the solution. In some aspects, the antenna elements 5315, 5317, 5319 and 5321 are on the same side as the BGA / LGA 5301 attachment side (the side on which the BGA / LGA is attached to the MB). In some aspects, the cutout is implemented as a contoured machined cutout made by a path that follows the PCB contour.

[0914] Also shown are antennas 5311 and 5313 on the top side of the subsystem. In some aspects, discrete electronic components that require Z height can fit in the cut-out 5304 in the PCB. In some aspects, the shielded RFIC itself can be placed in the cut-out at a contact-free area for operation and save the overall Z height of the solution. In other words, an integrated circuit chip (e.g., an RFIC) is typically accompanied by some discrete components of a complementary chip (e.g., decoupling capacitors) as well as other functions. In some aspects, these components can be placed in the gap 5304, rather than the antenna elements being in the gap. However, if the component is part of a radio transceiver circuit located in the gap, appropriate RFI / EMI shielding should be implemented, as described above.

[0915] Fig.53C 5301 and also showing a cutout or gap 5304. It can be seen, and as briefly discussed above, that the upward facing antennas 5330, 5331 and 5332, 5333 are in some aspects two arrays of two antenna elements. Other configurations of antenna elements are possible based on a given design to achieve a solution appropriate to the needs of a given situation by one skilled in the art.

[0916] While the above description discusses the use of the subsystem in a mobile device, the subsystem may also be used in a base station, although a base station implementation may not benefit from having radiation in two or more directions. While the base station array size may be limited to one axis, modularity may facilitate the placement of the subsystem in desired directions, including in a ring around a pole. Fig.53E An arrangement of subsystems arranged in a circular manner around a pole for radiation coverage in substantially all directions according to some aspects is shown. Subsystems 5341, 5342, 5343, 5344, 5345, 5346, 5347, 5348 are attached to pole 5341. Each subsystem may be as shown. Fig.53A 53, wherein the BGA / LGA stackup 5301 is attached to the motherboard 5323. The direction of radiation will be indicated by arrows in all or substantially all directions.

[0917] Although a rectangular shaped subsystem is shown, other shapes are possible (such as, for example, a square or corner shape). Fig.53D A U-shaped cutout in a PCB is shown for enabling an antenna to radiate out through the cutout in accordance with some aspects. The array of pads 5324, 5326, which are gold pads in some aspects, are electrical contacts for signaling the subsystem and also serve as a mechanical attachment means when the subsystem is soldered to them.

[0918] Fig.53FA subsystem of a corner shape according to some aspects is shown. A top view shows a subsystem 5350 having four antenna elements 5351. One of the four antenna elements is shown in dashed lines for the purpose of showing that antenna elements can exist on both sides of the subsystem. Subsystem 5350 is shown in the illustrated aspect as being λxλ in size because if the antenna element itself is λ / 2 (as discussed further below), then the actual size of the subsystem with a 2x2 antenna array will be approximately λxλ as shown with all overhead and ground around the element. The bottom view shows a shielded RFIC located in gap 5304E, wherein the shield 5356 and RFIC 5355 are shown in a full line view for clarity of illustration. A BGA ball or LGA ball is shown at 5354. Antenna element 5351 is shown as a broadside element (e.g., a patch antenna), but in some aspects can be replaced by an end-fire element (e.g., a dipole) for end-fire coverage.

[0919] Figure 53G Shown is placed in the corner of the main board 5323 Fig.53A A subsystem, wherein 5361 hidden from view is an RFIC shield, and the antenna element is 5362, wherein only one antenna element is numbered in the drawing to save space. Fig.53H A side view of the subsystem 5364 attached to the mainboard 5323 via BGA balls 5306 is shown, with antenna elements 5362 , 5263 shown in a side view looking into the page, and a shielded RFIC 5367 with discrete components also within a shield 5368 .

[0920] Fig.53I 53 is a top view of a configuration of a dual shield subsystem 5370 having a shape for use in a corner according to some aspects. Subsystem 5370 is shown with a cut-off corner edge 5376. Four broadside antenna elements 5371 are placed adjacent to the side of a shield 5374 that shields an RFIC or other integrated circuit 5375, which are shown in solid lines for illustration purposes, but are actually within the shield 5374. Endfire antenna elements 5372 are placed around the periphery of the subsystem. Dimensions are shown similarly to and with reference to antenna element 5371 with respect to antenna element 5377. Fig.53J A slide view of the subsystem of FIG. 531A is shown according to some aspects. Shown is a top shield 5383 with integrated circuit 5382 and a bottom shield 5384 with integrated circuit 5385. Antenna elements 5386, 5387 and 535388, 5389 are present on opposite sides of the subsystem 5300. The subsystem is attached to the MB 5323 as shown by welding or other suitable attachment means.

[0921] BGA balls (or LGA pads) at both ends of the arrangement have an additional advantage during assembly, since no additional support is required when the subsystem is soldered to the MB. It has been observed that the subsystem is soldered or otherwise attached at the corners of the PCB, such as at Figure 3C and Figure 4 B, there is nothing actually holding the subsystem in space while the balls or LGA pads are being soldered along the corner "L". The subsystem will fall under its own weight during the process. However, by having a rectangular subsystem with balls or LGA pads at the far end, e.g. Fig.53B There is no need to worry that the subsystem will fall anywhere other than where it should be due to gravity.

[0922] In the PCB assembly process, the PCB can be placed on a conveyor. It can then be soldered and then by pick and place (or manually), the components are placed in their positions on the solder bonded pads. The PCB then passes through an oven and the solder melts under the components before soldering them to the PCB. The PCB is then cooled and cleaned, resulting in an assembled PCB. In some cases, because some components are also glued before the soldering process, they do not move. However, in the case of corners, this may not be significantly helpful because gravity may pull the subsystem off the PCB before it can be soldered. In these cases, special mechanisms should be added to support the parts that may "fall off" and keep them in place.

[0923] For widespread deployment of 60GHz or 5G technology, 60GHz system-in-package SIP production testing is likely to be very expensive or possibly unaffordable. The signal will be radiated and received at the millimeter wave (mmWave) frequency range (e.g., 60GHz) for some aspects, but for other aspects, 28GHz, 73GHz, or other mmWave bands are also available. In general, due to the complexity of the SIP and any associated assembly, testing should include antenna testing. Therefore, the test will be a test of radiation. On-chip "built-in self-test" (BIST) can be used to help with this testing, but the BIST will most likely not include antenna element testing.

[0924] Typically, because the device to be tested (here, the SIP) includes a phased antenna array, multiple antennas and transceiver elements will need to be tested. These requirements render conventional testers inappropriate because their operating frequencies are much lower than mmWave frequencies, and these tests typically do not include radiated tests. Instead, conductive or contact tests (e.g., probing) are typically used. However, 60 GHz systems are extremely sensitive to even very small non-idealities. For example, if a 60 GHz probe is used to test the gain of an amplifier, the repeatability of the landing and the aging of the probe may introduce many dB of gain variation, making probe-based 60 GHz production testing very difficult.

[0925] In addition, 60GHz systems typically integrate 60GHz antennas on packages that include radio frequency integrated circuits (RFICs) of SIPs. This eliminates cable losses that would be very high at 60GHz and allows phased arrays that achieve desired coverage to be easily implemented. These package configurations will also have to be tested, which is an expensive proposition. In addition, high-volume manufacturing (HVM) testing requires understanding antenna and assembly failure modes (such as mishandling of antenna substrates or defective assembly of RFICs on substrates). Experiments have shown that 60GHz systems are far more sensitive to assembly defects than 2.5GHz-6GHz systems. For these reasons, it is desirable to include antennas in 60GHz HVM testing. Therefore, it is generally believed that nearly unbearably expensive 60GHz equipment will need to be added to the tester to perform 60GHz testing.

[0926] Disclosed is a practical way to perform HVM production self-test of 60GHz systems by solving the above problems through the use of loopback testing. Loopback testing refers to the routing of electronic signals, digital data streams or items from their source through the system and back to their source without intentional processing or modification. This is primarily a way to test the transmission or transport infrastructure of a SIP.

[0927] There are various examples. As an example, a communication channel with only one communication endpoint can be tested. Any message sent by the channel is immediately and ideally received only by the same channel. In telecommunications, loopback equipment performs transmission tests of access lines from a service switching center, which usually does not require the assistance of personnel at the terminal being served. In telecommunications, loopback or loop is a hardware or software method of feeding a received signal or data from a sender back to the sender. It is used as an aid in debugging physical connection problems. As a test, many data communication devices can be configured to send a specific pattern (e.g., all 1s) on an interface and can detect the reception of the signal on the same port. This is called a loopback test and can be performed in a modem or transceiver by connecting its output to its own input. The circuit between two points in different locations can be tested by applying a test signal on the circuit in one location and causing the network device at another location to send the signal back through the circuit. If the device receives its own signal back, this indicates that the circuit is functioning.

[0928] Using 60GHz equipment as an alternative to the above 60GHz system testing can either be well characterized / stable using expensive equipment (such as a vector network analyzer (VNA)), or a customized subsystem with third-party components. In view of the cost, stability of the measurement and / or aging of the customized subsystem, these two methods have limitations. The disclosed self-contained self-test solution uses a 60GHz system to test itself. This avoids the need for expensive / sensitive 60GHz equipment. It naturally also includes antennas in the test, which is critical for the 60GHz system in package, and also solves the inevitable on-chip and on-package crosstalk problems. The reflector on the tester makes it possible to loop back the baseband to the baseband including the antenna. The loopback self-test scheme is sometimes used to test RFIC at lower frequencies, but not the antenna. According to some aspects, the disclosed system extends the loopback to include the antenna as a component of the 60GHz system.

[0929] Fig.54A 5400 is a top view of a 60 GHz phased array system in package (SIP) according to some aspects. The SIP 5400 may include Figure 3AIn the RF circuit 325 of the mmWave communication circuit 300 shown, but the SIP 5400 is not limited to this. According to some aspects, the SIP 5400 includes an antenna array 5401 and a 60GHz RFIC 5403 on or within a substrate 5405, which may be a low temperature co-fired ceramic (LTCC). The RFIC 5403 receives an input signal via a connector 5406. The antenna array 5401 includes an array of elements 542 visible in more detail at 5402. According to some aspects, the array is fed by the RFIC 5403 via a series of microstrip feed lines. According to some aspects, one antenna element of the array visible at 5407 is fed by a feed line 5409. The second antenna element of the array visible at 5407' is fed by a feed line 5409'. The feed line 5409' is structured in this way to slow down the RF signal from the RFIC. In other words, the feed line length is matched, so that the group RF signal delay of the antenna is matched. This helps with beamforming calibration (e.g., less static mismatch, reduced sensitivity of calibration to channel frequency). According to some aspects, a series of balls 5413 are raised portions for signal connections to the package when the chip is flipped on the package. Although an array of 542 antennas is shown, in some aspects more than 542 antennas or less than 542 antennas may be used.

[0930] Fig.54B Showing some aspects Fig.54B Side perspective view of a SIP. Fig.54B A stepped platform 5404 is shown including three step-like levels 5408, 5410, 5412 according to some aspects. Because antennas typically require additional substrate layers for proper operation, antenna 5412 is on the highest level. Level 5410, which includes RFIC 5403, does not include vias, which may not be helpful for mmWave signals. Therefore, in some aspects, the feed line is routed directly on the top layer 5412. In other aspects, the feed line goes "inside" the dielectric to reach the antenna at level 5410. Level 5408 is thinner to provide space for connector 5406.

[0931] Fig.55 A 60 GHz SIP is shown placed on a self-tester in accordance with some aspects. The SIP placed on the tester can be generally seen at 5500. A tester useful for testing, such as the tester described herein, typically includes at least one computer, power, software, computer readable hardware storage including computer instructions that when executed by the computer test the system under test according to a predetermined test, and a docking capability including a test station for receiving and securing the system under test. SIP 5400 can be a 542 antenna (one of which is enumerated as 5401) and RFIC 5403 on a substrate 5405. Fig.54A 5400 of the type shown. RFIC 5403 may include a power amplifier 5416 configured to drive the antenna of SIP 5400 and a low noise amplifier 5420 configured to receive from the antenna of SIP 5400. Phase shifters 5414, 5418 may be included as needed to assist in beamforming. One of the antenna elements T of the phased array is set in transmit mode. The transmit (TX) antenna 5422 transmits a 60 GHz signal. The reflector 5502 fits on the tester and reflects the 60 GHz signal back to the SIP, where it is controlled by the receive (RX) antenna 5424. The reflector will in some aspects be on top of the IC being tested, and therefore on top of the tester discussed above and discussed in further detail below. Some current testers have arms with mmWave horn antennas and downconverters / upconverters to receive or transmit reference signals for calibration. In the disclosed system, the reference radio at the end of the arm of the current tester would be replaced by a simple reflector 5502. This should allow for easy adaptation of today's testers (which are typically test circuits designed for less than 60 GHz) to be suitable for mmWave testing.

[0932] In some aspects, the signal received by antenna 5424 is amplified and down-converted in the RFIC. Fig.55 The arrangement establishes a loopback around the entire 60 GHz system, which can be used to measure certain key performance metrics (e.g., gain), determine whether a part is good or should be discarded, and / or calibrate the part for manufacturing variations (e.g., mismatch discussed in more detail below). This arrangement addresses two important issues for 60 GHz HVM testing:

[0933] 1. It establishes baseband to baseband loopback on the tester. Therefore, the tester does not need an expensive 60GHz upgrade. In some aspects, only an inexpensive reflector (such as a metal fixture) may be required to fit on the tester.

[0934] 2. Loopback includes the 60GHz antenna. Loopback testing can therefore target antenna-related issues (such as substrate mishandling) or assembly defects. Because the antenna is in loopback testing, there is a complete system test, not just an RFIC test.

[0935] Fig.56A FIG. 56A shows a test setup for a first portion of a test for addressing undesired on-die or on-package crosstalk in a SIP according to some aspects. In FIG. 56A , 5600 indicates a first setup for addressing crosstalk. In some aspects, the element is Fig.54A and Fig.54B Elements shown are identical elements and will be given the same reference numerals for clarity.

[0936] RFIC 5403 includes a power amplifier 5601 and a low noise amplifier 5603, each of which is coupled to antennas 5407, 5407', respectively. Crosstalk is indicated at 5605, 5607. The system under test 5600 is in Fig.55 The tester shown in FIG. 1 is a tester in which the reflector is removed, but in some aspects this operation can be automatically performed by an electromechanical removal / addition mechanism. Fig.56B 5602 shows a second test setup for addressing undesired on-chip or on-package crosstalk in a SIP. In some aspects, except that the reflector 5502 has been added back (which can also be done automatically by an electromechanical removal / addition mechanism in some aspects), Fig.56B The components and Fig.56A The components shown are the same.

[0937] Fig.57 5700 is an example of an automated test rig suitable for testing a 60 GHz phased array SIP according to some aspects. Fig.55 The test setup of FIG. 56C can be attached to an automated test rig. TM 16 TM Automated tester 5701, which when modified as described herein is an example of a system that can be programmed to implement the testing discussed. It should be understood by those skilled in the art that the tester model described is one of multiple testers that can test less than 60 GHz and can be modified for the 60 GHz testing described herein. According to some aspects, tester 5701 includes mmWave port architecture 5703, production waveguide interconnect 5705, and mmWave test instrument module 5707. The tester can be modified by adding the above-mentioned testing aspects.

[0938] Fig.58 Shows that according to some aspects can be added to Fig.57 5800, a reflector 5502 is attached to a test bench 5801. It can be used to mount a system to be tested 5803 to a Fig.57The test bench 5801 of the test bench of the tester of the appropriate system test bench may include or interface with automated electromechanical equipment to place the system on the test bench for testing and remove the system after testing, as is typically done in HVM. The reflector 5502 is conceptually connected to the tester by a robotic arm 5805 in the aspects to be discussed. It should be understood by those skilled in the art that although the attachment method is conceptually shown by the robotic arm 5805, in fact, in some aspects, the attachment method can be through an electromechanical removal / addition mechanism used in the crosstalk testing described herein. For example, in some aspects, there is an arm on the side of the tester to which the reflector will be attached. If appropriate, there may also be an associated motor to provide tilt for the reflector.

[0939] Many 60 GHz systems are quite asymmetric, that is, they are intended to be primarily a source of high-rate signals (e.g., a Blu-ray player) or a sink of high-rate signals (e.g., an HD TV). That being said, many 60 GHz systems still include both TX and RX paths. For example, an example product solution has the following parameters:

[0940] 60GHz# 60GHz# Source (Blu-ray) 32 4 Xinsu(TV) 8 32

[0941] In the case such as above, the loopback receiver can be one of the already available receivers of the system to be tested. Fig.55 The scheme produces minimal overhead. Because the RFIC of the system to be tested is a phased array transceiver in some aspects, there are multiple RXs and TXs. Therefore, while the TXs (one TX or all TXs with beamforming) are being tested, one of these RXs can be dedicated as a reference receiver. In other words, because the mmWave receiver on the RFIC itself can be used in some aspects, no additional mmWave receiver is required. However, if desired, a dedicated test receiver can also be used. Because 60GHz circuits are typically small due to the high operating frequency, even a dedicated receiver will be a small cost overhead.

[0942] According to some aspects, Fig.55 The loopback test can be used to perform many important 60GHz tests. Tests can include:

[0943] 1. Turn on the TX elements and send radio signals via the TX antenna, and turn on the RX elements one by one and receive radio signals via the RX antenna, wherein the radio signal is reflected by the reflector to the RX antenna, and the received radio signal looped back to the RX antenna via the reflector is measured. A baseband signal can be used for the radio signal. If one of the loopback measurements is lower than the rest, this will indicate a bad TX path (e.g., bad assembly). According to some aspects, the defective path can be disabled and the part can potentially be sold as a good part (because the phased array has large redundancy, one less element is likely to be acceptable for link budget purposes). This test is an attempt to ensure that all TXs have the same power level ...

Claims

1. A transceiver, comprising: a plurality of patch antennas disposed on a first surface of the substrate; A radio frequency integrated circuit RFIC coupled to the plurality of patch antennas, the RFIC being disposed on the second surface of the substrate and configured to: process RF signals received via the plurality of patch antennas; and A shielding body is disposed on the second surface and protects the RFIC from radio frequency interference (RFI) and electromagnetic interference (EMI).

2. The transceiver according to claim 1, further comprising: A plurality of redistribution layers within the substrate couple the RFIC to the plurality of patch antennas.

3. The transceiver according to claim 2, further comprising: A plurality of solder balls are disposed between the plurality of redistribution layers and the plurality of patch antennas.

4. The transceiver according to claim 1, further comprising: A plurality of surface mount devices (SMDs) are provided on the second surface of the substrate.

5. The transceiver according to claim 4, wherein: The RFIC is configured to process the RF signal based on one or more of the plurality of SMDs.

6. The transceiver according to claim 4, further comprising: A molding compound is disposed in a cavity formed between the shield and the substrate.

7. The transceiver according to claim 1, wherein: Each of the plurality of patch antennas is configured as a dual polarization antenna structure with ±45° tilt excitation.

8. The transceiver according to claim 1, wherein: Each patch antenna of the plurality of patch antennas is configured as a parasitic stacked dual patch.

9. The transceiver according to claim 8, wherein: The parasitic stacked double patch comprises: a driven element coupled to the feed line; and Parasitic components.

10. The transceiver according to claim 1, further comprising: Horizontal surface mount device SMD components.

11. The transceiver according to claim 10, wherein: The horizontal SMD component includes at least one patch antenna from among the plurality of patch antennas.

12. The transceiver according to claim 11, wherein: The at least one patch antenna comprises: Parasitic chip components; and A driven capacitive patch antenna element coupled to a dual feed line.

13. The transceiver according to claim 1, further comprising: a baseband circuit configured to generate a baseband signal based on the digital output signal, The RFIC is configured to generate an output signal for transmission via the plurality of patch antennas, wherein the output signal is based on the baseband signal.

14. The transceiver according to claim 13, further comprising: Touch screen display; and a signal processor coupled to the touch screen display via an interconnect, the signal processor being configured to: detecting a signal input received from the touch screen display via the interconnect; and Based on the signal input, the digital output signal is generated.

15. A method for processing a radio frequency (RF) signal, the method comprising: receiving RF signals via a plurality of patch antennas disposed on the first surface of the substrate; down-converting the RF signal into a baseband signal using a radio frequency integrated circuit RFIC, wherein the RFIC is disposed on the second surface of the substrate and coupled to the plurality of patch antennas via a plurality of redistribution layers within the substrate; as well as During down-conversion, the RFIC is protected from radio frequency interference (RFI) and electromagnetic interference (EMI) using a shielding body, the shielding body being disposed on the second surface.

16. The method according to claim 15, further comprising: disposing a plurality of solder balls between the plurality of redistribution layers and the plurality of patch antennas; as well as The RFIC is coupled to the plurality of patch antennas via the plurality of redistribution layers and the plurality of solder balls.

17. The method according to claim 15, further comprising: The RF signal is processed based on one or more of a plurality of surface mount devices (SMDs), the plurality of SMDs being disposed on the substrate.

18. The method according to claim 15, further comprising: generating a baseband signal based on the digital output signal using a baseband circuit; generating an output signal based on the baseband signal; as well as Transmission of the output signal is performed via the plurality of patch antennas.

19. The method according to claim 18, further comprising: detecting a signal input received from the touch screen display via the interconnect; as well as The digital output signal is generated based on the signal input.

20. A system for processing a radio frequency (RF) signal, the system comprising: means for receiving RF signals, the means for receiving comprising a plurality of patch antennas disposed on a first surface of the substrate; A component for down-converting the RF signal into a baseband signal, the component for down-converting comprising a radio frequency integrated circuit RFIC, the RFIC being disposed on the second surface of the substrate and coupled to the plurality of patch antennas via a plurality of redistribution layers within the substrate; as well as A component for protecting the RFIC from radio frequency interference (RFI) and electromagnetic interference (EMI) during reception is disposed on the second surface.

21. The system of claim 20, further comprising: A component for processing the RF signal based on one or more of a plurality of surface mount devices (SMDs), the plurality of SMDs being arranged on the substrate.

22. The system of claim 20, further comprising: means for generating a baseband signal based on the digital output signal; means for generating an output signal based on said baseband signal; and Means for transmitting the output signal via the plurality of patch antennas.

23. The system of claim 22, further comprising: A component for detecting signal input; and Means for generating a digital output signal based on said signal input.

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