Semiconductor device, electronic system device and driving method thereof

Abstract

Embodiments of the present disclosure relate to semiconductor devices, electronic system devices, and driving methods thereof. The electronic system device includes a semiconductor device and a power generation device for generating a power supply voltage. The semiconductor device includes a control circuit coupled to the power generation device via a power supply node and a substrate bias control circuit coupled to the control circuit. The electronic system device includes a DC-DC converter and a switch arranged between the power supply node and the DC-DC converter. The control circuit sets the switch to an on state after receiving the power supply voltage. After the switch is controlled to be in an on state, the DC-DC converter receives the power supply voltage. The substrate bias control circuit provides a substrate bias voltage to the control circuit before the DC-DC converter receives the power supply voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-071675 filed on April 3, 2019 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, an electronic system device, and a driving method thereof. For example, the present invention can be applied to a semiconductor device and an electronic system device driven by a power supply voltage generated by a power generation device, and a driving method thereof. Background Art

[0004] In recent years, an energy harvesting (environmental power generation) technology has been proposed that obtains electric energy from energy such as solar energy, vibration energy, and thermal energy and drives an electronic system device based on the electric energy that has been provided. The electronic system device includes a semiconductor device and an interface device. The interface device is, for example, a radio device or a sensing device.

[0005] In addition to the semiconductor device and the interface device, the electronic system device using the energy harvesting technology may also be provided with a DC-DC (Direct Current - Direct Current) converter for providing a stable voltage to the interface device.

[0006] The disclosed technologies are listed below.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2001-218387

[0008] Patent document 1 discloses a double-layer capacitor energy storage power supply device for an electronic system device using energy harvesting technology, including a solar cell, a load controller and a DC-DC converter. Patent document 1 discloses that the standby power consumed by the DC-DC converter is eliminated. Summary of the invention

[0009] However, since the electric double layer capacitor energy storage power supply device of Patent Document 1 includes many devices, a large amount of electric power is required at startup, and there is a possibility of instantaneous voltage drop. Therefore, there is a problem that the electric double layer capacitor energy storage power supply device cannot be started stably.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0011] An electronic system device according to one embodiment includes a power generation device for generating a first power supply voltage. The electronic system device also includes a semiconductor device. The semiconductor device includes a control circuit coupled to the power generation device via a first power supply node and a substrate bias control circuit coupled to the control circuit. The electronic system device includes a DC-DC converter, which is coupled to the power generation device in parallel with the control circuit via the first power supply node. The electronic system device also includes a first switch arranged between the first power supply node and the DC-DC converter and coupled to the first power supply node and the DC-DC converter. The control circuit includes a field effect transistor. The control circuit also sets the first switch from an off state to an on state after receiving the first power supply voltage. After the first switch is controlled to the on state, the DC-DC converter receives the first power supply voltage via the first switch. Before the DC-DC converter receives the first power supply voltage, the substrate bias control circuit provides a substrate bias voltage to the field effect transistor.

[0012] In a method for driving an electronic system device according to an embodiment, the electronic system device includes a power generation device for generating a first power supply voltage. The electronic system device also includes a semiconductor device. The semiconductor device includes a control circuit coupled to the power generation device via a power supply node and a substrate bias control circuit coupled to the control circuit. The control circuit includes a field effect transistor. The electronic system device includes a DC-DC converter, which is coupled to the power generation device in parallel with the control circuit via a power supply node. The electronic system device also includes a switch arranged between the power supply node and the DC-DC converter and coupled to the power supply node and the DC-DC converter. In the method for driving an electronic system, the control circuit receives the first power supply voltage via the power supply node. After the control circuit receives the first power supply voltage, the control circuit sets the switch from the off state to the on state. After the switch is controlled to the on state, the DC-DC converter receives the first power supply voltage via the switch. The substrate bias control circuit provides a substrate bias voltage to the field effect transistor before the DC-DC converter receives the first power supply voltage.

[0013] A semiconductor system device according to an embodiment drives and controls a DC-DC converter by a power supply voltage generated by a power generation device. The semiconductor device includes a first terminal coupled to the power generation device, a control circuit coupled to the first terminal via a power supply node, and a substrate bias control circuit coupled to the control circuit. The semiconductor device includes a second terminal, which is coupled to the first terminal in parallel with the control circuit via the power supply node and coupled to the DC-DC converter. The semiconductor device includes a switch arranged between the power supply node and the second terminal and coupled to the power supply node and the second terminal. The control circuit includes a field effect transistor. The control circuit also sets the switch from the off state to the on state after receiving the power supply voltage. The second terminal provides the power supply voltage to the DC-DC converter after the switch is controlled to the on state. The substrate bias control circuit provides the substrate bias voltage to the field effect transistor before the second terminal provides the power supply voltage to the DC-DC converter.

[0014] According to the embodiment, a semiconductor device and an electronic system device can be stably started up based on a power supply voltage generated by a power generation device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram showing a configuration example of an electronic system device according to the first embodiment.

[0016] Figure 2 is a cross-sectional diagram showing a configuration example of a SOTB transistor.

[0017] Figure 3 is a cross-sectional diagram showing a configuration example of a MOS transistor.

[0018] Figure 4 is a timing chart for explaining the operation of the electronic system device according to the first embodiment.

[0019] Figure 5 is a block diagram showing a configuration example of an electronic system device according to a modified example of the first embodiment.

[0020] Figure 6 is a block diagram showing a configuration example of an electronic system device according to the second embodiment.

[0021] Figure 7 is a timing chart for explaining the operation of the electronic system device according to the second embodiment. DETAILED DESCRIPTION

[0022] In the following embodiments, for convenience, when necessary, the description will be made by dividing into multiple parts or embodiments, but unless otherwise specified, they are not independent of each other, and one is a modified example, application, detailed description, supplementary description, etc. of part or all of the other.

[0023] In the following embodiments, the number of elements, including the number of constituent elements, values, quantities, ranges, etc., is not limited to a specific number, but may be not less than or equal to a specific number unless the number is specifically indicated and explicitly limited in principle.

[0024] Furthermore, in the following embodiments, constituent elements (including operation steps and the like) are not necessarily essential unless they are specifically specified and are considered to be obviously essential in principle.

[0025] Similarly, in the following embodiments, when reference is made to the shapes, positional relationships, and the like of components and the like, the shapes and the like are assumed to be substantially similar except where expressly specified and deemed obvious in principle.

[0026] First embodiment

[0027] Electronic system device configuration

[0028] Figure 1 is a block diagram showing a configuration example of the electronic system device 1 according to the first embodiment.

[0029] The electronic system device 1 includes a power generation device P, a diode D, capacitor components C1 and C2, an auxiliary battery SC, a semiconductor device MC1, a switch S1, a DC-DC converter DM, and interface circuits SM and WLM. The electronic system device 1 is driven based on energy harvesting technology. In other words, the semiconductor device MC1, the DC-DC converter DM, and the interface circuits SM and WLM in the electronic system device 1 are driven based on energy harvesting technology. The interface circuits SM and WLM are devices for interacting with the outside of the electronic system device 1. In the first embodiment, the interface circuit SM is a sensing device, and the interface circuit WLM is a wireless device. Figure 1 The case where two interface circuits are provided is shown, but the number of interface circuits is not limited to this case. The capacitance components C1 and C2 and the auxiliary battery SC may be capacitors. In addition, in the electronic system apparatus 1, the operating voltage of the interface circuits SM and WLM is different from the operating voltage of the control circuit CNT in the semiconductor device MC1.

[0030] The power generation device P outputs power for driving the electronic system device 1. For example, the current output by the power generation device P is 5 μA. The power generation device P generates a power supply voltage for driving the semiconductor device MC1, the DC-DC converter DM, and the interface circuits SM and WLM. The power generation device P of the first embodiment is a solar cell. However, the power generation device P is not limited to a solar cell, and may be a micro power source, such as a thermocouple that can only provide a relatively low power and an antenna for receiving weak radio waves. That is, the electronic system device 1 according to the first embodiment is activated by using the power generation device P, which collects energy obtained in the environment and outputs electric power. The power generation device P is coupled to the terminal TE1 of the semiconductor device MC1 via a diode D. The power generation device P generates a power supply voltage VP and supplies the power supply voltage VP to the terminal TE1 via a diode D.

[0031] The semiconductor device MC1 includes terminals TE1, TE2, TE3, TE4, TE5, TE6, TE7, TE8 and TE9, switches S2 and S3, monitoring circuits M1 and M2, a control circuit CNT, a substrate bias control circuit VBC, a horizontal shift circuit LS1 and a dedicated input / output circuit IO1. The semiconductor device MC1 includes a built-in capacitor ( Figure 1 The semiconductor device MC1 controls the DC-DC converter DM. The semiconductor device MC1 communicates data signals with the interface circuits SM and WLM.

[0032] The terminal TE1 is coupled to the monitoring circuit M1 and the terminal TE2 via the power node N1. The terminal TE2 is coupled to the capacitance component C1. That is, the monitoring circuit M1 and the capacitance component C1 are coupled in parallel with the terminal TE1 via the power node N1. The terminal TE1 supplies the power voltage VP to the terminal TE2 via the power node N1. Therefore, the terminal TE2 supplies the power voltage VP to the capacitance component C1. Therefore, the charge output from the power generation device P is accumulated in the capacitance component C1 via the terminals TE1 and TE2 and the power node N1, and the capacitance component C1 obtains the power voltage VP as the power voltage VC. Mainly, the capacitance component C1 is provided to provide a stable voltage to the control circuit CNT.

[0033] The terminal TE1 is coupled to the switch S2 via the power node N1 and the power node N2. The switch S2 is coupled to the control circuit CNT and the terminal TE4 via the power node N3. That is, the switch S2 is provided between the power generation device P and the power node N3. As described above, the monitoring circuit M1 is coupled to the power node N1 between the switch S2 and the power generation device P. That is, the monitoring circuit M1 monitors the power voltage of the power node N1 between the terminal TE1 and the terminal TE2, and controls the switch S2 based on the power voltage VC of the power node N1. Specifically, the monitoring circuit M1 provides the control signal CS1 to the switch S2, and sets the switch S2 to the on / off state. When the power voltage VC is higher than the threshold voltage, the monitoring circuit M1 provides the high-level control signal CS1 to the switch S2, and sets the switch S2 from the off state to the on state. That is, through the monitoring circuit M1, the power voltage VC is provided as the power voltage VCC to the power node N3 via the switch S2.

[0034] The control circuit CNT and the terminal TE4 are coupled in parallel with the switch S2 via the power node N3. That is, the power voltage VCC is provided to the control circuit CNT and the terminal TE4 via the power node N3. Therefore, the control circuit CNT and the terminal TE4 are coupled to the power generation device P via the switch S2 and the power node N3, and receive the power voltage VP generated by the power generation device P as the power voltage VCC. The terminal TE4 provides the power voltage VCC as the power voltage VIN to the DC-DC converter DM via the switch S1.

[0035] In addition, the terminal TE1 is coupled to the switch S3 via the power supply nodes N1 and N2. The switch S3 is coupled to the power supply node N2 between the power supply node N1 and the switch S2. The switch S3 is set to an on / off state based on the control signal CS2 from the control circuit CNT. The switch S3 is coupled to the terminal TE3 and the monitoring circuit M2. Specifically, the terminal TE3 and the monitoring circuit M2 are coupled in parallel with the switch S3. The terminal TE3 is coupled to the auxiliary battery SC, that is, the charge output by the power generation device P is accumulated in the auxiliary battery SC via the terminals TE1 and TE3, the power supply nodes N1 and N2, and the switch S3, and the auxiliary battery SC obtains the power supply voltage VP as the power supply voltage VS. Mainly, the auxiliary battery SC is provided to supply a stable voltage to the DC-DC converter DM. The monitoring circuit M2 monitors the power supply voltage between the switch S3 and the terminal TE3, and provides the control signal CS3 to the control circuit CNT. Specifically, when the power supply voltage VS is higher than the threshold voltage, the monitoring circuit M2 provides a high-level control signal CS3 to the control circuit CNT.

[0036] The control circuit CNT supplies a control signal CS4 to the switch S1 via the terminal TE5 and controls the switch S1. The control circuit CNT also supplies a control signal CS2 to the switch S3 and controls the switch S3. The control circuit CNT also supplies a control signal CS5 to the terminal TE11 of the DC-DC converter DM via the terminal TE6 and controls the DC-DC converter DM. In addition, the control circuit CNT controls the dedicated input / output circuit IO1 via the horizontal shift circuit LS1. The control circuit CNT includes a built-in capacitor ( Figure 1 not shown).

[0037] In addition, the control circuit CNT includes a field effect transistor. The field effect transistor is, for example, a SOTB (silicon on thin buried oxide) transistor or a MOS (metal oxide semiconductor) transistor. In the present embodiment, a MOS transistor is different from a SOTB transistor and is referred to as a body transistor. A SOTB transistor refers to a transistor using a substrate on which a thin insulating film and a thin silicon film are formed on a silicon substrate. A p-type SOTB transistor refers to a SOTB transistor in which the channel through which the leakage current flows is a p-type channel, and an n-type SOTB transistor refers to a SOTB transistor in which the channel through which the leakage current flows is an n-type channel. Similarly, a MOS transistor whose channel is a p-channel is referred to as a p-type MOS transistor, and a MOS transistor whose channel is an n-type channel is referred to as an n-type MOS transistor.

[0038] The control circuit CNT may be composed of only SOTB transistors, or may be composed of only MOS transistors. Of course, the control circuit CNT may be composed of both SOTB and MOS transistors. Figure 2 and 3 Describe the detailed structures of SOTB transistors and MOS transistors.

[0039] The substrate bias control circuit VBC is coupled to the control circuit CNT and controls the substrate bias voltage of the field effect transistor in the control circuit CNT. Specifically, the substrate bias control circuit VBC provides the substrate bias voltage VBP and the substrate bias voltage VBN to the control circuit CNT, controls the threshold voltage of the field effect transistor in the control circuit CNT, and suppresses the leakage current.

[0040] The dedicated input / output circuit IO1 is coupled to the terminal TE12 of the DC-DC converter DM via the terminal TE7, and receives the power supply voltage VOUT from the DC-DC converter DM via the terminal TE7. The dedicated input / output circuit IO1 operates based on the power supply voltage VOUT. The dedicated input / output circuit IO1 is coupled to the terminal TE14 of the interface circuit SM via the terminal TE8. The dedicated input / output circuit IO1 receives the data signal DS1 from the interface circuit SM via the terminal TE8, or provides the data signal DS1 to the interface circuit SM. In addition, the dedicated input / output circuit IO1 is coupled to the terminal TE16 of the interface circuit WLM via the terminal TE9. The dedicated input / output circuit IO1 receives the data signal DS2 from the interface circuit WLM via the terminal TE9, or provides the data signal DS2 to the interface circuit WLM.

[0041] The horizontal shift circuit LS1 is provided between the control circuit CNT and the dedicated input / output circuit IO1. Since the operation voltage of the control circuit CNT is different from the operation voltage of the dedicated input / output circuit IO1, the horizontal shift circuit LS1 enables communication between the control circuit CNT and the dedicated input / output circuit IO1.

[0042] The switch S1 is coupled to the terminal TE4 of the semiconductor device MC1 and the terminal TE10 of the DC-DC converter DM, and is arranged between the two. In other words, the switch S1 is arranged between the power supply node N3 and the DC-DC converter DM, and is coupled to the power supply node N3 and the DC-DC converter DM. The switch S1 is set to an on / off state based on the control signal CS4. The power supply voltage VCC is provided to the DC-DC converter DM as the power supply voltage VIN via the switch S1.

[0043] The DC-DC converter DM includes terminals TE10, TE11, and TE12. In addition, the DC-DC converter DM includes Figure 1 Built-in capacitance not shown in the figure. For example, the built-in capacitance is a capacitance component coupled to the terminal TE10. The capacitance component can be arranged inside the DC-DC converter DM or outside the DC-DC converter DM as long as it is coupled to the terminal TE10. In other words, the built-in capacitance can be a capacitance component coupled between the switch S1 and the terminal TE10 of the DC-DC converter DM. In addition, it is not limited to the capacitance component and can be a capacitor. The DC-DC converter DM receives a power supply voltage VIN from the power supply device P via the semiconductor device MC1, generates a power supply voltage VOUT having a voltage value different from the power supply voltage VIN, and provides the power supply voltage VOUT.

[0044] Specifically, the DC-DC converter DM receives the power supply voltage VIN from the terminal TE4 of the semiconductor device MC1 via the switch S1 and the terminal TE10. That is, the DC-DC converter DM is coupled to the control circuit CNT connected in parallel with the power supply device P via the power node N3, and receives at least the power supply voltage VP generated by the power generation device P as the power supply voltage VIN. Accordingly, the DC-DC converter DM starts. In addition, the DC-DC converter DM generates the power supply voltage VOUT based on the control signal CS5 input from the terminal TE11, and provides the power supply voltage VOUT via the terminal TE12. In particular, unless the DC-DC converter DM receives the high-level control signal CS5, the DC-DC converter DM does not provide the power supply voltage VOUT. The value of the power supply voltage V OUT is different from the values ​​of the power supply voltages VP, VIN, VCC and VS. For example, the power supply voltage VOUT is 3.3V and the power supply voltage VIN is 2.6V. The terminal TE12 of the DC-DC converter DM is coupled with the capacitance component C2 , the terminal TE7 of the semiconductor device MC1 , the terminal TE13 of the interface circuit SM, and the terminal TE15 of the interface circuit WLM, and supplies the power supply voltage VOUT to each of them.

[0045] The capacitor component C2 is coupled to the terminal TE13 of the interface circuit SM, the terminal TE15 of the interface circuit WLM and the terminal TE12 of the DC-DC converter DM. The capacitor component C2 is mainly used to eliminate ripples from the DC-DC converter.

[0046] The interface circuit SM includes terminals TE13 and TE14. The interface circuit SM receives the power supply voltage VOUT from the terminal TE12 of the DC-DC converter DM via the terminal TE13, thereby starting up. The interface circuit SM senses the outside of the electronic system device 1. Therefore, the interface circuit SM provides the data signal DS1 to the terminal TE8 of the semiconductor device MC1 via the terminal TE14. Alternatively, the interface circuit SM receives the data signal DS1 from the semiconductor device MC1. In other words, the semiconductor device MC1 and the interface circuit SM communicate the data signal DS1.

[0047] The interface circuit WLM includes terminals TE15 and TE16. The interface circuit WLM receives the power supply voltage VOUT via the terminal TE15, thereby starting up. The interface circuit WLM wirelessly communicates with the outside of the electronic system device 1. Therefore, the interface circuit WLM provides the data signal DS2 to the terminal TE9 of the semiconductor device MC1 via the terminal TE16. Alternatively, the interface circuit WLM receives the data signal DS2 from the semiconductor device MC1. In other words, the semiconductor device MC1 and the interface circuit WLM communicate the data signal DS2.

[0048] Configuration of MOS transistor and SOTB transistor

[0049] Figure 2 is a cross-sectional diagram showing a configuration example of a SOTB transistor.

[0050] When the control circuit CNT is formed of a SOTB transistor, the control circuit CNT includes a p-type SOTB transistor PT1 and an n-type SOTB transistor NT1. In the SOTB transistor, a deep n-type well region DNW is formed on a p-type substrate SU.

[0051] In the p-type SOTB transistor PT1, an n-type well region NW is formed on the n-type well region DNW. A thin insulating film BOX is formed on the NW-type well region. A semiconductor layer SL1 is formed on the n-type well region NW to sandwich the thin insulating film BOX. A p-type well region serving as a source region of the p-type SOTB transistor PT1 is formed in the semiconductor layer SL1. + The p-type region SR1 and the p-type region serving as the drain region of the p-type SOTB transistor PT1 + In the semiconductor layer SL1, the p + Type region SR1 and p + The channel region CH1 substantially free of impurities is formed between the type region DR1. The impurity concentration of the channel region CH1 is equal to or less than 3×10 17 cm -3 The gate electrode G1 of the p-type SOTB transistor PT1 is formed on the channel region CH1 via the gate insulating film DL1.

[0052] In the n-type SOTB transistor NT1, a p-type well region PW is formed on the n-type well region DNW. A thin insulating film BOX is formed on the p-type well region PW. A semiconductor layer SL2 is formed on the p-type well region PW to sandwich the thin insulating film BOX. An n-type well region as a source region of the n-type SOTB transistor NT1 is formed in the semiconductor layer SL2. + The n-type region SR2 and the n-type drain region of the n-type SOTB transistor NT1 + In the semiconductor layer SL2, in the n + Type area SR2 and n + The channel region CH2 substantially does not contain impurities. The impurity concentration of the channel region CH2 is equal to or less than 3×10 17 cm -3 The gate electrode G2 of the n-type SOTB transistor NT1 is formed on the channel region CH2 via the gate insulating film DL2.

[0053] For example, the thickness of the thin insulating film BOX is about 10 nanometers. In the p-type SOTB transistor PT1, the n-type region NR + is formed on the n-type well region NW so that the substrate bias control circuit VBC provides the substrate bias voltage VBP to the n-type well region NW.+ The p-type region PR is formed on the p-type well region PW, so that the substrate bias control circuit VBC provides the substrate bias voltage VBN to the p-type well region PW. Therefore, the threshold voltages of the p-type SOTB transistor PT1 and the n-type SOTB transistor NT1 are controlled by the substrate bias voltages VBP and VBN provided by the substrate bias control circuit VBC, and the leakage current is suppressed. Therefore, the power consumed by the control circuit CNT is reduced. The p-type SOTB transistor PT1, the n-type SOTB transistor NT1, and the p-type SOTB transistor NT1 are controlled by the substrate bias voltages VBP and VBN provided by the substrate bias control circuit VBC, and the leakage current is suppressed. + Type area PR and n + The type regions NR are separated from each other by the element isolation film STI.

[0054] Figure 3 It is shown Figure 3 A cross-sectional view of a configuration example of a MOS transistor in FIG. Figure 2 Unlike the SOTB transistor, the thin insulating film BOX is not formed in the MOS transistor.

[0055] When the control circuit CNT is constituted by a MOS transistor, the control circuit CNT includes a p-type MOS transistor PT2 and an n-type MOS transistor NT2.

[0056] In the p-type MOS transistor PT2, the p + The p-type region SR3 and the p-type region serving as the drain region of the p-type MOS transistor PT2 + The n-type region DR3 is formed on the n-type well region NW. + Type region SR3 and p + A channel region CH3 containing impurities is formed between the p-type MOS regions DR3. A gate electrode G3 of the p-type MOS transistor PT2 is formed on the channel region CH3 via a gate insulating film DL3.

[0057] In the n-type MOS transistor NT2, an n-type well region serving as a source region of the n-type MOS transistor NT2 is formed on the p-type well region PW. + The n-type region SR4 and the n-type region serving as the drain region of the n-type MOS transistor NT2 + Type zone DR4. + Type area SR4 and n + A channel region CH4 containing impurities is formed between the n-type regions DR4. A gate electrode G4 of the n-type MOS transistor NT2 is formed on the channel region CH4 via a gate insulating film DL4.

[0058] In the p-type MOS transistor PT2, n +The n-type region NR is formed on the n-type well region NW, so that the substrate bias control circuit VBC provides the substrate bias voltage VBP to the n-type well region NW. + The p-type region PR is formed on the p-type well region PW, so that the substrate bias control circuit VBC provides the substrate bias voltage VBN to the p-type well region PW. Therefore, the threshold voltages of the p-type MOS transistor PT2 and the n-type MOS transistor NT2 are controlled by the substrate bias voltages VBP and VBN provided by the substrate bias control circuit VBC, and the leakage current is suppressed. Therefore, the power consumed by the control circuit CNT is reduced.

[0059] However, in the n-type MOS transistor NT2 and the p-type MOS transistor PT2, the channel region CH3 and the channel region CH4 are formed in the n-type well region NW and the p-type well region PW containing impurities, respectively. For example, when a plurality of p-type MOS transistors PT2 are formed in the control circuit CNT, a plurality of n-type well regions NW are also formed. When the impurity concentrations of the plurality of n-type well regions NW vary from each other, the threshold voltages of the plurality of p-type MOS transistors PT2 vary from each other. In addition, there is a pn junction between the n-type well region NW and the source / drain region of the p-type MOS transistor PT2. Therefore, in the p-type MOS transistor PT2, when the substrate bias control circuit VBC provides the substrate bias voltage VBP to the n-type well region NW, a leakage current caused by the pn junction is generated. The same applies to the above-mentioned n-type MOS transistor NT2.

[0060] In contrast, in the p-type SOTB transistor PT1 and the n-type SOTB transistor NT1, the channel region CH1 in the semiconductor layer SL1 and the channel region CH2 in the semiconductor layer SL2 substantially do not contain impurities. Therefore, the change in the threshold voltage of the p-type SOTB transistor PT1 and the n-type SOTB transistor NT1 caused by the change in the amount of impurities can be reduced. In addition, since there is substantially no impurity, the threshold voltage of the p-type SOTB transistor PT1 and the n-type SOTB transistor NT1 changes in proportion to the substrate bias voltage VBP and VBN. In addition, in the p-type SOTB transistor PT1, since the source region and the drain region of the p-type SOTB transistor PT1 are formed in the semiconductor layer SL1, there is no pn junction with the well region NW. Therefore, the leakage current caused by the pn junction can be prevented. Since the insulating film BOX is inserted between the well region NW of the p-type SOTB transistor PT1 and the semiconductor layer SL1 used as the channel region, the leakage current can be prevented from flowing between the semiconductor layer SL1 and the well region NW even when the substrate bias voltage VBP is provided. As a result, the SOTB transistor operates stably while reducing power consumption. As described above, the same applies to the n-type SOTB transistor NT1. Therefore, the SOTB transistor can consume less power than the MOS transistor.

[0061] When the control circuit CNT is composed of a SOTB transistor and a MOS transistor, the substrate bias voltage VBP provided to the n-type well region NW of the SOTB transistor and the substrate bias voltage VBP provided to the n-type well region NW of the MOS transistor may be different voltages. Similarly, the substrate bias voltage VBN provided to the p-type well region PW of the SOTB transistor and the substrate bias voltage VBN provided to the p-type well region PW of the MOS transistor may be different voltages. In other words, the substrate bias voltages VBP and VBN provided to the SOTB transistor and the MOS transistor, respectively, may be different.

[0062] Operation of the Electronic System Device According to the First Embodiment

[0063] Figure 4 is a timing chart for explaining the operation of the electronic system device 1 according to the first embodiment. In the initialization of the electronic system device 1, the switches S1, S2 and S3 are in the off state. Similarly, the control signals CS1, CS2, CS3, CS4 and CS5 are floating (high Z).

[0064] At time T0 , the power generation device P generates a power supply voltage VP by, for example, lighting or sunlight, and provides the power supply voltage VP.

[0065] Therefore, at time T1, the power supply voltage VP is supplied from the power generation device P to the capacitor component C1 via the diode D, the terminal TE1, the power supply node N1 and the terminal TE2, and charging of the capacitor component C1 begins. As a result, the capacitor component C1 obtains the power supply voltage VP as the power supply voltage VC. During charging, the switches S1, S2 and S3 are in the off state. In addition, various built-in capacitors in the semiconductor device MC1 begin to charge, and the semiconductor device MC1 starts. The monitoring circuit M1 is also started, and the monitoring circuit M1 sets the control signal CS1 from the floating state to the low level.

[0066] The monitoring circuit M1 monitors the power supply voltage VC of the power supply node N1. When the power supply voltage VC is higher than the threshold voltage, the monitoring circuit M1 switches the control signal CS1 from a low level to a high level at time T2 and provides the control signal CS1 to the switch S2. As a result, the switch S2 is set from an off state to an on state.

[0067] Therefore, at time T3, the power supply voltage VC is provided as the power supply voltage VCC via the switch S2. Therefore, the power supply voltage VCC is provided to the control circuit CNT and the terminal TE4 via the power supply node N3. That is, the control circuit CNT receives at least the power supply voltage VP generated by the power generation device P. As a result, the built-in capacitor in the semiconductor device MC1 including the control circuit CNT begins to be charged immediately. Therefore, a large startup current flows through the semiconductor device MC1. Since the switch S3 is in the off state, the power supply voltage VCC is not provided to the DC-DC converter DM via the switch S3. Therefore, the power supply voltage is not provided to the interface circuits SM and WLM. As a result, the timing of the startup current of the semiconductor device MC1 is different from the timing of the startup current of the other devices, so that the power supply voltage VC of the capacitor component C1 does not drop immediately.

[0068] At time T4 , the power supply voltage VCC becomes a high level and the startup of the control circuit CNT is completed.

[0069] Therefore, at time T5, the control circuit CNT sets the control signals CS2, CS4 and CS5 to a low level from a floating state. The switch S1 is in the off state as in the initialization. The substrate bias control circuit VBC also provides substrate bias voltages VBP and VBN to the control circuit CNT. Specifically, the substrate bias voltage VBP is a positive potential voltage, and the substrate bias voltage VBN is a negative potential voltage. As a result, the threshold voltage of the field effect transistor in the control circuit CNT is controlled, and the leakage current of the field effect transistor is reduced. Therefore, the power consumed by the semiconductor device MC1 is reduced. In addition, when the substrate bias voltages VBP and VBN are provided, the semiconductor device MC1 operates in a low power consumption mode. For example, the semiconductor device MC1 in the low power consumption mode operates synchronously with the low speed clock signal. In other words, the semiconductor device MC1 operates in a low speed mode.

[0070] After providing the substrate bias voltages VBP and VBN at time T6, the control circuit CNT switches the control signal CS2 from a low level to a high level at time T7, and provides the control signal CS2 to the switch S3. As a result, the switch S3 is set from an off state to an on state. That is, after the control circuit CNT receives the power supply voltage VCC, the control circuit CNT sets the switch S3 to an on state. The substrate bias control circuit VBC also provides the substrate bias voltages VBP and VBN to the field effect transistor of the control circuit CNT before the switch S3 is set to an on state. This is to reduce the power consumption of the semiconductor device MC1.

[0071] Therefore, at time T8, charging of the auxiliary battery SC starts from the power generation device P via the diode D, the terminal TE1, the power supply nodes N1 and N3, the switch S3 and the terminal TE3. In addition, the auxiliary battery SC obtains the power supply voltage VP from the capacitor component C2 as the power supply voltage VS. The monitoring circuit M2 is also started, and the monitoring circuit M2 sets the control signal CS3 from the floating state to the low level.

[0072] When the monitoring circuit M2 monitors the power supply voltage VS and the power supply voltage VS is higher than the threshold voltage, the monitoring circuit M2 switches the control signal CS3 from a low level to a high level at time T9. Therefore, the startup of the semiconductor device MC1 is completed. After the startup of the semiconductor device MC1 is completed, the semiconductor device MC1 is in a standby mode.

[0073] At time T10, when the semiconductor device MC1 is in the standby state, the semiconductor device MC1 receives an interrupt signal (not shown). Therefore, the control circuit CNT switches the control signal CS4 from a low level to a high level, and provides the control signal CS4 to the switch S1 via the terminal TE5. Therefore, the switch S1 is set from the off state to the on state.

[0074] As a result, at time T11, the power supply voltage VIN is provided to the terminal TE10 of the DC-DC converter DM. In other words, the DC-DC converter DM receives the power supply voltage VCC as the power supply voltage VIN via the switch S1. The power supply voltage VIN at time T11 includes at least the power supply voltage VS and the power supply voltages VP and VC. Therefore, the built-in capacitor (not shown) of the DC-DC converter DM begins to charge, and the DC-DC converter DM starts. As described above, the built-in capacitor is a capacitor coupled to the terminal TE10, etc. At this time, a large startup current flows through the DC-DC converter DM. Since the startup of the semiconductor device MC1 has been completed, the startup timing of the DC-DC converter DM does not overlap with the startup timing of the semiconductor device MC1. Therefore, the power supply voltages VC, VS and VIN will not drop immediately. Since a large startup current is not generated simultaneously in the semiconductor device MC1 and the DC-DC converter DM, a voltage drop does not occur immediately in the electronic system device 1, and the electronic system device 1 is not reset.

[0075] After the power supply voltage VIN reaches the high level at time T12, the control circuit CNT switches the control signal CS5 from the low level to the high level at time T13. The control circuit CNT supplies the control signal CS5 to the terminal TE11 of the DC-DC converter DM via the terminal TE6.

[0076] Therefore, at time T14, the DC-DC converter DM provides the power supply voltage VOUT as an output voltage to the capacitor component C2, the terminal TE7 of the dedicated input / output circuit IO1, the terminal TE13 of the interface circuit SM, and the terminal TE15 of the interface circuit WLM via the terminal TE12. Therefore, the built-in capacitors of the capacitor component C2 and the interface circuits SM and WLM are charged. Accordingly, the interface circuits SM and WLM are started. Since the startup of the semiconductor device MC1 and the DC-DC converter DM has been completed, the startup timing of the interface circuit SM and WLM does not overlap with the startup timing of the semiconductor device MC1 and the DC-DC converter DM. Therefore, since a large startup current is not generated simultaneously in each device of the electronic system device 1, an instantaneous voltage drop does not occur in the electronic system device 1, and the electronic system device 1 does not reset. Therefore, the electronic system device 1 can be started based on a current of several μA levels output from the power generation device P.

[0077] After the capacitor component C2 and the built-in capacitors of the interface circuits SM and WLM are charged, the startup of the electronic system device 1 is completed at time T15. After the startup of the electronic system device 1 is completed, the electronic system device 1 enters the standby state.

[0078] At time T16, when the electronic system apparatus 1 is in the standby state, the semiconductor device MC1 receives an interrupt signal (not shown). Therefore, the substrate bias control circuit VBC stops supplying the substrate bias voltages VBP and VBN to the control circuit CNT. Therefore, the semiconductor device MC1 starts operating in the normal mode. For example, compared with the semiconductor device MC1 in the low power consumption mode, the semiconductor device MC1 in the normal mode operates in synchronization with the high-speed clock signal. As a result, the semiconductor device MC1 can perform higher-speed processing than the semiconductor device MC1 in the low power consumption mode.

[0079] After the substrate bias control circuit VBC stops providing the substrate bias voltages VBP and VBN, the semiconductor device MC1 starts communicating with the interface circuits SM and WLM. Between time T17 and time T18, the dedicated input / output circuit IO1 of the semiconductor device MC1 receives the data signal DS1 from the interface circuit SM or provides the data signal DS1 to the interface circuit SM. The dedicated input / output circuit IO1 also receives the data signal DS2 from the interface circuit WLM or provides the data signal DS2 to the interface circuit WLM.

[0080] After the above communication operation is completed, at time T19, the substrate bias control circuit VBC supplies the substrate bias voltages VBP and VBN to the control circuit CNT. Therefore, the semiconductor device MC1 operates in the low power consumption mode. Therefore, the power consumption of the semiconductor device MC1 can be reduced. In other words, when the semiconductor device MC1 does not perform the communication operation, the semiconductor device MC1 operates in the low power consumption mode, and the standby current of the semiconductor device MC1 is suppressed. Therefore, the power consumed by the electronic system apparatus 1 is reduced.

[0081] At time T20 , when the semiconductor device MC1 receives an interrupt signal (not shown), the control circuit CNT switches the control signal CS5 from the high level to the low level.

[0082] Therefore, at time T21, the DC-DC converter DM stops supplying power to the power supply voltage VOUT. As a result, the power of the capacitance component C2 is naturally discharged as a leakage current of the interface circuits SM and WLM, etc., and the power supply voltage VOUT switches to a low level.

[0083] At time T22, when the semiconductor device MC1 receives an interrupt signal (not shown), the control circuit CNT switches the control signal CS4 from a high level to a low level. Thus, the switch S1 is set from an on state to an off state.

[0084] As a result, at time T23, the supply of the power supply voltage VIN is stopped. The built-in capacitor DM of the DC-DC converter discharges spontaneously, and the power supply voltage VIN transitions from a high level to a low level. As a result, the electronic system device 1 switches to the standby mode. In addition, when the switch S1 is set to the on state, the leakage current of the DC-DC converter DM flows. Therefore, the power consumed by the electronic system device 1 can be reduced by setting the switch S1 to the off state.

[0085] When the electronic system device 1 is operated again, the Figure 4 Since the electronic system device 1 suppresses the consumption current as described above, the electronic system device 1 can perform the intermittent operation.

[0086] Therefore, in the electronic system device 1, the startup time of the semiconductor device MC1 and the DC-DC converter DM is different, and the startup time thereof is also different from the startup time of the interface circuits SM and WLM. Therefore, an instantaneous voltage drop in the electronic system device 1 does not occur. As a result, the electronic system device 1 can be stably started without being reset even based on a current of several μA levels output from the power generation device P. In addition, when the DC-DC converter DM and the interface circuits SM and WLM are started, the semiconductor device MC1 operates in a low power consumption mode. Therefore, the electronic system device 1 can be stably started. In standby mode, since the semiconductor device MC1 operates in a low power consumption mode and suppresses the leakage current of the DC-DC converter DM, the power consumption is low. As a result, in the electronic system device 1, intermittent operation can be achieved even by an energy acquisition technology in which the current output is unstable.

[0087] Modification example of the first embodiment

[0088] Figure 5 1 is a block diagram showing a configuration example of an electronic system device 2 according to a modified example of the first embodiment. Components similar to those of the electronic system device 1 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof are omitted. The startup operation of the electronic system device 2 is mainly the same as the startup operation of the electronic system device 1.

[0089] Unlike the electronic system device 1, the electronic system device 2 as a modified example includes a semiconductor device MC2 and a horizontal shift device LS2. Specifically, unlike the semiconductor device MC1, the semiconductor device MC2 includes a switch S1 in the semiconductor device MC2. The semiconductor device MC2 includes a general input / output circuit IO2 instead of the dedicated input / output circuit IO1 of the semiconductor device MC1. The general input / output circuit IO2 operates based on the same power supply voltage as the control circuit CNT. Therefore, the semiconductor device MC2 does not include the horizontal shift circuit LS1 in the semiconductor device MC1. Instead, the electronic system device 2 includes the horizontal shift device LS2 outside the semiconductor device MC2.

[0090] In the semiconductor device MC2, the switch S1 is provided between the power supply node N3 and the terminal TE4. Similar to the operation of the semiconductor device MC1, after the control circuit CNT receives the power supply voltage VCC via the power supply node N3, the substrate bias control circuit supplies the substrate bias voltage VBP and VBN to the control circuit CNT. Thereafter, the control circuit CNT sets the switch S1 from the off state to the on state. Then, the terminal TE4 supplies the power supply voltage VIN to the DC-DC converter DM.

[0091] Unlike the dedicated input / output circuit IO1, the general input / output circuit IO2 receives the power supply voltage VIN from the terminal TE4 via the terminal TE7 and operates based on the power supply voltage. In addition, the general input / output circuit IO2 operates based on the same power supply voltage as the control circuit CNT. Therefore, the control circuit CNT of the semiconductor device MC2 can directly control the general input / output circuit IO2. The general input / output circuit IO2 communicates the data signals DS1 and DS2 with the interface circuits SM and WLM via the horizontal shift device LS2.

[0092] Since the horizontal shift device LS2 is arranged outside the semiconductor device MC2, the horizontal shift device LS2 includes terminals TE17, TE18, TE19, TE20, TE21, TE22 and TE23. Terminal TE17 receives a control signal CS5 from the control circuit CNT of the semiconductor device MC2, and starts the operation of the horizontal shift device LS2 based on the control signal CS5. Terminal TE18 receives a power supply voltage VIN via a switch S1 of the semiconductor device MC2. Terminal TE21 receives a power supply voltage VOUT from a DC-DC converter DM. The horizontal shift device LS2 operates based on the power supply voltages VIN and VOUT. Therefore, the interface circuit SM and the general input / output circuit IO2 communicate the data signal DS1 via the terminals TE19 and TE22. Similarly, the interface circuit WLM and the general input / output circuit IO2 communicate the data signal DS2 via the terminals TE20 and TE23.

[0093] Therefore, in the electronic system device 2, since the switch S1 is formed in the semiconductor device MC2, the number of external devices outside the semiconductor device MC2 can be reduced, and the terminal TE5 of the semiconductor device MC1 can also be reduced. Therefore, the electronic system device 2 can be miniaturized.

[0094] Furthermore, even when the operating voltage of the interface device SM and WLM is higher than the voltage that the semiconductor device MC2 can accept, the level shift device LS2 enables communication operation between the semiconductor device MC2 and the interface device SM and WLM. Therefore, the electronic system device 2 is more versatile than the electronic system device 1. Furthermore, similar to the electronic system device 1, the electronic system device 2 can be stably started based on the current of several μA level output from the power generation device P.

[0095] Second embodiment

[0096] Configuration of electronic system devices

[0097] Figure 6 Components similar to those of the electronic system device 1 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof are omitted.

[0098] The electronic system device 3 according to the second embodiment includes a semiconductor device MC3 instead of the semiconductor device MC1. In addition, unlike the electronic system device 1, the electronic system device 3 does not include a switch S1. The switch S3 of the semiconductor device MC3 is used as the switch S1 of the electronic system device 1. The semiconductor device MC3 does not include a terminal TE4. Therefore, the terminal TE3 of the semiconductor device MC3 is coupled to the terminal TE10 of the DC-DC converter DM via the power node N4. Therefore, the DC-DC converter DM receives the power supply voltage VIN from the terminal TE3. In the electronic system device 3, the control circuit CNT is coupled to the power generation device P via the power node N2, and the DC-DC converter DM is coupled to the control circuit CNT connected in parallel with the power generation device P via the power node N2.

[0099] Operation of the electronic system device according to the second embodiment

[0100] Figure 7 1 is a timing chart for explaining the operation of the electronic system device 3 according to the second embodiment. The initialization of the electronic system device 3 is the same as the initialization of the electronic system device 1.

[0101] Since each operation of the electronic system device 3 from time T30 to time T37 is the same as each operation of the electronic system device 1 from time T1 to time T7, the description thereof is omitted. Specifically, the operation at time T30 corresponds to the operation at time T0. The operation at time T31 corresponds to the operation at time T1. The operation at time T32 corresponds to the operation at time T2. The operation at time T33 corresponds to the operation at time T3. The operation at time T34 corresponds to the operation at time T4. The operation at time T35 corresponds to the operation at time T5. The operation at time T36 corresponds to the operation at time T6. The time T37 corresponds to the time T7.

[0102] After the switch S3 is changed from the off state to the on state, at time T38, the auxiliary battery SC is charged from the power generation device P via the diode D, the terminal TE1, the power supply nodes N1 and N3, the switch S3, the terminal TE3 and the power supply node N4. As a result, the auxiliary battery SC obtains the power supply voltage VS. In addition, the power supply voltage VS is provided to the terminal TE10 of the DC-DC converter DM as the power supply voltage VIN via the power supply node N4. In other words, the power supply voltage VS and VIN are the same. That is, the DC-DC converter DM receives the power supply voltage VIN via the switch S3. Therefore, the built-in capacitor of the DC-DC converter DM starts to charge, and the DC-DC converter DM starts to start. At this time, the startup current flows through the DC-DC converter DM. Since the startup of the control circuit CNT of the semiconductor device MC3 has been completed, the startup timing of the DC-DC converter DM does not overlap with the startup timing of the control circuit CNT. Therefore, the power supply voltages VC and VS do not drop at the same time. Since a large startup current is not simultaneously generated in the semiconductor device MC3 and the DC-DC converter DM, an instantaneous voltage drop does not occur in the electronic system device 3, and the electronic system device 3 is not reset.

[0103] The time T39 corresponds to the time T9. Thus, the startup of the semiconductor device MC3 is completed. After the startup of the semiconductor device MC3 is completed, the semiconductor device MC3 is in the standby mode.

[0104] After the power supply voltage VS and VIN reach a high level, the semiconductor device MC3 receives an interrupt signal (not shown). Therefore, at time T40, the control circuit CNT switches the control signal CS5 from a low level to a high level. The control circuit CNT provides the control signal CS5 to the terminal TE11 of the DC-DC converter DM via the terminal TE6. This operation corresponds to the operation of the electronic system device 1 at time T13.

[0105] In addition, since each operation of the electronic system device 3 from time T41 to time T48 is the same as each operation of the electronic system device 1 from time T14 to time T20, the description thereof is omitted. Specifically, the operation at time T41 corresponds to the operation at time T14. The operation at time T42 corresponds to the operation at time T15. The operation at time T43 corresponds to the operation at time T16. The operation at time T44 corresponds to the operation at time T17. The operation at time T45 corresponds to the operation at time T18. The operation at time T46 corresponds to the operation at time T19. The operation at time T47 corresponds to the operation at time T20. The operation at time T48 corresponds to the operation at time T21, whereby the electronic system device 3 switches to the standby mode. When the electronic system device 3 operates, it can be repeated. Figure 7 operation.

[0106] Therefore, the operation of the electronic system device 3 does not include the operation of the electronic system device 1 at times T10, T11, T12, T22, and T23. As described above, in the electronic system device 3, the switch S1 of the electronic system device 1 is not provided. Instead, the switch S3 of the semiconductor device MC3 is used as the switch S1 of the electronic system device 1. Therefore, since the electronic system device 3 does not include the switch S1 and the terminal TE5 connected to the switch S1, the electronic system device 3 can be more miniaturized than the electronic system device 1. In addition, since the electronic system device 3 does not have a control operation performed by the control signal CS4 of the electronic system device 1, the electronic system device 3 can be started faster than the electronic system device 1.

[0107] Similar to the electronic system device 1, in the electronic system device 3, the startup time of the semiconductor device MC3 and the DC-DC converter DM is different, and the startup time thereof is also different from the startup time of the interface circuits SM and WLM. Therefore, an instantaneous voltage drop does not occur in the electronic system device 3. As a result, even based on a current of several μA level output from the power generation device P, the electronic system device 3 can be stably started without being reset.

Claims

1. An electronic system device, comprising: A power generation device for generating a first power supply voltage; a semiconductor device comprising a control circuit coupled to the power generation device via a first power supply node and a substrate bias control circuit coupled to the control circuit; a DC-DC converter coupled to the power generation device in parallel with the control circuit via the first power supply node; as well as A first switch is provided between the first power supply node and the DC-DC converter and is coupled to the first power supply node and the DC-DC converter. The control circuit includes a field effect transistor, and after receiving a first power supply voltage, the first switch is set from an off state to an on state, wherein after the first switch is controlled to be in an on state, the DC-DC converter receives the first power supply voltage via the first switch, and The substrate bias control circuit provides a substrate bias voltage to the field effect transistor before the DC-DC converter receives the first power supply voltage, after the control circuit receives the first power supply voltage and before the first switch is set from an off state to an on state.

2. The electronic system device according to claim 1, The DC-DC converter generates a second power supply voltage different from the first power supply voltage.

3. The electronic system device according to claim 2, further comprising: Interface device, The interface device receives the second power supply voltage from the DC-DC converter and provides a data signal to the semiconductor device.

4. The electronic system device according to claim 3, wherein the semiconductor device includes an input / output circuit for receiving the second power supply voltage from the DC-DC converter, and The input / output circuit operates based on the second power supply voltage and receives the data signal from the interface device.

5. The electronic system device according to claim 4, The substrate bias control circuit stops providing the substrate bias voltage before the input / output circuit receives the data signal.

6. The electronic system device according to claim 5, The substrate bias control circuit provides the substrate bias voltage again after the input / output circuit receives the data signal.

7. The electronic system device according to claim 6, After the substrate bias control circuit provides the substrate bias voltage again, the control circuit sets the first switch from the on state to the off state.

8. The electronic system device according to claim 1, The field effect transistor comprises: substrate; a well region formed in the substrate; A semiconductor layer is formed on the well region via an insulating film; A source region, a drain region and a channel region are formed in the semiconductor layer; as well as a gate electrode provided on the channel region via a gate insulating film, The substrate bias control circuit provides the substrate bias voltage to the well region.

9. The electronic system device according to claim 8, further comprising: The first capacitor, The semiconductor device comprises: a second switch provided between the power generation device and the first power supply node; and a first monitoring circuit coupled between the second switch and the power generation device via a second power supply node, wherein the first capacitor is coupled to the second power supply node in parallel with the first monitoring circuit, The first monitoring circuit controls the second switch based on the voltage of the second power supply node.

10. The electronic system device according to claim 9, further comprising: Auxiliary battery, The semiconductor device comprises: a third switch coupled between the second power supply node and the second switch via a third power supply node; and a second monitoring circuit, coupled to the third switch, wherein the auxiliary battery is coupled to the third switch in parallel with the second monitoring circuit, and After the substrate bias control circuit provides the substrate bias voltage, the control circuit sets the third switch from an off state to an on state.

11. The electronic system device according to claim 10, further comprising: The second capacitor, The second capacitor is coupled to the DC-DC converter.

12. The electronic system device according to claim 2, wherein the control circuit provides a control signal to the DC-DC converter after the DC-DC converter receives the first power supply voltage, and The DC-DC converter generates the second power supply voltage based on the control signal.

13. A method for driving an electronic system device, the electronic system device comprising: A power generation device for generating a first power supply voltage; a semiconductor device comprising a control circuit and a substrate bias control circuit, the control circuit comprising a field effect transistor and coupled to the power generation device via a power supply node, the substrate bias control circuit coupled to the control circuit; a DC-DC converter coupled to the power generating device in parallel with the control circuit via the power supply node; as well as a switch disposed between and coupled to the power supply node and the DC-DC converter, wherein the control circuit receives the first power supply voltage via the power supply node, wherein after the control circuit receives the first power supply voltage, the switch is set from an off state to an on state by the control circuit, wherein the DC-DC converter receives the first power supply voltage via the switch after the switch is controlled to be in an on state, and The substrate bias control circuit provides the substrate bias voltage to the field effect transistor before the DC-DC converter receives the first power supply voltage, after the control circuit receives the first power supply voltage and before the switch is set to an on state.

14. The method for driving an electronic system device according to claim 13, The field effect transistor comprises: substrate; a well region formed in the substrate; a semiconductor layer formed on the well region via an insulating film; A source region, a drain region and a channel region are formed in the semiconductor layer; as well as a gate electrode provided on the channel region via a gate insulating film, The substrate bias control circuit provides the substrate bias voltage to the well region.

15. The method for driving an electronic system device according to claim 13, wherein the electronic system device further comprises: Interface device, wherein the DC-DC converter generates a second power supply voltage different from the first power supply voltage, and The interface device receives the second supply voltage from the DC-DC converter.

16. A semiconductor device that drives and controls a DC-DC converter by a power supply voltage generated by a power generation device, the semiconductor device comprising: a first terminal coupled to the power generating device; a control circuit including a field effect transistor and coupled to the first terminal via a power supply node; a substrate bias control circuit coupled to the control circuit; a second terminal coupled to the first terminal in parallel with the control circuit and to the DC-DC converter via the power supply node; as well as a switch disposed between the power supply node and the second terminal and coupled to the power supply node and the second terminal, wherein the control circuit sets the switch from an off state to an on state after receiving the power supply voltage via the first terminal, wherein the second terminal provides a power supply voltage to the DC-DC converter after the switch is controlled to be in an on state, and The substrate bias control circuit provides a substrate bias voltage to the field effect transistor before the second terminal provides the power supply voltage to the DC-DC converter, after the control circuit receives the power supply voltage and before the switch is set to an on state.

17. The semiconductor device according to claim 16, The field effect transistor comprises: substrate; a well region formed in the substrate; a semiconductor layer formed on the well region via an insulating film; A source region, a drain region and a channel region are formed in the semiconductor layer; as well as a gate electrode provided on the channel region via a gate insulating film, The substrate bias control circuit provides the substrate bias voltage to the well region.

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