Digital signal processing block

Abstract

The present disclosure relates to digital signal processing blocks. A digital signal processor (DSP) chip is disclosed. The DSP chip includes an input stage for receiving a plurality of input signals; a pre-adder coupled to the input stage and configured to perform one or more operations on one or more of the plurality of input signals; and a multiplier coupled to the input stage and the pre-adder and configured to perform one or more multiplication operations on one or more of the plurality of input signals or an output of the pre-adder. The DSP chip also includes an arithmetic logic unit (ALU) coupled to the input stage, the pre-adder, and the multiplier. The ALU is configured to perform one or more mathematical or logical operations on one or more of the plurality of input signals, an output of the pre-adder, or an output of the multiplier. The DSP chip also includes an output stage coupled to the ALU, the output stage configured to generate one or more output signals based at least in part on one or more outputs of the ALU or at least one of the plurality of input signals.

Description

Technical Field

[0001] Aspects of the present disclosure relate generally to electronic circuits, and more particularly to digital signal processing blocks. Background Art

[0002] A programmable logic device (PLD) is a well-known integrated circuit that can be programmed to perform a specified logic function. One type of PLD (e.g., a field programmable gate array or FPGA) typically includes an array of programmable blocks. These programmable blocks may include, for example, input / output blocks (IOBs), configurable logic blocks (CLBs), application specific random access memory (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay-locked loops (DLLs), and the like.

[0003] Each programmable block can include programmable interconnects and programmable logic. The programmable interconnects can include a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic can implement user-designed logic using programmable elements, which can include, for example, function generators, registers, arithmetic logic, and the like.

[0004] Programmable interconnects and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells, which define how the programmable elements are configured. Configuration data can be read from memory (such as from an external PROM) or written to the FPGA by an external device. Therefore, the collective state of the individual memory cells determines the functionality of the FPGA.

[0005] Another type of PLD is a complex programmable logic device, or CPLD. A CPLD may include two or more "function blocks" connected together and to input / output (I / O) resources via an interconnect switch matrix. Each function block of a CPLD may include a two-level AND / OR structure similar to that used in programmable logic array (PLA) and programmable array logic (PAL) devices. In a CPLD, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory and then downloaded to volatile memory as part of the initial configuration (programming) sequence.

[0006] For all of these programmable logic devices (PLDs), the functionality of the device is controlled by the data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells as in FPGAs and some CPLDs), non-volatile memory (e.g., FLASH memory as in some CPLDs), or any other type of memory cell.

[0007] Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various components on the device. These PLDs are known as mask-programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices and include devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.

[0008] The performance of designs instantiated in the programmable logic of an FPGA (FPGA fabric) is limited by the speed of the FPGA fabric. However, dedicated circuit resources, such as DSPs within an FPGA, can perform operations much faster than equivalent circuits implemented in the FPGA fabric. Therefore, it would be desirable and useful to provide means for extending the utility of such DSPs. Summary of the Invention

[0009] This Summary is provided to introduce some concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0010] Aspects of the present disclosure relate to a digital signal processor (DSP) slice configured to operate in each of a plurality of numerical modes. The DSP slice may include an input stage for receiving a plurality of input signals; a pre-adder coupled to the input stage, the pre-adder configured to perform one or more operations on one or more of the plurality of input signals. The DSP slice may also include a multiplier coupled to the input stage and the pre-adder, the multiplier configured to perform one or more multiplication operations on one or more of the plurality of input signals or an output of the pre-adder. The DSP slice may also include an arithmetic logic unit (ALU) coupled to the input stage, the pre-adder, and the multiplier, the ALU configured to perform one or more mathematical or logical operations on one or more of the plurality of input signals, an output of the pre-adder, or an output of the multiplier. The DSP slice may also include an output stage coupled to the ALU, the output stage configured to generate one or more output signals based at least in part on one or more outputs of the ALU or at least one of the plurality of input signals.

[0011] In another example, a method for selectively operating a DSP slice in one of a plurality of numerical modes is disclosed. The method may include: receiving one or more input signals to the DSP slice; receiving one or more control signals for the DSP slice; configuring the DSP slice to operate in a selected numerical mode of the plurality of numerical modes based at least in part on the one or more control signals; and performing one or more arithmetic or logical operations on the one or more input signals, the at least one or more arithmetic or logical operations being based at least in part on the selected numerical mode of the plurality of numerical modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The exemplary embodiments are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings. Throughout the drawings and the specification, like reference numerals refer to like elements.

[0013] Figure 1 shows a simplified block diagram of a DSP slice in which an example implementation may be implemented;

[0014] Figure 2 is a schematic diagram depicting a DSP slice according to some implementations;

[0015] Figure 3 is a block diagram of an example DSP slice, wherein components of the DSP slice are grouped into functional atoms;

[0016] Figure 4A shows an example grouping of 24-bit B inputs to a Booth encoder configured for use in 24-bit fixed-point numeric mode according to some implementations;

[0017] Figure 4B shows an example grouping of bits for a 24-bit B input used in a vector dot product computation in 8-bit fixed-point numeric mode according to some implementations;

[0018] Figure 5 illustrates a block diagram of operations for performing complex multiplication using an example DSP slice configured to operate in an 18-bit complex integer fixed-point numeric mode, according to some implementations;

[0019] Figure 6 is an illustrative flow chart showing example operations for selectively operating a DSP slice in one of a plurality of numerical modes in accordance with some embodiments; and

[0020] Figure 7 is an illustrative flow diagram of operations for configuring a DSP slice to operate in a selected one of a plurality of numerical modes, according to some implementations. DETAILED DESCRIPTION

[0021] Various aspects of the present disclosure may provide a digital signal processor (DSP) block that provides multiple numerical modes. By reducing the need for multiple DSPs to support operations using each of the multiple numerical modes, such a DSP block can allocate resources, such as programmable logic (PL) fabric resources, more efficiently. For example, a DSP that operates only with a single numerical mode may be less efficient when operating on data that is smaller than its native numerical mode. Similarly, multiple DSPs may be used to perform operations on complex values, which is less efficient than performing such operations in a single DSP block. More generally, enabling a single DSP slice to perform more operations can increase processing speed by reducing the additional fabric logic and routing that would otherwise be required for such operations. These and other aspects are described below with reference to the accompanying drawings.

[0022] In the following description, many specific details are set forth, such as examples of specific components, circuits, and processes, to provide a thorough understanding of the present disclosure. As used herein, the term "coupled" refers to direct coupling or coupling through one or more intermediate components or circuits. Moreover, in the following description and for the purpose of explanation, specific terms and / or details are set forth to provide a thorough understanding of the example embodiments. However, it will be clear to those skilled in the art that these specific details may not be required to practice the example embodiments. In other cases, well-known circuits and devices are shown in block diagram form to avoid obscuring the present disclosure. Any signal provided via the various buses described herein may be time-division multiplexed with other signals and may be provided via one or more common buses. In addition, the interconnections between circuit elements or software blocks may be shown as buses or single signal lines. Each bus may alternatively be a single signal line, and each single signal line may alternatively be a bus, and a single line or bus may represent any one or more of a variety of physical or logical mechanisms for communication between components. The example embodiments should not be construed as limited to the specific examples described herein, but rather include within their scope all embodiments defined by the appended claims.

[0023] As the demand for increased operating speed increases, functionality is being added in the form of configurable or programmable functions in system-on-chip (SoC) devices, field-programmable gate array (FPGA) devices, or other integrated circuits (ICs). One area where operating speed is being increased is digital signal processing. Described below are digital signal processing slices that can be replicated and have multiple instances in an IC. Such digital signal processing slices can, for example, be grouped in a column, where the output of one such slice can be the input of an adjacent slice. The following slices may include: a pre-adder; a multiplier, and an arithmetic logic unit (ALU). Each slice may be capable of many independent functions in each of a plurality of numerical modes. Such independent functions may include multiply-accumulate (MACC), multiply-add, four-input addition, barrel shift, wide bus multiplexing, amplitude comparison, bitwise logic functions, pattern detection, and wide counter operations. Slices can also be used in combination to perform a wide range of mathematical functions, DSP filtering operations, and complex arithmetic without the need for general-purpose FPGA logic.

[0024]

[0014] Given the above general understanding, various implementations for digital signal processing datapath elements or slices are generally described below.

[0025] Because one or more of the above implementations are described using a particular type of IC, a detailed description of an example IC is provided below. However, it should be understood that other types of ICs may benefit from one or more of the implementations described herein.

[0026] A programmable logic device ("PLD") is a well-known integrated circuit that can be programmed to perform a specified logic function. One type of PLD, such as a field programmable gate array ("FPGA"), typically includes an array of programmable blocks. These programmable blocks may include, for example, input / output blocks (IOBs), configurable logic blocks (CLBs), application specific random access memory blocks (BRAMs), multipliers, digital signal processing datapath elements or blocks ("DSPs"), processors, clock managers, delay locked loops ("DLLs"), and the like. As used herein, the terms "include" and "including" mean including, but not limited to, including.

[0027] Each programmable block can generally include programmable interconnects and programmable logic. The programmable interconnects can generally include a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). Programmable logic uses programmable elements, which can include, for example, function generators, registers, arithmetic logic, and the like, to implement user-designed logic.

[0028] Programmable interconnects and programmable logic can typically be programmed by loading a stream of configuration data into internal configuration memory cells, which define how the programmable elements are configured. Configuration data can be read from memory (such as from an external PROM) or written to the FPGA by an external device. Therefore, the collective state of the individual memory cells determines the functionality of the FPGA.

[0029] Another type of PLD is a complex programmable logic device (CPLD). A CPLD consists of two or more "function blocks" connected together and to input / output ("I / O") resources via an interconnect switch matrix. Each function block of a CPLD consists of a two-level AND / OR structure similar to that used in programmable logic array ("PLA") and programmable array logic ("PAL") devices. In a CPLD, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory and then downloaded to volatile memory as part of the initial configuration (programming) sequence.

[0030] For all of these programmable logic devices ("PLDs"), the functionality of the device can be controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells as in FPGAs and some CPLDs), non-volatile memory (e.g., FLASH memory as in some CPLDs), or any other type of memory cell.

[0031] Other PLDs can be programmed by applying a processing layer (such as a metal layer) that programmably interconnects the various components on the device. These PLDs are known as mask-programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices and include devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.

[0032] As mentioned above, some FPGAs can include many different types of programmable logic blocks in their arrays. For example, an FPGA architecture can include a large number of different programmable blocks, which can include multi-gigabit transceivers (MGTs), configurable logic blocks (CLBs), random access memory blocks (BRAMs), input / output blocks (IOBs), configuration and clock logic (CONFIG / CLOCK), DSP blocks, and specialized IO blocks (such as configuration ports, digital clock managers, analog-to-digital converters, system monitoring logic, etc.). Some FPGAs can also include specialized processor blocks.

[0033] In some FPGAs, each programmable block can include a programmable interconnect element (INT) with standardized connections to and from corresponding interconnect elements in each adjacent block. Together, the programmable interconnect elements can implement the programmable interconnect structure for the FPGA. Each programmable interconnect element can also include connections to and from programmable logic elements within the same block.

[0034] For example, a CLB may include a configurable logic element (CLE) that can be programmed to implement user logic and programmable interconnect elements. In addition to one or more programmable interconnect elements, a BRAM may also include a BRAM logic element (BRL). The number of interconnect elements included in a block may depend on the height of the block. In some implementations, the height of a BRAM block may be equal to an integer number of CLBs, such as 4, 5, or another suitable number. In addition to an appropriate number of programmable interconnect elements, a DSP block may also include a DSP logic element (DSPL). In addition to instances of programmable interconnect elements, an IOB may include, for example, one or more instances of an input / output logic element (IOL), such as two IOLs. For example, the actual I / O pad connected to an I / O logic element may not be limited to the area of ​​the I / O logic element.

[0035] In some implementations, regions of the die can be used for configuration, clock, and other control logic. In some implementations, such regions of the die can be horizontal or vertical regions located near the center of the die. Vertical columns can extend from such horizontal regions (or rows from such vertical regions) and can be used to distribute clock and configuration signals across the FPGA.

[0036] Some FPGAs may include additional logic blocks that may disrupt the regular column structure that makes up a large portion of the FPGA. For example, such additional logic blocks may include programmable blocks or specialized logic, such as processor blocks, that may span multiple columns of CLBs and BRAMs.

[0037] Figure 1A simplified block diagram of a DSP slice 100 in which an example implementation may be implemented is shown. More specifically, the DSP slice 100 may include an input module 110, a pre-addition module 120, a multiplier 130, an arithmetic logic unit (ALU) 140, and an output 150. Each module making up the DSP slice 100 may include one or more logic elements and interconnect elements as described above. The input module 110 may be configured to receive and buffer one or more input signals. The pre-addition module 120 may be configured to perform one or more arithmetic operations, such as one or more addition operations, on the one or more inputs received. The multiplier 130 may be configured to perform one or more multiplication operations on the inputs received or on one or more outputs of the pre-addition module 120. The ALU 140 may be configured to perform one or more operations on the input signals received or on one or more outputs of the pre-addition module 120 or the multiplier 130. Note that Figure 1 Only a simplified high-level depiction of the modules of an example DSP slice is shown, and therefore connectivity between the modules shown is not fully representative. One or more modules may be bypassed between input 110 and output 150. For example, input 110 may provide one or more input signals directly to multiplier 130 or ALU 140, rather than providing one or more input signals to a pre-adder module. The details of these functions will be discussed in detail below. More specifically, Figure 1 Each of the modules 110-150 shown may include the following: Figure 2 One or more elements described.

[0038] As described above, the example implementation can enable each of the multiple numerical modes to be implemented in a single DSP slice, thereby providing improved operation. More particularly, in a conventional DSP slice, performing multiple general operations may require the use of additional structural resources, such as structural routing resources. For example, such operations may include dot product calculations, matrix multiplications, FIR filtering, etc. The use of such additional structural resources may be an important limiting factor for the speed of performing these operations. Therefore, the example implementation can limit the structural resources required to perform such operations by enabling the example DSP slice to operate in multiple numerical modes. In some examples, multiple numerical modes may include fixed-point numerical modes and floating-point numerical modes. The numerical modes may also include complex integer numerical modes. In an example implementation, the numerical modes may include 24-bit fixed-point integer mode (INT24), 8-bit fixed-point integer mode (INT8), 18-bit complex fixed-point integer mode (CINT18), and 32-bit binary floating-point mode (FP32). Note that although these modes are referred to as numerical modes in this article, they may be referred to as precision modes, or alternatively as numbers.

[0039] Figure 2A block diagram of a DSP slice 200 according to an example implementation is shown. As described above, the DSP slice 200 can implement each of multiple numerical modes, such as an INT24 numerical mode, an INT8 numerical mode, a CINT18 numerical mode, and an FP32 numerical mode. The DSP slice 200 can be configured to operate in a selected one of the multiple numerical modes based on one or more control signals or attributes (such as one or more bits in a received bitstream). In one implementation, the numerical mode can be set based on one or more bits of a configuration bitstream. More specifically, in one such implementation, the mode can be selected based on decoded values ​​of one or more configuration memory cells, where the values ​​of the one or more configuration memory cells are set using the configuration bitstream. In some implementations, the configuration bitstream can be generated using a software tool, such as an electronic design automation software tool, or "EDA tool," which can include one or more abstract models of the example DSP slice. The specific model selected to abstract the example DSP slice can be determined explicitly (based on direct instantiation in a selected design for a PLD) or implicitly (based on the EDA tool's inference of the intended functionality and operation of a given design to be implemented by the PLD). An example explicit determination can be made by a designer that includes a representation (such as a hardware design language or HDL representation) of a circuit design that configures the example DSP slice to the selected numerical mode. In contrast, in an example implicit determination, the EDA tool can infer that the intended operation or function to be performed can be achieved by configuring the example DSP slice to operate in the selected numerical mode.

[0040] about Figure 2 , DSP chip 200 can receive Figure 2, four input data buses are represented by A, B, C, and D. In some implementations, the A input bus can be a 34-bit input bus, the B input bus can be a 24-bit input bus, the C input bus can be a 58-bit input bus, and the D input bus can be a 27-bit input bus. The A, B, C, and D input buses can be received by corresponding registers 201, 202, 203, and 204. Note that in some implementations, the A input register 201 and the B input register 202 can also receive corresponding cascade inputs ACIN and BCIN, for example, from corresponding cascade output signals of a second DSP slice (such as an adjacent DSP slice), and can output corresponding cascade output signals ACOUT and BCOUT to another DSP slice. For example, DSP slice 200 can be coupled to an adjacent DSP slice having the same structure as DSP slice 200, and the ACIN and BCIN signals can correspond to corresponding ACOUT and BCOUT signals output from the adjacent DSP slice. Such cascade inputs can be used, for example, for applications such as FIR filtering, complex multiplication, multiple-precision multiplication, and complex multiply-accumulate (MACC) operations. In some implementations, registers 201, 202, 203, and 204 may be Figure 1 A portion of input stage 110 is shown.

[0041] Note further that in some implementations, the D input bus may also be provided to the B input register 202, for example, for use in FP32 numerical mode, as discussed further below. In some implementations, one or more outputs from the A, B, and D input registers 201, 202, and 204 may be provided to the pre-adder 207. In some implementations, one or more of the A, B, and D inputs may be provided to the pre-adder 207. For example, the A input, the B input, or the D input may be selected as an input to the pre-adder 207. For example, the multiplexer 206 may control which of the A input, the B input, or the D input is provided to the pre-adder 207.

[0042] DSP slice 200 may also receive an INMODE control signal. INMODE may be a control signal provided to INMODE register 205. INMODE may include multiple bits, such as five. Certain bits of INMODE may provide control over the selection of the A and B input registers, such as by providing control inputs to corresponding multiplexers 201A and 202A. For example, the A and B input registers 201 and 202 may be dual-input registers to allow for two pipeline stages, and INMODE may provide selection for the first stage (A1 or B1, respectively) or the second stage (A2 or B2, respectively). INMODE may also control a balanced pipeline when dynamically switching between multiplication and addition operations. Furthermore, INMODE may control the multiplexing between D input register 204 and A or B input registers 201 or 202 (e.g., using one or more of multiplexers 201A, 202A, and 204A). INMODE may also provide subtraction control for pre-adder 207.

[0043] The DSP slice 200 may also receive a NEGATE control signal that may be provided to a NEGATE register 211 and provided to a multiplier 212. NEGATE may control certain aspects of the multiplier 212, as discussed further below. For example, NEGATE may control the sign of the input to the multiplier 212, thereby providing a multiplication with the negated input.

[0044] DSP slice 200 may also receive an OPMODE control signal that may be provided to OPMODE register 218. For example, OPMODE may provide multiplexer control signals for W multiplexer 214, X multiplexer 215, Y multiplexer 216, and Z multiplexer 217. These multiplexers may control the selection of four inputs to ALU 219. For example, the inputs to ALU 219 may include four 58-bit inputs provided from W multiplexer 214, X multiplexer 215, Y multiplexer 216, and Z multiplexer 217.

[0045] The DSP slice 200 may also receive an ALUMODE control signal that may be provided to an ALUMODE register 223. The ALUMODE may control the function to be performed by the ALU 219. For example, the ALUMODE may configure the ALU 219 to perform a four-input arithmetic operation on the four inputs received from the W multiplexer 214, the X multiplexer 215, the Y multiplexer 216, and the Z multiplexer 217. For example, the ALUMODE may configure the ALU 219 to output Z+W+X+Y+CARRYIN, Z-(W+X+Y+CARRYIN), or other four-input arithmetic operations. Other ALUMODEs may configure the ALU 219 to perform logic operations on two or more inputs provided by the W multiplexer 214, the X multiplexer 215, the Y multiplexer 216, and the Z multiplexer 217. For example, ALUMODE may configure ALU 219 to determine XOR, XNOR, AND, NAND, NOT, OR, and NOR operations on the W, X, Y, and Z inputs.

[0046] The DSP slice 200 may also receive a CARRYINSEL control signal, which may be provided to a CARRYINSEL register 221. CARRYINSEL may control which input is provided as a carry-in signal to the ALU 219. For example, CARRYINSEL may be provided as a control input to a multiplexer 222 to select one of multiple inputs as the carry-in signal for the ALU 219. The multiple inputs to the multiplexer 222 may include a CARRYIN input signal (provided to the multiplexer 222 via the CARRYIN register 220), a CARRYCASCIN signal, and a CARRYCASCOUT signal (a concatenated signal for large add / subtract / accumulate operations involving two adjacent DSP slices).

[0047] DSP slice 200 may also include a pre-adder 207 (which may be included in Figure 1 The DSP slice 100 may further include an AD register 208. The DSP slice 200 may further include a multiplexer 209, a multiplexer 210, a multiplier 212, and a multiplier register 213, each of which may be included in the DSP slice 100. Figure 1 The DSP slice 200 may also include a W multiplexer 214, an X multiplexer 215, a Y multiplexer 216, a Z multiplexer 217, an ALU 219, and a multiplexer 222, each of which may be included in Figure 1The DSP slice 200 may further include an XOR 224, an XOR register 225, a mode detection multiplexer 226, and a mode detection register 227. The DSP slice 200 may further include a carry register 228 and an output register (P) 229, which may be included in the Figure 1 The DSP slice 200 may further include a rounding / normalization module 230, a first floating-point multiplexer 231, a second floating-point multiplexer 232, and a floating-point adder 233, which may be included in some implementations. Figure 1 The functions of these components will be discussed below in the context of multiple numerical modes implemented by the DSP slice 200. For further discussion of these components, see https: / / www.xilinx.com / support / documentation / user_guides / ug579- ultrascale-dsp.pdf Available from Xilinx, “UltraScale Architecture DSP Slice User Guide,” June 4, 2018 (which is incorporated herein by reference).

[0048] As described above, the example implementation provides a DSP slice capable of operating in each of a plurality of numerical modes (such as INT24 numerical mode, INT8 numerical mode, CINT18 numerical mode, and FP32 numerical mode). However, not all components of the example DSP slice can be used in all numerical modes. For example, with respect to the DSP slice 200, certain components such as the rounding / normalization module 230, the first floating-point multiplexer 231 and the second floating-point multiplexer 232, and the floating-point adder 233 can only be used in the FP32 numerical mode. Therefore, when the FP32 numerical mode is not enabled, such components can be placed in a low-power state. In some implementations, the components of the DSP slice 200 can be individually enabled or disabled, while in some other implementations, the components can be grouped into multiple elements referred to as "atoms." Components or atoms that are not used with an enabled numerical mode can be placed in a low-power state. For example, when the multiplier 212 is not used, it can receive one or more control bits, such as the USE_MULT attribute, to signal that the multiplier 212 will enter a low-power state. In one implementation, ALU 219 can be configured to implement single instruction multiple data (SIMD) operations of a four-input adder / subtractor, which does not require the use of multiplier 212, and thus multiplier 212 can be signaled to enter a low power state during such operations. Similar properties can be used to place other components of DSP slice 200 into a low power state when not needed.

[0049] Figure 3 An example block diagram 300 of a DSP slice 200 is shown according to some implementations. More particularly, Figure 3 The components of the DSP slice 200 are shown grouped into functional atoms as described above. Thus, Figure 3 Included are A and B data atoms 302. For example, A and B data atoms 302 may include dual A register 201, dual B register 202, and associated multiplexers (such as one or more of multiplexers 201A, 202A, 204A, and 206). Figure 3 Also included are pre-add data atoms 304 and pre-add atom 306. These atoms may include, for example, pre-adder 207 and related components of DSP slice 200. For example, pre-add data atom 304 may include D input register 204, INMODE register 205, and may receive control signals such as INMODE and NEGATE. Pre-add data atom 304 may also receive one or more signals from adjacent DSP slices, such as one or more signals related to complex multiplication and conjugation, as discussed below with respect to CINT18 numeric mode. Figure 3 Also included is the floating point exponent atom 308 discussed below with respect to FP32 numeric mode. Figure 3 Also included are a multiplier atom 310 and a multiply data atom 312. These atoms may include the multiplier 212 and related components of the DSP slice 200. Figure 3 Also included is a C-data atom 314 , which may include components such as the C-data register 203 . Figure 3 A floating point adder atom 316 , described further below with respect to FP32 numeric mode, may also be included. Figure 3 A pattern detection atom 318 may also be included, which may include components related to pattern detection, such as the pattern detector 226 and the pattern detection register 227 . Figure 3 An ALU regulator atom 320 may also be included, which may receive control signals related to the functionality of the ALU 219, such as OPMODE, CARRYIN, CARRYINSEL, and ALUMODE. These control signals may be provided from the ALU regulator atom 320 to an ALU and MUX atom 322. The ALU and MUX atom 322 may include components such as the ALU 219 and related components such as the W, X, Y, and Z multiplexers 214-217. Figure 3 Normalization and rounding atoms 326 may also be included that can perform the operations discussed below with respect to FP32 numeric mode. Finally, Figure 3Output atoms 328 may be included that may incorporate components related to the output of the DSP slice 200, such as the output register 229 and related components. Note that several atoms are used only in FP32 numerical mode. When the DSP slice 200 is not operating in FP32 numerical mode, these atoms (308, 316, and 326) may be configured to be in a low power state or otherwise disabled when the DSP slice is not in FP32 numerical mode.

[0050] As described above, the DSP slice according to some example implementations may be capable of operating in multiple numerical modes, one of which may be an INT24 numerical mode. When configured to operate in the INT24 numerical mode, the DSP slice 200 may be configured to use Figure 2 The components shown can be used to provide a variety of functions. For example, multiplier 212 can be configured to support 27-bit by 24-bit two's complement multiplication. In some aspects, multiplier 212 can include a modified Booth encoder. ALU 219 can be configured to perform bitwise logical operations, such as two-input AND, OR, NOT, NAND, NOR, XOR, and XNOR operations. Wide XOR 224 can be configured to support up to 116-bit wide XOR functions. Wide XOR 224 can also be configured to support 12-bit, 22-bit, 24-bit, 34-bit, or 58-bit XOR functions. Pre-adder 207 can support 27-bit operations, such as addition and subtraction. The output of pre-adder 207 can provide input to multiplier 212. For example, the output of pre-adder 207 can be provided as two inputs to multiplier 212 to allow multiplier 212 to perform a square operation. For example, the output of pre-adder 207 can be provided to multiplexer 209 and multiplexer 210 for input to multiplier 212. Similarly, either the A input or the B input can be provided as two inputs to multiplier 212 for a similar square operation. Alternatively, pre-adder 207 can be bypassed so that the D input is provided to the multiplier instead of the A or B input.

[0051] In some implementations, only a portion of the A input may be provided as input to the A input of the multiplier 212. For example, as described above, if A is a 34-bit input, then 27 bits (such as the lower 27 bits) of the 34-bit A input may be provided as the A input of the multiplier 212. The entire 34-bit A input may be used in conjunction with the B input to provide a cascaded internal bus. For example, the 34-bit A input may form the upper 34 bits of such a cascaded bus, while the 24-bit B input may provide the lower 24 bits, thereby forming a 58-bit A:B cascaded internal bus.

[0052] The DSP slice 200 may also receive cascade control signals, such as CARRYCASCIN and CARRYCASCOUT. These control signals may enable adjacent DSP slices (such as two adjacent copies of the DSP slice 200) to implement cascaded accumulators / adders / subtractors. For example, CARRYCASCIN and CARRYCASCOUT may enable adjacent DSP slices to implement 116-bit accumulators, adders, and / or subtractors.

[0053] As described above, in INT24 numerical mode, ALU 219 can support SIMD operations. For example, such SIMD operations can include dual 24-bit SIMD addition / subtraction / accumulation operations. These operations can have two separate carry-out signals. In addition, SIMD operations can include four 12-bit SIMD addition / subtraction / accumulation operations. These four 12-bit SIMD operations can have four separate carry-out signals.

[0054] The DSP slice 200 may also include a pattern detector 226 whose output may be provided to a pattern detector register 227. For example, the pattern detector 226 may determine whether the output P of the DSP slice 200 matches a specified pattern (as specified by a pattern input to the pattern detector 226). In some implementations, the specified pattern may be masked. The pattern detector 226 may also support convergent rounding (in conjunction with the C input), overflow / underflow support, and accumulator terminal counting (with automatic counter reset).

[0055] As described above, multiplier 212 may include a modified Booth encoder. This Booth encoder may be used in both INT24 and INT8 numerical modes. In INT24 numerical mode, the multiplier may use radix-4 Booth recoding to reduce the number of partial products. More specifically, in INT24 mode, the two bits of the b input may be grouped into 3-bit groups, where the last bit of the previous group includes the two bits of the current group. Figure 4A An example grouping 400 of 24-bit B input for such a Booth encoder is shown according to some implementations. Figure 4A, each of the groups 410(1)-410(6) includes three bits such that one bit overlaps with a bit from the previous group. Thus, the first group 410(1) includes two zeros and the most significant bit of the B input, b

[23] , where b

[23] refers to the most significant bit of the 24-bit B input. The second group 410(2) includes b

[23] , b

[22] , and b

[21] , and the third group 410(3) includes b

[21] , b

[20] , and b

[19] . This pattern continues for the remaining bits of the B input, including groups 410(4) and 410(5), including b[5], b[4], b[3], and b[3], b[2], b[1], respectively. The final group 410(6) includes b[1], b[0], and NEG[0]. NEG[0] refers to the zeroth bit of the NEGATE control input, as described above. When NEG[0] is asserted, the B input is inverted for multiplier 212 .

[0056] The DSP slice can also be configured to operate in INT8 numerical mode. INT8 numerical mode can be used as a low-precision mode to support operations such as matrix multiplication that use less memory storage space and bandwidth compared to other numerical modes such as FP32 numerical mode. For example, compared to FP32 numerical mode, INT8 numerical mode can reduce the required memory storage space and bandwidth by 4 times. Matrix multiplication may require a series of dot product calculations. Therefore, in INT8 numerical mode, the DSP slice 200 can be configured to calculate the dot product (alternatively referred to as the inner product) between two vectors. More specifically, the DSP slice 200 can be configured to calculate the first vector With the second vector The dot product between and , where each a i is a 9-bit two's complement fixed-point number, and each b i is an 8-bit two's complement number. For example, a0 may correspond to bits a[8], a[7], ..., a[1], and a[0] (the eighth to zeroth bits of the A input, which may also be referred to as a[7:0]), and b0 may correspond to bits b[7:0] (the seventh to zeroth bits of the B input). The calculation of these vector dot products may also use the Booth encoder of the multiplier 212, but the grouping used in conjunction with the INT8 numerical mode is different from the grouping used with the INT24 numerical mode discussed above. The INT8 mode may also enable the calculation of such vector dot products with element-by-element inversion, where the element-by-element inversion is indicated using three bits of the NEGATE control signal. That is, instead of simply using one bit of the NEGATE control signal to invert the B input as a whole as discussed above with respect to the INT24 numerical mode, each b input may be individually inverted. i Negate.

[0057] Figure 4B An example grouping 450 of the bits of the B input for such a vector dot product calculation is shown. Figure 4B , group 450 includes each b i 4 groups corresponding to the INT24 mode. Thus, b0 460 corresponds to groups 460(1), 460(2), 460(3), and 460(4), b1 470 corresponds to groups 470(1), 470(2), 470(3), and 470(4), and b2 480 corresponds to groups 480(1), 480(2), 480(3), and 480(4). As with the groups in INT24 mode, each group includes three bits, one of which overlaps with the previous group, and the last bit includes one bit of the NEGATE control signal. Thus, b0 460 has a first group 460(1) including b[7], b[6], and b[5], a second group 460(2) including b[5], b[4], and b[3], a third group 460(3) including b[3], b[2], and b[1], and a final group 460(4) including b[1], b[0], and NEG[0]. i Include similar groups, such as Figure 4B As in INT24 mode, the NEGATE control signal is used to change the sign of the input to the multiplier 212, but in INT8 mode, each b i can be individually inverted to be input to the multiplier 212. Therefore, the first bit NEG[0] of the NEGATE control signal can be used to change the sign of b0, the second bit NEG[1] of the NEGATE control signal can be used to change the sign of b1, and the third bit NEG[2] of the NEGATE control signal can be used to change the sign of b3, as shown in FIG. Figure 4B shown.

[0058] Thus, in INT8 numeric mode, the modified Booth encoder of multiplier 212 may be configured to compute the terms a0b0, a1b1, and a2b2, and combine these terms to determine the dot product a0b0±a1b1±a2b2, where the three bits of the NEGATE control signal determine the sign of each term added to the dot product, as described above.

[0059] In some example DSP slices, the partial product u i and v i The sum is added in an array reduction block where the INT8 partial products are grouped for faster computation. The sum of these partial products can be expressed as a dot product of i b i item:

[0060] u0+v0=±a0b0

[0061] u1+v1=±a1b1

[0062] u2+v2=±a2b2

[0063] Therefore, by i +v i The dot product is calculated by adding the terms to get:

[0064]

[0065] In some examples, the first stage of addition of these partial products can be implemented using a first 4:2 adder that can be enabled as part of an array reduction block in INT8 numerical mode to add u0+v0 and u2+v2. A second 4:2 adder can also be implemented in INT8 numerical mode (and also in CINT18 numerical mode described below). The second 4:2 adder can be implemented before the optional partial product pipeline register and can add the third term u1+v1 of the dot product to complete the calculation of the dot product u+v=a0b0±a1b1±a2b2. In addition, as described above, the inputs to the multipliers can be pipelined. Assume that AMULT and BMULT are the respective outputs of multiplexers 209 and 210, i.e., the inputs to multiplier 212. Therefore, the dot product can be calculated as follows:

[0066] u+v=(-1) NEG[0] AMULT[8:0]BMULT[7:0]+(-1) NEG[1] AMULT[17:9]BMULT[15:8]+(-1) NEG[2] AMULT [26:18] BMULT [23:16]

[0067] As described above, the example DSP slice can also be configured to operate in CINT18 numerical mode (18-bit complex integer fixed-point numerical mode). To operate in CINT18 mode, two DSP slices (such as two adjacent copies of DSP slice 200) can be coupled with logic to enable the two slices to operate as a single 18-bit complex multiplier. For example, in CINT18 numerical mode, the two DSP slices can be configured to calculate the product between a first complex number and a second complex number, where each complex number can be represented as an 18-bit real part and an 18-bit imaginary part. More specifically, the first DSP slice can be configured to calculate the real component of the complex product, the second DSP slice can be configured to calculate the imaginary component of the complex product, and other logic can be configured to calculate the common term of the complex product. The other logic can be located on the first DSP slice, on the second DSP slice, or can be shared between the first DSP slice and the second DSP slice.

[0068] In some conventional DSP slices, in addition to the two DSP slices, additional fabric logic is required to perform complex multiplication operations. As described above, the additional fabric logic can slow down operations because the fabric routing and logic can form timing-critical paths, which requires the conventional DSP slice to run at a lower clock speed. The example DSP slice allows such operations to be performed without additional fabric logic, thereby increasing the speed of operation. As described below, the example DSP slice can also perform complex conjugate operations without the need for additional fabric logic.

[0069] Figure 5 A block diagram 500 illustrates operations for performing complex multiplication using an example DSP slice configured to operate in CINT18 numerical mode according to some implementations. As described above, in CINT18 numerical mode, two DSP slices may be configured to compute a product between two complex numbers. More specifically, the complex product may be a product of a first complex number a. I +ja Q With the second complex number b I +jb Q between. The first part 510 of the operation performed by the first DSP slice can calculate the imaginary term of the product. The second part 520 of the operation performed by the second DSP slice can calculate the real term of the product. The third part 530 of the operation can calculate the common term of the product. As described above, the common term calculated by the third part 530 can be determined by the first DSP slice and / or the second DSP slice. In some implementations, the common term can be calculated using logic shared between two adjacent DSP slices. In some implementations, the shared logic can only be used in CINT18 numerical mode. For example, the shared logic can correspond to one or more atoms of the DSP slice 200, and these atoms can be configured to be in a low power state unless the DSP slice 200 is in CINT18 numerical mode.

[0070] The complex product between the first complex number and the second complex number can be calculated as follows:

[0071] (a I +ja Q )(b I +jb Q )=(Kb Q (a Q +a I ))+j(K+b I (a Q -a I ))

[0072] where K = a I (b I +b Q ). Therefore, the real part of the product can be determined as (Kb Q (a Q +a I )), and the imaginary part of the product can be determined as (K+b I (a Q -a I )), where K = a I (b I +b Q ) represents the common term in the real and imaginary parts.

[0073] about Figure 5 The first DSP slice and the second DSP slice may receive the first complex number and the second complex number, for example, using A, B, C, and D inputs. For example, the first complex number and the second complex number may be provided as inputs to the first DSP slice and the second DSP slice. The first portion 510 may begin by calculating the imaginary term of the product using an adder 511 to calculate (a Q -a I ). For example, the first DSP slice may use pre-adder 207 to calculate the term to get from a Q Subtract a from I (As described above, INMODE can control whether pre-adder 207 performs addition or subtraction.) The difference can be provided to multiplier 512, which can be multiplier 212 of the first DSP. The real part of the second complex number b I It can also be provided to the multiplier 512 to calculate the product b I (a Q -a I The product may be provided to adder 513, which may also receive the common terms from third portion 530 and sum these terms to compute the imaginary term of the complex product (K+b I (a Q -a I)). The adder 513 may correspond to the ALU 219 of the first DSP slice.

[0074] Similar to the first part 510, the second part 520 can use the adder 521 to calculate (a Q +a I ), for example by using the pre-adder 207 of the second DSP slice to calculate the sum. The sum may be provided to the multiplier 522, which may also receive the imaginary part b of the second complex number Q The multiplier 522 may be the multiplier 212 of the second DSP slice. The product b determined by the multiplier 522 is then used. Q (a Q +a I ) may be provided to an adder 523. The adder 523 may be the ALU 219 of the second DSP slice and may also receive the common term from the third portion 530. The adder 523 may calculate the difference (Kb Q (a Q +a I )). This difference is the real part of the complex product.

[0075] The third part 530 can calculate the common term K by using adder 531 to calculate the common term K. Q and b I The sum is then calculated using multiplier 532 and a I The product between them to generate the common term K = a I (b I +b Q ), the common item can be provided to the first part 510 and the second part 520.

[0076] In some implementations, the DSP slice 200 can also be configured to perform a complex multiply-accumulate operation. Such a multiply-accumulate operation can perform the complex multiplication operation described above (i.e., multiplying two 18-bit complex numbers) and use the 58-bit C inputs of two adjacent DSP slices for 58-bit real and imaginary number feedback. As described above, the ALU 219 (which can perform the functions of adders 513 and 523 of Figure 4) can be configured to perform addition and accumulation operations. In some other implementations, the DSP slice 200 can be configured to perform a complex addition operation using two adjacent DSP slices, using the C inputs of the two DSP slices as the complex 58-bit inputs to perform the 58-bit complex addition operation.

[0077] Described above and in Figure 5 The complex multiplier depicted in FIG can also be configured to perform complex conjugate multiplication. More specifically, before performing the complex multiplication operation, the first complex number a can be I +ja Q and the second complex number bI +jb Q For example, such complex conjugate multiplication can be performed by selectively conjugating Figure 5 The adder is configured to perform addition or subtraction and selectively Figure 5 The multiplier is configured to selectively invert its input. More specifically, as described above, the pre-adder of each DSP slice (corresponding to adders 511 and 521) is configured to use a bit of the INMODE control signal (such as INMODE[3]) to control addition or subtraction. In addition, the INMODE control signal can also control selective product inversion in the multiplier. As described above, the Booth encoder of multiplier 212 can support product inversion. In some implementations, rather than using the inversion control signal for product inversion, a bit of the INMODE control signal (such as INMODE[3]) can be used to configure the multiplier to perform complex conjugate multiplication. The INMODE control signal bits can also be pipelined.

[0078] As described above, the DSP slice 200 can also be configured to operate in a 32-bit floating point (FP32) numerical mode. The example DSP slice can be configured to perform floating point multiplication and addition operations and floating point accumulation operations. Similar to the CINT18 mode, by coupling the DSP slices together, these operations can be performed without using additional fabric logic and routing resources, thereby allowing the DSP slice to achieve faster operating speeds compared to conventional DSP slices that require the use of additional fabric resources. For example, the DSP slice 200 can include floating point atoms that can be used in conjunction with fixed point atoms to implement a floating point arithmetic mode when the DSP slice is operating in FP32 mode. More particularly, with respect to Figure 2 , the DSP slice may include a rounding and normalization module 230, a first floating point multiplexer 231 and a second floating point multiplexer 232, and a floating point adder 233. In addition, the floating point components may be grouped into atoms, such as Figure 3As shown. For example, these atoms may include a floating-point exponent atom 308, a floating-point adder atom 316, and a normalization and rounding atom 326. As described above, these atoms can be selectively enabled when needed and placed in a low-power state when not needed. Therefore, when the DSP slice is operating in one of the fixed-point numerical modes such as INT8 or CINT18, these floating-point atoms can be disabled or placed in a low-power state. In FP32 numerical mode, the DSP slice 200 can perform floating-point operations, including floating-point multiplication and addition, multiplication accumulation, independent multiplication, and independent addition operations. Floating-point multiplication operations can be performed using the multiplier 212, while floating-point addition operations can be performed using separate logic (floating-point adder 233 / floating-point adder atom 316). Note that logic for performing floating-point multiplication operations can be present in the multiplier 212, while such logic is not used in the fixed-point numerical mode.

[0079] When the DSP slice operates in FP32 numerical mode, each floating point input to the multiplier 212 can be in IEEE binary 32 format (also known as single precision or FP32) or binary 16 format (also known as half precision or FP16). The format selected for each multiplier input can be signaled by one or more control attributes, such as the attribute A-FPTYPE corresponding to the selected format of the A input or B_D_FPTYPE corresponding to the selected format of the B input or D input. In some implementations, the output of the multiplier 212 and the floating point adder 233 can be in single precision format (FP32), regardless of whether the multiplier or adder input is in single precision or half precision format. This means that the overflow condition can be determined based on the maximum value of the FP32 format, regardless of the format of the input.

[0080] In some implementations, the floating-point adder 233 may only accept single-precision inputs (binary 32 / FP32). The floating-point adder 233 may include an internal loopback path that can be used for accumulation functions (such as for operations such as floating-point accumulation and sum operations). In some implementations, the output of the multiplier 212 can be fed to the floating-point adder 233 without additional structural routing. This can be used to support operations such as multiply-add (MADD) or multiply-accumulate (MAC) operations. In some implementations, for example, as described above, the ACIN and BCIN inputs can be used to cascade the floating-point inputs. For example, the B cascade signal can be selected as one of the B input, the D input, or the BCIN input. Similarly, the A cascade signal can be selected as one of the A input or the ACIN input.

[0081] In some implementations, when operating in FP32 numerical mode, the DSP slice 200 can comply with various aspects of one or more technical standards. For example, the DSP slice 200 can comply with various aspects of floating-point arithmetic in the IEEE 754 standard, such as: supporting FP32 format inputs to the multiplier 212 and the floating-point adder 233; supporting FP16 format inputs to the multiplier 212; supporting signaling of NaNs (not a number) and quiet NaNs (signaling NaNs causes invalidation, while quiet NaNs do not); sign handling of zero outputs of the multiplier 212 and the floating-point adder 233; and certain aspects of invalid operation handling that sets an invalid status flag.

[0082] When operating in FP32 numerical mode, certain aspects of the DSP slice 200 may conform to the IEEE 754 standard, but certain other aspects of the DSP slice 200 may not. For example, certain aspects of this non-conformance may be implemented to be compatible with the Intel Streaming SIMD Extensions (SSE) instruction set. More specifically, this non-conformance may be implemented to match the behavior of the Intel SSE instruction set with respect to addition and multiplication with the flush to zero (FTZ) feature and the denormalized as zero (DAZ) feature. For example, the DSP slice 200 may treat denormalized inputs as zero, meaning that inputs with a zero exponent and a mantissa not equal to zero are treated as zero. Additionally, if a number cannot be represented using the normalized value after normalization and rounding, the output may be zero, and the underflow flag may be raised. Furthermore, in some implementations, the DSP slice 200 may support rounding only to the nearest even integer in FP32 numerical mode. In some implementations, the mantissa associated with a NaN input may not be propagated to the output of the DSP slice 200.

[0083] Figure 6 is an illustrative flow chart of operations 600 for selectively operating a DSP slice in a selected numerical mode among a plurality of numerical modes, according to some implementations. Operations 600 may be performed by a suitable DSP slice, such as DSP slice 200. Such a DSP slice may be one of a plurality of DSP slices incorporated into a suitable programmable device, such as an FPGA. Figure 6, one or more input signals from the DSP slice may be received (602). For example, as described above, the one or more input signals may be one or more of the A, B, C, and D input signals, one or more of the carry input signals, one or more of the cascade input signals ACIN or BCIN, etc. One or more control signals from the DSP slice may also be received (604). As described above, the one or more control signals may include one or more of the INMODE, NEGATE, OPMODE, CARRYINSEL, or ALUMODE control signals. The DSP slice may be configured to operate in a selected numerical mode from a plurality of numerical modes based at least in part on the one or more control signals (606). As described above, the numerical mode may include one or more fixed-point numerical modes (such as INT24, INT8, or CINT18 numerical modes) and one or more floating-point numerical modes (such as FP32 numerical modes). Configuring the DSP slice to operate in the selected numerical mode from the plurality of numerical modes may include placing one or more modules of the DSP slice in a low power state when the selected numerical mode is not needed. For example, one or more modules that the DSP slice uses to operate in floating-point mode may not be needed for one or more fixed-point numerical modes, and therefore, the floating-point modules may be placed in a low-power state when the DSP slice is configured to operate in one or more fixed-point numerical modes.

[0084] Figure 7 is an illustrative flow diagram of operation 700 for configuring a DSP slice to operate in a selected numerical mode of a plurality of numerical modes according to some implementations. Operation 700 may be performed by a suitable DSP slice, such as DSP slice 200. Such a DSP slice may be one of a plurality of DSP slices incorporated into a suitable programmable device, such as an FPGA. Figure 7 , a configuration bitstream can be generated (702). As described above, in some implementations, a configuration bitstream can be generated to explicitly determine in which numerical mode the DSP slice is to operate (702A), such as when the designer includes a representation (such as an HDL representation) in which the DSP slice is to operate in a selected numerical mode. In some other implementations, a configuration bitstream can be generated to implicitly determine in which numerical mode the DSP slice is to operate (702B). For example, in the example implicit determination, the EDA tool can infer that the intended operation or functionality to be performed can be achieved by configuring the example DSP slice to operate in the selected numerical mode.

[0085] The DSP slice may receive the generated configuration bitstream (704). For example, the configuration bitstream may be received as the contents of one or more configuration memory cells, the contents of which may be set by the configuration bitstream. Based on the received configuration bitstream, the DSP slice may then be configured to operate in the selected numerical mode (706).

[0086] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0087] In addition, it will be appreciated by those skilled in the art that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on specific applications and the design constraints imposed on the entire system. Technicians can implement the described functionality in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the scope of this disclosure.

[0088] The methods, sequences, or algorithms described in conjunction with the various aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM latch, a flash memory latch, a ROM latch, an EPROM latch, an EEPROM latch, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An example storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor.

[0089] In the foregoing description, example embodiments have been described with reference to specific example embodiments thereof. However, it will be apparent that various modifications and changes may be made to the present disclosure without departing from the broader scope of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A digital signal processor (DSP) chip, comprising: an input stage for receiving a plurality of input signals; a pre-adder coupled to the input stage, the pre-adder configured to perform one or more operations on one or more of the plurality of input signals; a multiplier coupled to the input stage and the pre-adder, the multiplier configured to perform one or more multiplication operations on one or more of the plurality of input signals or an output of the pre-adder; an arithmetic logic unit (ALU) coupled to the input stage, the pre-adder, and the multiplier, the ALU configured to perform one or more mathematical or logical operations on one or more of the plurality of input signals, the output of the pre-adder, or the output of the multiplier; as well as an output stage coupled to the ALU, the output stage configured to generate one or more output signals based at least in part on one or more outputs of the ALU or at least one of the plurality of input signals, wherein the DSP slice is configured to operate in a selected one of a plurality of numerical modes based on one or more bits of a configuration bitstream, the plurality of numerical modes including one or more fixed-point numerical modes and one or more floating-point numerical modes, and one or more modules associated with the one or more floating-point numerical modes are configured to be placed in a low power state when the DSP slice is configured to operate in one or more of the fixed-point numerical modes.

2. The DSP slice of claim 1, wherein the one or more fixed-point numerical modes include a 24-bit integer fixed-point INT24 numerical mode. 3 . The DSP slice of claim 2 , wherein in the INT24 value mode, the multiplier is configured to selectively invert an output of the multiplier based on a bit of an invert control signal.

4. The DSP slice of claim 2, wherein the one or more fixed-point numerical modes further comprise an 8-bit integer fixed-point INT8 numerical mode. 5 . The DSP slice of claim 4 , wherein in the INT8 numerical mode, the DSP slice is configured to perform a vector dot product between a first input signal of the plurality of input signals and a second input signal of the plurality of input signals.

6. The DSP slice of claim 5, wherein the first input signal comprises three 9-bit fixed-point numbers, the second input signal comprises three 8-bit fixed-point numbers, and the vector dot product is between the three 9-bit fixed-point numbers and the three 8-bit fixed-point numbers.

7. The DSP slice of claim 6, wherein the DSP slice is configured to selectively negate each partial product between the three 9-bit fixed-point numbers and the three 8-bit fixed-point numbers based at least in part on a corresponding bit of a negation control signal.

8. The DSP slice of claim 1 , wherein the one or more fixed-point modes include an 18-bit complex fixed-point CINT18 numerical mode, and wherein in the CINT18 numerical mode, the DSP slice is configured to compute a complex product between a first complex number and a second complex number, the first complex number and the second complex number having an 18-bit real part and an 18-bit imaginary part, respectively.

9. The DSP slice of claim 8, wherein in the CINT18 numerical mode, the DSP is further configured to calculate a complex conjugate product between the first complex number and the second complex number.

10. The DSP slice of claim 8 , wherein in the CINT18 numerical mode, the DSP slice is configured to couple to a second DSP slice to compute the complex product, wherein the DSP slice is configured to determine one of a real part and an imaginary part of the complex product and the second DSP slice is configured to determine the other of the real part and the imaginary part.

11. The DSP slice of claim 10 , wherein the DSP slice and the second DSP slice include common term logic, wherein in the CINT numerical mode, the DSP slice and the second DSP slice are further configured to use the common term logic to determine a common term for each of the real part and the imaginary part.

12. The DSP slice of claim 1, wherein the one or more floating point value modes include a 32-bit floating point FP32 value mode.

13. The DSP slice of claim 12, wherein in the FP32 numerical mode, the multiplier is configured to determine a product between single-precision multiplier inputs and to determine a product between half-precision multiplier inputs.

14. The DSP slice of claim 1 , wherein when the DSP slice is configured to operate in a selected numerical mode among the plurality of numerical modes, one or more modules of the DSP slice associated with a second numerical mode among the plurality of numerical modes are controlled to a low power state.

15. The DSP slice of claim 1, wherein the multiplier is configured to be placed into a low power state based at least in part on multiplier usage attributes.

16. A method for operating a digital signal processor (DSP) slice, comprising: receiving one or more input signals to the DSP slice; receiving one or more control signals for the DSP slice; configuring the DSP slice to operate in a selected one of a plurality of numerical modes based at least in part on the one or more control signals; as well as performing one or more arithmetic or logical operations on the one or more input signals, the one or more arithmetic or logical operations being based at least in part on the selected one of the plurality of numerical modes, wherein the plurality of numerical modes include one or more fixed-point numerical modes and one or more floating-point numerical modes, wherein one or more modules of the DSP slice associated with the one or more floating-point numerical modes are configured to be placed in a low power state when the DSP slice is configured to operate in one or more of the fixed-point numerical modes.

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