Memory and method of forming the same

Abstract

The present application relates to a memory and a method for forming the same, the method comprising: providing a substrate; forming, in the substrate, a drain doped layer, a channel doped layer and a source doped layer which are sequentially stacked from inside of the substrate to a surface of the substrate; forming a bit line below the channel doped layer and at least partially in the drain doped layer, and a first isolation structure penetrating the bit line, the bit line and the first isolation structure extending along a first direction; forming, in the substrate, third isolation structures on both sides of the bit line extending along the first direction; and forming, in the substrate, a word line structure in the channel doped layer and a second isolation structure penetrating the word line structure, the word line structure and the second isolation structure extending along a second direction. The memory formed by the above method has improved storage density.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more particularly to a memory and a method for forming the same. Background Technology

[0002] In the current development of DRAM technology, reducing the area of ​​memory cells and increasing their density is a crucial issue. However, due to limitations imposed by the current process node, it is difficult to further reduce the area of ​​memory cells based on existing memory fabrication processes.

[0003] In DRAM memory, each memory cell includes a storage capacitor and an access transistor, which controls the writing or reading of data within the memory cell. Given the increasing difficulty in reducing the area of ​​memory cells, modifying the structure of the access transistor can be an important method for increasing memory storage density.

[0004] How to change the structure of access transistors to increase memory storage density is a problem that urgently needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a memory and a method for forming the same, thereby improving the storage density of the memory.

[0006] To address the aforementioned problems, the present invention provides a method for forming a memory, comprising: providing a substrate; forming a drain doped layer, a channel doped layer, and a source doped layer sequentially stacked from the interior of the substrate to the surface of the substrate; forming a bit line located below the channel doped layer and at least partially located within the drain doped layer, and a first isolation structure penetrating the bit line, the bit line and the first isolation structure extending along a first direction; forming a third isolation structure extending along the first direction and located on both sides of the bit line within the substrate; forming a word line structure located within the channel doped layer within the substrate, and a second isolation structure penetrating the word line structure, the word line structure and the second isolation structure extending along a second direction.

[0007] Optionally, the method for forming the bit line and the first isolation structure includes: forming a plurality of first trenches extending along a first direction in the substrate, the first trenches including a bit line trench located below the channel doped layer and at least partially located in the drain doped layer, and a first dividing trench located above the bit line trench and communicating with the bit line trench, the width of the bit line trench being greater than the width of the first dividing trench; forming a bit line in the bit line trench; deepening the first dividing trench to form a first isolation trench penetrating the bit line to below the drain doped layer, and forming a first isolation structure in the first isolation trench.

[0008] Optionally, the method for forming the first trench includes: etching the substrate using an anisotropic etching process to form a plurality of first dividing trenches extending along a first direction; forming a first protective layer on the sidewall of the first dividing trench; and etching the substrate along the bottom of the first dividing trench using an isotropic etching process to form the bit line trench.

[0009] Optionally, the method for forming the word line structure and the second isolation structure includes: forming a plurality of second trenches extending along a second direction in the substrate, the second trenches including word line trenches located in the channel doped layer and second dividing trenches located above the word line trenches and communicating with the word line trenches, the width of the word line trenches being greater than the width of the second dividing trenches; forming a gate dielectric layer that at least covers a portion of the inner wall of the word line trenches and word lines located on the surface of the gate dielectric layer in the word line trenches; deepening the bottom of the second dividing trenches to form a second isolation trench penetrating the word lines, and forming a second isolation structure in the second isolation trenches.

[0010] Optionally, the method for forming the second trench includes: etching the substrate using an anisotropic etching process to form a plurality of second dividing trenches extending along a second direction; forming a second protective layer on the sidewall of the second dividing trench; and etching the substrate along the bottom of the second dividing trench using an isotropic etching process to form the word line trench.

[0011] Optionally, it further includes: forming an isolation doped layer in the substrate below the drain doped layer; a portion of the bit line is located within the isolation doped layer.

[0012] Optionally, it further includes: forming a doped region between the bottom of the word line structure and the bit line, wherein the doping concentration of the doped region is greater than the doping concentration of the drain doped layer, and has the same doping type as the drain doped layer.

[0013] To address the aforementioned problems, the present invention also provides a memory, comprising: a substrate, wherein a drain doped layer, a channel doped layer, and a source doped layer are formed therein, stacked sequentially from the interior of the substrate to the surface of the substrate; a bit line located below the channel doped layer and at least partially within the drain doped layer, and a first isolation structure penetrating the bit line, the bit line and the first isolation structure extending along a first direction; a third isolation structure located within the substrate and extending along the first direction on both sides of the bit line; a word line structure located within the substrate and within the channel doped layer, and a second isolation structure penetrating the word line structure, the word line structure and the second isolation structure extending along a second direction.

[0014] Optionally, it may also include: an isolation doped layer located below the drain doped layer; and a portion of the bit line located within the isolation doped layer.

[0015] Optionally, it further includes: a doped region located between the bottom of the word line structure and the bit line, wherein the doping concentration of the doped region is greater than the doping concentration of the drain doped layer, and has the same doping type as the drain doped layer.

[0016] The memory formation method of the present invention forms a transistor with a ring gate structure in a substrate. The source, channel region and drain of the transistor are vertically arranged in the substrate. The word line is arranged around the channel region and the bit line is located below the drain doped layer. This method can reduce the size of the access transistor, thereby increasing the storage density of the memory. Attached Figure Description

[0017] Figures 1 to 18E This is a schematic diagram of the formation process of a memory according to a specific embodiment of the present invention. Detailed Implementation

[0018] The specific embodiments of the memory and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Please refer to Figures 1 to 18E This is a schematic diagram of the formation process of a memory in a specific embodiment of the present invention.

[0020] Please refer to Figure 1 A substrate 100 is provided, in which a drain doped layer 103, a channel doped layer 104 and a source doped layer 105 are formed in sequence from the interior of the substrate 100 to the surface of the substrate 100.

[0021] The substrate 100 is a semiconductor substrate, which can be a single-crystal silicon substrate, a single-crystal germanium substrate, a germanium-silicon substrate, etc. The substrate 100 can also be N-type or P-type doped. In this specific embodiment, the substrate 100 is a P-type doped single-crystal silicon substrate.

[0022] The drain doped layer 103, the channel doped layer 104, and the source doped layer 105 are sequentially formed using ion implantation or diffusion processes. The drain doped layer 103 forms the drain of the transistor, the channel doped layer 104 forms the channel region of the transistor, and the source doped layer 105 forms the source of the transistor. The remaining portion of the substrate 100 beneath the drain doped layer 103 serves as the substrate 101.

[0023] In this specific embodiment, ion implantation is used to form each doped layer. The substrate 101 is P-type doped, and N-type doped drain layer 103 is formed using N-type ion implantation, P-type doped channel layer 104 is formed using P-type ion implantation, and N-type doped source region 105 is formed using N-type ion implantation. By adjusting the ion energy of each ion implantation process, corresponding doped layers are formed at different depths on the substrate 100. In particular, low-energy ion implantation is used for the source doped layer 105, so that the source doped layer 105 is distributed on the surface of the substrate 100, which facilitates the subsequent formation of memory cells connected to the source on the surface of the source doped layer 105.

[0024] In this specific embodiment, an isolation doped layer 102 is formed between the substrate 101 and the drain doped layer 103 before forming the drain doped layer 103. The isolation doped layer 102 has the same doping type as the drain doped layer 103, and the doping concentration of the isolation doped layer 102 is lower than that of the drain doped layer 103. The isolation doped layer 102 is used to prevent metal atoms of the bit lines subsequently formed in the substrate 100 from diffusing into the substrate 101.

[0025] After each doped layer is formed, a bit line is formed below the channel doped layer 104 and at least partially within the drain doped layer 103, and a first isolation structure is formed through the bit line, the bit line and the first isolation structure extending along a first direction.

[0026] In one specific embodiment, firstly, a plurality of first trenches extending along a first direction are formed in the substrate 100. The first trenches include bit line trenches located below the channel doped layer 104 and at least partially located in the drain doped layer 103, and first dividing trenches located above the bit line trenches and communicating with the bit line trenches; then, the bit lines are formed in the bit line trenches.

[0027] Please refer to Figures 2A to 10B This is a structural schematic diagram of the bit line formation process in this specific embodiment.

[0028] Please refer to Figure 2A and Figure 2B A bit line mask layer with openings is formed on the surface of the substrate 100. Figure 2A For along Figure 2B A cross-sectional view of the secant line AA'.

[0029] In this specific embodiment, the bit line mask layer includes a mask layer 201 and sidewall protective layers 202 covering both sides of the mask layer 201. The first direction is the x-direction.

[0030] Please refer to Figure 3 Using the bit line mask layer as a mask, the substrate 100 is etched using an anisotropic etching process to form a plurality of first dividing grooves 301 extending along the first direction.

[0031] The substrate 100 can be etched using a plasma etching process to form the first dividing trench 301. A bit line is then formed below the first dividing trench 301. Therefore, the bottom surface of the first dividing trench 301 is located within the drain doped layer 103, so that the subsequently formed bit line can form an electrical connection with the drain doped layer 103.

[0032] Please refer to Figure 4 A first protective layer 401 is formed on the side wall of the first dividing groove 301.

[0033] The method for forming the first protective layer 401 includes: forming a first protective material layer on the inner wall surface of the first dividing groove 301 and on the surfaces of the mask layer 201 and the sidewall protective layer 202; using an anisotropic etching process, etching the first protective material layer along a direction perpendicular to the surface of the substrate 100 to remove the first protective material layer located at the bottom of the first dividing groove 301, forming a first protective layer 401 covering the sidewall of the first dividing groove 301, exposing the substrate material at the bottom of the first dividing groove 301. The first protective layer 401 may also cover the sidewall of the sidewall protective layer 202 (not shown in the figure).

[0034] Please refer to Figure 5 The substrate 100 is etched along the bottom of the first dividing groove 301 using an etching process to form the bit line groove 501.

[0035] The etching process can be a wet etching process or a dry etching process. In this specific embodiment, a wet etching process is used to etch the substrate at the bottom of the first dividing trench 301. The etching solution used in the wet etching process can be a solution with high etching selectivity for silicon, such as HNA, TMAH, or NaOH. The formed bit line trench 501 can have arc-shaped, Σ-shaped, vertical, or inclined sidewalls. Figure 5 The morphology of the median groove 501 is for illustrative purposes only and does not represent the actual morphology of the median groove 501 in the actual process.

[0036] In other specific embodiments, an etching gas with high etching selectivity for silicon can be used to dry etch the substrate 100 to form the bit line trench 501. The etching gas molecules react with the substrate 100 material to achieve anisotropic etching. The etching gas can be a fluorine-containing gas such as XeF2, CF4, or CH2F2. To improve etching efficiency, the etching gas can also be plasma-enhanced to increase its energy, thereby increasing the reaction rate with the substrate 100 material.

[0037] The isotropic etching process can simultaneously etch the substrate at the bottom of the first dividing trench 301 in both the vertical and horizontal directions, resulting in a bit line trench 501 with a width greater than the width of the first dividing trench 301. The bit line trench 501 is located within the drain doped layer 103 and the isolation doped layer 102, and there is a certain distance between the top of the bit line trench 501 and the channel doped layer 104 to avoid leakage problems caused by the subsequent bit lines connecting with the channel doped layer 104.

[0038] Please refer to Figure 6 In the bit line slot 501 (please refer to) Figure 5 The bit line 601 is formed inside.

[0039] The bit line 601 can be made of a metallic material, such as tungsten, copper, or silver. Before filling the bit line material, a diffusion-blocking layer, such as a TiN layer or TaN layer, can be formed on the inner wall surface of the bit line groove 501 to prevent the metal atoms of the bit line 601 from diffusing outward. In this specific embodiment, a chemical vapor deposition process can be used to deposit the bit line material in the bit line groove 501 to form the bit line 601. During the deposition process, some bit line material may also be deposited in the first dividing groove 301, which can be removed by etching to remove the bit line material outside the bit line groove 501.

[0040] Please refer to Figure 7 Remove the first protective layer 401 (please refer to...) Figure 6 The etching continues along the first dividing groove 301 to deepen the first dividing groove, forming a first isolation groove 701 that extends through the bit line 601 to below the drain doped layer 103.

[0041] An anisotropic etching process is used to sequentially etch the bit line 601 and the doped layer located at the bottom of the bit line 601 into the substrate 101 to form the first isolation trench 701.

[0042] The first isolation trench 701 divides the substrate 100 into multiple active regions extending along the x-direction, and the bit line 601 is divided into two sub-bit lines within different active regions.

[0043] To prevent leakage between the active regions on both sides of the first isolation trench 701, the depth of the first isolation trench 701 must be sufficient to isolate the doped layers between the active regions. Since the isolation doped layer 102 is also formed below the drain doped layer 103, the bottom of the first isolation trench 701 needs to be located below the isolation doped layer 102. In other specific embodiments, if the isolation doped layer 102 is not formed, the bottom of the first isolation trench 701 only needs to be located below the drain doped layer 103.

[0044] Please refer to Figure 8 A first isolation structure 801 is formed within the first isolation groove 701.

[0045] The first isolation structure 801 is made of insulating dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. The insulating dielectric material can be filled into the first isolation trench 701 using processes such as chemical vapor deposition or plasma-enhanced chemical vapor deposition to form the first isolation structure 801.

[0046] Preferably, the material of the first isolation structure 801 is different from the material of the mask layer 201 to avoid over-etching of the first isolation structure 801 during the removal of the mask layer 201. In other specific embodiments, the material of the first isolation structure 801 can be the same as the material of the mask layer 201, and the height of the mask layer 201 can be relatively low. Even if the first isolation structure 801 is etched simultaneously during the removal of the mask layer 201, it is sufficient that the etched first isolation structure 801 is not lower than the surface of the substrate 100.

[0047] Please refer to Figure 9 The mask layer 201 is removed, and the substrate 100 is etched using the sidewall protective layer 202 as a mask to form a third isolation trench 901. The third isolation trench 901 extends along a first direction.

[0048] An anisotropic etching process is used to etch the substrate 100 into the base 101 to form the third isolation trench 901. The third isolation trench 901 divides a single active region between adjacent first isolation structures 801 into two sub-active regions extending along a first direction.

[0049] Please refer to Figure 10A and 10B A third isolation structure 1001 is formed within the third isolation groove 901.

[0050] A third isolation structure 1001 extending along a first direction and located on both sides of the bit line is formed in the substrate 100. The third isolation structure 1001 and the bit line 601 have a certain distance between them, or the sidewall of the third isolation structure 1001 is connected to the bit line 601. Figure 10B This is a top view diagram showing the formation of the first isolation structure 801 and the third isolation structure 1001. The substrate 100 is divided into multiple sub-active regions extending along a first direction by the isolation structure 801 and the third isolation structure 1001, and each sub-active region has a sub-position line 601a or a sub-position line 601b formed therein.

[0051] After forming word lines and dividing the substrate 100 into a plurality of sub-active regions extending along a first direction, a word line structure located within the channel doped layer 104 and a second isolation structure penetrating the word line structure are formed within the substrate 100, the word line structure and the second isolation structure extending along a second direction.

[0052] Please refer to Figure 11A and 11B A word line mask layer 1101 is formed on the substrate 100. The word line mask layer 1101 has an opening that exposes the area within the substrate 100 where word lines are to be formed. Figure 11B This is a top view diagram showing the formation of the word line mask layer 1101. Figure 11A For along Figure 11B A cross-sectional view of the secant line BB'. The opening of the word line mask layer 1101 extends along a second direction. In this specific embodiment, the second direction is the Y direction, which is perpendicular to the first direction X direction. In other specific embodiments, the second direction may intersect with the first direction, but is not perpendicular to it.

[0053] The word line mask layer 1101 can be made of photoresist, silicon nitride, or silicon oxide, and is different from the materials of the substrate 100, the first isolation structure 801, and the third isolation structure 1001, so as to reduce damage to the substrate 100, the first isolation structure 801, and the third isolation structure 1001 during the subsequent removal of the word line mask layer 1101.

[0054] Please refer to Figure 12 Using the word line mask layer 1101 as a mask, the substrate 100 is etched using an anisotropic etching process to form a plurality of second dividing grooves 1201 extending along the second direction.

[0055] The bottom of the second dividing trench 1201 is located within the channel doped layer 104, so as to facilitate the subsequent formation of word line trenches within the trench doped layer 104. Preferably, the bottom surface of the second dividing trench 1201 is located within the channel doped layer 104, close to the source doped layer 105. In one specific embodiment, the depth of the second dividing trench 1201 is approximately 1 / 3 of the depth of the bit line 601.

[0056] Please refer to Figure 13 The substrate 100 is etched along the bottom of the second dividing groove 1201 to form the word line groove 1301.

[0057] An etching process can be used to continue etching the substrate 100 along the bottom of the second dividing groove 1201 to form the word line groove 1301.

[0058] Before etching, a second protective layer can be formed on the sidewall of the second partition groove 1201 to protect the sidewall of the second partition groove 1201. The method for forming the second protective layer includes: forming a second protective material layer on the inner wall surface of the second partition groove and the surface of the word line mask layer; using an anisotropic etching process, etching the second protective material layer along a direction perpendicular to the surface of the substrate 100, removing the second protective material layer located at the bottom of the second partition groove 1201, forming a second protective layer covering the sidewall of the second partition groove 1201, exposing the substrate material at the bottom of the second partition groove 1201. The second protective layer can also cover the sidewall of the word line mask layer 1101.

[0059] The material of the second protective layer can be silicon oxide, silicon nitride, silicon oxynitride, etc., which is different from the material of the substrate 100. The material of the substrate 100 has a larger etching selectivity ratio with the material of the second protective layer in order to protect the sidewall of the second dividing trench 1201.

[0060] The etching process can be a wet etching process or a dry etching process. In this specific embodiment, a wet etching process is used to etch the substrate at the bottom of the second dividing trench 1201. The etching solution used in the wet etching process can be a solution with high etching selectivity for silicon, such as HNA, TMAH, or NaOH. The formed word line trench 1301 can have arc-shaped, Σ-shaped, vertical, or inclined sidewalls. Figure 13 The morphology of the character groove 1301 described herein is for illustrative purposes only and does not represent the actual morphology of the character groove 1301 in the actual manufacturing process.

[0061] In other specific embodiments, an etching gas with high etching selectivity for silicon can be used to dry etch the substrate 100 to form the word line groove 1301. The etching gas molecules react with the substrate 100 material to achieve anisotropic etching. The etching gas can be a fluorine-containing gas such as XeF2, CF4, or CH2F2. To improve etching efficiency, the etching gas can be plasma-enhanced to increase its energy, thereby increasing the reaction rate with the substrate 100 material.

[0062] The etching process can simultaneously etch the substrate at the bottom of the second dividing trench 1201 in both the vertical and horizontal directions, such that the width of the formed word line trench 1301 is greater than the width of the second dividing trench 1201. The word line trench 1301 is located within the channel doped layer 104, and a word line structure is subsequently formed within the channel doped layer 104 to serve as the gate structure of the access transistor.

[0063] Please refer to Figure 14A and 14B A doped region 1401 is formed between the bottom of the word line slot 1301 and the bit line 601. The doping concentration of the doped region 1401 is greater than that of the drain doped layer 103, and it has the same doping type as the drain doped layer 103. Then, a dielectric layer 1402 is filled in the second dividing slot 1201 and the word line slot 1301. Figure 14B This is a top view of the dielectric layer 1402 after it has been formed. Figure 14A For along Figure 14B A cross-sectional view of the secant line BB'.

[0064] Using an ion implantation process, with the word line mask layer 1101 as a mask, ion implantation is performed on the substrate at the bottom of the word line trench 1301 to form the doped region 1401. The doped region 1401 is connected to the bit line 601, forming an ohmic contact with the bit line 601, thereby reducing the contact resistance between the drain doped layer 103 and the bit line 601.

[0065] The dielectric layer 1402 is used to protect the sidewalls of the word line groove 1301 and the second dividing groove 1201 during subsequent processes such as removing the word line mask layer 1101. In this specific embodiment, the material of the dielectric layer 1402 is silicon oxide. In other specific embodiments, the material of the dielectric layer 1402 may also be other dielectric materials such as silicon nitride and silicon oxynitride.

[0066] In other specific embodiments, it is also possible to omit the doped region 1401 and reduce the contact resistance between the drain doped layer 103 and the bit line 601 by increasing the doping concentration of the drain doped layer 103.

[0067] Please refer to Figure 15 Remove the word line mask layer 1101; remove the dielectric layer 1402 to expose the word line trench 1301 and the second dividing groove 1201.

[0068] The word line mask layer 1101 can be removed by wet etching to expose the source doped layer 105, as well as the first isolation structure 801 and the third isolation structure 1001.

[0069] The dielectric layer 1402 is then removed using an isotropic etching process with high selectivity. In this specific embodiment, a wet etching process can be used to remove the dielectric layer 1402. Since the material of the dielectric layer 1402 is the same as that of the first isolation structure 801 and the third isolation structure 1001, a portion of the thickness of the first isolation structure 801 and the third isolation structure 1001 will also be removed during the removal of the dielectric layer 1402.

[0070] Please refer to Figure 16 A gate dielectric layer 1601 is formed to at least cover a portion of the inner wall of the word line slot 1301, and then word lines 1602 located on the surface of the gate dielectric layer 1601 are formed in the word line slot 1301.

[0071] The gate dielectric layer 1601 can be made of dielectric materials such as silicon oxide, silicon oxynitride, hafnium oxide, or zirconium oxide. The gate dielectric layer 1601 can be formed using processes such as thermal oxidation or chemical vapor deposition.

[0072] The word line 1602 can be made of polycrystalline silicon or a metallic material, such as tungsten, copper, or silver. The word line material can be deposited in the second dividing trench 1201 and the word line trench 1301 using chemical vapor deposition or physical vapor deposition processes. Then, the word line material located in the second dividing trench 1201 is removed to form the word line 1602 located in the word line trench 1301. The trench doped layer 104 between adjacent word lines 1602 serves as the channel region of the transistor.

[0073] In this specific embodiment, a gate dielectric layer 1601 and a word line 1602 are sequentially formed on the top of the first isolation structure 801 and the third isolation structure 1001, such that the word line 1602 surrounds the source doped layer 105.

[0074] Please refer to Figure 17 A patterned mask layer 1702 is formed on the surface of the substrate 100 to expose the bottom of the second dividing groove 1201. The word line 1602 and the substrate 100 are etched to deepen the bottom of the second dividing groove and form a second isolation groove 1701 that extends through the word line 1602 to the surface of the bit line 601.

[0075] The second isolation trench 1701 is formed by anisotropic etching process.

[0076] Please refer to Figures 18A to 18E A second isolation structure 1801 is formed in the second isolation groove 1701, and then the patterned mask layer 1702 is removed.

[0077] The second isolation structure 1801 extends along the second direction, dividing each sub-active region along the second direction to form multiple arrayed access transistors 1800. The material of the second isolation structure 1801 can be insulating dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride. While filling the second isolation trench 1701 with dielectric material to form the second isolation structure, at the front... Figure 16 During the removal of the dielectric layer 1402, insulating dielectric material is also filled above the word lines 1602 formed in the recesses after the first isolation structure 801 and the third isolation structure 1001 are etched, and planarization processes such as chemical mechanical polishing are used to make the insulating dielectric material flush with the surface of the source doped layer 105.

[0078] The first isolation structure 801, the second isolation structure 1801 and the third isolation structure 1001 divide the substrate 100 into a plurality of arrayed access transistors 1800.

[0079] A cross-sectional view of the access transistor 1800 along the BB' direction is shown below. Figure 18A As shown in the schematic diagram of the cross-section along CC', Figure 18C As shown in the schematic diagram of the cross-section along DD', Figure 18D As shown. A schematic cross-sectional view along the AA' direction is shown below. Figure 18E As shown.

[0080] Subsequently, access cells, such as capacitors, can be formed on the source doped layer 105 of each access transistor 1800, and the bit line 601 can be led out by forming contact vias in the substrate to connect the bit line 601.

[0081] The above method forms a transistor with a ring gate structure in the substrate. The source, channel region and drain of the transistor are vertically arranged in the substrate. The word line is arranged around the channel region and the bit line is located below the drain doped layer. This can reduce the size of the access transistor, thereby increasing the storage density of the memory.

[0082] A specific embodiment of the present invention also provides a memory.

[0083] Please refer to all factors. Figure 10A , Figure 18A , Figure 18B , Figure 18C as well as Figure 18D ,in Figure 18A This is a top view of the memory. Figure 10A For along Figure 18A A cross-sectional view of the secant AA'; Figure 18B For along Figure 18A A cross-sectional view of the secant line BB'; Figure 18C For along Figure 18A A cross-sectional view of the secant CC'; Figure 18D For along Figure 18A A cross-sectional view of the secant line DD'.

[0084] The memory includes a substrate 100, within which a drain doped layer 103, a channel doped layer 104, and a source doped layer 105 are formed, sequentially stacked from the interior of the substrate 100 to its surface. The remaining portion of the substrate 100 below the drain doped layer 103 serves as a base 101. In one specific embodiment, the base 101 is P-type doped, the drain doped layer 103 is N-type doped, the channel doped layer 104 is P-type doped, and the source doped layer 105 is N-type doped.

[0085] In this specific embodiment, an isolation doped layer 102 is further formed between the drain doped layer 103 and the substrate 101. The isolation doped layer 102 and the drain doped layer 103 have the same doping type, and the doping concentration of the isolation doped layer 102 is less than that of the drain doped layer 103. The isolation doped layer 102 is used to prevent metal atoms of the subsequent bit line 601 from diffusing into the substrate 101.

[0086] The bit line 601 of the memory is located below the channel doped layer 104 and at least partially within the drain doped layer 103, and the bit line 601 extends along a first direction. The bit line is connected to the drain doped layer 103. A portion of the bit line 601 is also located within the isolation doped layer 102.

[0087] The memory also includes a first isolation structure 801 that extends through the bit line 601, the first isolation structure 801 extending along a first direction.

[0088] The memory also includes a third isolation structure 1001 located within the substrate 100 and extending along a first direction on both sides of the bit line 601. The third isolation structure 1001 and the first isolation structure 801 divide the substrate 100 into a plurality of sub-active regions extending along the first direction.

[0089] The word line structure of the memory is located within the substrate 100 and within the channel doped layer 104, with a portion of the channel doped layer 104 serving as a channel region between adjacent word line structures. A second isolation structure 1402 penetrates the word line structure, and both the word line structure and the second isolation structure 1402 extend along a second direction. In this specific embodiment, the second direction is perpendicular to the first direction. The word line structure includes a gate dielectric layer 1601 and word lines 1602.

[0090] The semiconductor structure within the area surrounded by the third isolation structure 1001, the second isolation structure 1402, and the first isolation structure 801 is a memory access transistor 1800.

[0091] In this specific embodiment, a doped region 1401 is further included, located between the bottom of the word line structure and the bit line 601. The doping concentration of the doped region 1401 is greater than that of the drain doped layer 103, and it has the same doping type as the drain doped layer 103. The doped region 1401 is connected to the bit line 601, forming an ohmic contact with the bit line 601, thereby reducing the contact resistance between the drain doped layer 103 and the bit line 601.

[0092] The memory also includes memory cells, such as capacitors, located on the surface of the source doped layer 105 of each access transistor 1800.

[0093] The access transistor 1800 of the aforementioned memory has a gate-around structure. Compared with transistors of other structures, it can effectively reduce the size of the access transistor with the same channel length, thereby increasing the storage density of the memory.

[0094] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a memory, characterized in that, include: Provide substrate; A drain doped layer, a channel doped layer, and a source doped layer are formed in the substrate, stacked sequentially from the interior of the substrate to the surface of the substrate. A bit line is formed below the channel doped layer and at least partially within the drain doped layer, and a first isolation structure extends through the bit line, the bit line and the first isolation structure extending along a first direction; wherein the step of forming the bit line includes: forming a first trench in the substrate, the first trench including a bit line trench located below the channel doped layer and at least partially within the drain doped layer, a first dividing trench located above the bit line trench and communicating with the bit line trench, and the width of the bit line trench being greater than the width of the first dividing trench; forming the bit line within the bit line trench; A third isolation structure extending along a first direction and located on both sides of the bit line is formed within the substrate; A word line structure is formed within the channel doped layer in the substrate, and a second isolation structure extends through the word line structure. The word line structure and the second isolation structure extend along a second direction. The step of forming the word line structure includes: forming a second trench in the substrate, the second trench including a word line slot located within the channel doped layer and a second dividing slot located above and communicating with the word line slot, wherein the width of the word line slot is greater than the width of the second dividing slot; and forming the word line within the word line slot.

2. The method for forming a memory according to claim 1, characterized in that, A plurality of first trenches extending along a first direction are formed in the substrate; The method for forming the first isolation structure includes: deepening the first dividing trench to form a first isolation trench that extends through the bit line to below the drain doped layer, and forming a first isolation structure within the first isolation trench.

3. The method for forming a memory according to claim 2, characterized in that, The method for forming the first trench includes: etching the substrate using an anisotropic etching process to form a plurality of first dividing trenches extending along a first direction; forming a first protective layer on the sidewall of the first dividing trench; and etching the substrate along the bottom of the first dividing trench using an isotropic etching process to form the bit line trench.

4. The method for forming a memory according to claim 1, characterized in that, A plurality of second trenches extending along a second direction are formed in the substrate; The method of forming the second isolation structure includes: forming a gate dielectric layer that at least covers the inner wall of a portion of the word line trench and a word line located on the surface of the gate dielectric layer within the word line trench; The bottom of the second dividing groove is deepened to form a second isolation groove that penetrates the character line, and a second isolation structure is formed within the second isolation groove.

5. The method for forming a memory according to claim 4, characterized in that, The method for forming the second trench includes: etching the substrate using an anisotropic etching process to form a plurality of second dividing trenches extending along a second direction; forming a second protective layer on the sidewall of the second dividing trench; and etching the substrate along the bottom of the second dividing trench using an isotropic etching process to form the word line trench.

6. The method for forming a memory according to claim 1, characterized in that, Also includes: An isolation doped layer is formed in the substrate below the drain doped layer; Some of the bit lines are located within the isolation doped layer.

7. The method for forming a memory according to claim 1, characterized in that, Also includes: A doped region is formed between the bottom of the word line structure and the bit line. The doping concentration of the doped region is greater than that of the drain doped layer, and the doping type is the same as that of the drain doped layer.

8. A memory, characterized in that, include: A substrate having a drain doped layer, a channel doped layer, and a source doped layer stacked sequentially from the interior of the substrate to the surface of the substrate. A bit line located below the channel doped layer and at least partially within the drain doped layer, and a first isolation structure extending through the bit line, the bit line and the first isolation structure extending along a first direction; a first trench formed in the substrate, the first trench including a bit line trench located below the channel doped layer and at least partially within the drain doped layer, and a first dividing trench located above the bit line trench and communicating with the bit line trench, the width of the bit line trench being greater than the width of the first dividing trench; a bit line formed within the bit line trench; A third isolation structure located on both sides of the bit line, extending along a first direction within the substrate; A word line structure located within the substrate and within the channel doped layer, and a second isolation structure extending through the word line structure, the word line structure and the second isolation structure extending along a second direction; a second trench formed within the substrate, the second trench including a word line groove located within the channel doped layer and a second dividing groove located above the word line trench and communicating with the word line trench, the width of the word line groove being greater than the width of the second dividing groove; a word line formed within the word line groove.

9. The memory according to claim 8, characterized in that, Also includes: An isolation doped layer located below the drain doped layer; Some of the bit lines are located within the isolation doped layer.

10. The memory according to claim 8, characterized in that, Also includes: The doped region located between the bottom of the word line structure and the bit line has a doping concentration greater than that of the drain doped layer and has the same doping type as the drain doped layer.

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