Controlling storage access for merge operations

Abstract

Storage access for the merge operation is minimized. Multiple records from multiple input lists are merged. The merge includes: determining that one of the input lists has become empty; and, based on this determination, checking the controls dedicated to that input list. These controls determine how to proceed, such as whether to end the merge or continue.

Description

Technical Field

[0001] One or more aspects generally involve facilitating processing within a computing environment, and in particular, facilitating merged processing. Background Technology

[0002] One aspect of computer processing that employs merging techniques is database processing. A database is an organized collection of data, typically divided into data records. Sorting and merging these data records is a common database operation performed by software applications.

[0003] Databases may require a large amount of storage, such as one trillion bytes or more. Therefore, when merging and sorting collections of data records, a significant portion of the time is spent transferring data between memory and processor storage devices. Summary of the Invention

[0004] This invention overcomes the shortcomings of the prior art and provides additional advantages by providing a computer program product for facilitating processing in a computing environment. The computer program product includes a computer-readable storage medium that can be read by a processor and stores instructions for performing a method. The method includes merging multiple records of multiple input lists by a processor. The merging includes: determining that one of the multiple input lists has become empty; and based on the determination that the input list has become empty, checking a control dedicated to the input lists, the control being used to determine how to proceed. Based on this control, processing is performed.

[0005] Using one or more controls to guide the behavior of operations (e.g., merge operations) when a specific input list becomes empty reduces data access, reduces the amount of data transferred, improves the performance of operations, and improves the overall performance within the computing environment.

[0006] In one example, the execution process includes ending the merge based on the control being a value, and in another example, the execution process includes continuing the merge based on the control being a different value.

[0007] In one embodiment, the control includes a plurality of indicators, and one of the plurality of indicators is assigned to a selected input list in the plurality of input lists, and another of the plurality of indicators is assigned to a different input list in the plurality of input lists.

[0008] Furthermore, in one embodiment, a determination is made regarding whether to store the indication that the input list has become empty in the selected location. This determination is based at least in part on the control. Based on the determination specifying that the indication should be stored, the indication of the input list is stored in the selected location.

[0009] As an example, determining whether to store an indication includes checking another control. The other control, set to a selected value, indicates that the indication will be stored in the selected location. This other control is set in part based on the selected control.

[0010] In one embodiment, setting another control includes checking whether the control is a defined value and determining whether a specific condition code has been set, wherein based on the control being a defined value and the specific condition code being set, the other control is set to a selection value.

[0011] As an example, the control is specified via instructions such as sorting instructions. In one example, the sorting instruction is defined based on the selected instruction set architecture. In one embodiment, the instruction specifies the location of a parameter block in memory, which includes the control.

[0012] This document also describes and claims protection for computer-implemented methods and systems relating to one or more aspects. Furthermore, this document also describes and claims protection for services relating to one or more aspects.

[0013] Other features and advantages are achieved through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered part of the claimed aspects. Attached Figure Description

[0014] The claims at the end of the specification specifically point out and clearly claim protection for one or more aspects as examples. The above-mentioned objects, features, and advantages of one or more aspects will be apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0015] Figure 1A An example of a computing environment that combines and uses one or more aspects of the present invention is shown;

[0016] Figure 1B This illustrates one or more aspects of the invention. Figure 1A Further details about the processor;

[0017] Figure 2 Another example of a computing environment that includes and uses one or more aspects of the present invention is shown;

[0018] Figure 3A This illustrates a format for a list sorting instruction according to one aspect of the invention;

[0019] Figure 3B An example of a field of an implicit register (general register 0) used by a list sorting instruction according to one aspect of the invention is shown;

[0020] Figure 3C An example of functional code for a list sorting instruction according to one aspect of the invention is shown;

[0021] Figure 3D An example of a field of an implicit register (general register 1) used by a list sorting instruction according to one aspect of the invention is shown;

[0022] Figure 3E An example is described, illustrating the contents of register R1 specified by a list sorting instruction according to one aspect of the invention;

[0023] Figure 3F An example is shown of the contents of register R1+1 used by a list sorting instruction according to one aspect of the invention;

[0024] Figure 3G An example is shown of the contents of register R2 specified by a list sorting instruction according to one aspect of the invention;

[0025] Figure 3H An example is shown of the contents of register R2+1 used by a list sorting instruction according to one aspect of the invention;

[0026] Figure 3I An example is shown of the contents of a parameter block used by the SORTL-QAF function of a list sorting instruction according to one aspect of the invention;

[0027] Figure 3J An example of a fixed-length record format used by a list sorting instruction according to one aspect of the invention is shown;

[0028] Figure 3K An example is shown of the contents of a parameter block used by the SORTL-SFLR function of a list sorting instruction according to one aspect of the invention;

[0029] Figures 4A-4B Examples of SORTL-SFLR according to one or more aspects of the present invention are shown;

[0030] Figure 5A An example illustrating the summarization of input values ​​for a SORTL-SFLR function according to one aspect of the invention;

[0031] Figure 5B An example illustrating a limitation on the modification of the input list address and length fields of the SORTL-SFLR function according to one aspect of the invention;

[0032] Figure 6AAn example of the first operand position / first operand before performing a SORTL with the merge mode indication set to zero, according to one aspect of the invention, is shown;

[0033] Figure 6B An example of the first operand position / first operand after performing a SORTL with the merge mode indication set to zero, according to one aspect of the invention, is shown;

[0034] Figure 6C An example of the second operand position / second operand before performing a SORTL with the merge mode indication set to zero, according to one aspect of the invention, is shown;

[0035] Figure 6D An example of the second operand position / second operand after performing a SORTL with the merge mode indication set to zero, according to one aspect of the invention, is shown;

[0036] Figure 7A An example of the first operand position / first operand before performing a SORTL with the merge mode indication set to 1 is shown according to one aspect of the invention;

[0037] Figure 7B An example of the first operand position / first operand after performing a SORTL with the merge mode indication set to 1 is shown according to one aspect of the invention;

[0038] Figure 8 An example of certain fields of a parameter block used according to one aspect of the invention is shown;

[0039] Figure 9 An example of a variable-length record format used by a list sorting instruction according to one aspect of the invention is shown;

[0040] Figure 10 An example of a process associated with the control of selection according to one aspect of the invention is shown;

[0041] Figure 11A-11B An example illustrating a process facilitated within a computing environment according to one aspect of the invention is shown;

[0042] Figure 12A Another example of a computing environment that includes and uses one or more aspects of the present invention is shown;

[0043] Figure 12B Show Figure 12A Further details about the memory;

[0044] Figure 13 This illustrates an embodiment of a cloud computing environment; and

[0045] Figure 14 An example of an abstract model layer is shown. Detailed Implementation

[0046] According to one aspect of the invention, a capability is provided to facilitate processing within a computing environment. As an example, a single instruction (e.g., a single architectural hardware machine instruction at a hardware / software interface) is provided to perform an operation to sort and / or merge data records, such as one or more input lists. This instruction, for example, executes on a general-purpose processor.

[0047] In one or more aspects, the instructions include one or more controls for minimizing the number of times data is transferred between memory and processor (e.g., central processing unit) storage devices during the merge operation. For example, minimizing the number of data transfers (e.g., records to be merged); minimizing data accesses. This improves the performance of the merge operation, as well as the overall system performance.

[0048] As an example, one or more controls are provided to guide the behavior of an operation when a particular input list becomes empty during the operation. Based on the input list becoming empty (e.g., the length of the input list becomes zero), the operation terminates or continues processing as specified by the appropriate control. In one example, controls and corresponding behaviors are provided for a single selected input list, independent of controls for other input lists.

[0049] In one example, when comparing keys of equal values ​​(of merged records), keys from the input list with independent null controls are selected as following other keys from other input lists with the same values, according to sort order.

[0050] When control specifies that the operation will end upon encountering an empty input list, and when an empty input list is encountered during the operation, the execution of the instruction terminates with a specific set of condition codes used to notify the program (e.g., the program issuing the instruction) of the condition. After the operation ends due to said condition, the program may modify one or more input list specifications before resuming the operation.

[0051] As an example, the instruction can be re-executed to restore the operation, and control applies to sorting in ascending and descending order.

[0052] See Figure 1AThe description includes an embodiment of a computing environment that incorporates and uses one or more aspects of the present invention. The computing environment 100 includes, for example, a processor 102 (e.g., a central processing unit), a memory 104 (e.g., main memory; also known as system memory, main storage device, central storage device, storage device), and one or more input / output (I / O) devices and / or interfaces 106 coupled to each other via, for example, one or more buses 108 and / or other connections.

[0053] In one example, processor 102 is based on International Business Machines Corporation (IBMC) of Armonk, New York. Hardware architecture, and such as This is part of a server, such as a server also provided and implemented by IBM using the z / Architecture hardware architecture. One embodiment of the z / Architecture hardware architecture is described in the publication entitled “z / Architecture Principles of Operation” (IBM Publication No. SA22-7832-11, 12th Edition, September 2017), which is hereby incorporated herein by reference in its entirety. However, the z / Architecture hardware architecture is merely one example architecture; other architectures and / or other types of computing environments may include and / or utilize one or more aspects of the invention. In one example, the processor executes an operating system, such as one also provided by IBM. operating system.

[0054] Processor 102 includes multiple functional components for executing instructions. For example... Figure 1B As depicted herein, these functional components include, for example, an instruction fetching component 120 for fetching instructions to be executed; an instruction decoding unit 122 for decoding the fetched instructions and obtaining operands of the decoded instructions; an instruction execution component 124 for executing the decoded instructions; a memory access component 126 for accessing memory as necessary for instruction execution; and a write-back component 130 for providing the results of the executed instructions. According to one or more aspects of the invention, one or more of these components may include at least a portion of one or more other components that provide sorting / merging processing (or other processing that may be used with one or more aspects of the invention) or have access to one or more other components. One or more other components include, for example, a sorting / merging component (or other component) 136. The functionality provided by component 136 is described in further detail below.

[0055] See Figure 2To describe another example of a computing environment that incorporates and uses one or more aspects of the present invention. In one example, the computing environment is based on the z / Architecture hardware architecture; however, the computing environment may be based on other architectures provided by IBM or other companies.

[0056] Reference Figure 2 In one example, the computing environment includes a central electronic complex (CEC) 200. The CEC 200 includes multiple components, such as memory 202 (also known as system memory, main memory, main storage device, central storage device, storage device) coupled to one or more processors (also known as central processing units (CPUs)) 204 and input / output subsystems 206.

[0057] Memory 202 includes, for example, one or more logical partitions 208, a hypervisor 210 that manages the logical partitions, and processor firmware 212. An example of hypervisor 210 is Processor Resource / System Manager (PR / SM) provided by International Business Machines Corporation of Armonk, New York. TM The firmware, as used herein, includes, for example, microcode of the processor. It includes, for example, hardware-level instructions and / or data structures used in implementations of higher-level machine code. In one embodiment, it includes, for example, proprietary code typically delivered as microcode, which includes trusted software or underlying hardware-specific microcode and controls operating system access to the system hardware.

[0058] Each logical partition 208 can function as a separate system. That is, each logical partition can be reset independently, running a guest operating system 220 such as z / OS or another operating system, and operated by different programs 222. The operating system or application running in the logical partition appears to have access to the complete system, but in reality, only a portion of it is available.

[0059] Memory 202 is coupled to processor (e.g., CPUs) 204, which is a physical processor resource that can be allocated to a logical partition. For example, logical partition 208 includes one or more logical processors, each representing all or shared physical processor resources 204 that can be dynamically allocated to the logical partition.

[0060] Furthermore, the memory 202 is coupled to the I / O subsystem 206. The I / O subsystem 206 may be part of or separate from the central electronic complex. It directs the flow of information between the main memory 202 and the input / output control unit 230, as well as the input / output (I / O) devices 240 coupled to the central electronic complex.

[0061] Many types of I / O devices can be used. One specific type is a data storage device 250. The data storage device 250 can store one or more programs 252, one or more computer-readable program instructions 254, and / or data, etc. The computer-readable program instructions can be configured to perform the functions of embodiments of various aspects of the present invention.

[0062] In one example, processor 204 includes a sorting / merging component (or other component) 260 for performing one or more sorting and / or merging operations (or other operations that may utilize one or more aspects of the invention). In different examples, one or more components may be present to perform these tasks. Many variations are possible.

[0063] The central electronic complex 200 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, it may include and / or be coupled to non-removable non-volatile magnetic media (commonly referred to as a "hard disk drive"), disk drives for reading from and writing to a removable non-volatile disk (e.g., a "floppy disk"), and / or optical disc drives for reading from or writing to a removable non-volatile optical disc (e.g., a CD-ROM, DVD-ROM, or other optical media). It should be understood that other hardware and / or software components may be used in conjunction with the central electronic complex 200. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archiving storage systems.

[0064] Furthermore, the Central Electronic Complex 200 can operate with many other general-purpose or special-purpose computing system environments or configurations. Examples of known computing systems, environments, and / or configurations that can be applied to the Central Electronic Complex 200 include, but are not limited to: personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the aforementioned systems or devices, etc.

[0065] While this document describes different examples of computing environments, one or more aspects of the invention can be used with many types of environments. The computing environments provided herein are merely examples. Furthermore, although one or more aspects of the invention are described with reference to sorting instructions, these aspects can be applied to other processes and / or instructions that perform merging. The sorting instruction is only one example.

[0066] According to one aspect of the invention, a processor (e.g., processor 102 or 204) employs an enhanced sorting facility that provides a mechanism for sorting multiple unsorted lists of input data into one or more sorted lists of output data. In one example, the enhanced sorting facility is installed in the system when a facility indicator is set to, for example, 1. As a specific example of a z / Architecture hardware architecture, when the enhanced sorting facility is installed in z / Architecture architecture mode, facility bit 150 is set to, for example, 1. In one embodiment, the facility also provides a mechanism for merging multiple sorted lists of input data into a single sorted list of output data. The facility includes, for example, list sorting instructions, embodiments of which are described below.

[0067] See Figure 3A-3K An embodiment describing the details associated with a list sorting instruction. In one example, the instruction executes on a general-purpose processor (e.g., processor 102 or 204). In this description, a specific location, a specific field, and / or a specific size of a field (e.g., a specific byte and / or bit) is indicated. However, other locations, fields, and / or sizes may be provided. Furthermore, while specifying that a bit is set to a specific value (e.g., 1 or 0) is given, this is merely an example. In other examples, the bit may be set to a different value, such as the opposite value or another value. Many variations are possible.

[0068] See Figure 3A In one example, the format of the List Sort (SORTL) instruction 300 is an RRE format representing registers and register operations with extended opcodes. As an example, the instruction includes an opcode field 302 (e.g., bits 0-15) with opcodes indicating sorting and / or merging operations, a first register field (R1) 304 (e.g., bits 24-27) specifying a first pair of general-purpose registers, and a second register field (R2) 306 (e.g., bits 28-31) specifying a second pair of general-purpose registers. The contents of the register specified by the R1 field 304 are referred to as the first operand (in memory), and the contents of the register specified by the R2 field 306 are referred to as the second operand (in memory). The contents of R1+1 specify the length of the first operand, and the contents of R2+1 specify the length of the second operand. In one example, bits 16-23 of the instruction are reserved and should contain zeros; otherwise, the program may operate incompatiblely in the future. As used herein, the program is the program that issues the list sort instruction. It can be a user program, an operating system, or another type of program.

[0069] In one embodiment, instruction execution includes the use of one or more implicit general-purpose registers (i.e., registers not explicitly specified by the instruction). For example, general-purpose registers 0 and 1 are used to execute list sorting instructions, as described herein. In one example, general-purpose register 0 is used to specify whether a merge will be performed and to specify the sorting function to be performed by the instruction, and general-purpose register 1 is used to provide the location of the parameter block used by the instruction. In another example, instead of using general-purpose register 0 to specify whether a merge will be performed; instead, the merge is set / not set by the machine (e.g., the processor) and cannot be changed by a mode indicator. Other variations are possible.

[0070] As an example, see Figure 3B General-purpose register 0 (308) contains a merge mode field 310 (described below) and a function code field 312. In one particular example, bits 57-63 of general-purpose register 0 contain the function code; however, in other embodiments, other bits may be used to contain the function code. In one example, a specified exception is identified when bits 57-63 of general-purpose register 0 specify an unassigned or uninstalled function code.

[0071] Example code for the list sorting instruction is in Figure 3C The diagram shows, for example, function code 0 (313) indicating the SORTL-QAF (Query Available) function; function code 1 (315) indicating the SORTL-SFLR (Fixed Length Record Sorting) function; and function code 2 (317) indicating the SORTL-SVLR (Variable Length Record Sorting) function. Each code uses a parameter block, and in one example, the size of the parameter block depends on the function. For example, for the SORTL-QAF function, the parameter block is 32 bytes; for SORTL-SFLR and SORTL-SVLR, the parameter block is 576 + 16 x N. IS , where N IS The number of input lists is specified by the interface size. No additional function codes are assigned in this example. Although example functions and function codes are described, other functions and / or function codes may be used.

[0072] As previously indicated, General-Purpose Register 0 also contains a merge mode field 310. In one example, bit 56 of General-Purpose Register 0 specifies the operating mode (merge mode) applied to functions such as SORTL-SFLR and SORLT-SVLR. In one example, bit 56 of General-Purpose Register 0 is ignored when the specified function is SORTL-QAF. Further, in one example, bits 0-55 of General-Purpose Register 0 are ignored.

[0073] See Figure 3DFurther details are provided regarding another implicit register (general-purpose register 1) used by the list sorting instruction. The contents of general-purpose register 1 (314) specify, for example, the logical address 316 of the leftmost byte of the parameter block in the memory device. In one example, the parameter block is specified on a double-word boundary; otherwise, a specification exception is identified. Further details regarding the parameter block are described below.

[0074] For specified functions (e.g., SORTL-QAF, SORTL-SFLR, SORTL-SVLR), the contents of general-purpose registers 0 and 1 are not modified. Furthermore, in one example, R1 field 304 specifies an even-odd pair of general-purpose registers. To specify an even register, do not specify general-purpose register 0; otherwise, a specification exception is detected. When the specified function is SORTL-SFLR or SORTL-SVLR, such as... Figure 3E-3F As shown, the content of general-purpose register R1 (318) specifies, for example, the logical address (320) of the leftmost byte of the first operand, while the content of general-purpose register R1+1 (322) specifies the length (324) of the first operand, for example, the number of bytes. When the specified function is SORTL-SFLR or SORTL-SVLR, for example, the first operand must be specified on a double-word boundary; otherwise, a specification exception is identified. Data in record form is selected from the set of the input list and stored at the location of the first operand (e.g., starting at the address specified by R1). When the SORTL-QAF function is specified, the contents of general-purpose registers R1 and R1+1 are ignored.

[0075] Furthermore, for specified functions (e.g., SORTL-QAF, SORTL-SFLR, SORTL-SVLR), in one example, field R2 306 specifies an even-odd pair of general-purpose registers. To specify an even register, do not specify general-purpose register 0; otherwise, a specification exception is identified. When the specified function is SORTL-SFLR or SORTL-SVLR, and the merge mode (MM) is zero, such as... Figure 3G-3H As shown, the content of general-purpose register R2 (326) specifies, for example, the logical address (328) of the leftmost byte of the second operand, and the content of general-purpose register R2+1 (330) specifies the length (332) of the second operand, for example, the number of bytes. In one example, when the specified function is SORTL-SFLR or SORTL-SVLR and the merge mode (MM) is zero, the second operand is specified on a double-word boundary; otherwise, a specification exception is identified. When MM is zero, the starting address and length of each output list (called the output list description (OLD)) are stored at the second operand location (e.g., starting at the address specified by R2). When the SORTL-QAF function is specified or MM is 1, the contents of general-purpose registers R2 and R2+1 are ignored.

[0076] During execution, in one embodiment, the function specified by the function code in general-purpose register 0 is executed. In one embodiment, as part of the operation when the specified function is SORTL-SFLR or SORTL-SVLR, the following occurs:

[0077] Increment the address in general-purpose register R1 by the number of bytes stored at the first operand location, and decrease the length in general-purpose register R1+1 by the same number.

[0078] When MM is 0, the address in general-purpose register R2 is incremented by the number of bytes stored at the second operand position, and the length in general-purpose register R2+1 is decremented by the same number.

[0079] In one example, the formation and updating of the address and length depend on the addressing mode.

[0080] In 24-bit addressing mode, in one embodiment, the following applies:

[0081] Bit positions 40-63 of general-purpose register 1, the contents of R1 and R2 constitute the addresses of the parameter block, the first operand, and the second operand, respectively, and the contents of bits 0-39 are ignored.

[0082] Bits 40-63 of the updated first and second operand addresses replace the corresponding bits in general-purpose registers R1 and R2, respectively. The carry at bit position 40 of the updated address is ignored, and bits 32-39 of general-purpose registers R1 and R2 are set to 0. Bit positions 0-31 of general-purpose registers R1 and R2 remain unchanged.

[0083] The contents of bits 32-63 in general-purpose registers R1+1 and R2+1 form 32-bit unsigned binary integers that specify the number of bytes in the first and second operands, respectively. The contents of bits 0-31 in general-purpose registers R1+1 and R2+1 are ignored.

[0084] The updated bits 32-63 of the first and second operand lengths replace the corresponding bits in general-purpose registers R1+1 and R2+1, respectively. The contents of bits 0 to 31 in general-purpose registers R1+1 and R2+1 remain unchanged.

[0085] In 31-bit addressing mode, in one embodiment, the following applies:

[0086] Bit positions 33-63 of general-purpose register 1, the contents of R1 and R2 constitute the addresses of the parameter block, the first operand, and the second operand, respectively, and the contents of bits 0-32 are ignored.

[0087] Bits 33-63 of the updated first and second operand addresses replace the corresponding bits in general-purpose registers R1 and R2, respectively. The carry at bit 33 of the updated address is ignored, and bit position 32 of general-purpose registers R1 and R2 is set to 0. Bit positions 0-31 of general-purpose registers R1 and R2 remain unchanged.

[0088] The contents of bits 32-63 in general-purpose registers R1+1 and R2+1 form 32-bit unsigned binary integers specifying the number of bytes in the first and second operands, respectively. The contents of bits 0-31 in general-purpose registers R1+1 and R2+1 are ignored.

[0089] The updated bits 32-63 of the first and second operand lengths replace the corresponding bits in general-purpose registers R1+1 and R2+1, respectively. The contents of bits 0-31 in general-purpose registers R1+1 and R2+1 remain unchanged.

[0090] In 64-bit addressing mode, in one embodiment, the following applies:

[0091] Bit positions 0-63 of general-purpose register 1, and the contents of R1 and R2 constitute the addresses of the parameter block, the first operand, and the second operand, respectively.

[0092] The bits 0-63 of the updated first and second operand addresses replace the corresponding bits in general-purpose registers R1 and R2, respectively. Carry-over bits at the updated address bits are ignored.

[0093] The bits 0-63 of general-purpose registers R1+1 and R2+1 form 64-bit unsigned binary integers that specify the number of bytes in the first operand and the second operand, respectively.

[0094] The updated first operand and the second operand length bits 0-63 replace the corresponding bits in general-purpose registers R1+1 and R2+1, respectively.

[0095] In register access mode, registers 1, R1, and R2 specify the address space containing the parameter block, the first operand, and the second operand, respectively.

[0096] Further details regarding the different functions are described below:

[0097] Function code 0: SORTL-QAF (Query Available Functions)

[0098] The SORTL-QAF (query) function provides a mechanism to indicate the availability of all installed functions, the format of the installed parameter blocks, and the available interface size. Interface size is the number of input lists available to the program. The parameter block size of the SORT-SFLR and SORT-SVLR functions is proportional to the interface size specified by the program.

[0099] refer to Figure 3I An example format for a parameter block describing a SORTL-QAF function. In one example, parameter block 340 for a SORTL-QAF function (e.g., function code 0) includes an installed function vector 342, an installed interface size vector 344, and an installed parameter block format vector 346. In a particular example, these vectors are stored in bytes 0-15, byte 16, and bytes 24-25 of the parameter block, respectively. Each of these vectors is further described below.

[0100] As an example, bits 0-127 of the installed function vector 342 correspond to function codes 0-127 of the list sorting instruction. If a bit is, for example, 1, the corresponding function is installed; otherwise, the function is not installed.

[0101] Furthermore, in one example, bits 0-7 of the installed interface size vector 344 indicate the size of the interface available to the program. The interface size is the number of input lists specified by the program used for the SORT-SFLR and SORTL-SVLR functions. In one example, bits 0-7 of the installed interface size vector 344 correspond to the following interface sizes: bits 0, 1, and 5-7 are reserved; bits 2–32 input lists; bits 3–64 input lists; and bits 4–128 input lists. Other examples are also possible.

[0102] When a bit in the installed interface size vector 344 is, for example, 1, the corresponding interface size is available to the program. One or more bits can be stored as 1. For example, the binary value 00101000 indicates that interface sizes for 32 and 128 input lists are available. In one example, bits 0-1 and 5-7 are reserved and stored as 0. Further, in one example, when an enhanced sorting facility is installed, an interface size for 32 input lists is available. Therefore, bit 2 is stored as 1. Other examples are also possible.

[0103] In addition to what has been described above, in one example, bits 0-15 of the installed parameter block format vector 346 correspond to parameter block formats 0 to 15, respectively. When a bit is 1, the corresponding parameter block format is installed; otherwise, the parameter block format is not installed. In one example, 0 is stored in reserved bytes 17-23 and 26-31 of the parameter block.

[0104] The SORT-QAF function ignores the contents of general-purpose registers R1, R2, R1+1, and R2+1.

[0105] Where applicable, identify PER (Program Event Recording) storage change events for parameter blocks. Where applicable, identify PER zero-address detection events for parameter blocks.

[0106] Condition code 0 is set when the SORTL-QAF function completes execution; in one example, condition codes 1, 2, and 3 are not applicable to the query function.

[0107] Function code 1: SORTL-SFLR (Sort Fixed-Length Records)

[0108] In one example, the input list set is sorted and stored as the output list set at the first operand position. Each list is a set of records, see [reference]. Figure 3J Each record 350 includes a key 352 (e.g., a fixed-length key) and a payload 354 (e.g., a fixed-length payload).

[0109] The records from the input list are sorted based on the key value. As described below, the records can be sorted in ascending or descending order, as specified in the Sort Order (SO) field of the parameter block associated with function code 1. The records in the input list can be listed in sorted order or not.

[0110] The records in the output list can originate from multiple input lists and are stored in sorted order. The number of output lists stored at the first operand position depends on the input data. In one example, only one output list is produced when each active input list contains records listed in the same order specified in the SO field.

[0111] As indicated above, bit 56 of general-purpose register 0 specifies the operating mode (referred to as merge mode (MM)) applicable to the SORTL-SFLR function. When merge mode is (for example) 0, for each output list stored at the first operand location, the corresponding output list description (OLD) is stored at the second operand location. Each OLD includes, for example, an 8-byte OLD-address and an 8-byte OLD-length, where the 8-byte OLD-address specifies the position of the first record in the corresponding output list, and the 8-byte OLD-length specifies, for example, the length of the corresponding output list in bytes. When merge mode is 1, the input lists are considered pre-sorted. That is, each active input list is considered to contain records in the same order as specified by the SO field of the parameter block.

[0112] When MM is 1 and each input list is pre-sorted, the result stored at the first operand position is a single list of output records in sorted order. When MM is 1 and each input list is not pre-sorted, the result is unpredictable.

[0113] When MM is (for example) 1, the contents of general-purpose registers R2 and R2+1 are ignored, and no information is stored at the second operand location. When MM is 1, the procedure used to distinguish the separations between output lists may not be executed, potentially improving the performance of the operation. When MM is 1, data is not stored in the continuation record recall buffer described below.

[0114] In one example, to generate a single list of records in sorted order from a set of records in random order, the program can perform the following procedure:

[0115] 1. Divide the initial list set evenly into a record set, where each list contains records in a random order. Execute a list sorting instruction with the initial list set as input and the merge mode equal to 0 to produce an intermediate list set (where each list contains records in sorted order), along with the storage location and length of each list in the intermediate list set.

[0116] 2. Execute the list sorting instruction with the intermediate list set as the input list and the merge mode equal to 1 to produce a final and single list containing records in sorted order.

[0117] Figure 4A An example of SORTL-SFLR with merge mode equal to 0 is shown below. This example includes inputs and outputs. As shown, there are three input lists 400: input list0, input list1, and input list2. Further, an example of the first operand 402 and the second operand 404 of the result is shown. In one example, the first operand 402 ( Figure 4A There are three lists, and as shown in the second operand 404, one starts at address 1000 and has a length of 18; another starts at address 1018 and has a length of 28; and the third starts at address 1040 and has a length of 20.

[0118] In one example, when two operations perform the same SORTL-SFLR function on the same unsorted set of input records with merge mode equal to 0 and the only difference between the two operations is the number of input lists used to specify the input data, the operation with a larger number of input lists results in a smaller number of output lists. Figure 4BThis demonstrates the use of six input lists 450 to compare with the use of three input lists. Figure 4A The example above demonstrates operations performed on the same input data. A first operand 452 with two output lists instead of three, and a second operand 454 providing descriptions of the two output lists, are also shown.

[0119] As noted, the SORTL-SFLR function uses parameter blocks, an example of which can be found here. Figure 3K The example parameter block described herein specifies a particular position (e.g., a specific byte and / or bit) within the parameter block for a specific field and a specific size of the field. However, other positions and / or sizes can be provided for one or more fields. Furthermore, while specifying that bits are set to specific values ​​(e.g., 1 or 0) is provided, this is merely an example. In other examples, bits may be set to different values, such as the opposite or another value. Many variations are possible.

[0120] In one example, parameter block 360 of the SORTL-SFLR function contains the following items:

[0121] Parameter Block Version Number (PBVN) 362: Bytes 0-1 of the parameter block specify the version and size of the parameter block. Bits 0-7 of PBVN have the same format and definition as bits 0-7 of the interface size list vector (byte 16) for the installation of parameter blocks for the SORTL-QAF (query) function. Bits 0-7 specify the number N of the input lists described in the parameter block. IS The evaluation formula (576 + 16 x N) is used. IS The size of the parameter block (in bytes) is determined by the SORTL-QAF function. One of bits 0-7 must have a value of 1; otherwise, a general operand data anomaly is identified. Bits 8-11 of PBVN are reserved and should contain 0; otherwise, the program may not be able to operate incompatiblely in the future. Bits 12-15 of PBVN contain an unsigned binary integer specifying the format of the parameter block. The SORTL-QAF function provides a mechanism to indicate the available parameter block formats. A general operand data anomaly is identified when the size or format of the specified parameter block is not supported by the model. PBVN is specified by the program and is not modified during instruction execution.

[0122] Model Version Number (MVN) 364: Byte 2 of the parameter block is an unsigned binary integer identifying the model of the executed instructions. The MVN is updated, for example, during instruction execution by the processor. The values ​​stored in the MVN are model-dependent.

[0123] When the continuation flag (CF) 368, as described below, is 1, MVN is the input to the operation. When CF is 1 and MVN identifies the same model as the currently executed instruction, data from the continuation state buffer (CSB) 390, as described below, can be used to resume the operation. When CF is 1 and MVN identifies a different model than the currently executed instruction, part or all of the CSB field can be ignored.

[0124] In one example, the program initializes MVN to zero. It is expected that the program will not modify MVN if instructions are re-executed for the purpose of resuming operations; otherwise, the results are unpredictable.

[0125] Sort Order (SO) 366: When bit 56 of the parameter block is 0, ascending sort order is specified; when it is 1, descending sort order is specified. When ascending order is specified, each record in the output list contains a key greater than or equal to the key of its adjacent record in the same output list (e.g., on the left). When descending order is specified, each record in the output list contains a key less than or equal to the key of its adjacent record in the same output list (e.g., on the left). SO is not updated during instruction execution.

[0126] Continuation Flag (CF) 368: Bit 63 of the parameter block. When 1, it indicates that the operation is partially complete and continues the contents of the status buffer 390. When the merge mode (MM) is 0, the operation can be resumed by calling the contents of the continuation record buffer. The program initializes the Continuation Flag (CF) to zero and does not modify CF if the instruction is re-executed for the purpose of resuming the operation; otherwise, the result is unpredictable. In one example, the processor modifies CF if the instruction is to be re-executed.

[0127] Record key length 370: Bytes 10-11 of the parameter block contain an unsigned binary integer specifying the size in bytes of the key in the record being processed during the operation. In one example, a general operand data anomaly is identified for any of the following conditions:

[0128] Specifies the key size as zero bytes.

[0129] Specify a key size that is not a multiple of 8.

[0130] Specify a key size greater than 4096 bytes.

[0131] The record key length is not updated during instruction execution.

[0132] Record payload length 372: When the SORTL-SFLR function is specified, bytes 14-15 of the parameter block contain an unsigned binary integer specifying the size in bytes of the payload in the record processed during the operation. In one example, a general operand data anomaly is identified for any of the following conditions:

[0133] The payload size is specified as a multiple of 8.

[0134] The sum of the specified key and payload size is greater than 4096 bytes.

[0135] A payload size of zero is valid.

[0136] When the SORTL-SVLR feature is specified, the record payload length field of the parameter block is ignored. The record payload length is not updated during instruction execution.

[0137] Operand Access Intent (OAI) 374: Bits 0-1 of byte 32 of the parameter block indicate to the CPU the future access intent for the input list and the first operand. The provided access intent can be used to modify cache line mounting and replacement policies for corresponding storage locations at different levels of the cache hierarchy.

[0138] When bit 0 of the OAI field is 1, the storage location designated to contain data for any active input list will be referenced as one or more operands in subsequent instructions. When bit 0 of the OAI field is 0, the storage location designated to contain data for any active input list will not be referenced as one or more operands in subsequent instructions.

[0139] When bit 1 of the OAI field is 1, the storage location designated to contain the first operand will be referenced as one or more operands in subsequent instructions. When bit 1 of the OAI field is 0, the storage location designated to contain the first operand will not be referenced as one or more operands in subsequent instructions.

[0140] There is no guarantee that the CPU will use this information. The duration for which this information can be used is undefined, but finite.

[0141] When the next sequential instruction following the Next Instruction Access Intent (NIAI) is a List Ordering (SORTL), the execution of SORTL is unaffected by NIAI.

[0142] OAI is not updated during instruction execution.

[0143] Active Input Lists Count Code (AILCC) 376: Bits 1-7 of byte 33 of the parameter block are 7-bit unsigned integers that specify the number of input lists that indicate the boundary between the active and inactive input lists. Input lists with list numbers that are, for example, less than or equal to the value in the AILCC field are active. Input lists with list numbers that are, for example, greater than the value in the AILCC field are inactive. The number of active input lists is one more than the value in the AILCC field.

[0144] Active input lists participate in operations. Inactive input lists do not participate in operations.

[0145] Bit 0 of byte 33 in the parameter block is a reserved bit and should contain zero; otherwise, the program may be incompatible in the future.

[0146] In one example, a general operand data anomaly is identified when the value of the AILCC field plus one is greater than the number of inputs described in the parameter block (as specified by bits 0 to 7 of the PBVN field).

[0147] The value specified in the AILCC field does not affect the size of the parameter block. Access exceptions apply to references to fields of parameter blocks that specify the address or length of an input list corresponding to an inactive input list.

[0148] AILCC is not updated during instruction execution.

[0149] Empty Input Lists Control (EILCL) 378: When bit 0 of byte 40 of the parameter block is 1, the operation ends when the length of input list0 becomes zero during the operation. When bit 0 of byte 40 of the parameter block is zero, the operation continues when the length of input list0 becomes zero during the operation. When bit 1 of byte 40 of the parameter block is 1, the operation ends when the length of the active input list other than input list0 becomes zero during the operation. When bit 1 of byte 40 of the parameter block is zero, the operation continues when the length of the active input list other than input list0 becomes zero during the operation.

[0150] When the length of the active input list is initially zero before the instruction is executed, the corresponding bit of EILCL is not applicable.

[0151] EILCL is not updated during instruction execution.

[0152] It is expected that the program will not modify EILCL when instructions are re-executed for the purpose of restoring operations; otherwise, the results will be unpredictable.

[0153] Empty Input List Flag (EILF) 380: When EILCL is binary 11, and the operation ends because the updated length of the active input list is zero, and condition code 2 is set, the processor stores the value 1 in bit 2 of byte 40 of the parameter block, for example; otherwise, the value 0 is stored in bit 2 of byte 40 of the parameter block. When EILF contains the value 1, the input list number of the input list that will become empty during the operation is placed in the EILN field of the parameter block. In one example, the program initializes EILF to zero.

[0154] When a recovery operation is in progress, the EILF can be referenced at the start of instruction execution. It is expected that the program will not modify the EILF if the instructions are re-executed for the purpose of recovery; otherwise, the results would be unpredictable.

[0155] Empty Input List Number (EILN) 382: When the condition causes the value 1 to be stored in the EILF field, the input list number of the input list that becomes empty during the operation is stored by the processor in byte 41 of the parameter block; otherwise, the value 0 is stored in byte 41 of the parameter block.

[0156] EILN is ignored at the start of the operation. In one example, the program initializes EILN to zero.

[0157] Incomplete Input List Flag (IILF) 384: When an operation ends due to an attempt to process an incomplete input list, for example, the processor stores the value 1 in bit 0 of byte 46 of the parameter block; otherwise, a zero value is stored in bit 0 of byte 46 of the parameter block. The active input list is considered incomplete when the length of the corresponding input list is greater than zero and less than the number of bytes of the record specified by the input list address. This condition may exist at the start of the operation or may be encountered during the operation. When IILF contains the value 1, the input list number of the incomplete input list encountered is placed in the IILN field of the parameter block. In one example, the program initializes IILF to zero.

[0158] The operation terminates due to an empty input list when it ends with condition code 2 and the result value in the IILF field is zero. The operation terminates due to an incomplete input list when it ends with condition code 2 and the result value in the IILF field is 1.

[0159] When a recovery operation is in progress, the IILF can be referenced at the start of instruction execution. It is expected that the program will not modify the IILF if the instruction is re-executed for the purpose of recovery; otherwise, the result would be unpredictable.

[0160] Incomplete Input List Number (IILN) 386: When a condition causes a value of 1 to be stored in the IILF field, for example, the processor stores the input list number of the encountered incomplete input list in byte 47 of the parameter block; otherwise, a zero value is stored in byte 47 of the parameter block. Which incomplete input list number is stored in the IILN field when multiple input lists are incomplete depends on the model. In one example, the program initializes IILN to zero.

[0161] IILN is ignored at the start of the operation.

[0162] Continuation Record Recall Buffer Origin 388: A 4KB buffer in the storage device (called the Continuation Record Recall Buffer) is provided by the program for the CPU to store and reference data between two executions of the same list sorting instruction (in cases where the operation is complete and can be resumed later). The 52 bits of the parameter block, starting from bit 0 of byte 56 to bit 3 of byte 62, contain an unsigned binary integer used to form the Continuation Record Recall address, aligned on the 4KB boundary. The Continuation Record Recall address is, for example, the logical address of the leftmost byte of the Continuation Record Recall Buffer.

[0163] In 24-bit addressing mode, bits 40 to 51, which are the starting points of the continue record recall buffer with 12 zeros appended to the right, form the continue record recall address. In 31-bit addressing mode, bits 33-51, which are the starting points of the continue record recall buffer with 12 zeros appended to the right, form the continue record recall address. In 64-bit addressing mode, bits 0 to 51, which are the starting points of the continue record recall buffer with 12 zeros appended to the right, form the continue record recall address.

[0164] In access register mode, access register 1 specifies the address space of the storage device containing the continue recording and recall buffer.

[0165] When the merge mode (MM) is zero, and the operation ends after storing one or more records without a normal completion, the key of the last record stored in the first operand is also stored in the continue record recall buffer. When MM is 1, the start point of the continue record recall buffer is ignored.

[0166] During instruction execution, the starting point of the continued recording buffer is not modified.

[0167] It is expected that if instructions are re-executed for the purpose of restoring operations, the program will not modify the start point of the continued recording buffer; otherwise, the result is unpredictable.

[0168] Continuation State Buffer (CSB) 390: Internal state data is stored in the parameter block bytes 64-575 by the processor when a condition causes the value 1 to be stored in the CF field; otherwise, bytes 64-575 of the parameter block are undefined and modifiable. The stored internal state data is model-dependent and can be subsequently used to resume operations when instructions are re-executed. In one example, the program initializes the continuation state buffer to zero. It is expected that the program will not modify the continuation state buffer if instructions are re-executed for the purpose of resuming operations; otherwise, the results are unpredictable.

[0169] As an example, internal state data includes information related to the input list, such as previous comparisons of records in the input list to determine the next comparison to be performed. Internal state data is model-dependent, as it can be stored or submitted differently depending on the processor model. Other variations are possible.

[0170] In one embodiment, instructions may be partially performed by one model in the configuration, and execution can be resumed on different models in the configuration. While different models may maintain different internal states in one embodiment, in one example, each model must be able to interpret (if any) the contents of the CSB used for the recovery operation. When the operation resumes, the MVN instructs the machine which contents of the CSB (if any) it can interpret.

[0171] Input List N Address (392, 394, 396): This parameter block defines multiple input lists. The number N of input lists defined in the parameter block. IS Specified by bits 0-7 of PBVN 362. The input list ranges from zero to (N). IS -1) Numbering. For each input list, the parameter block specifies, for example, the address of the input list in 8 bytes. For the Nth input list, bytes 576+16xN to 583+16xN of the parameter block specify, for example, the logical address of the leftmost byte of the Nth input list in the storage device.

[0172] Each input list address corresponding to the active input list specified by the AILCC field is the input to the operation and is updated by the operation. Each input list address corresponding to the inactive input list specified by the AILCC field is ignored by the operation.

[0173] In one embodiment, when the input list address is input to an operation, the following applies:

[0174] In 24-bit addressing mode, bits 40-63 of the input list address specify the position of the leftmost byte of the input list in the storage device, and bits 0-39 of the input list address are treated as 0.

[0175] In 31-bit addressing mode, bits 33-63 of the input list address specify the position of the leftmost byte of the input list in the storage device, and bits 0-32 of the input list address are treated as 0.

[0176] In 64-bit addressing mode, bits 0-63 of the input list address specify the location of the leftmost byte of the input list in the storage device.

[0177] In access register mode, access register 1 specifies the address space in the memory device that contains the active input list.

[0178] For an active input list, the corresponding input list address must be specified on the double-word boundary; otherwise, in one example, a general operand data anomaly was identified.

[0179] In one embodiment, when updating the input list address via an operation, the following applies:

[0180] When one or more records in the input list have been processed as part of an operation, the corresponding input list address is incremented by the number of bytes occupied by the processed record in the storage device. The formation and updating of the input list address depend on the addressing mode.

[0181] In 24-bit addressing mode, bits 40-63 of the updated input list address replace the corresponding bits in the input list address field of the parameter block, ignore the carry out at bit position 40 of the updated input list address, and set the contents of bits 0-39 of the input list address field of the parameter block to zero.

[0182] In 31-bit addressing mode, bits 33-63 of the updated input list address replace the corresponding bits in the input list address field of the parameter block, ignore the carry at bit position 33 of the updated input list address, and set the contents of bits 0-32 of the input list address field of the parameter block to zero.

[0183] In 64-bit addressing mode, bits 0-63 of the updated input list address replace the corresponding bits in the input list address field of the parameter block, ignoring any carry-over from bits 0 of the updated input list address.

[0184] In 24-bit and 31-bit addressing modes, when the execution of an instruction ends and the instruction is not suppressed, invalidated, or terminated, the input list address corresponding to each 64-bit of the active input list is updated, even if the address is not incremented.

[0185] Input List N Length 393, 395, 397: For each input list, the parameter block specifies the 8-byte length of the input list. For the Nth input list, bytes 584+16xN to 591+16xN in the parameter block contain an unsigned integer specifying the number of bytes in the Nth input list.

[0186] The length of each input list corresponding to the active input list, as specified by the AILCC field, is the input to the operation and is updated by the operation. The length of each input list corresponding to the inactive input list, as specified by the AILCC field, is ignored by the operation.

[0187] In various addressing modes, the bit positions 0-63 of the input list length field specify the length of the corresponding input list.

[0188] When one or more records in the input list have been processed as part of an operation, the length of the corresponding input list is reduced by the number of bytes occupied by the processed records in the storage device. In various addressing modes, bits 0-63 of the updated input list length replace bits 0-63 in the corresponding input list length field of the parameter block.

[0189] Reserved fields: There are multiple reserved fields in the parameter block (e.g., fields that do not contain other information). Reserved fields should contain zero as input to the operation; otherwise, future program operations may be incompatible. When the operation ends, reserved fields can be stored as zero or remain unchanged.

[0190] Figures 5A-5B This document summarizes an example of the raw and final values ​​of the inputs used for the SORTL-SFLR function, including the fields in the parameter block.

[0191] In one embodiment, it is neither necessary nor expected that the program should modify the parameter block to re-execute the instruction between the end of the operation with condition code 3 set and the branch back instruction for the purpose of resuming the operation.

[0192] In one embodiment, the SORTL-SFLR functionality includes multiple comparisons between keys of records from different input lists. In one example, when comparing keys, the following applies:

[0193] Treating keys as unsigned binary integers is also known as unstructured data.

[0194] When determining which key contains the lowest or highest value, it is not necessary to access all bytes of every key being compared. The number of bytes per key in each comparison (called the unit of key comparison) is model-dependent. The number of bytes of the keys accessed is an integer number of units of key comparison.

[0195] When comparing keys with equal values, in one example, the key from the input list with the highest input list number is chosen to precede other keys with the same value according to the sort order. In this case, the corresponding record from the input list with the highest input list number is stored as the first operand before other records with the same key value. This applies to both ascending and descending sort orders.

[0196] One implementation can maintain a history of previous comparisons between records from the active input list. This history can be referenced when it is available and applicable, instead of accessing and comparing previously compared records. Referencing this history reduces the execution time required to generate results, thereby improving processing within the computing environment.

[0197] The SORTL-SFLR function involves selecting records from a set of input lists in a specified sort order and placing the selected records at the first operand position. As the operation progresses, the current values ​​of the first operand address and the address of the active input list are maintained. This function operates on a unit basis. During each unit of operation, for each active input list, the key specified by the address corresponding to the current input list is checked, and a record is placed at the first operand position.

[0198] When the merge mode (MM) is zero, the active input list is specified in a random order, for example, from left to right, and each item in the list is considered to contain a record. When MM is zero, the records stored in the first operand location constitute one or more output lists, and the starting address and length of each output list are stored in the second operand location. When MM is zero, each operation unit includes the following steps in a specified order, as an example:

[0199] 1. Determine whether the next record to be stored at the first operand position can be included in the most recently output list (including the output list of records most recently stored at the first operand position), as follows:

[0200] When the Continuation Flag (CF) is zero and the first operation unit is being processed, no record has been stored in the first operand position, and the next record to be stored will be the first record in the output list.

[0201] When CF is 1, the previous execution of the instruction ended with condition code 1, and while the first operation unit is being processed for the current execution of the instruction, the next record to be stored will be the first record of the output list.

[0202] When CF is 1, IILF is 0, EILF is 0, the previous execution of the instruction ended with condition code 2, and the first operation unit is being processed for the current execution of the instruction, the next record to be stored will be the first record of the output list.

[0203] When CF is 1, IILF or EILF is 1, the previous execution of the instruction ended with condition code 2, and the first operation unit is being processed for the current execution of the instruction, the next record to be stored can be included in the most recently output list.

[0204] When CF is 1, the previous execution of the instruction ended with condition code 3, and while the first operation unit is being processed for the current execution of the instruction, the next record to be stored can be included in the most recently output list.

[0205] When the unit of operation being processed is not the first unit of operation currently being executed by the instruction, the next record to be stored can be included in the most recently output list.

[0206] 2. When the next record to be stored can be included in the most recently output list, determine the set of records eligible to be included in the most recently output list. For each active, non-empty, and not incomplete input list, the key of the record specified by the current input list address (the current input key) is compared with the key of the record most recently stored in the first operand position (the previously stored key). For this purpose, a reference to the previously stored key is not a reference to the first operand position. Instead, it is a reference to the input list from which the key is selected, or it is a reference to the continue recording recall buffer. When an operation is being resumed and the current execution of the instruction has not yet placed any record at the first operand position, it is a reference to the continue recording recall buffer.

[0207] When the sort order is ascending and the value of the current input key is greater than or equal to the value of a previously stored key, the current input key is considered to belong to the set of keys eligible to be included in the most recently output list. When the sort order is descending and the value of the current input key is less than or equal to the value of a previously stored key, the current input key is considered to belong to the set of keys eligible to be included in the most recently output list. When the number of keys eligible to be included in the most recently output list is zero, the next record to be stored will be the first record in the output list. When the number of keys eligible to be included in the most recently output list is non-zero, the next record to be stored will be included in the most recently output list.

[0208] 3. When the next record to be stored is included in the most recently outputted list, compare the keys in the set of keys eligible to be included in the most recently outputted list. When the sort order is ascending, select the smallest key value and the corresponding record. When the sort order is descending, select the largest key value and the corresponding record.

[0209] 4. When the next record to be stored will be the first record in the output list, compare the keys of the records specified by the address of the current input list corresponding to the active, non-empty, and not incomplete input list. If the sort order is ascending, select the smallest key value and the corresponding record. If the sort order is descending, select the largest key value and the corresponding record.

[0210] 5. Place the selected record at the current first operand position.

[0211] 6. Increment the address of the current first operand by the number of bytes equal to the length of the selected record.

[0212] 7. Increment the address of the current input list corresponding to the input list containing the selected record by the number of bytes equal to the length of the selected record.

[0213] As part of the operation when the merge mode is zero, for each output list stored at the first operand location, a corresponding output list description (OLD) is stored at the second operand location. Each OLD includes, for example, an 8-byte OLD address specifying the position of the first record in the corresponding output list, and an OLD length (in bytes) specifying the length of the corresponding output list. When the operation ends with condition code 3 equal to 1, condition code 2 and EILF equal to 1, or condition code 2 and IILF equal to 1, the most recently processed output list at the end of the operation may be partially processed and incompletely processed. That is, the number of records in the partially processed output list is an intermediate value and may increase when the operation resumes. In this case, the output list description (OLD) corresponding to the partially processed output list is not placed at the second operand location until the operation is resumed and the output list is fully processed.

[0214] When the merge mode is zero and the operation ends after storing one or more records without a normal completion, the key of the last record stored at the first operand position is also stored in the continue recording and recall buffer.

[0215] When the merge mode is zero and the operation completes normally, one or more output lists have been placed at the first operand position, and the output list descriptor has been placed at the second operand position. The program can use the output list descriptor as the address and length value of the input list in the parameter block of subsequent SORTL operations.

[0216] Figures 6A-6D This shows the first and second operands before and after performing SORTL-SFLR in merge mode equal to zero. See also Figures 6A-6B FOSA 600 is the starting address of the first operand: the location specified by R1; FOEA 602 is the ending address of the first operand: the location specified by R1+(R1+1)–1; and OL 604 is the output list (e.g., output list 1…output list N). Further, see… Figures 6C-6D SOSA 610 is the starting address of the second operand: the location specified by R2; SOEA 612 is the ending address of the second operand: the location specified by R2+(R2+1)–1; and OLD 614 is the output list specification (e.g., output list specification 1... output list specification N).

[0217] When the merge mode (MM) is 1, the active input list specifies a list where each record is treated as a list containing records sorted from left to right according to the SO field of the parameter block. When MM is 1, the records stored in the first operand position constitute a single output list. When MM is 1, each unit operation includes, for example, the following steps in the specified order:

[0218] 1. Compare the keys of the records specified by the address of the current input list corresponding to the active, non-empty, and incomplete input list. When the sort order is ascending, select the smallest key value and the corresponding record. When the sort order is descending, select the largest key value and the corresponding record.

[0219] 2. Place the selected record at the current first operand position.

[0220] 3. Increment the address of the current first operand by the number of bytes equal to the length of the selected record.

[0221] 4. Increment the address of the current input list corresponding to the input list containing the selected record by the number of bytes equal to the length of the selected record.

[0222] Figures 7A-7BThis example illustrates the first operand before and after performing SORTL-SFLR with merge mode equal to 1. See also Figures 7A-7B FOSA 700 is the starting address of the first operand: the location specified by R1; FOEA 702 is the ending address of the first operand: the location specified by R1+(R1+1)–1; and OL 704 is the output list (e.g., output list 1).

[0223] As part of the operation when the merge mode is zero or one, the input list address and length of the active input lists are updated. For each active input list, the input list address is incremented by the number of bytes from the input list that were selected and placed at the first operand position during the operation, and the input list length is decremented by the same number. The formation and updating of the input list address depend on the addressing mode.

[0224] As the operation progresses, an incomplete input list may be encountered. The incomplete input list is identified during the unit of operation attempting to reference records from it. Multiple units of operation may be completed before the incomplete input list is identified. This applies when the merge mode is 0 or 1.

[0225] As the operation proceeds, access exceptions may occur for access to the input list, the first operand, or the second operand (where applicable). Access exceptions are identified during an operation unit that attempts to access a storage location and an access exception exists for that location. Multiple operation units may complete before an incomplete input list is identified. This applies when the merge mode is 0 or 1.

[0226] When an operation ends with partial completion, internal state data, which may contain historical comparisons between records, can be stored in the Continuation State Buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, the contents of the CSB can be loaded into the implementation for the purpose of restoring the operation, and this history can be referenced when the operation is resumed. This applies when the merge mode is 0 or 1.

[0227] Normal completion occurs when the records from the active input list have been sorted and stored in the first operand.

[0228] In one embodiment, when the operation ends due to normal completion, the following occurs:

[0229] The addresses and lengths in general-purpose registers R1 and R1+1 are updated respectively.

[0230] When MM is zero, the address and length in general-purpose registers R2 and R2+1 are updated respectively.

[0231] Update the input listN address and input listN length fields for the active input list.

[0232] The model version number is set.

[0233] The continue flag is set to zero.

[0234] The empty input list flag is set to zero.

[0235] Empty input list numbers are set to zero.

[0236] The incomplete input list flag is set to zero.

[0237] The incomplete input list number is set to zero.

[0238] Condition code 0 is set.

[0239] The formation and updating of addresses and lengths depend on the addressing mode.

[0240] When a normal completion occurs, the CSB field of the parameter block is undefined after the operation ends.

[0241] In one embodiment, when the number of bytes determined by the CPU has been processed, the operation ends and the following occurs:

[0242] The addresses and lengths in general-purpose registers R1 and R1+1 are updated respectively.

[0243] When MM is zero, the address and length in general-purpose registers R2 and R2+1 are updated respectively.

[0244] Update the input listN address and input listN length fields for the active input list.

[0245] The model version number has been set.

[0246] The continue flag is set to 1.

[0247] When MM is zero and one or more records have been placed at the first operand position during instruction execution, the key value is stored in the continue recording and recall buffer.

[0248] The state buffer continues to be updated.

[0249] The empty input list flag is set to zero.

[0250] Empty input list numbers are set to zero.

[0251] The incomplete input list flag is set to zero.

[0252] The incomplete input list number is set to zero.

[0253] Condition code 3 has been set.

[0254] The formation and updating of addresses and lengths depend on the addressing mode.

[0255] The number of bytes determined by the CPU depends on the model and can be different each time an instruction is executed. The number of bytes determined by the CPU is usually non-zero. Although this number can be zero and manifest as a no-progress case, the CPU is protected against the constant recurrence of no-progress cases.

[0256] After an instruction ends with, for example, condition code 3, the program is expected not to modify any input or output specifications of the instruction and to return to the branch to re-execute the instruction to resume the operation.

[0257] In one embodiment, when bit 0 of the Empty Input List Control (EILCL) is 1, and the length of input list0 becomes zero during the operation, and normal completion is not applicable, the operation ends and the following occurs:

[0258] The addresses and lengths in general-purpose registers R1 and R1+1 are updated respectively.

[0259] When MM is zero, the address and length in general-purpose registers R2 and R2+1 are updated respectively.

[0260] Update the input listN address and input listN length fields for the active input list.

[0261] The model version number has been set.

[0262] The continue flag is set to 1.

[0263] When EILCL is binary 10 and MM is zero, the key value can be stored in the continue record and recall buffer. When EILCL is binary 11 and MM is zero, the key value is stored in the continue record and recall buffer. In either case, one or more records have been placed at the first operand position during instruction execution.

[0264] The state buffer continues to be updated.

[0265] The empty input list flag is set (see reference). Figure 8 (It shows the various parameter block fields when the operation ends).

[0266] Empty input list number is set (see reference) Figure 8 ).

[0267] The incomplete input list flag is set to zero.

[0268] The incomplete input list number is set to zero.

[0269] Condition code 2 has been set.

[0270] The formation and updating of addresses and lengths depend on the addressing mode.

[0271] In one embodiment, when bit 1 of the Empty Input List Control (EILCL) is 1, and the length of the active input list (excluding input list 0) becomes zero during the operation, and normal completion is not applicable, the operation ends and the following occurs:

[0272] The addresses and lengths in general-purpose registers R1 and R1+1 are updated respectively.

[0273] When MM is zero, the address and length in general-purpose registers R2 and R2+1 are updated respectively.

[0274] Update the input listN address and input listN length fields for the active input list.

[0275] The model version number has been set.

[0276] The continue flag is set to 1.

[0277] When EILCL is 01 (binary) and MM is 0, the key value can be stored in the continue record and recall buffer. When EILCL is 11 (binary) and MM is zero, the key value is stored in the continue record and recall buffer. In either case, one or more records have been placed at the first operand position during instruction execution.

[0278] The state buffer continues to be updated.

[0279] The empty input list flag is set (see reference). Figure 8 ).

[0280] Empty input list number is set (see reference) Figure 8 ).

[0281] The incomplete input list flag is set to zero.

[0282] The incomplete input list number is set to zero.

[0283] Condition code 2 has been set.

[0284] The formation and updating of addresses and lengths depend on the addressing mode.

[0285] In one embodiment, when an incomplete list of active inputs is encountered, the operation ends and the following occurs:

[0286] The addresses and lengths in general-purpose registers R1 and R1+1 are updated respectively.

[0287] When MM is zero, the address and length in general-purpose registers R2 and R2+1 are updated respectively.

[0288] Update the input listN address and input listN length fields for the active input list.

[0289] The model version number has been set.

[0290] The continue flag is set to 1.

[0291] When MM is zero and one or more records have been placed at the first operand position during instruction execution, the key value is stored in the continue recording and recall buffer.

[0292] The state buffer continues to be updated.

[0293] The empty input list flag is set to zero.

[0294] Empty input list numbers are set to zero.

[0295] The Incomplete Input List flag (IILF) is set to 1.

[0296] The input list number of any incomplete input list encountered is placed in the Incomplete Input List Number (IILN) field of the parameter block.

[0297] Condition code 2 has been set.

[0298] The formation and updating of addresses and lengths depend on the addressing mode.

[0299] In one embodiment, when the length of the first operand is insufficient to store another record, the operation ends, and the following occurs:

[0300] Update the address and length in general-purpose registers R1 and R1+1 respectively.

[0301] When MM is zero, update the address and length in general-purpose registers R2 and R2+1 respectively.

[0302] Update the input listN address and input listN length fields for the active input list.

[0303] The model version number is set.

[0304] The flag will remain set to 1.

[0305] When MM is zero and one or more records have been placed at the first operand position during instruction execution, the key value can be stored in the continue recording and recall buffer.

[0306] Update the continuation state buffer.

[0307] The empty input list flag is set to zero.

[0308] Empty input list numbers are set to zero.

[0309] The incomplete input list flag is set to zero.

[0310] The incomplete input list number is set to zero.

[0311] Set condition code 1.

[0312] The formation and updating of addresses and lengths depend on the addressing mode.

[0313] In one embodiment, the operation ends when the merge mode (MM) is zero and the length of the second operand is less than 16, and the following occurs:

[0314] Update the address and length in general-purpose registers R1 and R1+1 respectively.

[0315] Update the address and length in general-purpose registers R2 and R2+1 respectively.

[0316] Update the input listN address and input listN length fields for the active input list.

[0317] Set the model version number.

[0318] The flag will remain set to 1.

[0319] When one or more records have been placed at the first operand position during instruction execution, the key value can be stored in the continue recording and recall buffer.

[0320] Update the continuation state buffer.

[0321] The empty input list flag is set to zero.

[0322] Empty input list numbers are set to zero.

[0323] The incomplete input list flag is set to zero.

[0324] The incomplete input list number is set to zero.

[0325] Set condition code 1.

[0326] The formation and updating of addresses and lengths depend on the addressing mode.

[0327] The operation termination condition is called partial completion when the execution of an instruction ends in completion (not in suppression, invalidation, or termination) and normal completion does not occur.

[0328] Where applicable, identify PER storage change events for the first operand location, the second operand location, the continue recording and recall buffer, and portions of the stored parameter block. When a PER storage change event is identified, store fewer than 4KB of additional bytes in the operand location intersecting the specified PER storage area before reporting the event.

[0329] When applicable, PER zero-address detection events are identified for the parameter block, the first operand position, and the second operand position. Zero-address detection does not apply to the input list address specified in the parameter block or the start point of the continue recording recall buffer.

[0330] For examples of other conditions applied to the SORTL-SFLR function, see Other Conditions below.

[0331] When the instruction ends with condition code 1, the program may appropriately modify the address of the first operand, the length of the first operand, the address of the second operand, the length of the second operand, the address of any active input list, and the length of any active input list before resuming the operation.

[0332] When the instruction ends with condition code 2, IILF equal to zero, and EILF equal to zero, the program may appropriately modify the first operand address, first operand length, second operand address, second operand length, any active input list address, and any active input list length before resuming the operation.

[0333] When the instruction terminates with condition code 2 and EILF equal to 1, the program may appropriately modify the address and length of the input list specified by EILN, and then resume the operation. In this case, when merge mode (MM) is 1, the program may also modify the address and length of the first operand.

[0334] When the instruction terminates with condition code 2 and IILF equal to 1, the program may appropriately modify the address and length of the input list specified by IILN, and then resume operation. In this case, when merge mode (MM) is 1, the program may also modify the address and length of the first operand.

[0335] If the instruction ends with condition code 3 and the instruction is re-executed to resume the operation, the program may modify any active input list address or length, first operand address or length, or second operand address or length, with unpredictable results.

[0336] Function code 2: SORTL-SVLR (Sort Variable-Length Records)

[0337] Except for the following, the operation of the SORTL-SVLR function is the same as that of the SORTL-SFLR function:

[0338] Records include, for example, Figure 9 The diagram shows a fixed-length key 900, an 8-byte payload length (PL) 902, and a variable-length payload 904. Therefore, the record has a variable length.

[0339] Ignore bytes 14 to 15 of the parameter block for the SORTL-SVLR function.

[0340] The least significant byte of the payload length field for each record—for example, 2 bytes—contains an unsigned binary integer specifying the length of the payload in bytes within the same record. A payload length of zero is valid. In one example, the payload length will be, for example, a multiple of 8; otherwise, a general operand data anomaly is identified. The most significant byte of the payload length field—for example, 6 bytes—is reserved bytes and should contain zero; otherwise, future program operations may be incompatible. The sum of the key length 8 and the payload length is not greater than, for example, 4096; otherwise, in one example, a general operand data anomaly is identified. When a general operand data anomaly is identified due to an inappropriate payload length, the address of the input list corresponding to the active input list where the anomaly occurred specifies the logical address of the leftmost byte of the erroneous record. When a variable-length record is stored in the first operand position, the reserved bytes of the payload length field are not modified.

[0341] An incomplete input list cannot be identified during an operation unit that only attempts to reference the keys of records from an input list whose length is greater than the key size and less than the record size. In this case, the incomplete input list will be identified when attempting to store a record from an incomplete input list into the first operand position.

[0342] The parameter block for the SORTL-SVLR function is the same as that for the SORTL-SFLR function, except for bytes 14 to 15 as shown above.

[0343] For a description of other conditions applicable to the SORTL-SVLR function, please refer to the following section on Special Conditions.

[0344] In one embodiment, a specified exception is identified when an attempt is made to perform list sorting and any of the following applies:

[0345] Bits 57-63 of general-purpose register 0 specify unassigned or uninstalled function codes.

[0346] The R1 field specifies either an odd-numbered register or general-purpose register 0.

[0347] The R2 field specifies either an odd-numbered register or general-purpose register 0. This applies when the merge mode (MM) is 0 or 1.

[0348] The parameter block is not specified on the double word boundary.

[0349] Specify the SORTL-SFLR or SORTL-SVLR function, and do not specify the first operand on the double word boundary.

[0350] When MM is zero, specify the SORTL-SFLR or SORTL-SVLR function and do not specify a second operand on the double word boundary.

[0351] In one embodiment, a specified exception is identified when an attempt is made to perform list sorting and any of the following applies:

[0352] If the SORTL-SFLR or SORT-SVLR function is specified, and none or more bits in bits 0-7 of the parameter block version number contain the value 1, the operation is suppressed.

[0353] If SORTL-SFLR or SORTL-SVLR functionality is specified, and the size or format of the parameter block specified by the parameter block version number is not supported by the model, the operation is suppressed.

[0354] If the SORTL-SFLR or SORTL-SVLR function is specified, and the record key length is specified as a key size of 0, a key size that is not a multiple of 8, or a key size greater than 4096, the operation is suppressed.

[0355] If the SORTL-SFLR function is specified and the recorded payload length is not a multiple of 8, or the sum of the payload size and the key size is greater than 4096, the operation is suppressed.

[0356] If the SORTL-SVLR function is specified and the recorded payload length is not a multiple of 8, or the sum of the payload size and the key size is greater than 4088, then whether the operation is suppressed or terminated depends on the model.

[0357] If the SORTL-SFLR or SORTL-SVLR function is specified, and the value of the Active Input List Counter Code (AILCC) incremented by one is greater than the number of input lists described by the parameter block, the operation is suppressed.

[0358] Specifying the SORTL-SFLR or SORTL-SVLR function, and not specifying the input list address corresponding to the active input list on the double-word boundary, in which case the operation is suppressed.

[0359] Other conditions

[0360] In one embodiment, the following conditions apply:

[0361] Instruction execution is interruptible. When an interrupt occurs, the addresses in general-purpose registers R1 and R2, the lengths in general-purpose registers R1+1 and R2+1, and specific fields of the parameter block are updated so that the instruction can resume execution at the point of interruption when it is re-executed.

[0362] Access exceptions are not recognized for positions greater than 4KB to the right of the position specified by the first operand address.

[0363] If the access exception is detected due to the first operand, the second operand, or any list of inputs, the result is either an exception is detected or condition code 3 is set. If condition code 3 is set, assuming the exception condition still exists, the exception will be detected when the instruction is executed again to continue processing the same operand.

[0364] When a record's key crosses a page boundary and an access exception exists for both pages, either access exception can be identified.

[0365] When an access exception condition exists for multiple keys being processed during a single operation unit, any one of these conditions can be identified.

[0366] When a parameter block crosses a page boundary and an access exception condition exists for both pages, the access exception for the leftmost page is identified.

[0367] When an operation ends with partial completion, up to 4KB of data may have been stored within the first operand at the location specified by the updated first operand address or at a location to its right. Such storage results in the setting change bit (where applicable) and the recognition of a PER storage change event (where applicable). When an instruction is executed again to continue processing the same operand, the data will be stored repeatedly at these locations.

[0368] As observed by the CPU, other CPUs, and the channel program, references to the parameter block, the first operand, the output list description buffer, and the active input list can be multiple access references. Accesses to these storage locations are not necessarily block-parallel, and the sequence of these accesses or references is undefined.

[0369] In one embodiment, when the specified function is SORTL-SFLR or SORTL-SVLR and any of the following applies, the result is unpredictable:

[0370] The parameter block overlaps with any active input list or first operand.

[0371] Any active input list overlaps with the first operand.

[0372] The merge mode is zero, and the parameter block overlaps with the second operand or continue recording call buffer.

[0373] The merge mode is zero, and any active input list overlaps with the second operand or continue recording call buffer.

[0374] The merge mode is zero, and the first operand overlaps with the second operand or the continue recording and call buffer.

[0375] The merge mode is zero, and the second operand overlaps with the continue recording and call buffer.

[0376] Another CPU or channel program stores the key of the record in the input list or continues recording and then recalls the key of the record in the buffer.

[0377] Example result condition code:

[0378] 0 Completed normally

[0379] 1. The length of the first operand is less than the size of the record, or the merge mode is zero and the length of the second operand is less than 16 (i.e., the length of the first or second operand is insufficient to continue).

[0380] 2. An incomplete input list is encountered (IILF = 1), or EILCL is non-zero and the length of the input list becomes zero during the operation (i.e., an incomplete or empty input list is encountered).

[0381] 3. The amount of data determined by the CPU is processed (i.e., the CPU's determination is complete).

[0382] Program error:

[0383] Access (extract, input list; extract and store, parameter block and continue recording and recall buffer; store, operand 1 and 2)

[0384] Data with DXC (Data Exception Code) 0, general operands

[0385] Operation (if enhanced sorting facilities are not installed)

[0386] Specification

[0387] Transaction constraints

[0388] The following section illustrates the execution priority of list sorting instructions. When multiple conditions exist with priority values ​​beginning with 13, the identified condition is the one encountered first as the operation proceeds. When the operation is being resumed (the continuation flag is 1 at the start of instruction execution), the history of previous comparisons between keys can be used instead of the initial, non-empty input list of the access activity. As a result, access exceptions for accessing a particular input list may not be encountered at the same processing point compared to when the history of previous comparisons is not used. When variable-length records are processed, conditions that function as a function of record length can be partially evaluated before the payload length is determined and fully evaluated after the payload length is determined. As a result, the priority observed among such conditions can differ when the existence of a condition is determined after only a partial evaluation of the requirements, rather than after a full evaluation of all requirements.

[0389] Execution Priority (SORTL)

[0390] 1.-6. Exceptions with the same priority as program interrupt conditions used in general cases.

[0391] 7.A Second instruction half-word access exception.

[0392] 7.B Operational error.

[0393] 7.C Transaction Constraints.

[0394] 8. A specification exception attributable to an invalid function code or an invalid register number.

[0395] 8.B is attributed to a specification exception where the first operand was not specified on the double-word boundary.

[0396] 8.C is attributed to an exception where the first operand was not specified on the double-word boundary.

[0397] 8.D is attributed to a specification exception where a second operand was not specified on a double-word boundary and the merge mode is zero.

[0398] 9. Access exception for bytes 0-7 of the access parameter block.

[0399] 10. General operand data anomalies caused by unsupported values ​​in the PBVN field of the parameter block.

[0400] 11. Access exception for bytes other than bytes 0-7 in the access parameter block.

[0401] 12. Invalid values ​​of fields other than PBVN in the parameter block cause general operand data anomalies.

[0402] 13.A. Access error for accessing the active input list.

[0403] 13.B When the merge mode is 0, an access exception occurs when accessing the continued record and calling the buffer.

[0404] 13.C Access exception for the first operand.

[0405] 13.D An access exception occurs when the merge mode is 0 and the second operand is accessed.

[0406] 13.E is attributed to condition code 2, which is based on an incomplete input list.

[0407] 13. F is a condition code attributed to insufficient length of the first operand.

[0408] 13.G is attributed to condition code 1, which indicates that the length of the second operand is insufficient when the merge mode is 0.

[0409] 13.H is attributed to a general operand data anomaly caused by an invalid payload length in a variable-length record.

[0410] 13. I is attributed to condition code 2 for an empty input list.

[0411] 14. Condition code 3.

[0412] Programming Notes. In one embodiment:

[0413] 1. The intended use of the empty input lists control (EILCL) is as follows:

[0414] EILCL(0:1)

[0415] (Binary) description

[0416] 00 Stops after the records in the active input list (e.g., all records in all active input lists) have been sorted.

[0417] 10. Stop after the input list0 (which is always active) becomes empty.

[0418] 11. Stop after any activity input list becomes empty.

[0419] 2. When the Active Input List Counter Code (AILCC) is zero, there exists, for example, only one active input list, and the result stored at the first operand position is the same as the data obtained from input list0.

[0420] 3. A model that implements separate instruction and data caches can use an instruction cache to perform store operations on data in the active input list and retrieve references.

[0421] 4. When a program expects to call list sorting multiple times with a merge pattern equal to zero, as part of processing large datasets, in one example, the program utilizes the available input list and evenly distributes the records across the input list. This reduces the number of times the data is accessed when sorting the entire dataset.

[0422] 5. After a list sorting operation with a merge mode equal to zero ends with condition code 0 set and multiple output list descriptions (OLDs) in the second operand, a program aiming to generate a single list of records in sorted order calls another list sorting operation, specifying the input list as the result OLD from the previous list sorting call. In this case, in one example, the second call to the list sort specifies a merge mode equal to 1.

[0423] Similarly, in one embodiment, after multiple calls to the list sort with merge mode equal to zero as needed or expected, in order to generate a complete set of sorted lists from a large number of randomly sorted records, in one example, the list sort with merge mode equal to 1 is called multiple times as needed or expected to generate a single sorted list.

[0424] 6. In one embodiment, to reduce the number of times each record is accessed when merging multiple sorted lists into (for example) a single list sorted in ascending order, the program performs the following processing:

[0425] Determine the maximum number N of input lists that can be used for list sorting.

[0426] Compare the keys of the first record in the sorted lists that have not yet been merged into a single list. Select the N lists with the smallest first key values.

[0427] Perform a list sort with merge mode (MM) equal to 1, where empty input list control (EILCL) equals binary 10, input list0 specifies only the first record of the list with the highest first key value among the selected N lists, and the remaining input lists specify the other N-1 selected lists.

[0428] After sorting the list that ends with condition code 2, IILF equal to zero, and EILF equal to zero, repeat the process.

[0429] 7. After the list sorting ends with condition code 1 set, in one example, the program performs the following action to reverse the operation before calling list sorting again:

[0430] If the length of the first operand is less than the maximum record length of the record being processed, the length of the first operand or the address and length of the first operand should be updated accordingly.

[0431] If the merge mode (MM) is zero and the second operand length is less than 16, then the second operand length or the second operand address and length should be updated accordingly.

[0432] If the length of any active input list is zero, the corresponding input list address and length can be updated to specify another list of records that will be included in the sorting operation.

[0433] 8. After the list sorting ends with condition code 2 set, in one example, the program performs the following action to reverse the operation before calling list sorting again:

[0434] If the Incomplete Input List Flag (IILF) is 1, the input list length or input list address and the length of the input list identified by the Incomplete Input List Number (IILN) should be updated appropriately.

[0435] If the Empty Input List Flag (EILF) is 1, the input list length or input list address and the length of the input list identified by the Empty Input List Number (EILN) should be updated appropriately.

[0436] If IILF is zero, EILF is zero, and the length of input list0 is zero, then the length of input list0 or the address and length of input list0 should be updated appropriately. Additionally, the address and length of the active input list can also be updated, which might be appropriate if there is only one record initially specified by input list0 and the empty input list control (EILCL) is binary 10.

[0437] If the merge mode (MM) is 1 and the first operand length is less than the maximum record length of the record being processed, then the first operand length or the first operand address and length should be updated appropriately.

[0438] If MM is zero and IILF is 1 or EILF is 1, then the address and length of the first operand and the address and length of the second operand should not be updated.

[0439] If MM is zero, IILF is zero, EILF is zero, and the length of the first operand is less than the maximum record length of the record being processed, then the length of the first operand or the address and length of the first operand should be updated appropriately.

[0440] If MM is zero, IILF is zero, EILF is zero, and the second operand length is less than 16, then the second operand length or the second operand address and length should be updated appropriately.

[0441] As described herein, in one aspect, a single instruction (e.g., a single architectural machine instruction, list sorting) is provided to perform sorting and / or merging operations on a general-purpose processor. In one example, a program implementing sorting and / or merging operations against a database and executing on a general-purpose processor can replace a significant subset of basic instructions to implement the operation with a single instruction. This instruction is, for example, a hardware instruction defined in an instruction set architecture (ISA). As a result, the complexity of the program associated with sorting and / or merging operations is reduced. Furthermore, the performance of the operation is improved, and thus the performance of the processor is improved.

[0442] Advantageously, list sorting instructions are executed on a general-purpose processor (e.g., a central processing unit, referred to herein as a processor) rather than a dedicated processor (such as a graphics processing unit (GPU), a database engine (DBE), or other types of dedicated processors).

[0443] Although different fields and registers are described, one or more aspects of the invention may use other, additional, or fewer fields or registers, or fields and registers of other sizes, etc. Many variations are possible. For example, implicit registers may be used in place of explicitly specified instruction registers or fields, and / or explicitly specified registers or fields may be used in place of implicit registers or fields. Other variations are also possible.

[0444] In one example, list sorting instructions operate on large amounts of data (such as megabytes or terabytes) in a database (e.g., a commercial database). Therefore, according to one aspect of the invention, one or more controls are provided to guide the behavior of a merge operation to minimize data access and the amount of data moved between memory and processor storage devices.

[0445] As an example, one or more controls include an empty input list control (EILCL), an empty input list flag (EILF), and an empty input list number (EILN). In one example, input list number 0 has an empty input list control that is independent of the other input lists.

[0446] The following example illustrates the difference in storage access between processing a merge operation without EILCL and processing a merge operation with EILCL (for the same input data):

[0447] EILCL: Objective: Minimize the number of data transfers.

[0448] - Enables software (e.g., a program) to merge large lists of inputs with minimal access to data in memory.

[0449] - The hardware supports a limited number of input lists.

[0450] The input to the merge operation is multiple lists, where each list contains multiple records in sorted order.

[0451] - The software maintains the metadata for each list that needs to be merged.

[0452] - Metadata includes the key value of the first record in the list to be processed.

[0453] - Each time the software invokes the sort / merge hardware, the software specifies the input to the hardware as a subset of a list containing the lowest first record key value (for ascending sort). The software specifies a single record for hardware IL0, which is the first record in the list that has the lowest key value (metadata) among the remaining lists (lists that are not being processed by calls to SORTL instructions).

[0454] -Suitable for sorting in ascending and descending order.

[0455] Example: Demonstrate the difference between processing merge operations without EILCL and processing merge operations with EILCL (for the same input data).

[0456] Machine: Each operation processes up to 4 input lists (ILs).

[0457] Input: 8 lists (each list contains, for example, 3 records in sorted order)

[0458] Order: Ascending

[0459]

[0460] No EILCL:

[0461] Operation 1: Merge L01, L02, L03, and L04 into a new list L11:

[0462]

[0463]

[0464] Operation 2: Merge L05, L06, L07, and L08 into a new list L21:

[0465] Operation 3: Merge L11 and L21 into the final list L31:

[0466]

[0467]

[0468] With EILCL:

[0469] The software maintains metadata (MD) for each list, including, for example, the key-value pair of the next record to be processed in the list.

[0470]

[0471] Operation 1: EILCL = "10"b, generate a new list: L11

[0472] IL0: L04-1 record: 21 (first record in the list with the fourth lowest metadata value)

[0473] IL1: L03 (List of metadata values ​​with the lowest values)

[0474] IL2: L01 (List of metadata values ​​with the second lowest value)

[0475] IL3: L05 (List of metadata values ​​with the third lowest value)

[0476]

[0477] Metadata for the list processed by software updates:

[0478]

[0479] Operation 2: EILCL = "10"b, append the result to L11

[0480] IL0: L08-1 record: 43 (first record in the list with the fourth lowest metadata value)

[0481] IL1: L01 (List of metadata values ​​with the lowest values)

[0482] IL2: L02 (List of metadata values ​​with the second lowest value)

[0483] IL3: L05 (List of metadata values ​​with the third lowest value)

[0484]

[0485] Metadata for the list processed by software updates:

[0486]

[0487] Operation 3: EILCL = "10"b, append the result to L11

[0488] IL0: L08-1 record: 63 (first record in the list with the fourth lowest metadata value)

[0489] IL1: L06 (List of metadata values ​​with the lowest values)

[0490] IL2: L02 (List of metadata values ​​with the second lowest value)

[0491] IL3:L04 (List of metadata values ​​with the third lowest value)

[0492]

[0493] Metadata for the list processed by software updates:

[0494]

[0495] Operation 4: EILCL = "10"b, append the result to L11

[0496] IL0: L06-1 record: 79 (first record in the list with the fourth lowest metadata value)

[0497] IL1: L03 (List of metadata values ​​with the lowest values)

[0498] IL2: L07 (List with the second lowest metadata value)

[0499] IL3: L08 (List of metadata values ​​with the third lowest value)

[0500]

[0501] Metadata for the list processed by software updates:

[0502]

[0503]

[0504] Operation 5: EILCL = "10"b, append the result to L11

[0505] IL0: L02-1 record: 90 (first record in the list with the fourth lowest metadata value)

[0506] IL1: L04 (List of metadata values ​​with the lowest values)

[0507] IL2: L05 (List of items with the second lowest metadata value)

[0508] IL3: L07 (List of metadata values ​​with the third lowest value)

[0509]

[0510] Metadata for the list processed by software updates:

[0511]

[0512]

[0513] Operation 6: EILCL = "00"b (Merge 2 lists - no need to stop, until fully completed), append the result to L11

[0514] IL0: L06 (Only one of the remaining two lists)

[0515] IL1:L07 (Only one of two remaining lists)

[0516] IL2: Not used

[0517] IL3: Not used

[0518]

[0519]

[0520] Note: - The storage device is accessed once for each record.

[0521] Although in this simple example, the procedure using EILCL executes 6 SORTL instructions instead of 3 (without EILCL), in typical use cases, a procedure using EILCL is less likely to make more calls to SORTL instructions than a procedure without EILCL. In one example, a typical use case has the following properties:

[0522] The SORTL command can handle more than four input lists.

[0523] Each list contains significantly more records.

[0524] The input includes a significantly larger list.

[0525] - In one embodiment, when considering overall performance, reducing the number of storage device accesses associated with each record is more important than the overall time consumed by executing SORTL instructions multiple times.

[0526] One or more aspects of this invention are inextricably linked to computer technology and facilitate processing within computers, thereby improving their performance. Using control to guide the behavior of operations (e.g., merge operations) when a particular input list becomes empty reduces data access, reduces the amount of data transferred, improves the performance of the operation, and improves the overall performance within the computing environment. Merged records can be used in many technical fields that manage and / or use large amounts of data, such as computer processing, medical procedures, security, etc. By providing optimization in sorting / merging, these technical fields are improved by reducing execution time when acquiring and using information, and by reducing storage requirements.

[0527] See Figure 10This describes an embodiment of a process associated with control used to guide the behavior of operations, such as merging operations. In one example, the process is performed by a processor (e.g., processor 102 or 204).

[0528] See Figure 10 Step 1000: Execute an instruction such as a list sorting instruction, another instruction to perform a merge, or another instruction that may use an input list that may have become empty. In this example, the instruction is a list sorting instruction that performs a merge operation on multiple input lists. Query 1002: Determine whether the input list of the instruction has become empty (e.g., the length of the input list has become zero). Step 1004: If it is determined that the input list has become empty, in one example, check the control (e.g., EILCL 378). As an example, the control includes an indicator for the input list0 (list 0) and another indicator for other input lists. The control indicators being checked are based on an empty input list. For example, if the empty input list is list0, the corresponding indicator of EILCL is checked (e.g., bit 0 of EILCL); and if the empty input list is not list0, other corresponding indicators of EILCL are checked (e.g., bit 1 of EILCL).

[0529] If the checked control indicator is set to a defined value (e.g., 0), query 1006, then in step 1008, the operation executed by the instruction (e.g., a merge operation) continues. However, if the checked control indicator is not set to a defined value, but to another value (e.g., 1), then in step 1010, the operation ends.

[0530] Further, in one embodiment, based on the operation ending because the input list becomes empty, a further determination is made regarding whether a control (e.g., EILCL) is set to a selected value (e.g., EILCL0:1 equals 11'b'), query 1012. If the value of EILCL is set to the selected value, then it is further determined whether the condition code (CC) generated by the execution of the instruction is set to a specific value (e.g., CC = 2), query 1014. Step 1016, based on EILCL being set to, for example, 11'b', the operation ending because the length of the active input list is equal to, for example, zero, and the condition code being set to, for example, 2, another control (e.g., EILF380) is set to the selected value (e.g., 1). Step 1018, further, an indication of an empty input list is stored. For example, the input list number of the empty input list is placed in the EILN field 382 of the parameter block.

[0531] Returning to query 1002, the process ends if the input list is not yet empty. Similarly, the process ends if the control is not set to a selected value (query 1012), or if the condition code is not set to a specific value (query 1014).

[0532] See Figure 11A-11B Further details are described for one embodiment that facilitates processing within a computing environment, as it relates to one or more aspects of the invention.

[0533] Reference Figure 11A In one embodiment, multiple records from multiple input lists are merged (1100). The merging includes, for example, determining that one of the multiple input lists has become empty (1102), and based on the determination that the input list has become empty, checking a control dedicated to that input list, which determines how to proceed (1104). Based on the control, processing is performed (1106).

[0534] In one example, the execution process includes ending the merge based on the control being a value (1108), and in another example, the execution process includes continuing the merge based on the control being another value (1110).

[0535] In one embodiment, the control includes a plurality of indicators (1112), and one of the plurality of indicators is assigned to a selection input list in a plurality of input lists, and another of the plurality of indicators is assigned to a other input list in a plurality of input lists (1114).

[0536] Furthermore, in one embodiment, see [link to embodiment]. Figure 11B The system makes a determination (1116) on whether to store the indication that the input list has become empty in the selected location. This determination is based at least in part on the control (1118). Based on the determination that the indication should be stored, the indication of the input list is stored in the selected location (1120).

[0537] As an example, determining whether to store the indication includes checking another control (1122). The other control, set to a selection value, indicates that the indication should be stored in the selection location (1124). The other control is set in part based on the control mentioned above (1126).

[0538] In one embodiment, another control is set (1128). Setting includes checking whether the control is a defined value (1130) and determining whether a specific condition code has been set, wherein based on the control being a defined value and the specific condition code being set, the other control is set to a selection value (1132).

[0539] As an example, the control is specified by an instruction (1134), such as a sorting instruction (1136). In one example, the sorting instruction is defined based on a selected instruction set architecture (1138). In one embodiment, the instruction specifies the location of a parameter block in memory, which includes the control (1140).

[0540] Other variations and embodiments are possible.

[0541] This invention can be used in many types of computing environments. See also Figure 12A Another embodiment of a computing environment incorporating and utilizing one or more aspects of the present invention is described. In this example, computing environment 10 includes, for example, a local central processing unit (CPU) 12, memory 14, and one or more input / output devices and / or interfaces 16 coupled to each other via, for example, one or more buses 18 and / or other connections. As an example, computing environment 10 may include International Business Machines Corporation of Armonk, New York. Processor; HP Superdome equipped with an Intel Itanium II processor, supplied by Hewlett-Packard, Palo Alto, California, USA; and / or other machines based on architectures supplied by International Business Machines Corporation, HP, Intel Corporation, Oracle, or other companies. IBM, z / Architecture, IBM Z, z / OS, PR / SM, and PowerPC are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction. Intel and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the U.S. and other countries.

[0542] The local central processing unit 12 includes one or more local registers 20, such as one or more general-purpose registers and / or one or more special-purpose registers used during processing within the environment. These registers include information representing the state of the environment at any given point in time.

[0543] Furthermore, the local central processing unit 12 executes instructions and code stored in memory 14. In a particular example, the central processing unit executes emulator code 22 stored in memory 14. This code enables a computing environment configured in one architecture to emulate another architecture. For example, emulator code 22 allows machines based on architectures other than the z / Architecture hardware architecture (such as PowerPC processors, HP Superdome servers, or others) to emulate the z / Architecture hardware architecture and execute software and instructions developed based on the z / Architecture hardware architecture.

[0544] refer to Figure 12BFurther details relating to emulator code 22 are described below. Client instructions 30 stored in memory 14 include software instructions (e.g., machine instructions) developed for execution in an architecture different from that of the native CPU 12. For example, client instructions 30 may have been designed to execute on a z / Architecture-based hardware processor, but are instead emulated on a native CPU 12, which could be, for example, an Intel Itanium II processor. In one example, emulator code 22 includes an instruction fetch routine 32 to fetch one or more client instructions 30 from memory 14, and optionally provides a local buffer for the fetched instructions. It also includes an instruction translation routine 34 to determine the type of the fetched client instructions and translate them into one or more corresponding native instructions 36. This translation includes, for example, identifying the function to be executed by the client instructions and selecting native instructions to execute said function.

[0545] Furthermore, emulator code 22 includes an emulation control routine 40 to cause native instructions to be executed. The emulation control routine 40 causes the local CPU 12 to execute a native instruction routine that emulates one or more previously fetched client instructions, and upon completion of this execution, returns control to the instruction fetch routine to emulate the fetching of the next client instruction or a set of client instructions. Execution of native instruction 36 may include, as determined by the translation routine, loading data from memory 14 into a register; storing data from a register back into memory; or performing some type of arithmetic or logical operation.

[0546] Each routine is implemented, for example, in software, which is stored in memory and executed by the local central processing unit 12. In other examples, one or more routines or operations are implemented in firmware, hardware, software, or a combination thereof. The registers of the emulated processor can be simulated using the local CPU's registers 20 or by using locations in memory 14. In embodiments, client instructions 30, native instructions 36, and emulator code 22 may reside in the same memory or may be distributed across different memory devices.

[0547] The computing environment described above is merely an example of a usable computing environment. Other environments may be used, including but not limited to other non-partitioned environments, other partitioned environments, and / or other simulation environments; the embodiments are not limited to any one of these environments.

[0548] Each computing environment can be configured to include one or more aspects of the present invention. For example, according to one or more aspects of the present invention, each computing environment can be configured to provide sorting and / or merging capabilities.

[0549] One or more aspects may involve cloud computing.

[0550] It should be understood that although this disclosure includes a detailed description of cloud computing, the implementation of the teachings cited herein is not limited to cloud computing environments. Rather, embodiments of the invention can be implemented in conjunction with any other type of computing environment now known or developed hereafter.

[0551] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, storage, applications, virtual machines, and services) that can be rapidly configured and deployed with minimal management effort or interaction with a service provider. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0552] The features are as follows:

[0553] On-demand self-service: Cloud consumers can automatically and unilaterally supply computing power, such as server time and network storage, on demand, without any manual interaction with service providers.

[0554] Extensive network access: Functionality is provided via a network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0555] Resource pooling: Providers' computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically allocated and reallocated as needed. Location independence is significant because consumers typically do not have control or knowledge of the exact location of the resources provided, but may be able to specify locations at higher levels of abstraction (e.g., country, state, or data center).

[0556] Rapid and flexible: In certain situations, features can be configured quickly and flexibly to rapidly expand and shrink and quickly release to shrink again. For consumers, the available features often appear unlimited, and can be purchased in any quantity at any time.

[0557] Measurable services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at some level of abstraction appropriate to the service type (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both service providers and users.

[0558] The service model is as follows:

[0559] Software as a Service (SaaS): This provides consumers with the ability to use the provider's applications running on cloud infrastructure. These applications can be accessed from different client devices through thin client interfaces such as web browsers (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, storage, or even individual application functionality, with possible exceptions such as limited user-specific application configuration settings.

[0560] Platform as a Service (PaaS): This provides consumers with the capability to deploy consumer-created or acquired applications on cloud infrastructure, using programming languages ​​and tools supported by the provider. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they have control over the deployed applications and, if any, the configuration of the application hosting environment.

[0561] Infrastructure as a Service (IaaS): This provides consumers with the ability to deploy and run processing, storage, networking, and other basic computing resources that can include any software, including operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but rather have control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

[0562] The deployment model is as follows:

[0563] Private cloud: A cloud infrastructure operated solely by an organization. It can be managed by the organization or a third party and can exist on-site or off-site.

[0564] Community cloud: A cloud infrastructure shared by multiple organizations that supports a specific community with common concerns (e.g., mission, security requirements, policies, and compliance considerations). It can be managed by an organization or a third party and can exist on-site or off-site.

[0565] Public cloud: Cloud infrastructure available to the public or large industry groups and owned by organizations that sell cloud services.

[0566] Hybrid cloud: A cloud infrastructure consisting of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0567] Cloud computing environments are service-oriented, emphasizing statelessness, loose coupling, modularity, and semantic interoperability. The core of cloud computing is its infrastructure, which includes a network of interconnected nodes.

[0568] Now see Figure 13The diagram illustrates an illustrative cloud computing environment 50. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 52, and local computing devices used by cloud consumers (such as personal digital assistants (PDAs) or cellular phones 54A, desktop computers 54B, laptop computers 54C, and / or automotive computer systems 54N) can communicate with the cloud computing nodes 52. The nodes 52 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as in a private cloud, community cloud, public cloud, or hybrid cloud or a combination thereof as described above. This allows the cloud computing environment 50 to provide infrastructure, platform, and / or software as a service, without requiring cloud consumers to maintain resources on their local computing devices. It should be understood that... Figure 13 The types of computing devices 54A-N shown are intended to be illustrative only, and computing node 52 and cloud computing environment 50 can communicate with any type of computerized device via any type of network and / or network-addressable connection (e.g., using a web browser).

[0569] Now see Figure 14 This demonstrates a cloud computing environment of 50 ( Figure 13 This provides a set of functional abstractions. It should be understood beforehand that... Figure 14 The components, layers, and functions shown are intended to be illustrative only, and embodiments of the invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0570] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include: a host 61; a server 62 based on a RISC (Reduced Instruction Set Computer) architecture; a server 63; a blade server 64; storage 65; and networking and interconnection components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0571] The virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual server 71; virtual storage 72; virtual network 73, including virtual private network; virtual application and operating system 74; and virtual client 75.

[0572] In one example, management layer 80 provides the functionality described below. Resource provisioning 81 provides dynamic acquisition of computing resources and other resources for performing tasks within the cloud computing environment. Metering and pricing 82 provides cost tracking as resources are utilized within the cloud computing environment and bills or invoices for the consumption of these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection for data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud resource allocation and management to ensure the required service level is met. Service level agreement (SLA) planning and fulfillment 85 provides pre-scheduling and procurement of cloud resources for future requirements of cloud resources anticipated according to the SLA.

[0573] Workload layer 90 provides examples of functionalities that can be leveraged in a cloud computing environment. Examples of workloads and functionalities that can be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analytics and processing 94; transaction processing 95; and sorting and / or merging processing 96.

[0574] Various aspects of the present invention can be systems, methods, and / or computer program products at any possible level of technical detail integration. The computer program product may comprise a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the present invention.

[0575] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital universal disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in grooves having instructions recorded thereon), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0576] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards these instructions for storage in a computer-readable storage medium within the corresponding computing / processing device.

[0577] The computer-readable program instructions used to perform the operations of this technical solution may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, as well as procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet through an Internet service provider). In some embodiments, electronic circuits (including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs)) may execute computer-readable program instructions using status information to personalize the electronic circuits in order to perform aspects of this technical solution.

[0578] This technical solution is described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the technical solution. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0579] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, which executes via the processor of the computer or other programmable data processing apparatus, creating means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium capable of instructing a computer, a programmable data processing apparatus, and / or other devices that function in a particular manner, such that the computer-readable storage medium having the instructions stored therein includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0580] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other apparatus, other programmable apparatus or other devices that cause a series of operational steps to be performed on a computer to produce a computer-implemented process, causing the instructions to be executed on a computer, other programmable apparatus or other devices to implement the functions and actions specified in one or more boxes of a flowchart and / or block diagram.

[0581] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to different embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or part of an instruction, including one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0582] In addition to the above, one or more aspects may be provided, committed to, deployed, managed, serviced, etc., by a service provider that provides customer environment management. For example, a service provider may create, maintain, and support computer code and / or computer infrastructure that executes one or more aspects for one or more customers. In return, the service provider may receive payments from consumers, for example, under subscription and / or fee agreements. Additionally or alternatively, the service provider may receive payments from the sale of advertising content to one or more third parties.

[0583] In one aspect, an application for performing one or more embodiments can be deployed. As an example, deploying the application includes providing computer infrastructure operable for performing one or more embodiments.

[0584] On the other hand, deployable computing infrastructure includes integrating computer-readable code into a computing system, wherein the code combined with the computing system is capable of executing one or more embodiments.

[0585] In another aspect, a process for integrating computing infrastructure can be provided, the process including integrating computer-readable code into a computer system. The computer system includes a computer-readable medium, wherein the computer medium includes one or more embodiments. The code integrated with the computer system is capable of executing one or more embodiments.

[0586] While various embodiments have been described above, these are merely examples. For instance, computing environments with other architectures can be used to include and utilize one or more embodiments. Furthermore, different instructions or operations can be used. Additionally, different registers can be used and / or other types of instructions (besides register numbers) can be specified. Many variations are possible.

[0587] Furthermore, other types of computing environments can benefit and can be used. As an example, a data processing system suitable for storing and / or executing program code is available, comprising at least two processors directly or indirectly coupled to memory elements via a system bus. Memory elements include, for example, local memory used during the actual execution of the program code, mass storage devices, and cache memory providing temporary storage for at least some of the program code to reduce the number of times code must be retrieved from mass storage devices during execution.

[0588] Input / output (I / O) devices (including but not limited to keyboards, monitors, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other storage media) can be coupled to the system directly or via an intermediate I / O controller. Network adapters can also be coupled to the system, enabling the data processing system to be coupled to other data processing systems or remote printers or storage devices via an intermediary private or public network. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.

[0589] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprising” and / or “including” are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0590] All means or steps in the following claims, plus the corresponding structures, materials, actions, and equivalents of functional elements (if any), are intended to include any structure, material, or action for performing the function in conjunction with other claimed elements as specifically claimed. Descriptions of one or more embodiments have been given for purposes of illustration and description, but are not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to best explain various aspects and practical applications, and to enable those skilled in the art to understand different embodiments with different modifications suitable for the particular intended use.

Claims

1. A computer program product for facilitating processing in a computing environment, the computer program product comprising: A computer-readable storage medium, which is processor-readable and stores instructions for performing a method comprising: The processor merges multiple records from multiple input lists, wherein the merging includes: Determine that the input list in the plurality of input lists has become empty; Based on the determination that the input list has become empty, a control dedicated to the input list is checked. This control, which serves as an input to the merge, is set before the merge and is not updated during the merge. The control includes multiple indicators, each having one or more bits. A first indicator of the multiple indicators is assigned to a selected input list in the multiple input lists to control processing based on the selected input list becoming empty during the merge. A second indicator of the multiple indicators is assigned to other input lists in the multiple input lists, which do not include the selected input list. The second indicator controls processing based on the other input lists becoming empty during the merge. The checking step includes determining that the empty input list is the selected input list in the multiple input lists, and based on the determination that the selected input list has become empty, checking the first indicator of the control dedicated to the selected input list; and Based on the control, the execution process includes: the first indicator based on the control is set to another value and the selected input list becomes empty while the merging continues.

2. The computer program product as claimed in claim 1, wherein, The execution process includes setting the first indicator based on the control to a value and the selected input list becoming empty, thereby ending the merge.

3. The computer program product as described in claim 1, wherein, The checking step includes determining that the empty input list is another input list among the plurality of input lists, checking the second indicator of the control dedicated to the other input list based on the determination that the other input list is empty, and the execution process includes continuing the merging based on the second indicator of the control being set to a selected value and the other input list being empty.

4. The computer program product of claim 1, wherein the control is included in a parameter block.

5. The computer program product as claimed in claim 1, wherein, The method further includes: Determining whether an indication that the input list has become empty should be stored in the selected location, the determination being at least in part based on the control; and Based on the determination that the instruction should be stored, the instruction from the input list is stored at the selected location.

6. The computer program product as described in claim 5, wherein, Determining whether to store the instruction includes checking another control, which is set to a selection value, indicating that the instruction should be stored in the selected location. This other control is set in part based on the instruction.

7. The computer program product as claimed in claim 6, wherein, The method further includes setting the other control, which includes: Check if the control is a defined value; and Determine whether a specific condition code has been set, wherein, based on the control being the defined value and the specific condition code being set, the other control is set to the selected value.

8. The computer program product as claimed in claim 1, wherein, The control is specified by instructions.

9. The computer program product as claimed in claim 8, wherein, The instructions include sorting instructions, which are defined based on the selected instruction set architecture.

10. The computer program product as claimed in claim 8, wherein, The instruction specifies the location of the parameter block in memory that includes the control.

11. A computer system for facilitating processing in a computing environment, the computer system comprising: Memory; as well as A processor communicating with the memory, wherein the computer system is configured to perform a method comprising: The processor merges multiple records from multiple input lists, wherein the merging includes: Determine that the input list in the plurality of input lists has become empty; Based on the determination that the input list has become empty, a control dedicated to the input list is checked. This control, which serves as an input to the merge, is set before the merge and is not updated during the merge. The control includes multiple indicators, each having one or more bits. A first indicator of the multiple indicators is assigned to a selected input list in the multiple input lists to control processing based on the selected input list becoming empty during the merge. A second indicator of the multiple indicators is assigned to other input lists in the multiple input lists, which do not include the selected input list. The second indicator controls processing based on the other input lists becoming empty during the merge. The checking step includes determining that the empty input list is the selected input list in the multiple input lists, and based on the determination that the selected input list has become empty, checking the first indicator of the control dedicated to the selected input list; and Based on the control, the execution process includes: the first indicator based on the control is set to another value and the selected input list becomes empty while the merging continues.

12. The computer system of claim 11, wherein, The execution process includes setting the first indicator based on the control to a value and the selected input list becoming empty, thereby ending the merge.

13. The computer system of claim 11, wherein the checking step includes determining that the empty input list is another input list among the plurality of input lists, checking a second indicator of control dedicated to the other input list based on determining that the other input list is empty, and the execution process includes continuing the merging based on the second indicator of the control being set to a selected value and the other input list being empty.

14. The computer system of claim 11, wherein, The method further includes: Determining whether an indication that the input list has become empty should be stored in the selected location, the determination being at least in part based on the control; and Based on the determination that the instruction should be stored, the instruction from the input list is stored at the selected location.

15. The computer system of claim 14, wherein, Determining whether to store the instruction includes checking another control, which is set to a selection value, indicating that the instruction should be stored in the selected location. This other control is set in part based on the instruction.

16. A computer-implemented method for facilitating processing in a computing environment, the computer-implemented method comprising: The processor merges multiple records from multiple input lists, wherein the merging includes: Determine that the input list in the plurality of input lists has become empty; Based on the determination that the input list has become empty, a control dedicated to the input list is checked. This control, which serves as an input to the merge, is set before the merge and is not updated during the merge. The control includes multiple indicators, each having one or more bits. A first indicator of the multiple indicators is assigned to a selected input list in the multiple input lists to control processing based on the selected input list becoming empty during the merge. A second indicator of the multiple indicators is assigned to other input lists in the multiple input lists, which do not include the selected input list. The second indicator controls processing based on the other input lists becoming empty during the merge. The checking step includes determining that the empty input list is the selected input list in the multiple input lists, and based on the determination that the selected input list has become empty, checking the first indicator of the control dedicated to the selected input list; and Based on the control, the execution process includes: the first indicator based on the control is set to another value and the selected input list becomes empty while the merging continues.

17. The computer implementation method as described in claim 16, wherein, The execution process includes setting the first indicator based on the control to a value and the selected input list becoming empty, thereby ending the merge.

18. The computer-implemented method as described in claim 16, wherein, The checking step includes determining that the empty input list is another input list among the plurality of input lists, checking the second indicator of the control dedicated to the other input list based on the determination that the other input list is empty, and the execution process includes continuing the merging based on the second indicator of the control being set to a selected value and the other input list being empty.

19. The computer-implemented method of claim 16, further comprising: Determining whether an indication that the input list has become empty should be stored in the selected location, the determination is based at least in part on the control; and Based on the determination that the instruction should be stored, the instruction from the input list is stored at the selected location.

20. The computer-implemented method as described in claim 19, wherein, Determining whether to store the instruction includes checking another control, which is set to a selection value, indicating that the instruction should be stored in the selected location. This other control is set in part based on the instruction.

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