Adapter plate, forming method thereof, packaging method and packaging structure

Abstract

A transfer board and its forming method, packaging method, and packaging structure, the transfer board forming method comprising: providing a substrate including an interconnection region and a capacitor region, the substrate including a front side and a back side facing each other; etching the front side of the substrate to form a first groove in the substrate in the interconnection region and a second groove in the substrate in the capacitor region; forming a capacitor in the second groove; etching a portion of the thickness of the substrate below the first groove to form a conductive through-hole; forming a through-hole interconnection structure in the conductive through-hole; and thinning the back side of the substrate to expose the through-hole interconnection structure. The embodiment of the present invention also forms a capacitor in the transfer board, thereby integrating the processes of forming the capacitor and forming the transfer board, eliminating the additional step of forming the capacitor, which is beneficial for saving process steps, improving process integration, and thus reducing process costs and shortening production cycles. It also increases the functional diversity of the transfer board, thereby diversifying the application scenarios of the transfer board.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to an adapter board and a forming method, a packaging method, and a packaging structure thereof. Background Art

[0002] With the advancement of technology, three-dimensional (3D) integrated circuits (or 2.5D integrated circuits, etc.) based on silicon interposers have become the most promising solutions to enhance system performance, reduce power consumption, and support heterogeneous integration.

[0003] A silicon interposer is a connection structure made of silicon wafers, similar to a printed circuit board (PCB), but with smaller line widths and node spacing. Chips with different functions, such as CPUs and DRAM, can be connected to the same silicon interposer, allowing for many calculations and data exchanges to be performed through the interposer, saving power and increasing bandwidth. Furthermore, silicon interposers offer advantages such as reduced signal length, scalability for heterogeneous integration, and increased yield rates for system-on-chip (SOC) products.

[0004] Similar to a PCB, a silicon interposer typically features through-silicon vias (TSVs) interconnects. The results of joint computations between different chips can be transmitted to the connected circuit board via TSVs. Therefore, the silicon interposer acts as a bridge connecting multiple chips to the same circuit board. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a transfer board and a forming method thereof, a packaging method and a packaging structure, so as to improve the performance of the device.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming an adapter plate, comprising: providing a substrate, comprising an interconnection area for forming a through-hole interconnection structure, and a capacitor area for forming a capacitor, the substrate comprising a front side and a back side opposite to each other; etching the front side of the substrate to form a first groove in the substrate of the interconnection area, and forming a second groove in the substrate of the capacitor area; forming a capacitor in the second groove, the capacitor comprising a first electrode located on the sidewall and bottom of the second groove, a capacitor dielectric layer located on the first electrode, and a second electrode located on the capacitor dielectric layer, the second electrode filling the second groove; after forming the capacitor, etching a portion of the thickness of the substrate below the first groove to form a groove in the substrate, the groove and the first groove constituting a conductive through-hole; forming a through-hole interconnection structure in the conductive through-hole; thinning the back side of the substrate to expose the through-hole interconnection structure on the back side of the substrate.

[0007] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing a circuit board; bonding the adapter board provided by the embodiment of the present invention to the circuit board, so that the through-hole interconnection structure is electrically connected to the circuit board, and the back side of the substrate is arranged opposite to the circuit board; providing a chip; bonding the chip to the adapter board formed by the method for forming the adapter board provided by the embodiment of the present invention, so that the chip is electrically connected to the capacitor, and the chip is electrically connected to the through-hole interconnection structure, wherein the chip is located on the front side of the substrate.

[0008] Correspondingly, an embodiment of the present invention also provides a transfer board, comprising: a substrate, comprising an interconnection area for forming a through-hole interconnection structure, and a capacitor area for forming a capacitor, the substrate comprising a front side and a back side facing each other; a capacitor located in a partial thickness of the substrate in the capacitor area, the capacitor comprising a first electrode in contact with the substrate, a capacitor dielectric layer located on the first electrode, and a second electrode located on the capacitor dielectric layer, the side walls of the second electrodes are in contact, and the top surface of the capacitor faces away from the back side of the substrate; a through-hole interconnection structure running through the substrate of the interconnection area.

[0009] Correspondingly, an embodiment of the present invention also provides a packaging structure, including: a circuit board; an adapter board provided by an embodiment of the present invention, bonded to the circuit board, the through-hole interconnection structure is electrically connected to the circuit board, and the back side of the substrate is arranged opposite to the circuit board; a chip, bonded to the adapter board, the chip is electrically connected to the capacitor, and the chip is electrically connected to the through-hole interconnection structure, wherein the chip is located on the front side of the substrate.

[0010] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0011] In the method for forming the adapter plate provided by an embodiment of the present invention, the front surface of the substrate is etched to form not only a first groove in the substrate in the interconnection area, but also a second groove in the substrate in the capacitor area; then, a capacitor is formed in the second groove, and the substrate is etched partially below the first groove to form a groove in the substrate, the groove and the first groove constitute a conductive through-hole, and a through-hole interconnection structure is formed in the conductive through-hole; therefore, the embodiment of the present invention also forms the capacitor in the adapter plate, thereby integrating the process of forming the capacitor and forming the adapter plate, eliminating the additional step of forming the capacitor, which is beneficial to saving process steps, improving process integration, and thus helping to reduce process costs and shorten production cycles; moreover, the adapter plate provided by an embodiment of the present invention also has capacitors formed therein, which is beneficial to improving the functional diversity of the adapter plate, thereby diversifying the application scenarios of the adapter plate.

[0012] In the packaging method provided by the embodiment of the present invention, the adapter board formed by the method for forming the adapter board provided by the embodiment of the present invention is bonded to the circuit board, so that the through-hole interconnection structure is electrically connected to the circuit board, and the chip is bonded to the adapter board, so that the chip is electrically connected to the capacitor, and the chip is electrically connected to the through-hole interconnection structure; wherein the front side of the substrate is arranged opposite to the chip, and the back side of the substrate is arranged opposite to the circuit board. Compared with the solution of bonding the capacitor to the circuit board and locating the capacitor between the adapter board and the circuit board, the capacitor in the embodiment of the present invention is formed in the adapter board, and the distance between the capacitor and the chip is smaller, which is conducive to improving the RC delay of the device, increasing the signal transmission rate, and thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural diagram of a packaging structure;

[0014] Figures 2 to 9 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming an adapter plate of the present invention;

[0015] Figure 10 It is a structural schematic diagram corresponding to each step in an embodiment of the packaging method of the present invention. DETAILED DESCRIPTION

[0016] The devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a packaging structure.

[0017] refer to Figure 1 , showing a structural schematic diagram of a packaging structure.

[0018] The packaging structure includes: a circuit board 1; a capacitor 2, bonded to the circuit board 1 and electrically connected to the circuit board 1; an adapter board 3, the adapter board 3 including a substrate 4 and a through-hole interconnection structure 5 passing through the substrate 4, the substrate 4 including a front side 41 and a back side 42 opposite to each other, the back side of the substrate 4 bonded to the circuit board 1 and located on the capacitor 2, the through-hole interconnection structure 5 electrically connected to the circuit board 1, and the through-hole interconnection structure 5 is also electrically connected to the capacitor 2; a chip 6, bonded to the front side 41 of the substrate 4, the chip 6 is electrically connected to the capacitor 2, and the chip 6 is electrically connected to the through-hole interconnection structure 5.

[0019] In the above-mentioned packaging structure, the capacitor 2 is bonded to the circuit board 1, and the capacitor 2 is located between the adapter board 3 and the circuit board 1. The distance between the capacitor 2 and the chip 6 is relatively far, which can easily worsen the signal delay problem between the capacitor 2 and the chip 6 and increase power consumption. For example, when the chip 6 is a CPU, it can easily reduce the performance of the device. Moreover, the capacitor 2 is bonded to the circuit board 1, and the process of forming the packaging structure requires an additional separate process for forming the capacitor 2, which can easily lead to a complicated process flow and high process cost.

[0020] In order to solve the technical problem, an embodiment of the present invention provides a method for forming an adapter plate, comprising: providing a substrate, comprising an interconnection area for forming a through-hole interconnection structure, and a capacitor area for forming a capacitor, the substrate comprising a front side and a back side opposite to each other; etching the front side of the substrate to form a first groove in the substrate of the interconnection area, and forming a second groove in the substrate of the capacitor area; forming a capacitor in the second groove, the capacitor comprising a first electrode located on the sidewall and bottom of the second groove, a capacitor dielectric layer located on the first electrode, and a second electrode located on the capacitor dielectric layer, the second electrode filling the second groove; after forming the capacitor, etching a portion of the thickness of the substrate below the first groove to form a groove in the substrate, the groove and the first groove constituting a conductive through-hole; forming a through-hole interconnection structure in the conductive through-hole; and thinning the back side of the substrate to expose the through-hole interconnection structure on the back side of the substrate.

[0021] In the method for forming the adapter plate provided by an embodiment of the present invention, the front surface of the substrate is etched to form not only a first groove in the substrate in the interconnection area, but also a second groove in the substrate in the capacitor area; then, a capacitor is formed in the second groove, and the substrate is etched partially below the first groove to form a groove in the substrate, the groove and the first groove constitute a conductive through-hole, and a through-hole interconnection structure is formed in the conductive through-hole; therefore, the embodiment of the present invention also forms the capacitor in the adapter plate, thereby integrating the process of forming the capacitor and forming the adapter plate, eliminating the additional step of forming the capacitor, which is beneficial to saving process steps, improving process integration, and thus helping to reduce process costs and shorten production cycles; moreover, the adapter plate provided by an embodiment of the present invention also has capacitors formed therein, which is beneficial to improving the functional diversity of the adapter plate, thereby diversifying the application scenarios of the adapter plate.

[0022] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] Figures 2 to 9 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming an adapter plate of the present invention.

[0024] refer to Figure 2 , providing a substrate 100, including an interconnection region I for forming a through-hole interconnection structure, and a capacitance region II for forming a capacitor, the substrate 100 includes a front side 11 and a back side 12 facing each other.

[0025] The substrate 100 is used to provide a platform for subsequent process steps.

[0026] In this embodiment, the substrate 100 serves as an interposer for isolating the through-hole interconnect structure and the capacitor.

[0027] As an example, the substrate 100 is a silicon interposer, and the material of the substrate 100 includes silicon. Silicon is a commonly used material in the semiconductor field, which is conducive to improving process compatibility and saving costs. Moreover, a second trench is subsequently formed in the substrate 100 of the capacitor region II, and a capacitor is formed in the second trench. The capacitor is a silicon-based capacitor. By selecting a silicon interposer, it is also beneficial to improve the compatibility of forming the capacitor and forming the adapter plate, thereby facilitating the mass production of the adapter plate and the capacitor. Specifically, in this embodiment, the material of the substrate 100 is single crystal silicon, thereby ensuring that the substrate 100 can isolate the subsequently formed through-hole interconnect structure and the capacitor.

[0028] In this embodiment, the substrate 100 further includes a capacitor region II for forming a capacitor, which prepares for the subsequent formation of a capacitor in the substrate 100 in the capacitor region II.

[0029] In this embodiment, the figure shows that the capacitor region II and the interconnection region I are adjacent to each other. In other embodiments, the capacitor region may not be adjacent to the interconnection region; in other embodiments, the capacitor region may be adjacent to the interconnection region.

[0030] refer to Figure 3 , the front surface 11 of the substrate 100 is etched to form a first trench 10 in the substrate 100 of the interconnection region I, and a second trench 20 in the substrate 100 of the capacitor region II.

[0031] The first trench 10 is used to prepare for the subsequent formation of a conductive through hole, wherein the conductive through hole is used to provide a formation space for a through hole interconnection structure.

[0032] The second trench 20 is used to provide a formation space for the subsequent formation of a capacitor.

[0033] By forming the second trench 20 during the process of forming the first trench 10, the process of forming the second trench 20 is integrated with the first trench 10, which is beneficial to improving process integration and process compatibility. In addition, the process of forming the second trench 20 does not require the use of an additional mask, which is also beneficial to saving costs.

[0034] In this embodiment, during the steps of forming the first trench 10 and the second trench 20, the opening size of the first trench 10 is larger than the opening size of the second trench 20. Subsequently, a capacitor is formed in the second trench 20. During the capacitor formation process, the capacitor is also formed at the bottom and sidewalls of the first trench 10. By making the opening size of the first trench 10 larger than the opening size of the second trench 20, after the capacitor is subsequently formed, there is still residual space in the first trench 10. After the substrate 100 below the first trench 10 is subsequently etched to form a conductive via, the conductive via can also provide a spatial location for forming a through-hole interconnect structure.

[0035] In the step of forming the first trench 10 , the opening size of the first trench 10 is a first size.

[0036] It should be noted that the opening size of the second trench 20 should not be too small or too large. If the opening size of the second trench 20 is too small, it is easy to cause the space for the subsequent capacitor to be formed to be too small, and it is also easy to increase the difficulty of the process of forming the capacitor in the second trench 20; if the opening size of the second trench 20 is too large, since the subsequent capacitor needs to fill the second trench 20, the thickness of the capacitor to be deposited in the process of forming the capacitor is too large. Accordingly, in order to ensure that after the substrate 100 under the first trench 10 is subsequently etched to form a conductive through-hole, the conductive through-hole still has enough space for forming a through-hole interconnection structure, the opening size of the required first trench 10 is also too large, which easily increases the area occupied by the capacitor and the through-hole interconnection structure, and reduces the unit area density of the capacitor and the through-hole interconnection structure. To this end, in the step of forming the second trench 20, the opening size of the second trench 20 is 0.2μm to 3μm, for example: 0.5μm to 2μm, 1μm, 1.5μm, etc.

[0037] In this embodiment, an anisotropic dry etching process is used to etch the front surface 11 of the substrate 100 to form the first trench 10 and the second trench 20. The anisotropic dry etching process has the characteristic of anisotropic etching, which helps improve the controllability of the etching profile, thereby improving the cross-sectional morphology quality of the first trench 10 and the second trench 20. For example, the smoothness and steepness of the sidewalls of the first trench 10 and the second trench 20 are improved. In addition, the anisotropic dry etching process has high etching precision, which helps reduce damage to the substrate 100.

[0038] As an example, the anisotropic dry etching process is a reactive ion etching (RIE) process. During the RIE process, a radio frequency voltage is applied between flat electrodes, and the generated plasma chemically and physically etches the layer to be etched. The plasma generated by the gas discharge contains a large number of chemically active gas ions. These gas ions interact with the material surface, causing surface atoms to undergo chemical reactions, generating volatile products. These volatile products are then discharged from the reaction chamber via the vacuum pumping system. As the surface layer of the material undergoes a "reaction-stripping-emission" cycle, the material is etched layer by layer to a specified depth. In addition to surface chemical reactions, energetic ions bombarding the material surface also sputter surface atoms, producing a certain etching effect. Therefore, the use of the RIE process is beneficial for further improving the cross-sectional morphology quality of the first trench 10 and the second trench 20, and is also beneficial for precisely controlling the depth of the first trench 10 and the second trench 20.

[0039] Combined with reference Figure 4 After forming the first trench 10 and the second trench 20 , and before forming the capacitor, the method for forming the adapter plate further includes: forming a first insulating layer 110 on the sidewalls and bottom surface of the first trench 10 , and the sidewalls and bottom surface of the second trench 20 .

[0040] The first insulating layer 110 is used to achieve electrical insulation between the capacitor and the substrate 100 .

[0041] To this end, the material of the first insulating layer 110 is an insulating material, such as one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the first insulating layer 110 is silicon oxide. Silicon oxide is a commonly used insulating material in the semiconductor field, which is beneficial to improving process compatibility and reducing process costs. Moreover, silicon oxide has good insulation performance, which is beneficial to ensuring the insulation performance of the first insulating layer 110 between the capacitor and the substrate 100. In addition, the adhesion between silicon oxide and other material layers (for example, the material of the substrate 100 and the material of the subsequent capacitor) is good, which is beneficial to improving the adhesion between the subsequent capacitor and the substrate 100. In addition, the first trench 10 and the second trench 20 are formed by an etching process, and the first insulating layer 110 is located on the sidewalls and bottom surfaces of the first trench 10 and the second trench 20, which is also beneficial to improving the surface smoothness and flatness of the first trench 10 and the second trench 20, reducing the interface defects of the first trench 10 and the second trench 20, and providing a good interface for forming a capacitor.

[0042] As an example, the first insulating layer 110 is formed by an atomic layer deposition (ALD) process.

[0043] Continue to refer Figure 4A capacitor 120 is formed in the second trench 20 , and the capacitor 120 includes a first electrode 21 located on the sidewall and bottom of the second trench 20 , a capacitor dielectric layer 22 located on the first electrode 21 , and a second electrode 23 located on the capacitor dielectric layer 22 , and the second electrode 23 fills the second trench 20 .

[0044] The embodiment of the present invention forms the capacitor 120 in the second groove 20, thereby integrating the process of forming the capacitor 120 and forming the adapter plate, eliminating the additional step of forming the capacitor 120, which is beneficial to saving process steps, improving process integration, and further beneficial to reducing process costs and shortening production cycles; moreover, the adapter plate provided by the embodiment of the present invention also has a capacitor 120 formed therein, which is beneficial to improving the functional diversity of the adapter plate, thereby diversifying the application scenarios of the adapter plate.

[0045] Specifically, during the packaging process, the adapter board provided in an embodiment of the present invention is bonded to a circuit board, and the chip is bonded to the adapter board, so that the chip is electrically connected to the capacitor 120. The capacitor 120 is electrically connected to the chip and is used as a bypass capacitor or a decoupling capacitor, thereby playing an anti-interference role.

[0046] Specifically, the bypass capacitor filters out the high-frequency noise in the input signal and the high-frequency clutter carried by the previous stage, which is conducive to eliminating self-excitation and making the amplifier work stably; the decoupling capacitor filters out the interference of the output signal, reducing the probability of voltage drop due to sudden changes in current, thereby meeting the changes in the driving circuit current and reducing mutual coupling interference.

[0047] In this embodiment, the capacitor 120 is formed in the second groove 20. The capacitor 120 is a three-dimensional structure, which is beneficial to increasing the surface area of the capacitor 120 without increasing the footprint of the capacitor 120, thereby facilitating improving the density of the capacitor 120 and the electrostatic capacitance per unit area of the capacitor 120.

[0048] As an example, the capacitor 120 is a silicon-based capacitor. Silicon-based capacitors have advantages such as low insertion loss and high stability. In addition, the electrode material of a silicon-based capacitor includes silicon, which is a commonly used and easily available material in semiconductor processes, which is conducive to improving process compatibility and reducing process costs.

[0049] The first electrode 21 and the second electrode 23 are made of a conductive material. As an example, the capacitor 120 is a silicon-based capacitor, and the first electrode 21 and the second electrode 23 are made of polysilicon (Poly) doped with conductive ions.

[0050] The conductive ions include N-type ions (eg, P ions, As ions, or Sb ions) or P-type ions (eg, P-type ions may be B ions, Ga ions, or In ions).

[0051] The capacitor dielectric layer 22 is used to electrically isolate the first electrode 21 from the second electrode 23. The capacitor dielectric layer 22 is made of an insulating material. As an example, the capacitor dielectric layer 22 is made of the same material as the first insulating layer 110, and the capacitor dielectric layer 22 is made of silicon oxide, which helps improve process compatibility.

[0052] The process of forming the capacitor 120 includes one or more of an atomic layer deposition process, a chemical vapor deposition process, and a physical vapor deposition process.

[0053] Specifically, in this embodiment, an atomic layer deposition process is used to sequentially form the first electrode 21 , the capacitor dielectric layer 22 , and the second electrode 23 .

[0054] In this embodiment, a first electrode 21, a capacitor dielectric layer 22, and a second electrode 23 are sequentially formed at the bottom and side of the second trench 20. In the process of forming the second electrode 23, the second electrodes 23 located on the sidewalls of the second trench 20 are in contact with each other, so that the capacitor 120 fills the second trench 20.

[0055] In this embodiment, in the step of forming the capacitor 120, the capacitor 120 is also formed on the sidewall and bottom of the first trench 10, wherein the portion of the capacitor 120 located on the sidewall of the first trench 10 serves as the capacitor side 120a, and the portion of the capacitor 120 located on the bottom of the first trench 10 serves as the capacitor bottom 120b.

[0056] It should be noted that in the step of forming the capacitor 120, the thickness of the capacitor side portion 120a along the direction perpendicular to the side wall of the first trench 10 is a second size. Compared with the first size, the second size should not be too small or too large. The capacitor 120 needs to fill the second trench 20, so the thickness of the capacitor side portion 120a will not be too small, that is, the second size will not be too small; at the same time, in order to ensure that after the capacitor 120 is formed, in the subsequent step of etching the substrate 100 below the first trench 10 to form a conductive through-hole, the conductive through-hole still has enough space for forming a through-hole interconnection structure, thereby ensuring that the resistance of the through-hole interconnection structure is not too large, and then ensuring the electrical connection performance of the through-hole interconnection structure, the second size should not be too large. For this reason, in this embodiment, the second size is 10% to 30% of the first size.

[0057] refer to Figure 5 After forming the capacitor 120 , a portion of the thickness of the substrate 100 below the first trench 10 is etched to form a groove 30 in the substrate 100 , and the groove 30 and the first trench 10 constitute a conductive through-hole 40 .

[0058] The conductive through-hole 40 is used to provide a formation space for forming a through-hole interconnection structure.

[0059] In this embodiment, the conductive via 40 is a through silicon via (TSV).

[0060] In this embodiment, the steps of forming the conductive through hole 40 include: removing the capacitor bottom 120b exposed by the capacitor side 120a to expose a portion of the bottom surface of the first groove 10; etching the partial thickness of the substrate 100 below the first groove 10 exposed by the capacitor side 120a to form the groove 30.

[0061] Therefore, the conductive via 40 is surrounded by the groove 30 and the capacitor side portion 120 a.

[0062] The process for etching the partial thickness of the substrate 100 below the first trench 10 includes an anisotropic dry etching process. In this embodiment, a reactive ion etching process is used to etch the partial thickness of the substrate 100 below the first trench 10, which is beneficial for improving the cross-sectional morphology quality of the groove 30 and, in turn, the cross-sectional morphology quality of the conductive via 40.

[0063] Combined with reference Figure 6 After forming the conductive through-hole 40 and before forming the through-hole interconnection structure, the method for forming the transfer board further includes: forming a second insulating layer 130 on the bottom surface and sidewall of the conductive through-hole 40.

[0064] Subsequently, a through-hole interconnection structure is formed in the conductive through-hole 40, and the second insulating layer 130 is used to achieve electrical isolation between the substrate 100 and the through-hole interconnection structure, and to achieve electrical isolation between the capacitor 120 and the through-hole interconnection structure, thereby helping to reduce the impact of the capacitor 120 formed in the first trench 10 on the through-hole interconnection structure.

[0065] The material of the second insulating layer 130 is an insulating material. In this embodiment, the material of the second insulating layer 130 is silicon oxide.

[0066] In this embodiment, the process of forming the second insulating layer 130 includes an atomic layer deposition process.

[0067] refer to Figure 7 , forming a through-hole interconnection structure 140 in the conductive through-hole 40 .

[0068] Subsequently, the back surface 12 of the substrate 100 is thinned to expose the through-hole interconnection structure 140 .

[0069] After the interposer is formed, the interposer is bonded to the circuit board, and the chip is bonded to the interposer. The through-hole interconnect structure 140 is used to achieve electrical connection between the chip and the circuit board. Alternatively, when the interposer is bonded between the chips, the through-hole interconnect structure 140 is also used to achieve electrical connection between the chips.

[0070] In this embodiment, the through-hole interconnect structure 140 is a through silicon via (TSV) interconnect structure. TSV interconnect structures enable vertical conduction between a circuit board and a chip, or between chips, maximizing the density of three-dimensional stacking and reducing the horizontal area of a 3D IC. TSV interconnect structures have the characteristics of short connection distance and high strength, enabling thinner and smaller packages with better performance and significantly reduced size and weight. TSVs also help reduce power consumption and increase operating speed.

[0071] In this embodiment, the through-hole interconnect structure 140 includes a barrier layer (not shown) located on the bottom surface and sidewalls of the conductive through-hole 40 , and a conductive layer (not shown) located on the barrier layer and filling the conductive through-hole 40 .

[0072] The barrier layer is used to reduce the probability of the material of the conductive layer diffusing into the second insulating layer 130 , thereby improving the reliability of the through-hole interconnect structure 140 .

[0073] In this embodiment, a metal material with high chemical stability is selected as the material of the barrier layer, for example, one or more materials selected from Ti, Ta, TiN and TaN.

[0074] In this embodiment, the conductive layer is made of a material with high conductivity, such as metal materials such as copper, tungsten, cobalt, and nickel.

[0075] refer to Figures 8 and 9 , the back surface 12 of the substrate 100 is thinned so that the back surface 12 of the substrate 100 exposes the through-hole interconnection structure 140.

[0076] Through the thinning process, the through-hole interconnection structure 140 is exposed on the back side 12 of the substrate 100, so that the through-hole interconnection structure 140 can penetrate the substrate 100 in the interconnection area I, preparing for the subsequent through-hole interconnection structure 140 to achieve vertical interconnection between the circuit board and the chip, or between chips.

[0077] In this embodiment, a chemical mechanical polishing (CMP) process is used to thin the back surface 12 of the substrate 100 .

[0078] In this embodiment, after the back surface 12 of the substrate 100 is thinned, the depth of the capacitor 120 along a direction perpendicular to the surface of the substrate 100 accounts for 30% to 60% of the thickness of the substrate 100 .

[0079] The through-hole interconnect structure 140 includes a first portion 41 close to the back surface 12 of the substrate 100 , and a second portion 42 close to the front surface 11 of the substrate 100 and connected to the first portion 41 .

[0080] It should be noted that, in conjunction with the reference Figure 8 In this embodiment, after forming the through-hole interconnection structure 140 and before thinning the back side 12 of the substrate 100, the method for forming the adapter plate further includes: forming a first dielectric layer 150 on the front side 11 of the substrate 100, wherein a first interconnection structure 160 is formed in the first dielectric layer 150, the first interconnection structure 160 is electrically connected to the capacitor 120, and the first interconnection structure 160 is electrically connected to the through-hole interconnection structure 160.

[0081] The first dielectric layer 150 is used to achieve electrical isolation between the first interconnect structures 160 .

[0082] The first interconnect structure 160 is used to realize electrical connection between the through-hole interconnect structure 140 and other interconnect structures, chips, circuit boards or components. Specifically, the first interconnect structure 160 can be a redistribution layer (RDL).

[0083] In the actual process, the method for forming the adapter plate can also include: after the thinning process, forming a second dielectric layer (not shown) on the back side 12 of the substrate 100, forming a second interconnection structure (not shown) in the second dielectric layer, the second interconnection structure is electrically connected to the capacitor 120, and the second interconnection structure is also electrically connected to the through-hole interconnection structure 140.

[0084] The second dielectric layer is used to achieve electrical isolation between the second interconnect structures.

[0085] The second interconnect structure is used to electrically connect the through-hole interconnect structure 140 with other interconnect structures, chips, circuit boards or components.

[0086] It should be noted that in actual processes, bumps can also be formed on the first interconnect structure 160 and the second interconnect structure. The bumps are used to electrically connect the first interconnect structure 160 or the second interconnect structure to external circuits, chips, circuit boards, or other components.

[0087] Accordingly, the present invention also provides a packaging method. Figure 10 , shows a structural schematic diagram corresponding to each step in an embodiment of the packaging method of the present invention.

[0088] refer to Figure 10 , providing a circuit board 300.

[0089] The circuit board 300 is used to connect various electronic components to form a predetermined circuit, thereby playing the role of relay transmission.

[0090] Specifically, circuit board 300 is short for printed circuit board (PCB). A printed circuit board, also known as a printed circuit board or printed wiring board, is manufactured using electronic printing technology. A printed circuit board is a substrate for assembling electronic components. It is a printed board with interconnections and components printed according to a predetermined design on a general-purpose substrate.

[0091] Continue to refer Figure 10 The adapter plate 200 is bonded to the circuit board 300 so that the through-hole interconnect structure 140 is electrically connected to the circuit board 300, and the back surface 12 of the substrate 100 is arranged opposite to the circuit board 300.

[0092] By bonding the adapter plate 200 to the circuit board 300 , the adapter plate 200 can achieve electrical connection between the chip and the circuit board 300 after the chip is bonded to the adapter plate 200 .

[0093] Specifically, in this embodiment, the transfer board 200 is bonded to the circuit board 300 via a solder ball 310. The solder ball 310 is electrically connected to the through-hole interconnect structure 140 via a second interconnect structure.

[0094] The material of the solder ball 310 includes tin-lead (Sn / Pb), tin-indium (Sn / In), tin-copper-silver (Sn / Cu / Ag) alloy, etc.

[0095] Continue to refer Figure 10 , providing chip 400.

[0096] Chip 400 is used as the chip to be integrated during the packaging process and is subsequently bonded to the adapter plate 200, thereby achieving electrical connection between the adapter plate 200 and the circuit board. Chip 400 can be one or more active components, passive components, micro-electromechanical systems, optical components, and other components with different functions. Specifically, chip 400 can be a memory chip, a communication chip, a processor, or a logic chip.

[0097] As an example, the chip 400 is a processor, for example, a CPU (Central Processing Unit) or other chip capable of outputting high-frequency signals.

[0098] The closer the distance between the capacitor 120 and the CPU is, the smaller the power consumption of the high-frequency circuit is.

[0099] Continue to refer Figure 10 , the chip 400 is bonded to the adapter board 200 formed by the adapter board forming method provided in an embodiment of the present invention, so that the chip 400 is electrically connected to the capacitor 120, and the chip 400 is electrically connected to the through-hole interconnection structure 140; the chip 400 is located on the front side 11 of the substrate 100.

[0100] In an embodiment of the present invention, the adapter board 200 formed by the adapter board forming method provided in the embodiment of the present invention is bonded to the circuit board 300, so that the through-hole interconnection structure 140 is electrically connected to the circuit board 300, and the chip 400 is bonded to the adapter board 200, so that the chip 400 is electrically connected to the capacitor 120, and the chip 400 is electrically connected to the through-hole interconnection structure 140; wherein, the front side of the substrate 100 is arranged opposite to the chip 400, and the back side of the substrate 100 is arranged opposite to the circuit board 300. Compared with the solution of bonding the capacitor to the circuit board and locating the capacitor between the adapter board and the circuit board, the capacitor 120 in the embodiment of the present invention is formed in the adapter board 200, which not only eliminates the process of additionally forming the capacitor 120, but also makes the distance between the capacitor 120 and the chip 400 smaller, which is conducive to improving the RC delay of the device, increasing the signal transmission rate, and thus improving the performance of the device.

[0101] In particular, in this embodiment, the chip 400 is a CPU, and shortening the distance between the capacitor 120 and the chip 400 is beneficial to significantly improve the performance of the device.

[0102] It should be noted that, in the actual process, the order of bonding the adapter board 200 to the circuit board 300 and the chip 400 to the adapter board 200 is determined according to the actual process requirements. The embodiment of the present invention does not limit the order of bonding the adapter board 200 to the circuit board 300 and the chip 400 to the adapter board 200.

[0103] Correspondingly, the present invention also provides a transfer plate. Figure 9 , shows a structural schematic diagram of an embodiment of the adapter plate of the present invention.

[0104] The adapter plate includes: a substrate 100, including an interconnection area I for forming a through-hole interconnection structure, and a capacitor area II for forming a capacitor, the substrate 100 includes a front side 11 and a back side 12 facing each other; a capacitor 120, located in a partial thickness of the substrate 100 in the capacitor area II, the capacitor 120 includes a first electrode 21 in contact with the substrate 100, a capacitor dielectric layer 22 located on the first electrode 21, and a second electrode 23 located on the capacitor dielectric layer 22, the side walls of the second electrode 23 are in contact, and the top surface of the capacitor 120 faces away from the back side 12 of the substrate 100; a through-hole interconnection structure 140, which passes through the substrate 100 in the interconnection area I.

[0105] The embodiment of the present invention further provides the capacitor 120 in the adapter plate, thereby integrating the process of forming the capacitor 120 and forming the adapter plate, eliminating the additional step of forming the capacitor 120, which is beneficial to saving process steps, improving process integration, and further beneficial to reducing process costs and shortening production cycles; moreover, the adapter plate provided by the embodiment of the present invention is also provided with the capacitor 120, which is beneficial to improving the functional diversity of the adapter plate, thereby diversifying the application scenarios of the adapter plate.

[0106] The substrate 100 is used to provide a platform for the process. In this embodiment, the substrate 100 serves as an interposer for isolating the through-hole interconnect structure 140 and the capacitor 120 .

[0107] In this embodiment, the substrate 100 is a silicon interposer, and the material of the substrate 100 includes silicon. Silicon is a commonly used material in the semiconductor field, which is conducive to improving process compatibility and saving costs. Moreover, the capacitor 120 is a silicon-based capacitor. By selecting a silicon interposer, it is also conducive to improving the compatibility of forming the capacitor 120 and forming the adapter plate, thereby facilitating the mass production of the adapter plate and the capacitor. Specifically, in this embodiment, the material of the substrate 100 is single crystal silicon, thereby ensuring that the substrate 100 can electrically isolate the through-hole interconnect structure 140 from the capacitor 120.

[0108] In this embodiment, the figure shows that the capacitor region II is adjacent to the interconnection region I. In other embodiments, the capacitor region may not be adjacent to the interconnection region. In still other embodiments, the capacitor region may be adjacent to the interconnection region.

[0109] Specifically, during the packaging process, the adapter board provided in an embodiment of the present invention is bonded to a circuit board, and the chip is bonded to the adapter board, so that the chip is electrically connected to the capacitor 120. The capacitor 120 is electrically connected to the chip and is used as a bypass capacitor or a decoupling capacitor, thereby playing an anti-interference role.

[0110] Specifically, the bypass capacitor filters out the high-frequency noise in the input signal and the high-frequency clutter carried by the previous stage, thereby eliminating self-excitation and making the amplifier work stably; the decoupling capacitor filters out the interference of the output signal, reducing the probability of voltage drop due to sudden changes in current, thereby meeting the changes in the driving circuit current and reducing mutual coupling interference.

[0111] In this embodiment, a second groove is formed in the substrate 100 of the capacitor region I, and the capacitor 120 is formed in the second groove. The capacitor 120 has a three-dimensional structure, which is beneficial for increasing the surface area of the capacitor 120 without increasing the footprint of the capacitor 120, thereby facilitating an increase in the density of the capacitor 120 and the electrostatic capacitance per unit area of the capacitor 120.

[0112] As an example, the capacitor 120 is a silicon-based capacitor. Silicon-based capacitors have advantages such as low insertion loss and high stability. In addition, the electrode material of a silicon-based capacitor includes silicon, which is a commonly used and easily available material in semiconductor processes, which is conducive to improving process compatibility and reducing process costs.

[0113] The first electrode 21 and the second electrode 23 are made of a conductive material. As an example, the capacitor 120 is a silicon-based capacitor, and the first electrode 21 and the second electrode 23 are made of polysilicon (Poly) doped with conductive ions.

[0114] The capacitor dielectric layer 22 is used to electrically isolate the first electrode 21 from the second electrode 23. The capacitor dielectric layer 22 is made of an insulating material. As an example, the capacitor dielectric layer 22 is made of silicon oxide, which is beneficial for improving process compatibility.

[0115] It should be noted that the width of the capacitor 120 should not be too small or too large along the direction parallel to the surface of the substrate 100. If the width of the capacitor 120 is too small, since the capacitor 120 is formed in the second groove, the opening size of the second groove is correspondingly too small, which easily increases the difficulty of forming the capacitor 120 and reduces the formation quality of the capacitor 120; if the width of the capacitor 120 is too large, it is easy to cause the area occupied by the capacitor 120 in the direction parallel to the surface of the substrate 100 to be too large, which is not conducive to increasing the density of the capacitor 120. To this end, in this embodiment, the width of the capacitor 120 in the direction parallel to the surface of the substrate 100 is 0.2μm to 3μm, for example: 0.5μm to 2μm, 1μm, 1.5μm, etc.

[0116] It should also be noted that the percentage of the depth of the capacitor 120 to the thickness of the substrate 100 along the direction perpendicular to the surface of the substrate 100 should not be too small or too large. If the percentage of the depth of the capacitor 120 to the thickness of the substrate 100 is too small, it is not conducive to increasing the surface area of the capacitor 120 and the electrostatic capacitance per unit area of the capacitor 120; if the percentage of the depth of the capacitor 120 to the thickness of the substrate 100 is too large, it is easy to cause the depth of the capacitor 120 to be too large. The capacitor 120 is a long strip structure. Since the formation process of the adapter plate includes the process of thinning the back side of the substrate 100, a large depth of the capacitor 120 is likely to cause a high risk of the capacitor 120 being broken or delaminated. For this reason, in this embodiment, the depth of the capacitor 120 along the direction perpendicular to the surface of the substrate 100 is 30% to 60% of the thickness of the substrate 100.

[0117] The through-hole interconnect structure 140 includes a first portion 41 close to the back surface 12 of the substrate 100 and a second portion 42 close to the front surface 11 of the substrate 100 and connected to the first portion 41 ; the capacitor 120 is also located between the sidewall of the second portion 42 and the substrate 100 .

[0118] The capacitor 120 is also located between the sidewall of the second portion 42 and the substrate 100. This is because during the formation of the interposer, a first trench is formed in the substrate 100 in the interconnection region I. During the formation of the capacitor 120, the capacitor 120 is also formed in the first trench. The through-hole interconnect structure 140 is formed after the capacitor 120 is formed, and the through-hole interconnect structure 140 is correspondingly formed in the first trench containing the capacitor 120. Specifically, the capacitor 120 located between the sidewall of the second portion 42 and the substrate 100 is the capacitor side portion 120a.

[0119] The adapter board further includes a first insulating layer 110 located between the capacitor 120 and the substrate 100 .

[0120] The first insulating layer 110 is used to achieve electrical insulation between the capacitor 120 and the substrate 100 .

[0121] To this end, the material of the first insulating layer 110 is an insulating material, such as one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the first insulating layer 110 is silicon oxide. Silicon oxide is a commonly used insulating material in the semiconductor field, which is beneficial to improving process compatibility and reducing process costs. Moreover, silicon oxide has good insulation performance, which is beneficial to ensuring the insulation performance of the first insulating layer 110 between the capacitor 120 and the substrate 100. In addition, silicon oxide has good adhesion to other material layers (for example, the material of the substrate 100 and the material of the capacitor 120), which is beneficial to improving the adhesion between the capacitor 120 and the substrate 100, as well as the interface performance between the capacitor 120 and the substrate 100.

[0122] During the packaging process, the interposer is bonded to the circuit board, and the chip is bonded to the interposer. The through-hole interconnect structure 140 is used to achieve electrical connection between the chip and the circuit board. Alternatively, when the interposer is bonded between the chips, the through-hole interconnect structure 140 is also used to achieve electrical connection between the chips.

[0123] In this embodiment, the through-hole interconnect structure 140 is a through silicon via (TSV) interconnect structure. TSV interconnect structures enable vertical conduction between a circuit board and a chip, or between chips, maximizing the density of three-dimensional stacking and reducing the horizontal area of a 3D IC. TSV interconnect structures have the characteristics of short connection distance and high strength, enabling thinner and smaller packages with better performance and significantly reduced size and weight. TSVs also help reduce power consumption and increase operating speed.

[0124] In this embodiment, the through-hole interconnection structure 140 includes: a conductive layer (not shown) penetrating the substrate 100 in the interconnection region I, and a barrier layer (not shown) located on the sidewall of the conductive layer.

[0125] In this embodiment, the conductive layer is made of a material with high conductivity, such as metal materials such as copper, tungsten, cobalt, and nickel.

[0126] The barrier layer is used to reduce the probability of the material of the conductive layer diffusing into the second insulating layer 130 , thereby improving the reliability of the through-hole interconnect structure 140 .

[0127] In this embodiment, a metal material with high chemical stability is selected as the material of the barrier layer, for example, one or more materials selected from Ti, Ta, TiN and TaN.

[0128] The transfer board further includes a second insulating layer 130 located between the capacitor 120 and the through-hole interconnection structure 140 , and between the through-hole interconnection structure 140 and the substrate 100 .

[0129] The second insulating layer 130 is used to achieve electrical isolation between the substrate 100 and the through-hole interconnect structure 140, and to achieve electrical isolation between the capacitor 120 and the through-hole interconnect structure 140, thereby helping to reduce the impact of the capacitor 120 between the sidewall of the second portion and the substrate 100 on the through-hole interconnect structure 140.

[0130] The material of the second insulating layer 130 is an insulating material. In this embodiment, the material of the second insulating layer 130 is silicon oxide.

[0131] In this embodiment, the adapter board also includes: a first dielectric layer 150, located on the front side 11 of the substrate 100; a first interconnection structure 160, located in the first dielectric layer 150, the first interconnection structure 160 is electrically connected to the capacitor 120, and the first interconnection structure 160 is electrically connected to the through-hole interconnection structure 160.

[0132] The first dielectric layer 150 is used to achieve electrical isolation between the first interconnect structures 160 .

[0133] The first interconnect structure 160 is used to realize electrical connection between the through-hole interconnect structure 140 and other interconnect structures, chips, circuit boards or components.

[0134] Specifically, the first interconnect structure 160 may be a redistribution layer (RDL).

[0135] In the actual process, the adapter board can also include: a second dielectric layer (not shown), located on the back side 12 of the substrate 100; a second interconnection structure (not shown), located in the second dielectric layer, the second interconnection structure is electrically connected to the capacitor 120, and the second interconnection structure is also electrically connected to the through-hole interconnection structure 140.

[0136] The second dielectric layer is used to achieve electrical isolation between the second interconnect structures.

[0137] The second interconnect structure is used to electrically connect the through-hole interconnect structure 140 with other interconnect structures, chips, circuit boards or components.

[0138] It should be noted that in actual processes, bumps can also be formed on the first interconnect structure 160 and the second interconnect structure. The bumps are used to electrically connect the first interconnect structure 160 or the second interconnect structure to external circuits, chips, circuit boards, or other components.

[0139] The adapter plate can be formed by the forming method described in the above embodiment, or by other forming methods. For the detailed description of the adapter plate of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0140] Accordingly, the present invention also provides a packaging structure. Figure 10 , shows a structural schematic diagram of an embodiment of the packaging structure of the present invention.

[0141] The packaging structure includes: a circuit board 300; the adapter board 200 provided by the present invention, bonded to the circuit board 300, the through-hole interconnection structure 140 is electrically connected to the circuit board 300, and the back side 12 of the substrate 100 is arranged opposite to the circuit board 300; a chip 400, bonded to the adapter board 200, the chip 400 is electrically connected to the capacitor 120, and the chip 400 is electrically connected to the through-hole interconnection structure 140, wherein the chip 140 is located on the front side 11 of the substrate 100.

[0142] The adapter plate 200 provided in the embodiment of the present invention is bonded to the circuit board 300, so that the through-hole interconnection structure 140 is electrically connected to the circuit board 300, and the chip 400 is bonded to the adapter plate 200, so that the chip 400 is electrically connected to the capacitor 120, and the chip 400 is electrically connected to the through-hole interconnection structure 140; wherein, the front side of the substrate 100 is arranged opposite to the chip 400, and the back side of the substrate 100 is arranged opposite to the circuit board 300. Compared with the solution of bonding the capacitor to the circuit board and locating the capacitor between the adapter plate and the circuit board, the capacitor 120 in the embodiment of the present invention is formed in the adapter plate 200, which not only eliminates the process of additionally forming the capacitor 120, but also makes the distance between the capacitor 120 and the chip 400 smaller, which is conducive to improving the RC delay of the device, increasing the signal transmission rate, and thus improving the performance of the device.

[0143] The circuit board 300 is used to connect various electronic components to form a predetermined circuit and plays a role in relay transmission.

[0144] Specifically, circuit board 300 is short for printed circuit board (PCB). A printed circuit board, also known as a printed circuit board or printed wiring board, is manufactured using electronic printing technology. A printed circuit board is a substrate for assembling electronic components. It is a printed board with interconnections and components printed according to a predetermined design on a general-purpose substrate.

[0145] Specifically, in this embodiment, the adapter board 200 and the circuit board 300 are bonded via solder balls 310. The solder balls 310 are electrically connected to the through-hole interconnection structure 140 via a second interconnection structure.

[0146] The material of the solder ball 310 includes tin-lead (Sn / Pb), tin-indium (Sn / In), tin-copper-silver (Sn / Cu / Ag) alloy, etc.

[0147] Chip 400 is used as the chip to be integrated during the packaging process and is subsequently bonded to the adapter plate 200, thereby achieving electrical connection between the adapter plate 200 and the circuit board. Chip 400 can be one or more active components, passive components, micro-electromechanical systems, optical components, and other components with different functions. Specifically, chip 400 can be a memory chip, a communication chip, a processor, or a logic chip.

[0148] As an example, chip 400 is a chip capable of outputting high-frequency signals, such as a CPU (Central Processing Unit). The capacitor 120 is electrically connected to the chip 400 and is used as a bypass capacitor or decoupling capacitor to provide anti-interference. The smaller the distance between the capacitor 120 and the CPU, the lower the power consumption of the high-frequency circuit. Therefore, by shortening the distance between the capacitor 120 and the chip 400, the performance of the device can be significantly improved.

[0149] The packaging structure can be formed by the packaging method described in the above embodiment, or by other methods. For the detailed description of the packaging structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0150] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming an adapter plate, characterized in that: include: Providing a substrate, comprising an interconnection region for forming a through-hole interconnection structure and a capacitance region for forming a capacitor, the substrate comprising a front surface and a back surface facing each other; Etching the front surface of the substrate to form a first trench in the substrate of the interconnection region and a second trench in the substrate of the capacitor region, wherein the opening size of the first trench is larger than the opening size of the second trench; forming a capacitor in the second trench, the capacitor comprising a first electrode located on the sidewalls and bottom of the second trench, a capacitor dielectric layer located on the first electrode, and a second electrode located on the capacitor dielectric layer, wherein the second electrode fills the second trench; In the step of forming the capacitor, the capacitor is further formed on the sidewalls and bottom of the first trench, wherein the portion of the capacitor located on the sidewalls of the first trench serves as a capacitor side portion, and the portion of the capacitor located on the bottom of the first trench serves as a capacitor bottom portion; After forming the capacitor, etching a portion of the thickness of the substrate below the first trench to form a groove in the substrate, wherein the groove and the first trench constitute a conductive through-hole; the steps of forming the groove include: removing the bottom of the capacitor exposed at the side of the capacitor to expose a portion of the bottom surface of the first trench; etching a portion of the thickness of the substrate below the first trench exposed at the side of the capacitor to form the groove; forming a through-hole interconnection structure in the conductive through-hole, wherein the through-hole interconnection structure includes a second portion close to the front surface of the substrate, and the capacitor is further located between a sidewall of the second portion and the substrate; and the through-hole interconnection structure further includes a first portion close to the back surface of the substrate and connected to the second portion; The back side of the substrate is thinned to expose the through-hole interconnection structure on the back side of the substrate.

2. The method for forming an adapter plate according to claim 1, wherein: In the step of forming the first groove, the opening size of the first groove is a first size; In the step of forming the capacitor, along a direction perpendicular to the sidewall of the first trench, the thickness of the capacitor side portion is a second size, and the second size is 10% to 30% of the first size.

3. The method for forming an adapter plate according to claim 1, wherein: After forming the first trench and the second trench and before forming the capacitor, the method for forming the adapter plate further includes: forming a first insulating layer on the sidewall and bottom surface of the first trench and the sidewall and bottom surface of the second trench.

4. The method for forming an adapter plate according to claim 1, wherein: After forming the conductive through-holes and before forming the through-hole interconnection structure, the method for forming the transfer board further includes: forming a second insulating layer on the bottom surface and sidewalls of the conductive through-holes.

5. The method for forming an adapter plate according to claim 1, wherein: An anisotropic dry etching process is adopted to etch the front surface of the substrate to form the first trench and the second trench.

6. The method for forming an adapter plate according to claim 1, wherein: The materials of the first electrode and the second electrode include polysilicon doped with conductive ions.

7. The method for forming an adapter plate according to claim 1, wherein: The process of forming the capacitor includes one or more of an atomic layer deposition process, a chemical vapor deposition process, and a physical vapor deposition process.

8. The method for forming an adapter plate according to claim 1, wherein: An anisotropic dry etching process is adopted to etch a portion of the thickness of the substrate below the first trench.

9. A packaging method, characterized in that: include: Provide circuit boards; bonding the adapter plate formed by the method according to any one of claims 1 to 8 to the circuit board so that the through-hole interconnect structure is electrically connected to the circuit board, and the back surface of the substrate is arranged opposite to the circuit board; Provide chips; The chip is bonded to an interposer formed by the method according to any one of claims 1 to 8, so that the chip is electrically connected to the capacitor and the chip is electrically connected to the through-hole interconnect structure, wherein the chip is located on the front side of the substrate.

10. An adapter plate, characterized in that: include: A substrate comprising an interconnection region for forming a through-hole interconnection structure and a capacitance region for forming a capacitor, the substrate comprising a front surface and a back surface facing each other; a capacitor located in a partial thickness substrate in the capacitor region, the capacitor comprising a first electrode in contact with the substrate, a capacitor dielectric layer located on the first electrode, and a second electrode located on the capacitor dielectric layer, sidewalls of the second electrode of the capacitor in the capacitor region being in contact with each other, and a top surface of the capacitor facing away from the back surface of the substrate; a through-hole interconnection structure extending through the substrate of the interconnection region; The through-hole interconnect structure includes a second portion close to the front surface of the substrate, and a first portion close to the back surface of the substrate and connected to the second portion. The capacitor is also located between the side wall of the second portion and the substrate, and the first portion of the through-hole interconnect structure protrudes from the capacitor between the side wall of the second portion and the substrate.

11. The adapter plate according to claim 10, wherein: The adapter plate further includes a first insulating layer located between the capacitor and the substrate.

12. The adapter plate according to claim 10, wherein: The materials of the first electrode and the second electrode include polysilicon doped with conductive ions.

13. The adapter plate according to claim 10, wherein: The material of the substrate includes silicon.

14. The adapter plate according to claim 10, wherein: The capacitor has a width in a direction parallel to the surface of the substrate of 0.2 μm to 3 μm.

15. The adapter plate according to claim 10, wherein: In a direction perpendicular to the surface of the substrate, the depth of the capacitor accounts for 30% to 60% of the thickness of the substrate.

16. The adapter plate according to claim 10, wherein: The transfer board further includes a second insulating layer located between the capacitor and the through-hole interconnection structure and between the through-hole interconnection structure and the substrate.

17. A packaging structure, characterized in that: include: Circuit board; The adapter plate according to any one of claims 10 to 16, bonded to the circuit board, the through-hole interconnect structure is electrically connected to the circuit board, and the back surface of the substrate is arranged opposite to the circuit board; A chip is bonded to the transfer board, the chip is electrically connected to the capacitor, and the chip is electrically connected to the through-hole interconnection structure, wherein the chip is located on the front side of the substrate.

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