Built-in self-test method and interconnection interface

Abstract

A built-in self-test (BIST) method includes the following operations: a transmitting unit selects a standard sequence, uses the standard sequence and a header corresponding to the standard sequence to generate a test sequence, and transmits the test sequence to a receiving unit via a path under test; and a receiving unit parses the received test sequence to extract the header and a received sequence, obtains the standard sequence corresponding to the header based on the parsed header, and compares the standard sequence with the received sequence to obtain a test result for the path under test.

Description

Technical Field

[0001] The present invention relates to circuit testing technology, and in particular to built-in self-test (BIST) technology. Background Art

[0002] Integrated circuit (IC) manufacturers use built-in self-test (BIST) technology to perform faster and lower-cost IC testing.

[0003] As the density required for integrated circuit packaging increases, the design of interconnection interfaces between ICs is becoming more and more sophisticated.

[0004] Therefore, how to simply and efficiently test the packet transmission path provided by this sophisticated interconnection interface has become an important issue. Summary of the Invention

[0005] The present disclosure provides a built-in self-test (BIST) method, comprising the following operations: a transmitting unit selects a golden pattern, uses the golden pattern and a header corresponding to the golden pattern to generate a test pattern, and transmits the test pattern to a receiving unit via a path under test; and a receiving unit parses the received test pattern to extract the header and a received pattern, obtains the golden pattern corresponding to the header based on the parsed header, and compares the golden pattern and the received pattern to obtain a test result for the path under test.

[0006] In some embodiments, comparing the standard sequence and the received sequence to obtain the test result of the tested path includes calculating a bit error rate (BER) by comparing the received sequence and the standard sequence.

[0007] In some embodiments, generating a test sequence using a standard sequence and a header corresponding to the standard sequence includes: adding the header to the beginning of the standard sequence to generate the test sequence.

[0008] The present disclosure also provides an interconnect interface with a built-in self-test (BIST), comprising a first connection interface and a second connection interface coupled to the first connection interface. The first connection interface comprises a first sequence generation module and a first sequence comparison module, respectively located in a first transmitting portion and a first receiving portion of the first connection interface. The second connection interface comprises a second sequence generation module and a second sequence comparison module, respectively located in a second transmitting portion and a second receiving portion of the second connection interface. In the first transmitting portion, the first sequence generation module is configured to select a first standard sequence and generate a first test sequence using the first standard sequence and a first header corresponding to the first standard sequence. The first test sequence is transmitted to the second receiving portion of the second connection interface via a first path under test. In the second receiving portion, the first header and the first received sequence are parsed from the received first test sequence. The second sequence comparison module is configured to obtain the first standard sequence corresponding to the first header based on the parsed first header, and compare the first standard sequence with the first received sequence to obtain a first test result for the first path under test.

[0009] In certain embodiments, in the second transmitting unit, a second sequence generation module is configured to select a second standard sequence and generate a second test sequence using the second standard sequence and a second header corresponding to the second standard sequence. The second test sequence is then transmitted to the first receiving unit of the first connection interface via the second tested path. In the first receiving unit, the second header and the second received sequence are parsed from the received second test sequence. The first sequence comparison module is further configured to obtain the second standard sequence corresponding to the second header based on the parsed second header, and compare the second standard sequence with the second received sequence to obtain a second test result for the second tested path.

[0010] In some embodiments, at the first transmitting unit, a first sequence generation module is configured to select a third standard sequence and generate a third test sequence using the third standard sequence and a third header corresponding to the third standard sequence. The third test sequence is then transmitted to the first receiving unit via a third tested path. At the first receiving unit, the third header and a third received sequence are parsed from the received third test sequence. The first sequence comparison module is configured to obtain the third standard sequence corresponding to the third header based on the parsed third header and compare the third standard sequence with the third received sequence to obtain a third test result for the third tested path.

[0011] In some embodiments, the first connection interface is coupled to a first device, and the second connection interface is coupled to a second device. The first device and the second device are configured to communicate via the first connection interface and the second connection interface. In some embodiments, the first device and the second device are sockets, dies, or chiplets.

[0012] The built-in self-test technology disclosed herein provides a simple and efficient testing solution for packet transmission paths of sophisticated connection interfaces between ICs. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present disclosure will be better understood from the following description of exemplary embodiments with accompanying drawings. In addition, it should be understood that in the flowcharts of the present disclosure, the execution order of each block may be changed, and / or certain blocks may be changed, deleted, or merged.

[0014] Figure 1 FIG. 4 is a communication architecture of an interconnection interface according to an embodiment of the present invention.

[0015] Figure 2 FIG. 4 is a schematic structural diagram illustrating two packages communicating via an interconnection interface according to an embodiment of the present invention.

[0016] Figure 3 FIG. 4 is a schematic diagram illustrating a structure in which two dies in a package communicate through an interconnection interface according to an embodiment of the present invention.

[0017] Figure 4 FIG. 4 is a schematic structural diagram of a core particle according to an embodiment of the present invention.

[0018] Figure 5 FIG. 4 is a flow chart illustrating a method for performing a built-in self-test (BIST) in an interconnect interface according to an embodiment of the present invention.

[0019] Figure 6 FIG. 1 is a schematic diagram illustrating an exemplary interconnection interface and transmission of a test sequence thereof according to an embodiment of the present invention.

[0020] Figure 7 FIG. 1 is a schematic diagram illustrating an exemplary connection interface and transmission of a test sequence thereof according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following description lists various embodiments of the present invention, but is not intended to limit the scope of the present invention. The actual scope of the invention is defined by the scope of the patent application.

[0022] In the various embodiments listed below, the same reference numerals will be used to represent the same or similar elements or components.

[0023] The present disclosure provides a method and an interconnection interface for performing built-in self-test (BIST) on a packet transmission path between two devices. The interconnection interface described herein is first introduced below.

[0024] Figure 1 FIG. 1 is a communication architecture of the interconnection interface 101 according to an embodiment of the present invention. Figure 1As shown, the interconnection interface 101 includes a connection interface 102 and a connection interface 103, and the connection interface 102 and the connection interface 103 are respectively coupled to the devices Device0 and Device1 to directly communicate with Device0 and Device1. Figure 1 In the example, connection interface 102 is drawn on the outside of Device0, and connection interface 103 is drawn on the outside of Device1, but the present invention is not limited to this. In some embodiments, connection interface 102 may be located inside Device0, and connection interface 103 may be located inside Device1. Connection interface 102 and connection interface 103 can communicate via physical lines. This creates a full-duplex design for interconnection interface 101, allowing interconnection interface 101 to provide a bidirectional transmission channel between Device0 and Device1.

[0025] Specifically, device Device0 can transmit packet signal 104 and frequency signal 105 via transmitter TX0 of connection interface 102, which are received by receiver RX0 of connection interface 103. Conversely, device Device1 can transmit packet signal 106 and frequency signal 107 via transmitter TX1 of connection interface 103, which are received by receiver RX1 of connection interface 102.

[0026] During the transmission process, packets may be affected by noise, interference, distortion, bit synchronization problems, attenuation, etc. in the transmission channel, resulting in a discrepancy between the packets sent by the transmitter and the packets received by the receiver. This discrepancy is what the built-in self-test technology of the present disclosure intends to detect.

[0027] In one embodiment, devices Device0 and Device1 are two sockets. In another embodiment, devices Device0 and Device1 are two dies. In yet another embodiment, devices Device0 and Device1 are two chiplets. The following describes in more detail embodiments of two packages, two dies, or two chiplets communicating via an interconnect interface.

[0028] Figure 2 FIG is a schematic diagram showing a structure in which two packages communicate via an interconnection interface 200 according to an embodiment of the present invention. Figure 2 As shown, encapsulated socket0 and socket1 are connected to each other through the interconnection interface 200. Figure 2In the example, each package contains two clusters, labeled cluster0 and cluster1. In other cases, each package can contain one or more clusters. Each cluster contains a number of CPU cores (not shown in the example). Figure 2 Each package may contain a last level cache (LLC), an interconnect bus (i.e., the physical lines of the interconnect interface 200), and various other components (such as an input / output controller, a clock module, a power module, etc.). Each package may also be connected to a dual in-line memory module (DIMM).

[0029] Package socket 0 and socket 1 can communicate with each other by transmitting packets with a specific format through the interconnection interface 200. In this way, the CPU core in package socket 0 can access the hardware resources of socket 1 (such as LLC, DIMM or other storage media). Similarly, the CPU core in package socket 1 can also access the hardware resources of socket 0. In this way, Figure 2 All CPU cores and input / output resources of the cluster can be centrally managed and scheduled, and the hardware resources of encapsulated socket0 and socket1 can be used in a unified manner. For example, Figure 2 Any CPU core or input / output device in the package can access the memory resources owned by package socket 0 and socket 1. For another example, by transmitting a packet maintaining cache coherency through the interconnection interface 200, package socket 0 and socket 1 can maintain cache coherency between each other.

[0030] Figure 3 FIG. 3 is a schematic diagram illustrating a structure in which two dies in a package communicate via an interconnection interface 300 according to an embodiment of the present invention. Figure 3 As shown, package 301 contains two dies: Die0 and Die1, and an interconnection interface 300 between the two. Die0 and Die1 are interconnected through the interconnection interface 300. In other cases, there can be more dies in a package. Figure 3 In the example, each die contains two clusters, labeled cluster0 and cluster1. In other cases, each die can contain one or more clusters. Each cluster contains a number of CPU cores (not shown in the example). Figure 3 In addition, each die may include a last-level cache (LLC), an interconnect bus (i.e., the physical lines of the interconnect interface 300), and various other components (such as input / output controllers, clock modules, power modules, etc.).

[0031] exist Figure 3 In the embodiment, the die Die0 and Die1 can communicate by transmitting packets with a specific format to each other through the interconnection interface 300. In this way, the CPU core in the die Die0 can access the hardware resources of Die1. Similarly, the CPU core in the die Die1 can also access the hardware resources of Die0.

[0032] Figure 4 FIG. 4 is a schematic diagram showing the structure of the core particle 400 according to an embodiment of the present invention. Figure 4 As shown, chiplet 400 may include a memory controller, an interconnect bus (i.e., the physical wiring of the interconnect interface 400), and various other components (such as a routing module, a coherence module, I / O control, power control, etc.). Chiplet 400 may further connect to dual in-line memory modules (DIMMs) and I / O devices. Chiplet 400 may be connected to other chiplets, such as compute nodes, coprocessors, and accelerators, via interconnect interface 401.

[0033] In order to form a larger interconnection interface, more packages, dies and cores can be linked through the interconnection interface to form a planar or three-dimensional interconnection architecture. In one embodiment, a single package can contain multiple dies or cores.

[0034] Figure 5 The embodiment of the present invention is shown in the interconnection interface (eg Figure 2 The interconnection interface 200, Figure 3 The interconnection interface 300 or Figure 4 Flowchart of a method 500 for built-in self-testing performed within the interconnect interface 400 in FIG. Figure 5 As shown, the method 500 includes operations 501 - 503 performed by the sending part, and operations 504 - 506 performed by the receiving part.

[0035] The method 500 begins with operation 501 of the sending unit. In operation 501, one of multiple sequences is selected as a standard sequence (golden pattern). Then, the method proceeds to operation 502.

[0036] In one embodiment, the sequence is represented by an n-bit binary sequence. The present invention does not limit the size of n. For example, the sequence can be represented by a 10-bit binary sequence, such as "0101100010" or "0110100101".

[0037] The sequence may correspond to a certain hardware configuration or test requirement. That is, in operation 501, a standard sequence is selected based on the hardware configuration or test requirement. In some embodiments, the microprocessor or microcontroller may pre-set several modes of hardware configuration or test requirement, along with the corresponding sequence for each mode. One of these modes may be selected as the current mode, and the sequence corresponding to the current mode may be obtained as the standard sequence.

[0038] In step 502 , a test sequence is generated using a standard sequence and a header corresponding to the standard sequence. Then, operation 503 is entered.

[0039] In one embodiment, the header is represented by an m-bit binary sequence. The present invention does not limit the size of m, but m is typically much smaller than the n-bit standard sequence. For example, the 10-bit standard sequence "0101100010" corresponds to a 2-bit header "00," and the 10-bit standard sequence "0110100101" corresponds to a 2-bit header "01." In some embodiments, both the header and the standard sequence correspond to pre-configured hardware configurations or test requirements of a microprocessor or microcontroller.

[0040] In one embodiment, a header is added to the beginning of a standard sequence to generate a test sequence. For example, if the standard sequence is "0101100010" and its corresponding header is "00," the test sequence is created by adding "00" to the beginning of "0101100010," resulting in a test sequence of "000101100010." Alternatively, if the standard sequence is "0110100101" and its corresponding header is "01," the test sequence is created by adding "01" to the beginning of "0110100101," resulting in a test sequence of "010110100101."

[0041] In step 503 , the test sequence is transmitted to the receiving unit via the tested path. Then, the process proceeds to operation 504 .

[0042] In one embodiment, the tested path may be a physical line between the transmitting unit and the receiving unit, such as the electrical physical layer of the aforementioned interconnection interface, but the present invention is not limited thereto.

[0043] In step 504 , the receiving unit parses the received test sequence to obtain the header and the received sequence.

[0044] Under normal circumstances, the test sequence received by the receiving unit is identical to the test sequence sent by the transmitting unit. Therefore, the received sequence parsed in step 504 is identical to the standard sequence used by the transmitting unit to generate the test sequence. However, during the transmission of the test sequence from the transmitting unit via the path under test to the receiving unit, it may be affected by noise, interference, distortion, bit synchronization issues, attenuation, and other factors in the transmission channel, resulting in a discrepancy between the test sequence received by the receiving unit and the test sequence generated by the transmitting unit. Therefore, in the event of an error, the received sequence parsed from the received test sequence in step 504 may differ from the standard sequence used by the transmitting unit to generate the test sequence.

[0045] For example, under normal circumstances, the test sequence sent in step 503 is "000101100010," and the test sequence received in step 504 is also "000101100010." The parsed header and received sequence are "00" and "0101100010," respectively. However, under certain error conditions, the test sequence received in step 504 may be "000100101010," which differs from "000101100010." The parsed header and received sequence are "00" and "0100101010," respectively, indicating a difference between the received sequence and the standard sequence.

[0046] In some embodiments, the header can be formatted in a special data format to reduce the probability of header errors during transmission. For example, a header formatted with multiple consecutive 0s and 1s, such as "000111," has a much lower probability of error during transmission than a data format with frequent alternations of 0s and 1s, such as "010101." In some embodiments, a header can tolerate a small amount of data errors and still be recognized as a correct header. In other preferred embodiments, other methods for checking and correcting transmitted data can be employed to at least ensure that the header parsed by the receiving unit is trustworthy.

[0047] In operation 505 , according to the correspondence between the header and the standard sequence, the standard sequence is obtained based on the header. Then, the process proceeds to operation 506 .

[0048] In the above example, the standard sequence "0101100010" corresponds to the header "00," and the standard sequence "0110100101" corresponds to the header "01." Therefore, if the header parsed in operation 504 is "00," the standard sequence "0101100010" is obtained in operation 505; if the header parsed in operation 504 is "01," the standard sequence "0110100101" is obtained in operation 505.

[0049] In operation 506 , the standard sequence and the received sequence are compared to obtain a test result of the tested path. Method 500 ends.

[0050] In one embodiment, the test result is a bit error ratio (BER) obtained by comparing the standard sequence with the received sequence. The BER is calculated by dividing the number of bits that differ between the standard sequence and the received sequence by the total number of bits in the standard sequence and the received sequence. For example, assuming the standard sequence is a 10-bit sequence "0101100010" and the received sequence is "0100101010", there is a 2-bit difference between the two (the 4th and 7th bits), so the BER is 2 / 10 = 20%. For another example, assuming the standard sequence is a 10-bit sequence "0101100010" and the received sequence is "0011110010", there is a 3-bit difference between the two (the 2nd, 3rd, and 6th bits), so the BER is 3 / 10 = 30%.

[0051] Figure 6 FIG. 6 is a schematic diagram illustrating an exemplary interconnection interface 600 and transmission of a test sequence thereof according to an embodiment of the present invention. Figure 6 As shown, the interconnection interface 600 includes a connection interface 601 and a connection interface 602. The connection interface 601 includes a sequence generation module 603 and a sequence comparison module 605, which are respectively located in the sending part and the receiving part of the connection interface 601. Similarly, the connection interface 602 includes a sequence generation module 606 and a sequence comparison module 604, which are respectively located in the sending part and the receiving part of the connection interface 602. The connection interface 601 and the connection interface 602 are coupled to each other through a tested path 607 and a tested path 608. The tested path 607 and the tested path 608 can be two physically different physical lines, or they can be physically the same physical lines but with different signal transmission directions. In addition, the present invention does not limit the connection interface 601 or the connection interface 602 to necessarily completely including the tested path 607 or the tested path 608. In one embodiment, the connection interface 601 and the connection interface 602 may each include a portion of the tested path 607 and the tested path 608, that is, the electrical physical layer of the connection interface, while the other portions of the tested path 607 and the tested path 608 may be other components externally connected to the connection interface to form physical circuits.

[0052] The interconnection interface 600 is configured to perform the aforementioned built-in self-test method 500. In one embodiment, the sequence generation module 603 and the sequence generation module 606 in the transmitting portion perform operations 501-503 in the method 500, and the sequence comparison module 604 and the sequence comparison module 605 in the receiving portion perform operations 504-506 in the method 500. In some embodiments, the standard sequence selected in operation 501 is generated by other components of the interconnection interface 600, such as a microprocessor or microcontroller (not shown). Figure 6 ) are pre-set.

[0053] In general, the test sequence generated by the sequence generation module 603 in the transmitting portion of the connection interface 601 is transmitted to the receiving portion of the connection interface 602 via the tested path 607. The sequence comparison module 604 in the receiving portion of the connection interface 602 generates a test result for the tested path 607 based on the received test sequence. Conversely, the test sequence generated by the sequence generation module 606 in the transmitting portion of the connection interface 602 is transmitted to the receiving portion of the connection interface 601 via the tested path 608. The sequence comparison module 605 in the receiving portion of the connection interface 601 generates a test result for the tested path 608 based on the received test sequence. In some embodiments, the above-described operations of testing the tested paths 607 and 608 can be performed simultaneously.

[0054] Similar to Figure 1 In the illustrated communication architecture, the connection interface 601 and the connection interface 602 can be coupled to the first device and the second device (not shown) respectively. Figure 6 The first device and the second device are operable to communicate via the interconnect interface 600. The first device and the second device may be packages, dies, or chips as previously described.

[0055] Figure 7 FIG. 7 is a schematic diagram illustrating an exemplary connection interface 700 and transmission of a test sequence thereof according to an embodiment of the present invention. Figure 7 As shown, the connection interface 700 includes a sequence generation module 701 and a sequence comparison module 702, which are located in the sending part and the receiving part of the connection interface 700 respectively. Figure 7 The tested path 703 is drawn within the connection interface 700. However, the present invention does not limit the connection interface to including part or all of the tested path 703. In one embodiment, the tested path 703 may be the electrical physical layer of the connection interface 700. In other embodiments, part or all of the tested path 703 may be other components external to the connection interface that constitute a physical circuit.

[0056] The connection interface 700 can be equivalent to Figure 6601 or 602 in the example. If connection interface 700 is equivalent to connection interface 601, sequence generation module 701 is equivalent to sequence generation module 603, and sequence comparison module 702 is equivalent to sequence comparison module 605. If connection interface 700 is equivalent to connection interface 602, sequence generation module 701 is equivalent to sequence generation module 606, and sequence comparison module 702 is equivalent to sequence comparison module 604. Furthermore, connection interface 700 can be coupled to a package, die, or chip as described above.

[0057] The connection interface 700 is configured to perform the aforementioned built-in self-test method 500. In one embodiment, the sequence generation module 701 of the transmitting portion performs operations 501-503 of the method 500, and the sequence comparison module 702 of the receiving portion performs operations 504-506 of the method 500. In some embodiments, the standard sequence selected in operation 501 is generated by other components of the connection interface 700, such as a microprocessor or microcontroller (not shown). Figure 7 ) are pre-set.

[0058] Compared to Figure 6 In the built-in self-test interconnection interface 600, the sending part for sending the test sequence and the receiving part for receiving the test sequence are respectively in different connection interfaces (ie, connection interface 601 and connection interface 602). Figure 7 The sending and receiving of the test sequence are all performed in the same connection interface (ie, the connection interface 700). In one embodiment, the connection interface 700 may further include a switch (not shown). Figure 7 ), to switch between tests within the same connection interface and tests across connection interfaces.

[0059] The built-in self-test technology disclosed herein provides a simple and efficient testing solution for packet transmission paths of sophisticated connection interfaces between ICs.

[0060] In this specification and in the scope of patent applications, serial numbers, such as "first", "second", etc., are only for convenience of description and have no sequential relationship with each other.

[0061] The above paragraphs describe various aspects. Obviously, the teachings herein can be implemented in a variety of ways, and any specific architecture or functionality disclosed in the examples is merely representative. Based on the teachings herein, anyone skilled in the art will understand that each aspect disclosed herein can be implemented independently, or in combination with two or more aspects.

[0062] Although the present disclosure has been disclosed above with reference to the embodiments, they are not intended to limit the present disclosure. Anyone skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the invention shall be determined by the scope of the patent application attached hereto.

Claims

1. A built-in self-test method, comprising: At a transmitting unit, a standard sequence is selected, and a test sequence is generated using the standard sequence and a header corresponding to the standard sequence, and the test sequence is transmitted to a receiving unit via a tested path; and The receiving unit parses the header and a receiving sequence from the received test sequence, obtains the standard sequence based on the parsed header according to the correspondence between the header and the standard sequence, and compares the standard sequence with the receiving sequence to obtain a test result of the tested path.

2. The method of claim 1 , wherein comparing the standard sequence and the received sequence to obtain the test result of the tested path comprises: By comparing the received sequence with the standard sequence, a bit error rate (BER) is calculated.

3. The method of claim 1 , wherein generating the test sequence using the standard sequence and the header corresponding to the standard sequence comprises: The header is added to the beginning of the standard sequence to generate the test sequence.

4. A built-in self-test (BST) interconnect interface, comprising: A first connection interface, comprising a first sequence generating module and a first sequence comparing module, wherein the first sequence generating module and the first sequence comparing module are respectively located in a first transmitting portion and a first receiving portion of the first connection interface; a second connection interface coupled to the first connection interface, the second connection interface comprising a second sequence generating module and a second sequence comparing module, the second sequence generating module and the second sequence comparing module being located in a second transmitting portion and a second receiving portion of the second connection interface, respectively; wherein the first sequence generating module is configured to select a first standard sequence in the first transmitting portion, and generate a first test sequence using the first standard sequence and a first header corresponding to the first standard sequence, and the first test sequence is transmitted to the second receiving portion of the second connection interface via a first tested path; and In the second receiving unit, the first header and a first received sequence are parsed from the received first test sequence. The second sequence comparison module is configured to obtain the first standard sequence based on the parsed first header according to a correspondence between the first header and the first standard sequence, and compare the first standard sequence with the first received sequence to obtain a first test result of the first tested path.

5. The interconnection interface of claim 4 , wherein in the second transmitting portion, the second sequence generating module is configured to select a second standard sequence, use the second standard sequence and a second header corresponding to the second standard sequence to generate a second test sequence, and transmit the second test sequence to the first receiving portion of the first connection interface via a second tested path; and In the first receiving unit, the second header and a second received sequence are parsed from the received second test sequence. The first sequence comparison module is further configured to obtain the second standard sequence corresponding to the second header based on the parsed second header, and compare the second standard sequence with the second received sequence to obtain a second test result of the second tested path.

6. The interconnection interface of claim 4 , wherein in the first transmitting portion, the first sequence generating module is configured to select a third standard sequence and generate a third test sequence using the third standard sequence and a third header corresponding to the third standard sequence, wherein the third test sequence is transmitted to the first receiving portion via a third tested path; and In the first receiving unit, the third header and a third received sequence are parsed from the received third test sequence. The first sequence comparison module is configured to obtain the third standard sequence corresponding to the third header based on the parsed third header, and compare the third standard sequence with the third received sequence to obtain a third test result for the third tested path.

7. The interconnection interface as claimed in claim 4, wherein the first connection interface is coupled to a first device, and the second connection interface is coupled to a second device; and The first device and the second device are operable to communicate via the interconnection interface. 8 . The interconnect interface of claim 7 , wherein the first device and the second device are packages, dies, or chips.

9. The interconnection interface of claim 4, wherein the first sequence comparison module is further configured to calculate a bit error rate (BER) by comparing the first received sequence with the first standard sequence to obtain the first test result of the first tested path.

10. The interconnection interface of claim 4, wherein the first sequence generating module is further configured to add the first header to a beginning position of the first standard sequence to generate the first test sequence.

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