Improved method for reactive slave authentication

By creating incentive components, passing components and reference model components in the UVM verification platform, and writing response sequences in the reference model, the complex communication problem of rslt_agent component and rsp_agent component in the prior art is solved, and a more efficient verification path and better reusability of the verification environment is achieved.

CN114116345BActive Publication Date: 2025-03-21YUNHE ZHIWANG (SHANGHAI) TECHNOLOGY CO LTD
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Patent Information

Application Number
CN202111404713.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-11-24
Publication Date
2025-03-21
Estimated Expiration
2041-11-24

AI Technical Summary

Technical Problem

In the prior art, the rslt_agent component and the rsp_agent component communicate in the verification environment complex, resulting in unclear logic division, affecting the reusability of the verification environment.

Method used

By building a UVM verification platform, we create incentive components, delivery components and reference model components, and write response sequences in the reference model to complete the driving of the response results, achieving complete verification of the device under test.

Benefits of technology

Simplifies the verification path, improves the verification quality, and improves the reusability of the verification environment.

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Abstract

The present invention discloses an improved method for reactive slave verification, comprising the following steps: building a UVM verification platform, creating an excitation component, a transfer component and a reference model component; writing an input excitation in the excitation component, and the excitation component sending the input excitation to the interface component and the reference model component; the device under test acquires and processes the input excitation to obtain a signal result; the device under test outputs the signal result to the interface component; the transfer component acquires and encapsulates the signal result in the interface component to obtain transaction information; the transfer component broadcasts the transaction information to the reference model component; the reference model component processes the transaction information and the input excitation to obtain a response result; the reference model component configures and starts a response sequence, and transmits the response result to the interface component; the interface component outputs the response result to the device under test. The present invention can perform perfect verification on the device under test, the verification path is simpler, and the verification quality is improved while improving the reusability of the verification environment.
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Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to an improved method for verification using reactive slaves. Background Art

[0002] In the prior art, such as Figure 1 As shown in the figure, the req, rslt and rsp interfaces are usually encapsulated into req_agent components, rslt_agent components, and rsp_agent components, which work in active, passive and active modes respectively; first, the req_agent component works in active mode, the user writes the sequence input stimulus of the req_agent component and sends the input stimulus to the interface through the sequencer and driver of the req_agent component, and then the DUT (Device Under Test) performs calculations based on the input stimulus and outputs the signal result to the interface. At the same time, the monitor in the req_agent will broadcast the input stimulus to the reference model to calculate the expected result. Then, the rslt_agent component works in passive mode, the monitor of the rslt_agent component monitors the signal result in the interface and encapsulates the signal result into transaction information and broadcasts it outward, at this time, it is mainly broadcast to the analysis component and the sequencer in the rsp_agent component. Obviously, broadcasting to the analysis component is mainly used to analyze and compare the signal results. The purpose of broadcasting to the sequencer in the rsp_agent component is to generate a reactive slave sequence stimulus for response. At this time, the rsp_agent component works in active mode. It will use the transaction information as input stimulus to respond to the action of the DUT. At this time, the sequencer in the rsp_agent component generates a corresponding response sequence, which is sent and driven to the interface through the driver to be used as a signal input to the DUT.

[0003] However, the prior art has the defect of poor reusability. The monitor in the rslt_agent component needs to communicate with the sequencer in the rsp_agent component in the verification environment, and the rsp_agent component needs to implement some logic for generating reactive slave sequences. The above will lead to unclear logic division, making it impossible for the rslt_agent component and the rsp_agent component to be effectively encapsulated into an independent package, thereby adversely affecting the reusability of the verification environment. Summary of the invention

[0004] According to an embodiment of the present invention, an improved method for reactive slave authentication is provided, comprising the following steps:

[0005] Build UVM verification platform, create stimulus components, transfer components and reference model components;

[0006] Write input stimulus in the stimulus component, and the stimulus component sends the input stimulus to the interface component and reference model component of the UVM verification platform;

[0007] The device under test of the UVM verification platform obtains and processes input stimuli to obtain signal results;

[0008] The device under test outputs a signal result to the interface component;

[0009] The transfer component obtains and encapsulates the signal result in the interface component to obtain transaction information;

[0010] The delivery component broadcasts transaction information to the reference model component;

[0011] The reference model component processes transaction information and input stimuli to obtain response results;

[0012] Write response sequences, configure and start response sequences with reference to model components, and pass response results to interface components;

[0013] The interface component outputs the response result to the device under test to perform an action response.

[0014] Furthermore, the excitation component works in active mode.

[0015] Furthermore, the transfer component works in passive mode.

[0016] Further, the response sequence is written in the reference model component.

[0017] According to the improved method of reactive slave verification in an embodiment of the present invention, a response sequence is constructed and started in a reference model to drive the response result. Error injection into the input stimulus can be used to fully verify the device under test. The verification path is simpler, the verification quality is improved, and the reusability of the verification environment is enhanced.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The schematic diagram of the verification method using reactive slave mode in the prior art;

[0020] Figure 2 A flowchart of an improved method for reactive slave authentication according to an embodiment of the present invention;

[0021] Figure 3 The schematic diagram is a schematic diagram of an improved method for reactive slave authentication according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings to further illustrate the present invention.

[0023] First, combine Figure 2~3 The improved method for reactive slave verification in the embodiment is used to verify a chip and has a wide range of application scenarios.

[0024] like Figure 2 As shown, the improved method for reactive slave authentication according to the embodiment of the present invention comprises the following steps:

[0025] In S1, Figure 2~3 As shown in the figure, build a UVM (Universal Verification Methodology) verification platform, create stimulus components (req_agent), transfer components (rslt_agent) and reference model components.

[0026] In S2, if Figure 2~3 As shown, the input stimulus is written in the stimulus component (req_agent), and the stimulus component (req_agent) sends the input stimulus to the interface component (interface) and the reference model component of the UVM verification platform.

[0027] Furthermore, the incentive component (req_agent) works in active mode.

[0028] In S3, such as Figure 2~3 As shown in the figure, the device under test (DUT) of the UVM verification platform obtains and processes input stimuli to obtain signal results.

[0029] In S4, Figure 2~3 As shown, the device under test (DUT) outputs signal results to the interface component (interface).

[0030] In S5, Figure 2~3 As shown, after the monitor in the transmission component (rslt_agent) monitors the signal result in the interface component (interface), the transmission component (rslt_agent) obtains and encapsulates the signal result in the interface component (interface) to obtain transaction information.

[0031] Furthermore, the delivery component (rslt_agent) works in passive mode.

[0032] In S6, Figure 2~3 As shown, the delivery component (rslt_agent) broadcasts transaction information to the reference model component.

[0033] In S7, Figure 2~3 As shown, the reference model components process transaction information and input stimuli to obtain response results.

[0034] In S8, Figure 2~3 As shown, write the response sequence, configure and start the response sequence with reference to the model component, and pass the response result to the interface component (interface).

[0035] Furthermore, the response sequence is written in the reference model component, which is convenient for users to use

[0036] The random constraints of System Verilog inject errors into the sequence to verify the device under test (DUT) more perfectly. At the same time, users can construct richer incentives for the random constraints of the uvm_sequence_item class, and can construct erroneous response incentives through random constraints. Then, by monitoring the internal operation state and operation results of the device under test (DUT), the correctness of the function of the device under test (DUT) can be further judged, thereby verifying the device under test (DUT) more perfectly.

[0037] In S9, Figure 2~3 As shown, the interface component (interface) outputs a response result to the device under test (DUT) to perform an action response.

[0038] The difference between this embodiment and the prior art is that it no longer adopts the reactive slave mode, but adopts the proactive master mode. Here, it can also be seen that the user encapsulates the req, rslt and rsp interfaces into req_agent, rslt_agent and rsp_agant components respectively. First, the stimulus component (req_agent) works in active mode. The user will write the input stimulus of the stimulus component (req_agent) and send the input stimulus to the interface component (interface) through the sequencer and driver of the stimulus component (req_agent). Then the device under test (DUT) performs calculations based on the input stimulus and outputs the signal result to the interface component (interface). At the same time, the monitor in the stimulus component (req_agent) broadcasts the input stimulus to the reference model to calculate the response result. Then, the transfer component (rslt_agent) works in passive mode. After the monitor in the transfer component (rslt_agent) detects the signal result in the interface component (interface), the transfer component (rslt_agent) encapsulates the signal result into transaction information and broadcasts it to the reference model component. The reference model combines input stimulus and transaction information to calculate the response result; the user writes the response sequence in the reference model, the reference model configures and starts the response sequence, and drives the response result to the interface component (interface) through the response component (rslt_agent), and then the interface component (interface) outputs the response result to the device under test (DUT) to complete the action response of the DUT.

[0039] Above, refer to Figure 2~3 An improved method for reactive slave verification according to an embodiment of the present invention is described. By constructing a response sequence and starting it in a reference model to drive the response result, the device under test (DUT) can be fully verified by injecting errors into the input stimulus. The verification path is simpler, the verification quality is improved, and the reusability of the verification environment is improved.

[0040] It should be noted that, in this specification, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprises..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0041] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. An improved method for reactive slave authentication, characterized in that: The following steps are included: Build UVM verification platform, create stimulus components, transfer components and reference model components; Writing an input stimulus in the stimulus component, and the stimulus component sending the input stimulus to the interface component and the reference model component of the UVM verification platform; The device under test of the UVM verification platform acquires and processes the input stimulus to obtain a signal result; The device under test outputs the signal result to the interface component; The transmission component obtains and encapsulates the signal result in the interface component to obtain transaction information; The delivery component broadcasts the transaction information to the reference model component; The reference model component processes the transaction information and the input stimulus to obtain a response result; Writing a response sequence, the reference model component configuring and starting the response sequence, and delivering the response result to the interface component; The response sequence is written in the reference model component; The interface component outputs the response result to the device under test to perform an action response.

2. The improved method for reactive slave authentication as claimed in claim 1, characterized in that: The excitation component operates in active mode.

3. The improved method for reactive slave authentication as claimed in claim 1, characterized in that: The transmission component operates in passive mode.

Citation Information

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