A channel randomization circuit and method based on time-interleaved ADC

Abstract

The present invention proposes a channel randomization circuit and method based on a time-interleaved ADC, comprising: a channel selection module, configured to output M clock reception control signals and N encoded data reception control signals according to a master clock and a generated random number; a multi-phase clock distribution module, configured to generate N multi-phase clocks according to a sampling master clock, and redistribute the multi-phase clocks according to the clock reception control signals to output M redistributed clock signals; a time-interleaved ADC module, configured to output M output data and a corresponding number of channel quantization completion signals according to the redistributed clock signals; an adjustable delay module, configured to set the delay size of the data reception control signal; and a timing distribution control module, configured to control the output data to be arranged and output in chronological order according to the delayed data reception control signal and the channel quantization completion signal.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital converters, and in particular to a channel randomization circuit and method based on a time-interleaved ADC. Background Art

[0002] In recent years, with the continuous development of integrated circuit manufacturing technology and 5G technology, there is an increasing demand for ultra-high-speed, high-precision, high-performance ADCs in both military and civilian fields. In order to achieve ultra-high-speed (above 1GHz sampling rate) and high-resolution (above 10Bit) ADCs, the time-interleaved structure has gradually become the designer's preferred structure due to its simple principle and excellent performance. It improves the overall sampling rate of the ADC by time-division multiplexing according to the channel sequence.

[0003] Although the time-interleaved structure can greatly improve the sampling rate, due to the characteristics of integrated circuit technology, each channel in the multi-channel interleaved structure cannot be completely identical, which will lead to mismatches between the channels. Common mismatches are mainly offset mismatch, gain mismatch, sampling time mismatch, bandwidth mismatch, etc. In addition, in some single-channel ADC structures (SAR structure, pipelined structure), there is also mismatch between channels due to capacitor mismatch. This series of mismatches will greatly affect the dynamic performance of the ADC, causing the ADC's effective number of bits (ENOB) and spurious-free dynamic range (SFDR) to decrease. Summary of the Invention

[0004] In view of the above problems in the prior art, the present invention proposes a channel randomization circuit and method based on a time-interleaved ADC, which mainly solves the problem that the existing circuit is difficult to achieve channel randomization without affecting the performance of the original time-interleaved ADC.

[0005] In order to achieve the above-mentioned and other purposes, the technical solutions adopted by the present invention are as follows.

[0006] A channel randomization circuit based on a time-interleaved ADC, comprising:

[0007] a channel selection module, configured to output M clock reception control signals and N encoded data reception control signals according to a master clock and a generated random number; wherein M and N are positive integers, and M is greater than N;

[0008] a multi-phase clock distribution module, configured to generate N multi-phase clocks according to a sampling master clock, and redistribute the multi-phase clocks according to the clock reception control signal, and output M redistributed clock signals;

[0009] A time-interleaved ADC module, configured to output M output data and a corresponding number of channel quantization completion signals according to the redistributed clock signal;

[0010] An adjustable delay module, used to set the delay size of the data reception control signal; and

[0011] The timing distribution control module is connected to the output end of the adjustable delay module and the output end of the time interleaving ADC module respectively, and is used to control the output data to be arranged and output in time sequence according to the delayed data receiving control signal and the channel quantization completion signal.

[0012] Optionally, the channel selection module includes: a pseudo-random number generation circuit and a channel selection circuit;

[0013] The pseudo-random number generation circuit receives the master clock and a set of random number output enable signals, and outputs a set of random number output signals; the channel selection circuit receives the random number output signals and the master clock, and outputs the clock reception control signal and the data reception control signal.

[0014] Optionally, the channel selection circuit includes:

[0015] The clock status register has N addresses, each address represents a multi-phase clock, and the value stored in each address represents the channel to which the multi-phase clock at the corresponding address is connected;

[0016] A channel status register having M addresses, each address representing a channel, and a value stored in each address representing a multi-phase clock accessed by the channel at the corresponding address; and

[0017] Idle channel register, used to store channels that are not connected to the multi-phase clock;

[0018] When the master clock arrives, it is determined whether to exchange the channel stored in the address currently processed in the clock status register with the channel stored in the idle channel register according to the random number output signal; the channel status register exchanges the value stored in the corresponding address according to the exchange result between the clock status register and the idle channel register;

[0019] The corresponding clock reception control signal is output according to the value stored in the channel status register, and at the same time, the data reception control signal is output according to the value stored in the clock status register.

[0020] Optionally, when the random number output signal is at a high level, the channel stored at the corresponding address in the clock status register is exchanged with the channel stored in the idle channel register;

[0021] When the random number output signal is at a low level, no swapping action is performed.

[0022] Optionally, each of the data receiving control signals includes a K-bit binary coded signal, then 2 K Greater than or equal to M.

[0023] Optionally, the multi-phase clock distribution module includes: a multi-phase clock generation circuit and a clock redistribution transmission gate array circuit;

[0024] The multi-phase clock generation circuit is composed of N cascaded D flip-flops, with the output end of the last D flip-flop connected to the input end of the first D flip-flop to form a loop, and the output end of each D flip-flop outputs a multi-phase clock corresponding to a different channel; and

[0025] The clock redistribution transmission gate array circuit has M output terminals, each of which is composed of M transmission switches connected in parallel. Each transmission switch includes an input terminal, an output terminal, and a control terminal. The input terminal of the transmission switch receives one of the multi-phase clocks as input, and the control terminal of the transmission switch receives one of the clock reception control signals of the corresponding channel.

[0026] Optionally, the transmission switch includes:

[0027] a transmission gate, comprising a PMOS transistor and an NMOS transistor, wherein the source of the PMOS transistor and the source of the NMOS transistor are short-circuited to serve as the input of the transmission gate, the drain of the PMOS transistor and the drain of the NMOS transistor are short-circuited to serve as the output of the transmission gate, and the gate of the NMOS transistor serves as the control terminal of the transmission gate to receive the clock reception control signal; and

[0028] An inverter, wherein an input end of the inverter receives the clock receiving control signal, and a gate of the PMOS is connected to an output end of the inverter.

[0029] Optionally, the time-interleaved ADC module includes M time-interleaved ADC circuits, each of which outputs output data of one channel and a quantization completion signal;

[0030] When the redistributed clock input to the current time-interleaved ADC circuit is at a high level, if the channel quantization completion signal of the current time-interleaved ADC circuit is at a low level, the current time-interleaved ADC circuit has not completed quantization; if the channel quantization completion signal of the current time-interleaved ADC circuit is at a high level, the current time-interleaved ADC circuit has completed quantization.

[0031] Optionally, the adjustable delay module includes multiple delay units, each input signal is connected to one delay unit; the delay unit includes: a first inverter, a second inverter, S delay control NMOS tubes and S delay capacitors, wherein S corresponds to the number of bits of the delay control word of the input delay unit;

[0032] The output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter serves as the output end of the corresponding delay unit, and the input end of the first inverter serves as the input end of the corresponding delay unit; the delay control NMOS transistors are connected in parallel, and the drain of each delay control NMOS transistor is connected to the connection path between the output end of the first inverter and the input end of the second inverter through one of the delay capacitors, and the gate of each delay control MOS transistor is connected to one bit of the delay control word.

[0033] Optionally, the timing allocation control module includes:

[0034] A channel addressing decoder circuit is used to decode the delayed data receiving control signal into a thermometer code signal with a bit number M;

[0035] a data redistribution transmission gate array circuit, configured to receive a control signal and the output data of the time-interleaved ADC module and a channel quantization completion signal after decoding, and output the redistributed output data and the redistributed channel quantization completion signal; and

[0036] A data output D flip-flop circuit is used to take the reallocated output data as input and the reallocated channel quantization completion signal as a clock to output the reordered output data.

[0037] Optionally, the data redistribution transmission gate array circuit is composed of a transmission switch array, wherein the transmission switch includes an input terminal, an output terminal, and a control terminal, and each input signal corresponds to one transmission switch; each data bit of the output data of each time-interleaved ADC module is connected to the input terminal of one transmission switch, and each decoded data reception control signal is connected to the control terminals of R transmission switches, where R is the number of bits of the output data;

[0038] The channel quantization completion signal of each time-interleaved ADC module is connected to the input end of one of the transmission switches, and each of the decoded data reception control signals is connected to the control end of the corresponding transmission switch;

[0039] The output end of the transmission switch outputs the reallocated output data or the reallocated channel quantization completion signal.

[0040] Optionally, the data output D flip-flop circuit is composed of N groups of flip-flop arrays, each group of flip-flop arrays contains R D flip-flops, the input end of each D flip-flop receives one bit of the reallocated output data as input, each group of the flip-flop arrays receives a reallocated channel quantization completion signal as a clock input, and the output end of each group of the flip-flop arrays outputs one of the reordered output data.

[0041] Optionally, the master clock and the sampling master clock have the same frequency; or, the frequency of the master clock is an integer multiple of the sampling master clock frequency and the multiple is coprime with the number of remaining channels after removing redundant channels.

[0042] A channel randomization method based on a time-interleaved ADC, comprising:

[0043] Outputting M clock reception control signals and N encoded data reception control signals according to the master clock and the generated random number; wherein M and N are positive integers, and M is greater than N;

[0044] Generate N multi-phase clocks according to the sampling master clock, and redistribute the multi-phase clocks according to the clock reception control signal to output M redistributed clock signals;

[0045] Outputting M output data and a corresponding number of channel quantization completion signals according to the reallocated clock signal;

[0046] The delay size of the data receiving control signal is set, and the output data is controlled to be arranged and output in time sequence according to the delayed data receiving control signal and the channel quantization completion signal.

[0047] As described above, the channel randomization circuit and method based on time-interleaved ADC of the present invention have the following beneficial effects.

[0048] By introducing a delay, the ADC is prevented from receiving the data receiving control signal too early, which causes the data to be output in advance. Through channel selection and multi-phase clock distribution, the ADC output data that has been disrupted is output in time sequence, effectively improving the spurious-free dynamic range of the time-interleaved ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Schematic diagram of channel randomization in one embodiment of the present invention.

[0050] Figure 2 FIG. 4 is a schematic diagram of a channel randomization principle including redundant channels according to an embodiment of the present invention.

[0051] Figure 3FIG. 4 is a circuit schematic diagram of a channel randomization circuit based on a time-interleaved ADC in one embodiment of the present invention.

[0052] Figure 4 FIG. 4 is a logic function diagram of a channel selection circuit in one embodiment of the present invention.

[0053] Figure 5 The figure is a schematic diagram of the operation process of the channel selection circuit on the clock status register and the channel status register in one embodiment of the present invention.

[0054] Figure 6 Schematic diagram of the corresponding relationship between the output signal of the channel selection circuit and the value stored in the register in one embodiment of the present invention.

[0055] Figure 7 FIG. 1 is a schematic diagram of a multi-phase clock generation circuit according to an embodiment of the present invention.

[0056] Figure 8 FIG. 1 is a schematic diagram of a clock redistribution transmission gate array circuit in one embodiment of the present invention.

[0057] Figure 9 FIG. 1 is a schematic diagram of the circuit structure of a delay unit in one embodiment of the present invention.

[0058] Figure 10 FIG. 4 is a circuit schematic diagram of a data redistribution transmission gate array according to an embodiment of the present invention.

[0059] Figure 11 1 is a schematic diagram of a data output D flip-flop circuit in one embodiment of the present invention.

[0060] Figure 12 FIG. 1 is a spectrum diagram of a time-interleaved ADC in an example in which mismatch is added but no randomization is performed according to an embodiment of the present invention.

[0061] Figure 13 FIG. 1 is a spectrum diagram of a time-interleaved ADC in an example after adding mismatch and performing randomization according to an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0063] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0064] In order to solve the impact of mismatch on the performance of time-interleaved ADC, academia and industry have proposed a lot of correction algorithms to correct the mismatch between channels. However, the correction effect is often not ideal and it is impossible to eliminate all mismatches. On this basis, in order to further improve the performance of time-interleaved ADC, it is necessary to use a channel randomization solution. It improves the spurious-free dynamic range (SFDR) of the time-interleaved ADC by disrupting the working order of each channel ADC and flattening the spurious caused by the mismatch between channels to the noise floor, without affecting the effective number of bits (ENOB) of the time-interleaved ADC itself. The concept of channel randomization is shown in the figure below. Figure 1 As shown, the normal operating order of a four-channel time-interleaved ADC is channel 1, channel 2, channel 3, channel 4, channel 1, and so on. However, after channel randomization, the original operating order of 1, 2, 3, 4 is disrupted, becoming a random order of 1, 4, 1, 3, 2, and so on. While the total number of channels remains unchanged, the disrupted operating order can cause a channel to begin quantization before completing its previous quantization. Taking a four-channel time-interleaved ADC as an example, the conventional design approach is to use a single channel's quantization time four times the total quantization time of the time-interleaved ADC. The regular channel operating order ensures that after channel 1 begins quantization, it takes at least four quantization cycles (the time it takes for channels 1, 2, 3, and 4 to complete quantization in sequence) for channel 1 to begin quantizing the next input signal. However, if the channel operating order is randomly disrupted, channel 1 may be used again before four cycles have passed. To avoid this problem and ensure sufficient quantization time for each channel while still disrupting the operating order of each channel, randomization circuits typically add an additional channel to ensure sufficient quantization time for each channel. The specific principle is as follows Figure 2 As shown, channels that have been quantized for more than four clock cycles are marked as idle channels and placed in the idle channel area. This distinguishes channels in quantization from those not quantized (idle channels). Each time a new quantization is started, channels that have been quantized for more than four clock cycles are marked as idle channels and placed in the idle channel area. Then, an idle channel is randomly selected from the idle channel area to start the current quantization. This ensures that at least two channels can be randomly selected in each quantization, achieving a randomized effect.

[0065] To achieve the above-mentioned channel randomization function, the present invention provides a channel randomization circuit based on a time-interleaved ADC. The circuit includes the following modules: a channel selection module, configured to output M clock reception control signals and N encoded data reception control signals based on a master clock and a generated random number; wherein M and N are positive integers and M is greater than N; a multi-phase clock distribution module, configured to generate N multi-phase clocks based on a sampling master clock and redistribute the multi-phase clocks based on the clock reception control signals to output M redistributed clock signals; a time-interleaved ADC module, configured to output M output data and a corresponding number of channel quantization completion signals based on the redistributed clock signals; an adjustable delay module, configured to set the delay of the data reception control signals; and a timing distribution control module, respectively connected to the output of the adjustable delay module and the output of the time-interleaved ADC module, configured to control the output data to be arranged and outputted in chronological order based on the delayed data reception control signals and the channel quantization completion signals.

[0066] See also Figure 3 In one embodiment, the channel selection module may include a pseudo-random number generation circuit and a channel selection circuit; the multi-phase clock distribution module includes: a multi-phase clock generation circuit and a clock redistribution transmission gate array circuit; the time interleaved ADC module includes an M-channel time interleaved ADC circuit; the timing distribution control module includes: a channel address decoder circuit, a data redistribution transmission gate array circuit and a data output D flip-flop circuit.

[0067] For ease of explanation, the value M in the following description refers to the number of channels in the multi-channel interleaved ADC, including redundant channels. The number of redundant channels can be configured based on actual application requirements and is not limited here. The following embodiments illustrate the case where the number of redundant channels is 1, so the value N is set to the total number of channels minus 1 (i.e., M-1).

[0068] The pseudo-random number generation circuit is implemented using a linear feedback shift register (LFSR). Its inputs are the digital circuit master clock CLK1 and the random number output enable signal RANDOM_EN, and its output is the random number output signal RANDOM_OUT, which can be set to a 1-bit signal. When the digital circuit master clock is input normally, if the RANDOM_EN signal is high, RANDOM_OUT normally outputs a pseudo-random number. If the RANDOM_EN signal is low, RANDOM_OUT only outputs a low level and does not output a random number. The pseudo-random number generation circuit can be implemented using digital synthesis. Because the randomness of the required pseudo-random number must be as large as possible to meet the requirements of performance optimization, the taps of the LFSR are usually greater than 40. The data generated by the LFSR is generally a multi-bit signal with a larger bit width than the taps. The most significant bit of this signal is used as the output of the pseudo-random number generation circuit. Using Verilog to write the digital circuit and implementing the LFSR through synthesis can greatly save chip area and improve design efficiency.

[0069] In one embodiment, the channel selection circuit can be implemented using digital synthesis. Its input is the random number output signal RandomOut output by the pseudo-random number generation circuit and the digital circuit main clock CLK1. Its output has two parts, one of which is the N+1 (i.e., M) channel clock receiving control signal CH1_CLK_CONTROL <n:1>~CH M_CLK_CONTROL <n:1>, a total of M N-bit control signals; the other part is the N-channel data receiving control signal CH1_DATA_CONTROL <k:1>~CHN_DATA_CONTROL <k:1>, a total of N K-bit control signals, K is the number of coding bits, its value is determined by the number of channels M, its purpose is to reduce the number of transmission bits of the control signal, the coding can be binary coding, before coding the data receiving control signal can use thermometer code, each signal has M bits, after coding is K bits. The logical function of the channel selection circuit is as follows Figure 4 As shown in Figure 1, the number of redundant channels is typically 1. Therefore, it is assumed that channels 1 to N represent the number of channels required for the interleaved ADC without randomization, with channel M being the redundant channel. The channel selection circuit primarily operates on three registers: the first is the clock status register, which has N addresses, each representing a multiphase clock (for example, address 1 represents multiphase clock 1, and address N represents multiphase clock N). Since multiphase clocks do not require redundancy, there are at most N multiphase clocks, so the maximum address of the clock status register is N. The value stored in each address represents the channel to which the multiphase clock represented by that address is connected (for example, CHANNEL1 stored in address 1 indicates that multiphase clock 1 is connected to channel 1, and CHANNELN stored in address N indicates that multiphase clock N is connected to channel N). The second is the channel status register, which has M addresses, each representing a different channel (for example, address 1 represents channel 1, address N represents channel N, and address M represents channel M). Because there is one redundant channel, the number of addresses in the channel status register (M) is one more than the number of addresses in the clock status register (N). The value stored in each address represents the multi-phase clock accessed by the channel represented by the address (for example, CLK1 stored in address 1 indicates that multi-phase clock 1 is accessed to channel 1, and CLKN stored in address N indicates that multi-phase clock N is accessed to channel N). Due to the existence of redundant channels, the address of the channel status register will be one more than the number of multi-phase clocks, which will inevitably result in a channel without multi-phase clock access, so it is represented by NOCLK (for example, NOCLK stored in address M indicates that channel M is not accessed to the multi-phase clock and is in a redundant state). In the actual circuit, the NOCLK is a constant low level; the third is the idle channel register, which stores channels without multi-phase clock access (for example, CHANNELM in the idle channel register indicates that channel M has no multi-phase clock access and is in an idle state).

[0070] In the initial state, the clock status register sequentially stores CHANNEL1 through CHANNELN at addresses 1 through N. The channel status register sequentially stores CLK1 through CLKN at addresses 1 through N, and stores NOCLK at address M. The idle channel register stores CHANNELM. These indicate that when the system powers on and begins operation, each multiphase clock sequentially corresponds to a channel, while redundant channels without a corresponding multiphase clock become idle channels. When the digital circuit's main clock first arrives, the channel selection circuit operates on address 1 of the clock status register. Specifically, the channel selection circuit controls the value stored in address 1 based on an externally input random number (i.e., the random number output signal RandomOUT). If the externally input random number is high, the channel selection circuit swaps the value stored in address 1 with the value stored in the idle channel register. At the same time, the channel status register determines which two address values ​​in the channel status register need to be exchanged based on the value in the exchanged clock status register address 1 and the value in the idle channel register (for example, if CHANNEL1 in the clock status register address 1 and CHANNELM in the idle channel register are exchanged, then the value in the address 1 of the channel status register and the value stored in address M need to be exchanged). The process is as follows: Figure 5 As shown, after the exchange is completed, wait for the next master clock to arrive. If RandomOut is low, then no operation is performed on the clock status register, and the channel status register remains unchanged waiting for the next digital circuit master clock. When the digital circuit master clock comes for the second time, the channel selection circuit exchanges address 2 of the clock status register. When the operation of address N is completed, the next clock arrives and the address 1 is operated again, and this cycle continues. While the three registers are constantly changing, the channel selection circuit outputs the corresponding signal according to the values ​​stored in the clock status register and the channel status register. According to the channel status register, the channel selection circuit will output M N-bit thermometer code signals CH1_CLK_CONTROL <n:1>~CHM_CLK_CONTROL <n:1>The values ​​of these M signals correspond to the values ​​stored in the channel status register addresses 1 to M. If the channel status register value is CLK1, then the signal is an N-bit thermometer code 00000…01. If the channel status register value is CLK2, then the signal is an N-bit thermometer code 00000…10. Similarly, if it is CLKN, then the signal is an N-bit thermometer code 10000…00. If it is NOCLK, then the signal is an N-bit all-zero 00000…00. Based on the clock status register, the channel selection circuit will output N K-bit binary code signals CH1_DATA_CONTROL <k:1>~CH1N_DATA_CONTROL <k:1>The value of K is determined by the number of channels M. They satisfy the binary relationship, that is, the Kth power of two must be greater than or equal to M (for example, if M is 8, K is at least 3; if M is 17, K is at least 5, and so on). These N K-bit binary code signals correspond to the values ​​of the clock status register address 1 to address N. If the value of the clock status register is CHANNEL1, then the signal is 00...01. If the value of the clock status register is CHANNEL2, then the signal is 00...10. Their corresponding relationship is as follows Figure 6 shown.

[0071] See also Figure 7 In one embodiment, a multiphase clock generation circuit is composed of N cascaded D flip-flops, with the output of the last D flip-flop feeding the input of the first D flip-flop forming a loop. Its function is to provide N multiphase clocks for the time-interleaved ADC circuit. The input signal of the multiphase clock generation circuit is the sampling master clock CLK_SAMPLE, whose frequency is often consistent with the sampling frequency of the interleaved ADC. Its output signal is N multiphase clock signals CLKIN <1> ~CLKIN <n>The CLK_SAMPLE signal is input to the clock input of all D flip-flops. The signal output from the data output Dout of the first D flip-flop is input to the data input Din of the next D flip-flop. At the same time, the output signal from the data output Dout of the first D flip-flop is also used as the output CLKIN of the multi-phase clock generation circuit. <1> Similarly, the signal output from the output terminal Dout of the second D flip-flop is input to the data input terminal Din of the third D flip-flop. At the same time, the output signal from the data output terminal Dout of the second D flip-flop is also used as the output CLKIN of the multi-phase clock circuit generation circuit. <2> , and so on, until the last D flip-flop. The input signal of the last D flip-flop is the signal output by the output of the previous D flip-flop, and the signal output by its output Dout is input to the input of the first D flip-flop. At the same time, the signal output by the output of the last D flip-flop is also used as the output CLKIN of the multi-phase clock generation circuit. <n>.

[0072] In one embodiment, the clock redistribution transmission gate array circuit is mainly composed of a transmission switch array, and the input of the clock redistribution transmission gate array circuit is the N-channel multi-phase clock CLKIN generated by the multi-phase clock generation circuit. <1> ~CLKIN <n>And the N+1 (ie M) channel clock receiving control signal CH1_CLK_CONTROL output by the channel selection circuit <n:1>~CHM_CLK_CONTROL <n:1>The output of the clock redistribution transmission gate array circuit is the redistributed M-channel multi-phase clock CLKOUT <1> ~CLK OUT <m>The function of the clock redistribution transmission gate array circuit is to receive the control signal based on the input M-channel clock and distribute the input N-channel multi-phase clock to each time-interleaved ADC circuit. The circuit structure of the clock redistribution transmission gate array circuit is as follows: Figure 8 As shown in Figure 1, the clock redistribution transmission gate array circuit is composed of multiple transmission switches, each of which includes an input terminal, a control terminal, and an output terminal. The clock redistribution transmission gate array circuit has M output signals, each of which is composed of the outputs of N transmission switches connected in parallel. The input terminals of these N transmission switches are respectively multi-phase clocks CLKIN <1> ~CLKIN <n>, and the control end varies according to the output signal. If the output signal is CLKOUT <1> , then the control end is CH1_CLK_CONTROL <1> ~CH1_CLK_CONTROL <n>, if the output signal is CLKOUT <2> , then the control end is CH2_CLK_CONTROL <1> ~CH2_CLK_CONTROL <n>, and so on, if the output signal is CLKOUT <m>, then the control signals are CHM_CLK_CONTROL <1> ~CHM_CLK_CONTROL <n>, a total of N*M transmission switches are required. The transmission switch consists of a transmission gate and an inverter. The transmission gate is composed of a PMOS transistor and an NMOS transistor with their sources shorted together and their drains shorted together. The sources of the NMOS and PMOS transistors are shorted together as the input of the transmission gate, and the drains serve as the output. The control signal is directly connected to the gate of the NMOS transmission gate and also to the input of the inverter. The output of the inverter is connected to the gate of the PMOS transmission gate.

[0073] In one embodiment, an M-channel time-interleaved ADC circuit is a time-interleaved ADC circuit having M channels. It does not refer to a specific type of ADC. Any time-interleaved ADC having M channels and capable of outputting data and quantized signals for each channel is acceptable. Its input signal is the redistributed M-channel multi-clock CLKOUT output by the clock redistribution transmission gate array circuit. <1> ~CLKOUT <m>, its output signal is the M channel quantization completion signal Q <m:1>The channel output data is DATA1 OUT to DATAMOUT for each channel. The channel quantization completion signal indicates whether the channel has completed quantization. When the multi-bit clock input to the channel is high, the channel quantization completion signal is low, indicating that the channel is in the process of quantization but has not yet completed. When the channel is quantized, the channel quantization completion signal goes high, indicating that the channel has completed quantization. Channel output data refers to the output result of the ADC for each channel. It is usually multi-bit data, and the number of bits depends on the ADC resolution.

[0074] In one embodiment, the adjustable delay module circuit is composed of an inverter, an NMOS transistor and a capacitor, and its input signal is the N-channel data receiving control signal CH1_DATA_CONTROL output by the channel selection circuit. <k:1>~CHN_DATA_CONTROL <k:1>And the delay control word DELAY used to control the delay size <s:1>, S represents the number of bits of the delay control word. The more bits, the higher the delay control accuracy. Its output signal is the delayed N channel data receiving control signal CH1_DATA_CONTROL_DELAY <k:1>~CHN_DATA_CONTROL_DELAY <k:1>Its function is to adjust the delay of the data receiving control word so that the data receiving control word does not reach the subsequent circuit too quickly, ensuring that the control signal is received when the ADC is about to complete quantization, and avoiding receiving the control signal too early and causing the data to be output in advance. It consists of many delay units, and each bit of input signal requires a delay unit. The specific structure of the delay unit is as follows Figure 9 As shown. The delay unit consists of two inverters, S delay control NMOS tubes and S delay capacitors. The single-bit input signal INPUT is connected to the input of the inverter. On this output path, S capacitors are connected in parallel. The other end of each capacitor is connected to the drain of a delay control NMOS tube. At the same time, the gate of the delay control NMOS tube is connected to the corresponding delay control word. The control word controls the delay control NMOS tubes of all delay units together. The output of the inverter is connected to the input of the next inverter, and the output of the next inverter is the output of the delay unit. The size and number of the delay capacitors together determine the range and accuracy of the delay. The size of the delay is controlled by controlling the delay control word.

[0075] In one embodiment, the channel address decoder circuit is composed of logic gates, and its input is the delayed N-channel data receiving control signal CH1_DATA_CONTROL_DELAY. <k:1>~CHN_DATA_CONTROL_DELAY <k:1>The output is the decoded N-channel data receiving control signal CH1_DATA_EN <m:1>

[0076] CHN_DATA_EN <m:1>The function of the channel address decoder circuit is to decode the binary N-channel data receiving signal after the delay of the adjustable delay module into a thermometer code with an M-bit number. Since the physical distance between the channel selection circuit and the data output terminal is usually far, if the N-channel data receiving control signal is directly output using the M-bit thermometer code, the layout wiring will be too long and complicated. Therefore, the N-channel data receiving signal is first output using the K-bit binary code, and after passing through the adjustable delay module circuit, it reaches a position close to the data output terminal, and then the channel address decoder circuit is used to decode the K-bit binary code into the M-bit thermometer code. The specific circuit of the channel address decoder depends on the value of M.

[0077] In one embodiment, the data redistribution transmission gate array circuit is mainly composed of a transmission switch array. The structure of the transmission switch is the same as that of the clock redistribution transmission gate array circuit. The input of the data redistribution transmission gate array circuit has three parts. The first part is the channel quantization completion signal Q output by the M-channel time-interleaved ADC circuit. <m:1>, which is M single-bit signals; the second part is the channel output data DATA1OUT~DATAMOUT output by the M-channel time-interleaved ADC circuit, which is M multi-bit signals, and the number of bits depends on the resolution of the time-interleaved ADC; the third part is the decoded N-channel data receiving control signal CH1_DATA_EN output by the channel address decoder circuit <m:1>CHN_DATA_EN <m:1>The output of the data redistribution transmission gate array circuit has two parts. The first part is the N-channel output data after redistribution, which is N multi-bit signals. The number of bits depends on the resolution of the time-interleaved ADC. The second part is the N-channel quantization completion signal QOUT after redistribution. <n:1>, which is N single-bit signals. The function of the data redistribution transmission gate array circuit is to redistribute the output data of the input M channels and the channel quantization completion signal to N channels. This is because the working order of the channels is disrupted and the output data of each channel is not arranged in chronological order. Therefore, it is necessary to redistribute the disrupted signals in the working order so that the final output data is arranged in chronological order. The circuit diagram of the data redistribution transmission gate array circuit is shown in the figure. Figure 10 As shown, for the sake of convenience, it is assumed that the resolution (number of bits) of the time-interleaved ADC is R bits, so the input DATA1OUT~DATAMOUT is represented as DATA1OUT <r:1>~DATAMOUT <r:1>The output data of the N-channel after redistribution is represented as CH1OUT <r:1>~CHNOUT <r:1>The first part of the input signal DATA1OUT <r:1>~DATAMOUT <r:1>The decoded N-channel data receiving control signal is connected to the control terminal of different transmission switches according to the different input signals. Each control signal is connected to the control terminal of R transmission switches. For example, the control signal CH1_DATA_EN <1> Connect to DATA1OUT <1> ~DATA1OUT <r>The control terminal of the transmission switch of the input signal, the control signal CH1_DATA_EN <2> Connect to DATA2OUT <1> ~DATA2OUT <r>The control terminal of the transmission switch of the input signal... the control signal CH1_DATA_EN <m>Connect to DATAMOUT <1> ~DATAMOUT <r>It is the control terminal of the transmission switch of the input signal. The subsequent control signals are similar, the control signal CH2_DATA_EN <1> To the control signal CHM_DATA_EN <1> They are connected to DATA1OUT <1> ~DATA1OUT <r>The control terminal of the transmission switch of the input signal... the control signal CH2_DATA_EN <m>To the control signal CHM_DATA_EN <m>Connect to DATAMOUT <1> ~DATAMOUT <r>It is the control end of the transmission switch of the input signal, and so on. The second part of the input signal QOUT <m:1>Similar to the input signal in the first part, it is also connected to the input end of the transmission switch, and the input decoded N-channel data receiving control signal is also connected to the control end of different transmission switches according to different input signals. The difference is that each control signal only needs to be connected to the control end of one transmission switch. For example, the control signal CH1_DATA_EN <1> Connect to Q <1> The control terminal for the input signal, the control signal CH1_DATA_EN <2> Connect to Q <2> The control terminal of the transmission switch of the input signal... the control signal CH1_DATA_EN <m>Connect to Q <m>It is the control terminal of the transmission switch of the input signal. The subsequent control signals are similar, CH2_DATA_EN <m:1>To the control signal CHM_DATA_EN <m:1>Corresponding to Q <m>to Q <1> It is the control end of the transmission switch of the input signal, so a total of M*(R+1)*N transmission switches are required. The first part outputs the signal CH1OUT <r:1>~CHNOUT <r:1>According to the input signal and control signal of the transmission switch, they are connected to the output end of the corresponding transmission switch respectively. Each output signal must be connected to the output end of M transmission switches. For example, the output signal CH1OUT <1> ~CH1OUT <r>Respectively connected to the DATAMOUT <1> ~DATA1OUT <1> DATAMOUT <2> ~DATA1OUT <2> ...DATAMOUT <r>~DATA1OUT <r>As an input terminal, CH1_DATA_EN <m:1>As the output terminal of the transmission switch at the control end, the output signal CH2OUT <1> ~CH2OUT <r>Respectively connected to the DATAMOUT <1> ~DATA1OUT <1> DATAMOUT <2> ~DATA1OUT <2> ...DATAMOUT <r>~DATA1OUT <r>As an input terminal, CH2_DATA_EN <m:1>As the output end of the transmission switch of the control end, and so on, CHNOUT <1> ~CHNOUT <r>Respectively connected to the DATAMOUT <1> ~DATA1OUT <1> DATAMOUT <2> ~DATA1OUT <2> ...DATAMOUT <r>~DATA1OUT <r>As an input terminal, CH2_DATA_EN <m:1>The output of the transmission switch is used as the control terminal. Similarly, the other part of the output signal QOUT <n>According to the input signal of the transmission switch and the decoded data receiving control signal, they are connected to the output end of the corresponding transmission switch. Each output signal must be connected to the output end of M transmission switches. For example, QOUT <1> Connected by Q <m>~Q <1> As input, CH1_DATA_EN <m>~CH1_DATA_EN <1> As the output terminal of the control switch, QOUT <2> Connected by Q <m>~Q <1> As input terminal, CH2_DATA_EN <m>~CH2_DATA_EN <1> As the output end of the control switch, QOUT <n>Connected by Q <m>~Q <1> As input, CHM_DATA_EN <m>~CHM_DATA_EN <1> At the output end of the control switch as the control end.

[0078] In one embodiment, the data output D flip-flop circuit is mainly composed of a D flip-flop array, and its input signal is the redistributed N-channel quantization completion signal QOUT output by the data redistribution transmission gate array circuit. <n:1>And the N-channel output data CH1OUT~CHNOUT after redistribution, where QOUT <n:1>The output signal is the N-bit single-bit signal, CH1OUT~CHNOUT are multi-bit signals, and the number of bits depends on the resolution of the time-interleaved ADC. The output signal is the final output data of N channels CH1_OUT_DIFF~CHN_OUT_DIFF. The structure of the data output D flip-flop circuit is as follows: Figure 11 As shown, it is assumed that the resolution of the time-interleaved ADC is R (that is, the number of bits of the N-channel output data after redistribution is R). <r:1>~CHNOUT <r:1>They are connected to the Din input terminals (data input terminals) of R D flip-flops respectively, and the quantization completion signal is connected to each CH1OUT <r:1>~CHNOUT <r:1>As the CLK terminal of the D flip-flop data input signal (for example, QOUT <1> Access by CH1OUT <r:1>As the data input terminal of the D flip-flop CLK terminal, QOUT <2> Access by CH2OUT <r:1>The CLK terminal of the D flip-flop as the data input terminal, similarly, QOUT <n>Access by CHNOUT <r:1>As the CLK terminal of the D flip-flop of the data input terminal), a total of R*N D flip-flops are required. Output signal CH1OUT_DIFF <r:1>~CHNOUT_DIFF <r:1>Corresponding to the access to each CH1OUT <r:1>~CHNOUT <r:1>As the data output terminal (Dout terminal) of the D flip-flop data input signal (for example, CH1OUT_DIFF <r:1>Corresponding to the CH1OUT <r:1>As the data input terminal of the D flip-flop Dout terminal, CH2OUT_DIFF <r:1>Corresponding to the CH2OUT <r:1>As the data input terminal of the D flip-flop Dout terminal, and so on, CHNOUT_DIFF <r:1>Corresponding to the access by CHNOUT <r:1>Dout terminal of the D flip-flop as the data input terminal).

[0079] In one embodiment, the digital circuit master clock is typically consistent with the sampling master clock (i.e., has the same frequency). When the sampling master clock frequency is extremely high (above 1 GHz), the digitally synthesized circuit cannot support such a high frequency. Therefore, the frequency of the digital circuit master clock can be reduced. The reduced frequency must meet the following conditions: first, the reduced frequency must be an integer multiple of the sampling master clock (for example, reduced to the sampling frequency divided by 2, 3, 4, etc.); second, the frequency multiple must be coprime with the number of channels remaining after removing redundant channels (for example, for an 8-channel time-interleaved ADC after removing redundant channels, the reduced frequency of the digital circuit master clock can be divided by 3 or 5, but not by 2 or 4 because 2, 4, and 8 are not coprime). If these two conditions are met, the frequency of the digital circuit master clock can be reduced.

[0080] In one embodiment, to further verify the performance of the channel randomization circuit based on a time-interleaved ADC of the present invention, the channel randomization circuit based on a time-interleaved ADC is used for a time-interleaved SAR ADC with a sampling master clock of 4 GHz, a resolution of 12 bits (3 bits of redundancy in the ADC bit number, and 15 bits of actual output data), a Vpp of 0.8 V, and a total number of 17 channels (16 interleaved channels and 1 redundant channel for randomization) in a 28 nm CMOS process.

[0081] Based on the above indicators, the sampling master clock is 4 GHz, the multi-phase clock output by the multi-phase clock generation circuit is 16, the divided single-channel multi-phase clock speed is 250 MHz, and the digital circuit master clock is 800 MHz. The LFSR in the pseudo-random number generation circuit has a 42-bit number and a tap of [41, 20, 1]. The channel selector outputs 17 16-bit channel clock receive control signals and 16 5-bit channel data receive control signals. The number of delay control words is 5. The control words and capacitors are adjusted to ensure a delay of at least 1.25 ns. The number of bits in the channel quantization completion signal is 17, and the channel output data is 17 15-bit data. The number of reallocated channel quantization completion signals is 16, and the reallocated channel output data is 16 15-bit data. The final output signal is 16 15-bit data. Since there are 17 channels, the number of bits of the channel data receiving control signal is 5. The lower 4 bits of the 5-bit binary code 1111~0000 are used to represent channels 16 to channel 1, and the highest bit is used to represent channel 17 and non-channel 17. Therefore, in the channel address decoding circuit, a 4-16 decoder is used to convert the lower 4 bits into a 16-bit thermometer code. At the same time, whether the highest bit is 1 is directly judged whether it is channel 17. If it is 17, the 17th bit thermometer code is 1, otherwise it is 0. The combination of the two completes the decoding and converts the 5-bit binary code into a 17-bit thermometer code.

[0082] After the circuit is built, random offset values ​​in the range of -500uV to +500uV are added to the comparators in each single-channel ADC to simulate the mismatch caused by non-ideal factors. The spectrum simulation results with and without randomization are shown below. Figure 12 and Figure 13 As shown in the two spectrum results, it can be seen that after randomization is enabled, the performance of the original time-interleaved ADC is not affected (ENOB is basically the same), and the SFDR (spurious-free dynamic range) of the time-interleaved ADC is improved by nearly 10 dB, which fully demonstrates that this technology achieves channel randomization and improves the performance of the time-interleaved ADC.

[0083] In one embodiment, the present invention further provides a channel randomization method based on a time-interleaved ADC, which is used to implement the channel randomization circuit based on a time-interleaved ADC described in the aforementioned circuit embodiment. Because the technical principles of the method embodiment are similar to those of the aforementioned circuit embodiment, the same technical details will not be repeated here.

[0084] In one embodiment, a channel randomization method based on a time-interleaved ADC includes: outputting M clock reception control signals and N encoded data reception control signals based on a master clock and a generated random number; wherein M and N are positive integers, and M is greater than N; generating N multi-phase clocks based on a sampling master clock, and redistributing the multi-phase clocks based on the clock reception control signals to output M redistributed clock signals; outputting M output data and a corresponding number of channel quantization completion signals based on the redistributed clock signals; setting a delay size for the data reception control signal, and controlling the output data to be arranged and outputted in chronological order based on the delayed data reception control signal and the channel quantization completion signal.

[0085] In summary, the present invention provides a channel randomization circuit and method for time-interleaved ADCs. While achieving channel randomization without affecting the performance of the original time-interleaved ADC, the randomization method also improves the SFDR of the time-interleaved ADC under mismatch conditions. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial value.

[0086] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention. < / n> < / m> < / m> < / n> < / m> < / m> < / m> < / m> < / n> < / r> < / r> < / r> < / r> < / r> < / r> < / r> < / r> < / r> < / m> < / m> < / m> < / r> < / m> < / m> < / r> < / r> < / m> < / r> < / r> < / m> < / n> < / m> < / n> < / n> < / n> < / m> < / n> < / n> < / n>

Claims

1. A channel randomization circuit based on time-interleaved ADC, characterized in that: include: A channel selection module is configured to output M clock reception control signals and N encoded data reception control signals according to a master clock and a generated random number; wherein M and N are positive integers, and M is greater than N; the channel selection module comprises: a pseudo-random number generation circuit and a channel selection circuit; the pseudo-random number generation circuit receives the master clock and a set of random number output enable signals, and outputs a set of random number output signals; the channel selection circuit receives the random number output signals and the master clock, and outputs the clock reception control signal and the data reception control signal; the channel selection circuit comprises: a clock status register having N addresses, each address representing a multi-phase clock, and the value stored in each address representing the channel to which the multi-phase clock at the corresponding address is connected; the channel status register A register having M addresses, each address representing a channel, and a value stored in each address representing the multi-phase clock connected to the channel at the corresponding address; and an idle channel register for storing channels that are not connected to the multi-phase clock; when the master clock arrives, judging whether to exchange the channel stored in the currently processed address in the clock status register with the channel stored in the idle channel register according to the random number output signal; the channel status register exchanges the value stored in the corresponding address according to the exchange result between the clock status register and the idle channel register; outputting a corresponding clock reception control signal according to the value stored in the channel status register, and at the same time, outputting the data reception control signal according to the value stored in the clock status register; a multi-phase clock distribution module, configured to generate N multi-phase clocks according to a sampling master clock, and redistribute the multi-phase clocks according to the clock reception control signal, and output M redistributed clock signals; A time-interleaved ADC module, configured to output M output data and a corresponding number of channel quantization completion signals according to the redistributed clock signal; An adjustable delay module, used to set the delay size of the data reception control signal; and The timing distribution control module is connected to the output end of the adjustable delay module and the output end of the time interleaving ADC module respectively, and is used to control the output data to be arranged and output in time sequence according to the delayed data receiving control signal and the channel quantization completion signal.

2. The channel randomization circuit based on time-interleaved ADC according to claim 1, characterized in that: When the random number output signal is at a high level, the channel stored at the corresponding address in the clock status register is exchanged with the channel stored in the idle channel register; When the random number output signal is at a low level, no swapping action is performed.

3. The channel randomization circuit based on time-interleaved ADC according to claim 1, characterized in that: Note that each of the data receiving control signals includes a K-bit binary coded signal, then 2 K Greater than or equal to M.

4. The channel randomization circuit based on time-interleaved ADC according to claim 1, characterized in that: The multi-phase clock distribution module includes: a multi-phase clock generation circuit and a clock redistribution transmission gate array circuit; The multi-phase clock generation circuit is composed of N cascaded D flip-flops, with the output end of the last D flip-flop connected to the input end of the first D flip-flop to form a loop, and the output end of each D flip-flop outputs a multi-phase clock corresponding to a different channel; and The clock redistribution transmission gate array circuit has M output terminals, each of which is composed of M transmission switches connected in parallel. Each transmission switch includes an input terminal, an output terminal, and a control terminal. The input terminal of the transmission switch receives one of the multi-phase clocks as input, and the control terminal of the transmission switch receives one of the clock reception control signals of the corresponding channel.

5. The channel randomization circuit based on time-interleaved ADC according to claim 4, characterized in that: The transmission switch comprises: a transmission gate, comprising a PMOS transistor and an NMOS transistor, wherein the source of the PMOS transistor and the source of the NMOS transistor are short-circuited to serve as the input of the transmission gate, the drain of the PMOS transistor and the drain of the NMOS transistor are short-circuited to serve as the output of the transmission gate, and the gate of the NMOS transistor serves as the control terminal of the transmission gate to receive the clock reception control signal; and An inverter, wherein an input end of the inverter receives the clock receiving control signal, and a gate of the PMOS is connected to an output end of the inverter.

6. The channel randomization circuit based on time-interleaved ADC according to claim 1, characterized in that: The time-interleaved ADC module includes M time-interleaved ADC circuits, each of which outputs output data of one channel and a quantization completion signal; When the redistributed clock input to the current time-interleaved ADC circuit is at a high level, if the channel quantization completion signal of the current time-interleaved ADC circuit is at a low level, the current time-interleaved ADC circuit has not completed quantization; if the channel quantization completion signal of the current time-interleaved ADC circuit is at a high level, the current time-interleaved ADC circuit has completed quantization.

7. The channel randomization circuit based on time-interleaved ADC according to claim 1, characterized in that: The adjustable delay module includes multiple delay units, each input signal is connected to one delay unit; the delay unit includes: a first inverter, a second inverter, S delay control NMOS tubes and S delay capacitors, where S corresponds to the number of bits of the delay control word of the input delay unit; The output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter serves as the output end of the corresponding delay unit, and the input end of the first inverter serves as the input end of the corresponding delay unit; the delay control NMOS transistors are connected in parallel, and the drain of each delay control NMOS transistor is connected to the connection path between the output end of the first inverter and the input end of the second inverter through one of the delay capacitors, and the gate of each delay control NMOS transistor is connected to one bit of the delay control word.

8. The channel randomization circuit based on time-interleaved ADC according to claim 1, characterized in that: The timing distribution control module includes: A channel addressing decoder circuit is used to decode the delayed data receiving control signal into a thermometer code signal with a bit number M; a data redistribution transmission gate array circuit, configured to receive a control signal and the output data of the time-interleaved ADC module and a channel quantization completion signal after decoding, and output the redistributed output data and the redistributed channel quantization completion signal; and A data output D flip-flop circuit is used to take the reallocated output data as input and the reallocated channel quantization completion signal as a clock to output the reordered output data.

9. The channel randomization circuit based on time-interleaved ADC according to claim 8, characterized in that: The data redistribution transmission gate array circuit is composed of a transmission switch array, wherein the transmission switch includes an input terminal, an output terminal, and a control terminal, and each input signal corresponds to one transmission switch; each data bit of the output data of each time-interleaved ADC module is connected to the input terminal of one transmission switch, and each decoded data receiving control signal is connected to the control terminals of R transmission switches, where R is the number of bits of the output data; The channel quantization completion signal of each time-interleaved ADC module is connected to the input end of one of the transmission switches, and each of the decoded data reception control signals is connected to the control end of the corresponding transmission switch; The output end of the transmission switch outputs the reallocated output data or the reallocated channel quantization completion signal.

10. The channel randomization circuit based on time-interleaved ADC according to claim 8, characterized in that: The data output D flip-flop circuit is composed of N groups of flip-flop arrays, each group of flip-flop arrays contains R D flip-flops, the input end of each D flip-flop receives one bit of the reallocated output data as input, each group of the flip-flop arrays receives one of the reallocated channel quantization completion signals as clock input, and the output end of each group of the flip-flop arrays outputs one of the reordered output data.

11. The channel randomization circuit based on time-interleaved ADC according to claim 1, characterized in that: The master clock and the sampling master clock have the same frequency; or, the frequency of the master clock is an integer multiple of the sampling master clock frequency, and the multiple is coprime with the number of channels remaining after removing redundant channels.

12. A channel randomization method based on a time-interleaved ADC applied to the channel randomization circuit based on a time-interleaved ADC according to any one of claims 1 to 11, characterized in that: include: Outputting M clock reception control signals and N encoded data reception control signals according to the master clock and the generated random number; wherein M and N are positive integers, and M is greater than N; Generate N multi-phase clocks according to the sampling master clock, and redistribute the multi-phase clocks according to the clock reception control signal to output M redistributed clock signals; Outputting M output data and a corresponding number of channel quantization completion signals according to the reallocated clock signal; The delay size of the data receiving control signal is set, and the output data is controlled to be arranged and output in time sequence according to the delayed data receiving control signal and the channel quantization completion signal.

Images