digital processing circuitry

Abstract

The application discloses a digital processing circuit, comprising a logic unit, at least one combinational logic device, the combinational logic device comprising at least one input terminal; a filter unit is used to divide the waveform of the received initial input signal into at least two segments of waveforms within a cycle of the clock signal of the combinational logic device, and to prevent the back propagation of glitches contained in at least one segment of waveforms, so as to provide a filtered input signal to the input terminal of the combinational logic device. By preventing the back propagation of the glitches contained in at least one segment of waveforms in the initial input signal through the filter unit, the application can eliminate the influence of the glitches in the signal on the power consumption of the entire circuit in time, so as to effectively reduce the additional power consumption caused by the glitches.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and more particularly to a digital processing circuit. BACKGROUND

[0002] With the continuous development of power electronics technology, people's performance requirements for electronic devices are getting higher and higher. Among them, power consumption is one of the main factors hindering the development of electronic devices.

[0003] The power consumption in the digital processing circuit is mainly divided into dynamic power consumption and static power consumption. Static power consumption is generally derived from the leakage current of CMOS devices itself, which accounts for a small proportion in the digital processing circuit power consumption. Dynamic power consumption is mainly derived from the change of state in each combinational logic device in the circuit. Part of the state change is to achieve the logic function, and the other part is derived from the glitch mis-trigger in the initial input signal. When the initial input signal received by the input end of the combinational logic device reaches the gate unit at different times, the output end of the combinational logic device will appear signal jump due to glitch mis-trigger. The above glitch usually does not affect the actual function of the digital processing circuit in the charging and discharging process of the load capacitor, but it will cause more unnecessary power consumption. Therefore, we need to reduce the additional power consumption caused by the glitch as much as possible, so as to achieve the design requirement of low-power digital processing circuit. SUMMARY

[0004] Therefore, the present application provides a digital processing circuit, which reduces the power consumption of the whole digital processing circuit by processing the glitch of the input signal.

[0005] According to a first aspect of the present application, a digital processing circuit is provided, comprising: a logic unit comprising at least one combinational logic device, the combinational logic device comprising at least one input end; and

[0006] a filter unit connected to at least one input end of at least one combinational logic device in the logic unit, for dividing the waveform of the received initial input signal into at least two waveforms within one cycle of the clock signal of the combinational logic device, and preventing the glitch contained in at least one of the at least two waveforms from propagating backward, to provide a filtered input signal to the input end of the combinational logic device.

[0007] In one embodiment, the filter unit is configured to filter out the glitch in the waveform of the initial input signal received within the first half cycle of the clock signal.

[0008] In one embodiment, the filter unit comprises:

[0009] at least one flip-flop, each of the flip-flops being configured to filter out the glitch in one of the waveforms of the initial input signal.

[0010] In one embodiment, the trigger is a level trigger.

[0011] In one embodiment, the filter unit comprises:

[0012] a first trigger, an input of the first trigger receiving an initial input signal received by an input of the combinational logic device, a clock of the first trigger receiving the clock signal, and an output of the first trigger providing a filtered input signal of the initial input signal to the input.

[0013] In one embodiment, the filter unit divides the received initial input signal into two segments of waveforms within one cycle of the clock signal, and is used to filter glitches in the first segment of waveforms.

[0014] In one embodiment, an active trigger level of the clock signal is opposite to a type of active trigger level of the first trigger.

[0015] In one embodiment, the filter unit comprises:

[0016] a first delayer, delaying the clock signal and providing a first delay signal;

[0017] a second delayer, delaying the clock signal and providing a second delay signal;

[0018] a second trigger, an input of the second trigger receiving the initial input signal, a clock of the second trigger receiving the first delay signal, and an output of the second trigger outputting an intermediate signal; and

[0019] a third trigger, an input of the third trigger being connected to the output of the second trigger to receive the intermediate signal, a clock of the third trigger receiving the second delay signal, and an output of the third trigger providing the filtered input signal.

[0020] In one embodiment, delay coefficients of the first delayer and the second delayer are related to a period of the clock signal, and types of active trigger levels of the second trigger and the third trigger.

[0021] In one embodiment, the filter unit divides the received initial input signal into three segments of waveforms within one cycle of the clock signal, and is used to filter glitches in the first two segments of waveforms.

[0022] In one embodiment, the initial input signal is provided by an output of another combinational logic device in the logic unit.

[0023] In one embodiment, the logic unit is a multiplier formed by a combination of full adders and half adders, and the filter unit is connected to one of the inputs of one of the full adders.

[0024] The digital processing circuit provided by the embodiment of the present application connects the filter unit to at least one input of at least one combinational logic device in the logic unit, so as to divide the waveform of the initial input signal received in one cycle of the clock signal of the combinational logic device into at least two waveforms, and prevent the glitch contained in at least one of the at least two waveforms from propagating backward, thereby providing a filtered input signal to the input of the combinational logic device. The influence of the glitch on the power consumption of the entire circuit can be eliminated in time, thereby effectively reducing the additional power consumption caused by the glitch.

[0025] In another embodiment, the filter unit is used to filter out the glitch in the waveform of the initial input signal received in at least the first half of the cycle of the clock signal. In this way, the additional power consumption caused by the glitch in the logic unit can be reduced without introducing more power consumption of the filter unit.

[0026] In another embodiment, the test result of the filter unit arranged at one of the inputs of the multiplier in the multiplication circuit shows that the insertion of the filter unit at different inputs of the full adder can reduce the toggle rate of the output of the circuit, thereby reducing the power consumption. The use of this method can reduce the logic power consumption in the circuit by about 8.3% at most, thereby effectively reducing the dynamic power consumption in the multiplication circuit. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1a A schematic diagram of a digital circuit containing a generated glitch is shown; Figure 1b A schematic diagram of a digital circuit containing a propagated glitch is shown;

[0029] Figure 2 A schematic diagram of the structure of the digital processing circuit of the embodiment of the present application is shown;

[0030] Figure 3 A circuit schematic diagram of the multiplication circuit provided by the embodiment of the present application is shown;

[0031] Figure 4 A schematic diagram of the structure of the filter unit of the first embodiment of the present application is shown;

[0032] Figure 5 A waveform schematic diagram of the filter unit of the first embodiment of the present application is shown;

[0033] Figure 6 FIG2 shows a schematic structural diagram of a filtering unit according to a second embodiment of the present invention;

[0034] Figure 7 FIG. 4 is a waveform diagram of a filter unit according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention is described below based on the following embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, certain specific details are described in detail. Those skilled in the art can fully understand the present invention without describing these details. To avoid obscuring the essence of the present invention, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0036] Figure 1a A schematic diagram showing a digital circuit including a glitch generating circuit is shown. Figure 1b A schematic diagram of a digital circuit containing a propagation glitch is shown.

[0037] According to the order in which glitches are generated in digital circuits, they can be divided into generated glitches and propagating glitches. The AND gate includes a first input terminal A, a second input terminal B, and an output terminal Y. Figure 1a As shown, the digital circuit includes at least an AND gate, with a first input terminal A receiving a first signal and a second input terminal B receiving a second signal. When the glitch-free first signal and the glitch-free second signal arrive at the AND gate at different times, a generation glitch is formed. When the glitch-containing first signal and / or the second signal propagate through the AND gate, a propagation glitch is formed. Delay cells can generally be inserted into the input terminals of the logic gate unit to balance the paths of different initial input signals to reduce the generation of generation glitches. However, this method generally requires certain delay margins, and inserting delay cells increases the power consumption of the digital circuit. Hazard filtering can also be used to operate on the digital circuit itself. For example, by increasing the delay of the logic gate unit itself until it is greater than the delay difference of the initial input signals provided to the logic gate unit, the formation of generation glitches can be prevented. However, this method increases the overall delay constraints of the design.

[0038] The present application provides a digital processing circuit to better reduce the burrs of an initial input signal and thereby reduce the power consumption of a logic unit in the digital processing circuit.

[0039] Figure 2 FIG. 4 is a schematic structural diagram of a digital processing circuit according to an embodiment of the present invention.

[0040] likeFigure 2 As shown, the digital processing circuit 100 comprises a filter unit 110 and a logic unit 120. The logic unit 120 comprises at least one combinational logic device, which comprises at least one input terminal and is configured to provide an output signal OUT after logic operation. The combinational logic device is a kind of digital logic device whose output port is only related to the current input terminal of the device. The filter unit 110 is connected to at least one input terminal of at least one combinational logic device in the logic unit 120, and is configured to divide the waveform of an initial input signal IN1 received in one period of a clock signal CLK into at least two segments of waveforms, and prevent the glitch contained in at least one of the at least two segments of waveforms from propagating backward, so as to provide a filtered input signal IN2 obtained by filtering at least part of the glitch in the initial input signal to the input terminal of the combinational logic device connected thereto. The initial input signal IN1 is provided by, for example, the output terminal of another combinational logic device in the logic unit 120, or provided by an external device.

[0041] In one embodiment, the filter unit 110 is configured to filter the glitch in the waveform of the initial input signal IN1 received in at least the first half period of one period of the clock signal CLK. The glitch in the latter segment of the waveform of the initial input signal IN1 received in one period of the clock signal CLK has a lower impact on the entire logic unit 120 than the glitch in the former segment of the waveform of the initial input signal IN1.

[0042] In one embodiment, the filter unit 110 comprises at least one flip-flop, and each flip-flop is configured to filter the glitch in one segment of the waveform of the initial input signal IN1. Further, the flip-flop is a level-sensitive flip-flop.

[0043] Figure 3 A circuit schematic diagram of a multiplication circuit provided by an embodiment of the application is shown.

[0044] As shown in FIG. 1, the multiplication circuit comprises a filter unit 110 and a logic unit 120. The logic unit 120 comprises at least one combinational logic device, which comprises at least one input terminal and is configured to provide an output signal OUT after logic operation. The filter unit 110 is connected to at least one input terminal of at least one combinational logic device in the logic unit 120, and is configured to divide the waveform of an initial input signal IN1 received in one period of a clock signal CLK into at least two segments of waveforms, and prevent the glitch contained in at least one of the at least two segments of waveforms from propagating backward, so as to provide a filtered input signal IN2 obtained by filtering at least part of the glitch in the initial input signal to the input terminal of the combinational logic device connected thereto. The initial input signal IN1 is provided by, for example, the output terminal of another combinational logic device in the logic unit 120, or provided by an external device. Figure 3As shown, the illustrated digital processing circuit is a multiplication circuit for filtering at least part of glitches in the initial input signal, wherein the logic unit in the multiplication circuit is formed by a plurality of full adders and a plurality of half adders. In the present embodiment, for example, the multiplication circuit is composed of 4 half adders and 23 full adders, wherein the illustrated "FA" refers to a full adder, and the illustrated "HA" refers to a half adder. The multiplier structure in the multiplication circuit and its operation principle are not closely related to the main technical solution of the present application, and thus are not described herein. The full adder includes an addend input end a, an adder input end b, a carry output end c, and a first output end and a second output end. In the present embodiment, the filtering unit 110 in the multiplication circuit is arranged at the carry input end c of the full adder U6, for filtering at least part of the glitches in the initial input signal at the carry input end c of the full adder U6, and then reducing the power consumption of the entire multiplier by at least reducing the toggle rate of the full adder U6 in the multiplier. In the present embodiment, by arranging the filtering unit 110 at the carry input end c of the full adder U6, the toggle rates of the full adder U2, the full adder U3, the full adder U4, and the full adder U5 directly or indirectly connected to the full adder U6 are also reduced.

[0045] In other embodiments, the filtering unit 110 in the multiplication circuit is arranged at the adder input end b of the full adder U6, for filtering at least part of the glitches in the initial input signal at the adder input end b of the full adder U6, and then reducing the power consumption of the entire multiplier by at least reducing the toggle rate of at least one full adder in the multiplier.

[0046] In other embodiments, the filtering unit 110 in the multiplication circuit is arranged at the adder input end b of the full adder U6, for filtering at least part of the glitches in the initial input signal at the adder input end b of the full adder U6, and then reducing the power consumption of the entire multiplier by at least reducing the toggle rate of at least one full adder in the multiplier.

[0047] In other embodiments, the filtering unit 110 in the multiplication circuit can also be arranged at one of the input ends of other full adders. In other embodiments, the filtering unit 110 in the multiplication circuit can also be arranged at one of the input ends of at least one full adder and / or at least one half adder in the multiplier.

[0048] Figure 4 A structural schematic diagram of the filtering unit of the first embodiment of the present application is shown, Figure 5 A waveform schematic diagram of the filtering unit of the first embodiment of the present application is shown. In order to more clearly describe the present embodiment, Figure 5 Only the waveform of the received initial input signal IN1 in one clock signal period is shown in the present embodiment.

[0049] As Figure 4As shown, the glitch in the initial input signal IN1 received by one of the inputs of the combinational logic device is caused by the time difference of the first initial signal IN3 and the second initial signal IN4 reaching the input. The filter unit 110 includes a first flip-flop 111 connected to one of the inputs of the combinational logic device for dividing one period of the initial input signal IN1 into two waveforms and for filtering out the glitch in the partial waveform of the received initial input signal IN1 in one period of the clock signal CLK. The input of the first flip-flop 111 receives the initial input signal IN1 received by the input of the combinational logic device, the clock of the first flip-flop 111 receives the clock signal CLK of the combinational logic device, and the output of the first flip-flop 111 provides the filtered filter input signal IN2 to the input of the combinational logic device.

[0050] Further, the filter unit 110 further includes a first register 112 and a second register 113. The first register 112 receives the first initial signal IN3 and the clock signal CLK, and the second register 113 receives the second initial signal IN4 and the clock signal CLK. The first flip-flop 111 receives the first initial signal IN3 and the second initial signal IN4 via the first register 112 and the second register 113, respectively, and the first initial signal IN3 and the second initial signal IN4 together form the initial input signal IN1.

[0051] In other embodiments, for example, a third register is further included and connected to the output of the first flip-flop 111 to provide the filter input signal IN2 to the input of the combinational logic device.

[0052] In combination Figure 5 As shown, the period of the clock signal CLK is, for example, 1 ns, and the rising edge is the trigger edge. The first initial signal IN3 is delayed by, for example, 0.4 ns relative to the active edge of the clock signal CLK, and the second initial signal IN4 is delayed by, for example, 0.1 ns relative to the rising edge of the clock signal CLK, so that there is a glitch g1 in the waveform of the initial input signal IN1 received by the input of the first flip-flop 111 between 0.1 ns and 0.4 ns in one period of the clock signal CLK. The first flip-flop 113 receives the clock signal CLK and enters a latching state in the first half period close of the clock signal CLK, so that the glitch in the initial input signal IN1 between 0.1 ns and 0.4 ns in one period of the clock signal CLK cannot pass through the first flip-flop 111 normally, and the data continues to be transmitted until the falling edge of the clock signal CLK arrives, so that the above can prevent the glitch in the waveform of the initial input signal IN1 received in the first half period of one period of the clock signal CLK from continuing to pass backward.

[0053] Further, the active trigger edge of the clock signal CLK is opposite to the type of the active trigger level of the first flip-flop 111. Specifically, the first flip-flop 111 is a low-level triggered D flip-flop in this embodiment.

[0054] Further, the filter unit 110 divides the received initial input signal IN1 into two segments of waveforms within one period of the clock signal CLK, and is used to filter the glitches existing in the first segment of waveforms.

[0055] Figure 6 Fig. 4 shows a structural schematic diagram of the filter unit of the second embodiment of the present application, Figure 7 Fig. 5 shows a waveform schematic diagram of the filter unit of the second embodiment of the present application. In order to more clearly describe this embodiment, Figure 7 Fig. 5 only shows the waveform of the received initial input signal IN5 in one clock signal period, and the waveform of the received intermediate signal IN6 in one clock signal period.

[0056] The filter unit 210 provided by the second embodiment can be used to filter the glitches in the initial input signal IN5 when the period of the clock signal CLK is relatively long. For example, when the period of the clock signal CLK is relatively long, one or more high-level flip-flops and / or low-level flip-flops can be inserted at the same time to break the initial input signal received within one clock signal CLK period into multiple segments. When N high-level flip-flops and M low-level flip-flops are inserted and the delay coefficients of the clock signals received by the clock terminals of each flip-flop are adjusted, the initial input signal can be broken into N+M+1 segments. Since each segment of the broken waveforms is shorter, the distance that the glitches in the waveforms can be transmitted is shorter, and thus the additional power consumption caused by the glitches in the waveforms is smaller.

[0057] As Figure 6As shown, the initial input signal IN5 received by one input terminal of the combinational logic device has a glitch. The filter unit 210 includes a first delay unit 211, a second delay unit 212, a second flip-flop 213 and a third flip-flop 214. The first delay unit 211 delays the clock signal CLK and provides a first delay signal CLK1. The second delay unit 212 delays the clock signal CLK and provides a second delay signal CLK2. The second flip-flop 213 receives the initial input signal IN5 at its input terminal, receives the first delay signal CLK1 from the first delay unit 211 at its clock terminal, and outputs an intermediate signal IN6 at its output terminal. The third flip-flop 214 receives the intermediate signal IN6 at its input terminal, receives the second delay signal CLK2 from the second delay unit 212 at its clock terminal, and provides a filtered input signal IN7 at its output terminal. The initial input signal IN5 is provided by, for example, an output terminal of another combinational logic device in the logic unit.

[0058] Further, the delay coefficients of the first delay unit 211 and the second delay unit 212 are related to the period of the clock signal CLK, and the active trigger level types of the second flip-flop 213 and the third flip-flop 214.

[0059] Further, the filter unit 210 divides the initial input signal IN5 received within one period of the clock signal CLK into three segments, and filters out the glitches in the first two segments.

[0060] In combination Figure 7As shown, the period of the clock signal CLK is, for example, 1.2 ns. In this embodiment, the period of the clock signal CLK is divided into three segments by arranging the second flip-flop 213 and the third flip-flop 214 in series at the input end of the combinational logic unit. Specifically, the second flip-flop 213 is, for example, a high-level triggered D flip-flop, and the third flip-flop 214 is, for example, a low-level triggered D flip-flop. The first delay unit 211 delays the clock signal CLK by one third of a period to obtain the first clock signal CLK1, and the second delay unit 212 delays the clock signal CLK by two thirds of a period to obtain the second clock signal CLK2. The waveform of the initial input signal IN5 received in one period of the clock signal CLK is a three-segment waveform. The second flip-flop 213 is in a low-level latching state before the rising edge of the first delayed signal CLK1 arrives at 0.4 ns, so the glitch g2 in the waveform of the initial input signal IN5 received in the first third of the period of the clock signal CLK cannot be transmitted backward via the second flip-flop 213, for example. The third flip-flop 214 is in a high-level latching state before the falling edge of the second delayed signal CLK2 arrives at 0.8 ns, so the glitch g3 in the waveform of the intermediate signal IN6 received in the second third of the period of the clock signal CLK cannot be transmitted backward via the third flip-flop 214, for example.

[0061] In this application, as Figure 3 The filtering units provided in the multiplication circuit can adopt any of the above embodiments. For example, the multiplication circuit after inserting filtering units at different positions of the full adder in the multiplier is analyzed by using the RedHawk tool. Among them, inserting a filtering unit in the addend input end b or the addend input end a or the carry input end c of the full adder U6 can reduce the flip rate of the full adders U2-U6, and the above embodiments can reduce the power consumption of the entire multiplier. For example, when a filtering unit containing a low-level flip-flop is inserted in the addend input end a of the full adder U6, the power consumption of the multiplier is reduced by about 5 μW, which realizes a power consumption reduction of about 8.3%. Further, on the basis of the power consumption caused by the filtering unit itself, the total power consumption of the multiplication circuit provided in this application is still reduced.

[0062] In the design of digital circuit, the filter unit is inserted into the input terminal of the combinational logic device to reduce the invalid flip of the output terminal. The method can effectively control the delay constraint of the critical path. Even if the filter unit itself introduces power consumption, the purpose of reducing power consumption can still be achieved. After actual testing, it is found that the overall power consumption of the multiplier is reduced by about 8.3%. For circuits containing a large number of logic operations, higher low-power design requirements can be achieved.

[0063] Those skilled in the art can understand that the various modules or components according to the present application can be realized by hardware, firmware or software. The software includes, for example, coded programs formed by various programming languages such as JAVA, C / C++ / C#, SQL, etc.

[0064] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A digital processing circuit, wherein: include: a logic unit, comprising at least one combinational logic device, wherein the combinational logic device comprises at least one input terminal; as well as a filtering unit connected to at least one input terminal of at least one combinational logic device in the logic unit, configured to divide the waveform of the received initial input signal into at least two waveform segments within one cycle of the clock signal of the combinational logic device, and prevent burrs contained in at least one of the at least two waveform segments from propagating backward, so as to provide a filtered input signal to the input terminal of the combinational logic device; The filtering unit comprises: a first flip-flop, wherein an input terminal of the first flip-flop receives the initial input signal, a clock terminal of the first flip-flop receives the clock signal, an output terminal of the first flip-flop provides the filtered input signal, and the first flip-flop enters a latched state in the first half cycle of the clock signal, so that a glitch of the initial input signal in the first half cycle of the clock signal cannot be transmitted backward; Or the filtering unit includes: A first delay device, delaying the clock signal and providing a first delayed signal; A second delayer, delaying the clock signal and providing a second delayed signal; a second flip-flop, wherein an input terminal of the second flip-flop receives the initial input signal, a clock terminal of the second flip-flop receives the first delayed signal, and an output terminal of the second flip-flop outputs an intermediate signal; and a third flip-flop, wherein an input terminal of the third flip-flop is connected to an output terminal of the second flip-flop to receive the intermediate signal, a clock terminal of the third flip-flop receives the second delayed signal, and an output terminal of the third flip-flop provides the filtered input signal; The second trigger enters a latched state in the first third of the clock signal cycle, so that the glitches of the initial input signal in the first third of the clock signal cycle cannot be transmitted backward, and the third trigger enters a latched state in the second third of the clock signal cycle, so that the glitches of the intermediate signal in the second third of the clock signal cycle cannot be transmitted backward.

2. The digital processing circuit according to claim 1, wherein: The first trigger, the second trigger, and the third trigger are all level triggers.

3. The digital processing circuit according to claim 1, wherein: The effective trigger level of the clock signal is of opposite type to the effective trigger level of the first flip-flop.

4. The digital processing circuit according to claim 1, wherein: The delay coefficients of the first delay device and the second delay device are related to the period of the clock signal and the effective trigger level types of the second flip-flop and the third flip-flop.

5. The digital processing circuit according to claim 1, wherein: The filtering unit divides the received initial input signal into three waveform segments within one cycle of the clock signal, and is used to filter out burrs in the first two waveform segments.

6. The digital processing circuit according to claim 1, wherein: The initial input signal is provided by the output terminals of other combinational logic devices in the logic unit.

7. The digital processing circuit according to claim 1, wherein: The logic unit is a multiplier formed by combining a plurality of full adders and half adders, and the filtering unit is connected to one of the input ends of one of the full adders.

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