Method for supporting coexistence of heterogeneous CPUs in a qemu emulator

Abstract

The application discloses a method for supporting heterogeneous CPU coexistence in a Qemu simulator, and is based on the following configuration: defining a super CPU type when implementing the simulator, so that the super type definition contains three attributes of X86 CPU, Shenwei AI main core CPU and Shenwei AI slave core CPU, and the corresponding types are defined as SW types; the method comprises the following steps: step 1, registering the CPU types for different types of CPUs; and step 2, initializing the types for different types of CPUs. In the Qemu simulator, the method supports the heterogeneous CPU coexistence of the X86+Shenwei AI heterogeneous model through the heterogeneous CPU type definition and initialization process of the super type, and lays a foundation for realizing the full-system simulation of the X86+AI acceleration card in the same Qemu simulation environment.

Description

TECHNICAL FIELD

[0001] The application relates to a method for supporting heterogeneous CPU coexistence in a Qemu emulator, and belongs to the technical field of computing. BACKGROUND

[0002] Qemu (Quick Emulator) is an open-source full-system emulator and virtual machine monitor (VMM), which can simulate many types of CPUs, simulate CPUs through dynamic binary translation, and provide a series of hardware models, so that the guest OS believes that it is directly in contact with hardware, and actually is in contact with the hardware simulated by Qemu, and Qemu translates the instructions to the real hardware for operation. Through this mode, the guest OS can interact with the hard disk, network card, CPU, CD-ROM, audio device and USB device on the host. Qemu plays an important role in hardware development and basic software development.

[0003] The existing Qemu emulator is mainly designed for a unified system architecture and can support single-core or multi-core CPUs of the same architecture, such as X86, arm, mips, alpha, spark, etc. However, the problem of heterogeneous CPU coexistence is faced when an X86 server is added with a Sunway AI acceleration card for full-system simulation in the same Qemu emulator. SUMMARY

[0004] The application aims to provide a method for supporting heterogeneous CPU coexistence in a Qemu emulator, so as to solve the problem of how to simulate X86 and Sunway AI heterogeneous CPUs in the same Qemu emulator.

[0005] To achieve the above-mentioned purpose, the application provides a method for supporting heterogeneous CPU coexistence in a Qemu emulator, which is based on the following configurations for the X86+Sunway AI heterogeneous model:

[0006] A super CPU type is defined in the implementation of the emulator, so that the super type definition contains three attributes of X86 CPU, Sunway AI main core CPU and Sunway AI slave core CPU, and the corresponding types are defined as SW types;

[0007] The method comprises the following steps:

[0008] Step 1, register the CPU types for different types of CPUs, as follows:

[0009] Step 11, register the Sunway AI main core CPU type:

[0010] 1) Define the ShenWei AI main core CPU type;

[0011] 2) The parent class of the type is TYPE_SW64_CPU;

[0012] 3) The class initialization function is swai_cpu_class_init;

[0013] 4) The processor initialization function is swai_init;

[0014] 5) The type name is swai

[0015] 6) Call the type_register function to initialize the type;

[0016] Step 12, register the ShenWei AI slave core CPU type:

[0017] 1) Define the ShenWei AI slave core CPU type;

[0018] 2) The parent class of the type is TYPE_SW64_CPU;

[0019] 3) The class initialization function is slave_cpu_class_init;

[0020] 4) The processor initialization function is slave_cpu_init;

[0021] 5) The type name is slave-cpu

[0022] 6) Call the type_register_static function to initialize the type;

[0023] 7) Release the allocated resources;

[0024] Step 2, initialize the type for different types of CPUs, as follows:

[0025] Step 21, ShenWei AI main core CPU type initialization:

[0026] 1) Define a variable cc of type CPUClass and initialize it;

[0027] 2) Assign disas_set_info to swai_cpu_disas_set_info;

[0028] 3) The handle_mmu_fault function is swai_cpu_handle_mmu_fault;

[0029] 4) the interrupt handling function (do_interrupt) is swai_cpu_do_interrupt;

[0030] Step 22, the Sunway AI initializes from the core CPU type:

[0031] 1) define a variable cc of type CPUClass and initialize it;

[0032] 2) define a variable dc of type DeviceClass and initialize it;

[0033] 3) get the information of the SW64CPUClass scc from the ObjectClass object oc;

[0034] 4) get the information of the SlaveCPUClass slcc from the ObjectClass object oc;

[0035] 5) assign values to the members realize, props, etc. of dc;

[0036] 6) assign a value to the parent_realize member of slcc;

[0037] 7) assign values to the members has_work, set_pc, tcg_initialize, disas_set_info, dump_state, handle_mmu_fault, do_interrupt, get_phys_page_debug, do_unaligned_access, cpu_exec_interrupt, etc. in cc;

[0038] 8) initialize the global synchronization mutex qemu_global_sync_mutex;

[0039] 9) initialize the global response mutex qemu_global_reply_mutex;

[0040] 10) initialize the global rma mutex qemu_global_rma_mutex;

[0041] 11) initialize the synchronization mutex qemu_slave_syn_mutex for each slave core group;

[0042] 12) initialize the slave list mutex qemu_slave_list_lock.

[0043] Thanks to the use of the above technical solutions, the present application has the following advantages over the prior art:

[0044] The application provides a method for supporting heterogeneous CPU coexistence in a Qemu simulator, which supports heterogeneous CPU coexistence in the Qemu simulator by means of heterogeneous CPU type definition and initialization process of the super type for the X86+ Shenwei AI heterogeneous model, and lays a foundation for realizing full-system simulation of an X86+ AI acceleration card in the same Qemu simulation environment. DETAILED DESCRIPTION

[0045] Embodiment: The application provides a method for supporting heterogeneous CPU coexistence in a Qemu simulator, which mainly realizes support for heterogeneous CPU type structure definition and initialization processing flow, and solves the problems of heterogeneous CPU coexistence and initialization.

[0046] In the Qemu system simulator, the CPU is also a device, so the CPU class inherits from the Device class. Compared with other devices, the CPU device has a very large variety.

[0047] Firstly, the CPU has different architectures, and for each architecture of the CPU, the CPU manufacturer will continuously add new features and update the architecture of the CPU over time. This update results in various CPU models of the architecture.

[0048] In order to support X86 CPU, Shenwei AI main core CPU and Shenwei AI slave core CPU in the simulator at the same time, a super CPU type is defined in the implementation of the simulator, which covers the CPU features of X86, Shenwei AI main core and Shenwei AI slave core, and is specifically as follows:

[0049]

[0050]

[0051] In the above super type definition, CPUX86State and X86CPU are no longer the previous basic CPUX86State and X86CPU, and contain three attributes of X86, main core CPU and slave core CPU.

[0052] Meanwhile, the corresponding type is defined as the SW type, so that X86 CPU, Shenwei AI main core CPU and Shenwei AI slave core CPU can be respectively registered and created on the basis of the super type according to the needs when the CPU is created.

[0053]

[0054] The process of registering the Shenwei AI main core CPU type is as follows:

[0055] 1) Define the ShenWei AI main core CPU type;

[0056] 2) The parent class of the type is TYPE_SW64_CPU;

[0057] 3) The class initialization function is swai_cpu_class_init;

[0058] 4) The processor initialization function is swai_init;

[0059] 5) The type name is swai

[0060] 6) Call the type_register function to initialize the type;

[0061] 7) Release the allocated resources.

[0062] The process of registering the ShenWei AI slave core CPU type is as follows:

[0063] 1) Define the ShenWei AI slave core CPU type;

[0064] 2) The parent class of the type is TYPE_SW64_CPU;

[0065] 3) The class initialization function is slave_cpu_class_init;

[0066] 4) The processor initialization function is slave_cpu_init;

[0067] 5) The type name is slave-cpu

[0068] 6) Call the type_register_static function to initialize the type;

[0069] 7) Release the allocated resources.

[0070] During type initialization, the initialization content for different types of CPUs is also different;

[0071] The ShenWei AI main core CPU type initialization process is as follows:

[0072] 1) Define the variable cc type as CPUClass and initialize it;

[0073] 2) Assign disas_set_info to swai_cpu_disas_set_info;

[0074] 3) The handle_mmu_fault function is swai_cpu_handle_mmu_fault;

[0075] 4) the interrupt handling function (do_interrupt) is swai_cpu_do_interrupt;

[0076] The initialization flow of the Sunway AI from the core CPU type is as follows:

[0077] 1) a variable cc of the CPUClass type is defined and initialized;

[0078] 2) a variable dc of the DeviceClass type is defined and initialized;

[0079] 3) information of the SW64CPUClass scc is obtained from the ObjectClass object oc;

[0080] 4) information of the SlaveCPUClass slcc is obtained from the ObjectClass object oc;

[0081] 5) the realize, props and other members of the dc are assigned values;

[0082] 6) the parent_realize member of the slcc is assigned a value;

[0083] 7) the has_work, set_pc, tcg_initialize, disas_set_info, dump_state, handle_mmu_fault, do_interrupt, get_phys_page_debug, do_unaligned_access, cpu_exec_interrupt and other members in the cc are assigned values;

[0084] 8) the global synchronization mutex qemu_global_sync_mutex is initialized;

[0085] 9) the global response mutex qemu_global_reply_mutex is initialized;

[0086] 10) the global rma mutex qemu_global_rma_mutex is initialized;

[0087] 11) the synchronization mutex qemu_slave_syn_mutex is initialized for each slave core group;

[0088] 12) the slave list mutex qemu_slave_list_lock is initialized.

[0089] In order to better understand the present application, the terms used in the present text will be briefly explained as follows:

[0090] Qemu: Quick Emulator, an open source full-system emulator;

[0091] Heterogeneous: Mainly refers to the CPU using different instruction sets and different architectural designs.

[0092] AI: Artificial Intelligence.

[0093] Accelerator card: A processor product specially designed to accelerate algorithm execution. In the AI ​​field, accelerator cards generally use the PCIe interface to connect to the server.

[0094] Management core, main core: In a multi-core architecture, the core that is specifically responsible for management functions among the many processing cores of the CPU is called the management core, also called the main core.

[0095] Computing core and slave core: In a multi-core architecture, the core that is specifically responsible for computing functions among the many processing cores of the CPU is called a computing core, also called a slave core.

[0096] When using the above method to support the coexistence of heterogeneous CPUs in the Qemu emulator, in the Qemu emulator, for the heterogeneous model of X86+Shenwei AI, support for the coexistence of heterogeneous CPUs is achieved through the super-type heterogeneous CPU type definition and initialization process, laying the foundation for the full-system simulation of X86+AI accelerator card in the same Qemu simulation environment.

[0097] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications made in accordance with the spirit of the present invention are intended to be covered by the scope of protection of the present invention.

Claims

1. A method for supporting the coexistence of heterogeneous CPUs in a Qemu emulator, characterized by: The heterogeneous model for X86+Shenwei AI is based on the following configuration: When implementing the simulator, define a super CPU type, so that the super type definition includes three attributes: X86CPU, Shenwei AI master core CPU, and Shenwei AI slave core CPU. At the same time, define the corresponding type as SW type; The following steps are involved: Step 1: Register the CPU type for different types of CPUs, as follows: Step 11. Register the CPU type of the Shenwei AI main core: 1) Define the CPU type of Shenwei AI main core; 2) The parent class of the type is TYPE_SW64_CPU; 3) The class initialization function is swai_cpu_class_init; 4) The processor initialization function is swai_init; 5) The type name is swai 6) Call the type_register function to initialize the type; Step 12. Register the Shenwei AI slave core CPU type: 1) Define the CPU type of Shenwei AI slave core; 2) The parent class of the type is TYPE_SW64_CPU; 3) The class initialization function is slave_cpu_class_init; 4) The processor initialization function is slave_cpu_init; 5) Type name is slave-cpu 6) Call the type_register_static function to initialize the type; 7) Release allocated resources; Step 2: Perform type initialization for different types of CPUs, as follows: Step 21: Initialize the CPU type of the Shenwei AI main core: 1) Define the variable cc type as CPUClass and initialize it; 2) Assign disas_set_info to swai_cpu_disas_set_info; 3) The page fault handling function handle_mmu_fault is swai_cpu_handle_mmu_fault; 4) The interrupt handling function do_interrupt is swai_cpu_do_interrupt; Step 22, Shenwei AI is initialized from the core CPU type: 1) Define the variable cc type as CPUClass and initialize it; 2) Define the variable dc type as DeviceClass and initialize it; 3) Get the information of SW64CPUClass scc from ObjectClass object oc; 4) Get the information of SlaveCPUClass slcc from ObjectClass object oc; 5) Assign values ​​to the realize and props members of dc; 6) Assign a value to the parent_realize member of slcc; 7) Assign values ​​to the has_work, set_pc, tcg_initialize, disas_set_info, dump_state, handle_mmu_fault, do_interrupt, get_phys_page_debug, do_unaligned_access, and cpu_exec_interrupt members in cc; 8) Initialize the global synchronization mutex qemu_global_sync_mutex; 9) Initialize the global response mutex qemu_global_reply_mutex; 10) Initialize the global RMA mutex qemu_global_rma_mutex; 11) Initialize the synchronization mutex qemu_slave_syn_mutex for each slave core group; 12) Initialize the slave core list mutex qemu_slave_list_lock.

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