Self-Describing System Using a Single Source / Multiple Destination Cable

Abstract

An information processing system may include: a plurality of communication destinations; a communication source; a single-source / multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a respective communication destination of this branch; and a logic device communicatively coupled to the communication source and the single-source / multi-destination cable and configured to convey to each of the plurality of branches both analog source identification information and digital source identification information regarding the communication source.

Description

Technical Field

[0001] The present disclosure generally relates to information processing systems and, more particularly, to methods and systems for identifying all couplings of a single-source / multi-destination cable by a system management entity in an information processing system. Background Art

[0002] As the value and use of information continue to increase, individuals and businesses seek additional ways to process and store information. One option available to users is an information processing system. An information processing system typically processes, compiles, stores, and / or communicates information or data for business, personal, or other purposes, thereby allowing users to leverage the value of the information. Since the technologies and information processing needs and requirements vary among different users or applications, information processing systems may also vary in terms of what information is processed, how the information is processed, how much information is processed, stored, or communicated, and how quickly and efficiently the information can be processed, stored, or communicated. The variations in information processing systems allow the information processing systems to be general-purpose or configured for a particular user or particular use (such as financial transaction processing, flight reservation, enterprise data storage, or global communication). Additionally, an information processing system may include various hardware and software components that can be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.

[0003] Solid state drives (such as non-volatile memory express (NVMe) devices) may be coupled to an input / output (I / O) backplane, which in turn may be coupled to a motherboard via a peripheral component interconnect express (PCIe) cable. In some cases, such a cable may include a single-source / multi-destination cable (also referred to as a Y-shaped cable). However, under existing methods, multi-destination cable coupling may be limited to a hard-coded table of channel mapping and limited to symmetric bifurcation. In other words, in the case of using existing methods, the two destinations of a dual-destination cable must have the same bifurcation requirements because the two destinations share the same source. For example, if a single x16 source has a first destination that requires a single x8 link and a second destination that requires four x2 links, the two destinations may not be able to share the same source because each destination may disrupt the analog voltage detected at the source. Additionally, each destination may not be able to detect which eight channels it is coupled to at the source. Summary of the Invention

[0004] In accordance with the teachings of the present disclosure, the disadvantages and problems associated with existing methods for detecting connectivity in systems including single-source / multi-destination cables may be reduced or eliminated.

[0005] In accordance with an embodiment of the present disclosure, an information processing system may include: a plurality of communication destinations; a communication source; a single-source / multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a corresponding communication destination of this branch; and logic means communicatively coupled to the communication source and the single-source / multi-destination cable and configured to convey to each of the plurality of branches both analog source identification information and digital source identification information regarding the communication source.

[0006] In accordance with these and other embodiments of the present disclosure, a method may include, in an information processing system having a plurality of communication destinations, a communication source, and a single-source / multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a corresponding communication destination of this branch: conveying to each of the plurality of branches both analog source identification information and digital source identification information regarding the communication source.

[0007] In accordance with these and other embodiments of the present disclosure, an article of manufacture may include: a non-transitory computer-readable medium; and computer-executable instructions carried on the computer-readable medium, the instructions being readable by a processing device and which, when read and executed, cause the processing device to, in an information processing system having a plurality of communication destinations, a communication source, and a single-source / multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a corresponding communication destination of this branch: convey to each of the plurality of branches both analog source identification information and digital source identification information regarding the communication source.

[0008] The technical advantages of the present disclosure may be apparent to those skilled in the art from the drawings, description, and claims included herein. The objectives and advantages of the embodiments will be achieved and realized at least by the elements, features, and combinations particularly pointed out in the claims.

[0009] It will be understood that the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the claims set forth in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the embodiments of the present invention and their advantages may be obtained by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals indicate like features and in which:

[0011] Figure 1 A block diagram of an example information processing system in accordance with an embodiment of the present disclosure is shown;

[0012] Figure 2Shows an example waveform of source information signaling driven by a logic device in accordance with an embodiment of the present disclosure; and

[0013] Figure 3 Shows a block diagram of another example information processing system in accordance with an embodiment of the present disclosure. Detailed Description

[0014] By reference Figures 1 to 3 the preferred embodiments and their advantages are best understood, where like reference numerals are used to indicate like and corresponding parts.

[0015] For purposes of the present disclosure, an information processing system may include any tool or collection of tools operable to compute, classify, process, transmit, receive, retrieve, generate, switch, store, display, indicate, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for commercial, scientific, control, entertainment, or other purposes. For example, the information processing system may be a personal computer, a personal digital assistant (PDA), a consumer electronic device, a network storage device, or any other suitable device, and may vary in size, shape, performance, functionality, and price. The information processing system may include a memory, one or more processing resources (such as a central processing unit (“CPU”) or hardware or software control logic). Additional components of the information processing system may include one or more storage devices, one or more communication ports for communicating with external devices, and various input / output (“I / O”) devices (such as a keyboard, a mouse, and a video display). The information processing system may also include one or more buses operable to transfer communications between the various hardware components.

[0016] For purposes of the present disclosure, a computer-readable medium may include any tool or collection of tools that can retain data and / or instructions for a period of time. The computer-readable medium may include, but is not limited to: storage media such as direct access storage devices (e.g., hard disk drives or floppy disks), sequential access storage devices (e.g., magnetic tape disk drives), optical disks, CD-ROMs, DVDs, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and / or flash memory; and communication media such as wires, optical fibers, microwaves, radio waves, and other electromagnetic and / or optical carriers; and / or any combination of the foregoing.

[0017] For purposes of the present disclosure, an information processing resource may broadly refer to any component system, device, or equipment of an information processing system, including but not limited to processors, service processors, basic input / output systems, buses, memories, I / O devices and / or interfaces, storage resources, network interfaces, motherboards, and / or any other component and / or element of the information processing system.

[0018] Figure 1 FIG. 2 shows a block diagram of an exemplary information processing system 102 in accordance with an embodiment of the present disclosure. In some embodiments, the information processing system 102 may include a server or be an integral part of a server. In other embodiments, the information processing system 102 may be a personal computer. In these and other embodiments, the information processing system 102 may be a portable information processing system (e.g., a laptop computer, a notebook computer, a tablet computer, a handheld device, a smart phone, a personal digital assistant, etc.). As Figure 1 depicted, the information processing system 102 may include a motherboard 101 and a backplane 121 communicatively coupled to the motherboard 101 via a cable 112.

[0019] The motherboard 101 may include a circuit board configured to provide structural support for one or more information processing resources of the information processing system 102 and / or to electrically couple one or more of such information processing resources to each other and / or to other electrical or electronic components external to the information processing system 102. As Figure 1 shown, the motherboard 101 may include a processor 103, a memory 104 communicatively coupled to the processor 103, a host controller 106 communicatively coupled to the processor 103, a logic device 108 communicatively coupled to the host controller 106, and a source 110 communicatively coupled to the host controller 106 and the logic device 108.

[0020] The processor 103 may include any system, apparatus, or device configured to interpret and / or execute program instructions and / or process data, and may include, but is not limited to, a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or any other digital or analog circuit configured to interpret and / or execute program instructions and / or process data. In some embodiments, the processor 103 may interpret and / or execute program instructions and / or process data stored in the memory 104 and / or another component of the information processing system 102.

[0021] The memory 104 may be communicatively coupled to the processor 103 and may include any system, apparatus, or device (e.g., a computer readable medium) configured to retain program instructions and / or data for a period of time. The memory 104 may include RAM, EEPROM, PCMCIA cards, flash memory, magnetic storage devices, magneto-optical storage devices, or any suitable collection and / or set of volatile or non-volatile memories that retain data after power to the information processing system 102 is disconnected. Although the memory 104 is Figure 1 depicted as being integral with the motherboard 101, in some embodiments, all or a portion of the memory 104 may reside external to the motherboard 101.

[0022] The host controller 106 can be any system, apparatus, or device configured to control certain data paths (e.g., the data flow between the processor 103, the memory 104, and the peripherals) and support certain functions of the processor 103. The host controller 106 can also be referred to as the "chipset" or "platform controller hub" of the information processing system 102. One such function of the host controller 106 can include remote out-of-band management for the information processing system 102 to monitor, maintain, update, upgrade, and / or repair the information processing system 102. In some embodiments, such hardware and firmware can be compatible with Intel Active Management Technology.

[0023] The logic device 108 can include any system, apparatus, or device configured to transmit source information to a plurality of destinations 130A on the backplane 121 via a plurality of branches of the source information line 114 of the cable 112 as described in more detail below. As Figure 1 shown, the logic device 108 can be communicatively coupled to the host controller 106 via a system management bus (SMBus) or other suitable communication topology. In some embodiments, the logic device 108 can include a complex programmable logic device.

[0024] The source 110 can include any system, device, or apparatus configured to act as a cable interface for the cable 112 to communicate data between the host controller 106 and the cable 112 (e.g., via PCIe) and to communicate information from the logic device 108 to the cable 112 on the source information line 114. Thus, the source 110 can include a suitable connector or socket for receiving the cable 112.

[0025] The cable 112 can include a plurality of electrically isolated lines and can terminate at each end in a connector or other terminals configured to be electrically and mechanically coupled to the source 110 and the destinations 130. In some embodiments, the cable 112 can include a single-source / multi-destination cable having a plurality of branches. As Figure 1 shown, each branch of the cable 112 can include a series resistor 116 (e.g., resistors 116A, 116B, 116C, 116D), which enables the identification of channel start / offset and width at the destinations 130. Each of the resistors 116A, 116B, 116C, and 116D can have a different resistance. Although the cable 112 is shown in Figure 1 as having four branches for clarity and illustrative purposes, the cable 112 can include any suitable number of branches. Additionally, for clarity and illustrative purposes, Figure 1 the actual communication channels and communication lines for communicating data between the host controller 106 and the destinations 130 are not shown.

[0026] The backplane 121 may include any system, apparatus, or device (e.g., a printed circuit board) configured to provide power and / or signals (e.g., data and sideband signals) to each of one or more devices 134 received at corresponding connectors (e.g., socket connectors) of the backplane 121, such connectors being configured to mechanically couple and electrically couple the devices 134 to conductive paths of the backplane 121. As Figure 1 shown, the backplane 121 may include a plurality of destinations 130 (e.g., destinations 130A, 130B, 130C, and 130D), each destination being associated with a corresponding device 134.

[0027] Each destination 130 may include any system, apparatus, or device configured to serve as a cable interface for the cable 112 to convey data between the device 134 and the cable 112. Thus, each destination 130 may include a suitable connector or socket for receiving the cable 112.

[0028] Each device 134 may include any suitable input / output device configured to communicate with the processor 103 and, in some embodiments, may include one or more storage resources for storing data. For example, in some embodiments, the device 134 may include an NVMe storage device or other solid state drive. For illustrative purposes, four devices 134 are shown to be present in the backplane 121. However, the backplane 121 may include any suitable number of connectors for receiving the devices 134, and at any time, the corresponding devices 134 may not be loaded into such connectors, some or all of such connectors. In some embodiments, each device 134 may include a processing unit, such as a microcontroller unit (MCU), for performing some or all of the functions of such device 134.

[0029] Figure 2 An example waveform of source information signaling driven by the logic device 108 on the source information line 114 is shown in accordance with an embodiment of the present disclosure. As Figure 2 shown, in operation, according to existing methods for conveying analog source information, when activating the logic device 108, the logic device 108 may begin by tri-stating the source information line 114 to drive a high impedance static analog source signal 202 on the source information line 114 to identify the source 110. This analog source signal 202 may be sampled by the backplane 121 (e.g., such as a microcontroller unit, now shown) and used to identify the source 110 to the backplane 121. In Figure 2 the example shown, the static voltage level of the analog source signal 202 is within the voltage range V5, e.g., in a system with eight possible sources labeled 0 to 7, this may identify the source 110 as the source labeled 5.

[0030] In the case where the destination device 134 supports digital source identification (e.g., based on communication from the destination device 134 to the source 110 with discovery information of the destination device, not shown), the logic device 108 may communicate a digital source identifier frame 204 that includes a start bit 206 (e.g., driven high to indicate the start of the digital source identifier frame 204), a digital source signal 208, and a stop bit 210 (e.g., driven low to indicate the end of the digital source identifier frame 204). The digital source signal 208 may include a digital nibble, byte, word, or other datagram that is the digital equivalent of a label of the source 110 identified by the analog source signal 202 (e.g., in the Figure 2 example shown, 0101 = 5).

[0031] In addition, as Figure 2 shown, due to the series resistors 116 each having a different resistance, the logic device 108 may drive the stop bit 210 to an encoded analog voltage that can be sampled by the device 134 and may include analog encoded start / offset and / or width information regarding the communication channel associated with a particular branch of the cable 112 to which the device 134 is coupled. For example, in a particular embodiment, the possible analog voltages of the stop bit 210 may be encoded as follows:

[0032] ● V0: Channel 0, full width of source 110 (i.e., point-to-point, no branch)

[0033] ● V1: Channel 0, half width of source 110

[0034] ● V2: Channel 0, quarter width of source 110

[0035] ● V3: Channel 0, eighth width of source 110

[0036] ● V4: Channel 2, half width of source 110

[0037] ● V5: Channel 2, quarter width of source 110

[0038] ● V6: Channel 2, eighth width of source 110

[0039] Thus, in the Figure 2 particular embodiment shown, the analog voltage of V2 indicates that the branch to which a particular device 134 is coupled corresponds to channel 0 of a PCIe connection, which is a quarter width of the source 110 (e.g., if the source 110 is x16, then it is x4).

[0040] Accordingly, in addition to supporting a single source information line 114 that can convey both analog and digital information to multiple branch destinations of the cable 112, the systems and methods disclosed herein also support sharing the source information line 114 to convey both analog and digital source information. Additionally, the systems and methods disclosed herein support the ability for a destination device 134 to announce support for digital source information and then receive both analog and digital information on the same line, in order to enable backward compatibility with existing devices that do not support digital source information.

[0041] Figure 3 A block diagram of another example information processing system 102A in accordance with an embodiment of the present disclosure is shown. Figure 3 The information processing system 102A shown in is similar in many respects to Figure 1 the information processing system 102 shown in, and thus, only the main differences between the information processing system 102 and the information processing system 102A may be described below.

[0042] The main difference between the information processing system 102 and the information processing system 102A may lie in the use of a cable 112A instead of the cable 112, and the cable 112A may include a self-describing cable having a printed circuit board 302, such as that described in U.S. Patent Application Serial No. 17 / 124,774, filed December 17, 2020, which patent application is incorporated herein by reference in its entirety. In such an embodiment, the printed circuit board 302 may sample a static analog source signal 202 and drive a digital source identifier frame 204, including analog-encoded start / offset and / or width information of the digital source signal 208 and a stop bit 210 to the destination 130.

[0043] As used herein, when two or more elements are referred to as being "coupled" to each other, the term indicates that such two or more elements are in electronic communication or mechanical connection, as applicable, whether directly or indirectly connected, with or without intermediate elements.

[0044] This disclosure covers all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that would be envisioned by one of ordinary skill in the art. Similarly, where appropriate, the appended claims cover all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that would be envisioned by one of ordinary skill in the art. References in the appended claims to an apparatus or system, or a component of such apparatus or system, that is adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function cover such apparatus, system, or component, whether or not the apparatus, system, component, or the particular function is activated, turned on, or unlocked, so long as the apparatus, system, or component is adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform the particular function. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of this disclosure. For example, components of the systems and apparatuses may be integrated or separate. Additionally, operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components, and the methods described may include more, fewer, or other steps. Additionally, the steps may be performed in any suitable order. As used in this document, "each" refers to each member of a set or each member of a subset of a set.

[0045] Although example embodiments are shown in the drawings and described above, any number of techniques (whether currently known or not) may be used to implement the principles of this disclosure. This disclosure should in no way be limited to the example embodiments and techniques shown in the drawings and described above.

[0046] Unless otherwise specifically noted, the articles depicted in the drawings are not necessarily drawn to scale.

[0047] All of the examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the disclosure and concepts that the inventors have made for the advancement of the technology, and are to be construed as not being limited to such specifically recited examples and conditions. Although the embodiments of this disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations can be made to this disclosure without departing from the spirit and scope of this disclosure.

[0048] Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, after reviewing the above drawings and description, other technical advantages may become apparent to one of ordinary skill in the art.

Claims

1. An information processing system, the information processing system comprises: a plurality of communication destinations; a communication source; a single-source / multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a respective communication destination of this branch; and a logic device communicatively coupled to the communication source and the single-source / multi-destination cable and configured to drive a source information signal transmitted to each of the plurality of branches, wherein the source information signal comprises: an analog signal indicating a specific communication source during a first interval; and a digital signal indicating the specific communication source during a second interval.

2. The information processing system according to claim 1, wherein the digital signal comprises a digital source identifier frame identifying the communication source of at least one of the plurality of communication destinations.

3. The information processing system according to claim 1, wherein the analog signal comprises an analog voltage identifying the communication source of at least one of the plurality of communication destinations.

4. The information processing system according to claim 3, wherein the digital signal comprises a digital source identifier frame identifying the communication source of at least one of the plurality of communication destinations, wherein the digital source identifier frame comprises a digital datagram which is a digital equivalent of the analog voltage.

5. The information processing system according to claim 1, wherein the analog signal comprises at least one of start / offset information and width information regarding a branch of the single-source / multi-destination cable.

6. The information processing system according to claim 5, wherein the digital signal comprises a digital source identifier frame identifying the communication source of at least one of the plurality of communication destinations, wherein an analog voltage associated with bits of the digital source identifier frame encodes at least one of the start / offset information and the width information.

7. The information processing system according to claim 6, wherein: each branch of the single-source / multi-destination cable comprises a series resistance different from that of other branches; and the analog voltage encoding at least one of the start / offset information and the width information varies with one or more of the series resistances of the branch.

8. A method, the method comprising, in an information processing system having a plurality of communication destinations, a communication source, and a single-source / multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a respective communication destination of this branch: driving a source information signal transmitted to each of the plurality of branches, wherein the source information signal comprises: an analog signal indicating a specific communication source during a first interval; and a digital signal indicating the specific communication source during a second interval.

9. The method according to claim 8, wherein the digital signal comprises a digital source identifier frame identifying the communication source of at least one of the plurality of communication destinations.

10. The method according to claim 8, wherein the analog signal comprises an analog voltage identifying the communication source of at least one of the plurality of communication destinations.

11. The method according to claim 10, wherein the digital signal includes a digital source identifier frame identifying the communication source of at least one of the plurality of communication destinations, wherein the digital source identifier frame includes a digital datagram that is the digital equivalent of the analog voltage.

12. The method according to claim 8, wherein the analog signal includes at least one of start / offset information and width information regarding a branch of the single-source / multi-destination cable.

13. The method according to claim 12, wherein the digital signal includes a digital source identifier frame identifying the communication source of at least one of the plurality of communication destinations, wherein an analog voltage associated with bits of the digital source identifier frame encodes at least one of the start / offset information and the width information.

14. The method according to claim 13, wherein: each branch of the single-source / multi-destination cable includes a series resistance different from series resistances of other branches; and the analog voltage encoding at least one of the start / offset information and the width information varies with one or more of the series resistances of the branches.

15. An article of manufacture, the article of manufacture comprising: a non-transitory computer-readable medium; and computer-executable instructions carried on the computer-readable medium, the instructions being readable by a processing device and, when read and executed, causing the processing device in an information processing system having a plurality of communication destinations, a communication source, and a single-source / multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a corresponding communication destination of this branch: drive a source information signal transmitted to each of the plurality of branches, wherein the source information signal includes: an analog signal indicating a specific communication source during a first interval; and a digital signal indicating the specific communication source during a second interval.

16. The article of manufacture according to claim 15, wherein the digital signal includes a digital source identifier frame identifying the communication source of at least one of the plurality of communication destinations.

17. The article of manufacture according to claim 15, wherein the analog signal includes an analog voltage identifying the communication source of at least one of the plurality of communication destinations.

18. The article of manufacture according to claim 17, wherein the digital signal includes a digital source identifier frame identifying the communication source of at least one of the plurality of communication destinations, wherein the digital source identifier frame includes a digital datagram that is the digital equivalent of the analog voltage.

19. The article of manufacture according to claim 14, wherein the analog signal includes at least one of start / offset information and width information regarding a branch of the single-source / multi-destination cable.

20. The article as described in claim 19, wherein the digital signal includes a digital source identifier frame identifying the communication source of at least one of the plurality of communication destinations, and an analog voltage associated with the bits of the digital source identifier frame encodes at least one of the start / offset information and the width information.

21. The article as described in claim 20, wherein: each branch of the single-source / multi-destination cable includes a series resistance different from that of the other branches; and the analog voltage encoding at least one of the start / offset information and the width information varies with one or more of the series resistances of the branches.

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