A multi-channel analog isolation acquisition circuit and a chip

Abstract

The application discloses a kind of multi-channel analog isolation acquisition circuit and a kind of chip, the circuit includes multi-channel isolation power supply, multi-channel analog isolation conversion circuit and FPGA system;Multi-channel isolation power supply and multi-channel analog isolation conversion circuit are electrically connected one by one;Multi-channel analog isolation conversion circuit is connected with FPGA system;The analog isolation conversion circuit of any channel includes the signal conditioning circuit, voltage / digital conversion circuit and digital isolator ISO connected in turn;Multi-channel analog isolation conversion circuit realizes the conversion of the analog quantity to be sampled to digital quantity and digital quantity isolation and after isolation digital quantity is output to FPGA system, and FPGA system realizes digital signal filter and external SPI interface.The circuit has high integration, and the device occupies small area, and the output interface of digitization improves the versatility and flexibility of circuit, can realize the demand of tens of analog voltage signal isolation acquisition even hundreds of channels under smaller circuit area.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics, and relates to a multi-channel analog isolation acquisition circuit and a chip. BACKGROUND

[0002] In a spaceflight and aviation telemetry system, in order to monitor the working states of each electrical node, a large number of analog voltage signals such as voltage, current and temperature need to be measured, and in order to avoid loop common ground and reduce the mutual influence between each signal and system, the electrical nodes need to be measured in isolation.

[0003] As shown in the figure, the traditional analog signal isolation acquisition method is to realize the isolation of analog signals by taking linear optocoupler or digital optocoupler as the core device. Figure 1 Since the digital optocoupler and the linear optocoupler are both transmission devices based on optical medium, they inevitably have a series of problems such as low conversion accuracy, large size, low insulation voltage, high power consumption, etc. In order to realize multi-channel measurement, an analog switch needs to be added to select the acquisition channel, and an operational amplifier follower needs to be introduced to avoid the impedance mismatch problem caused by the analog switch. Finally, the measurement data converted by the analog-to-digital converter is input into the FPGA through the digital interface of the converter to form a complete isolation measurement system. Each acquisition channel must have an independent isolation power supply, and the entire acquisition circuit has a large number of devices, complex design steps, high cost and large printed board area, resulting in high price, low bandwidth, high power consumption, low precision and large printed board area.

[0004] With the development trend of miniaturization, lightweight and intelligentization of new generation spaceflight equipment, the number of channels that need to be measured in isolation in the telemetry system is increasing, even up to hundreds of channels, and new requirements for measurement accuracy are constantly being put forward, while the printed board area is constantly decreasing. The traditional measurement system is difficult to meet the growing measurement demand, and such a complex isolation acquisition circuit is difficult to meet the actual demand in terms of device cost, design difficulty and circuit board area, and it is urgent to develop a small, high-integration, multi-channel, built-in multi-channel isolation power supply analog voltage isolation acquisition circuit. SUMMARY

[0005] In view of the problems in the prior art, the present application provides a multi-channel analog isolation acquisition circuit and a chip, so as to realize the isolation acquisition of multi-channel analog voltage signals without distortion and high precision in a small circuit area.

[0006] The present application is realized by the following technical solutions:

[0007] A multi-channel analog isolation acquisition circuit, comprising a multi-channel isolation power supply, a multi-channel analog isolation conversion circuit and an FPGA system.

[0008] The current output end of the multi-channel isolated power supply is electrically connected with the current input end of the multi-channel analog isolated conversion circuit one by one; and the multi-channel analog isolated conversion circuit is connected with the FPGA system for data transmission.

[0009] The multi-channel isolated power supply comprises an input decoupling capacitor C1, an under-voltage protection circuit, a driving bootstrap circuit, a chopping circuit, a synchronous Buck controller U1, a planar transformer T1, a primary feedback loop and a multi-channel output end rectification filtering loop.

[0010] One end of the input decoupling capacitor C1 is connected with the positive end of an input power supply VIN, and the other end is grounded; the under-voltage protection circuit is connected with the positive end of the input power supply VIN and the synchronous Buck controller U1; the driving bootstrap circuit is connected with the positive end of the input power supply VIN and the synchronous Buck controller U1; the chopping circuit is connected with the synchronous Buck controller U1 and the planar transformer T1; the primary feedback loop is connected with the planar transformer T1 and the synchronous Buck controller U1; and the multi-channel output end rectification filtering loop is connected with the planar transformer T1 and the output V OUT .

[0011] The analog isolated conversion circuit of any channel in the multi-channel analog isolated conversion circuit comprises a signal conditioning circuit, a voltage / digital conversion circuit and a digital isolator ISO connected in sequence.

[0012] Preferably, the under-voltage protection circuit comprises resistors R1 and R2; the resistors R1 and R2 are connected in series as a voltage dividing circuit; the free end of the resistor R1 is connected with the positive end of the input power supply VIN, the free end of the resistor R2 is connected with the virtual ground end GND of the synchronous Buck controller U1, and the voltage dividing ends of the resistors R1 and R2 are connected with the enable end EN of the synchronous Buck controller U1.

[0013] Preferably, the driving bootstrap circuit comprises a Schottky diode D1 and a capacitor C4; the anode of the Schottky diode D1 is connected with the positive end of the input power supply VIN; the cathode of the Schottky diode D1 is connected with the bootstrap capacitor pin BST of the synchronous Buck controller; one end of the capacitor C4 is connected with the bootstrap capacitor pin BST of the synchronous Buck controller, and the other end is connected with the switching node SW of the synchronous Buck controller.

[0014] Preferably, the planar transformer T1 comprises a first printed board, a plurality of layers of second printed boards and a planar magnetic core; the first printed board is provided with a primary winding, and each of the plurality of layers of second printed boards is provided with a secondary winding; the first printed board and the plurality of layers of second printed boards are stacked, and the planar magnetic core is inserted on both sides of the stacked first printed board and the plurality of layers of second printed boards; the thickness of the stacked first printed board and the plurality of layers of second printed boards is consistent with the height of the planar magnetic core.

[0015] Preferably, the chopper circuit comprises an NMOS tube Q1 and an NMOS tube Q2; the gate of the NMOS tube Q1 is connected to the high-voltage opening end HO of the synchronous Buck controller U1, the drain of the NMOS tube Q1 is connected to the positive end of the input voltage VIN, and the source of the NMOS tube Q1 is connected to the drain of the NMOS tube Q2, the switching node SW of the synchronous Buck controller U1 and the primary winding; the gate of the NMOS tube Q2 is connected to the low-voltage opening end LO of the synchronous Buck controller, and the source of the NMOS tube Q2 is connected to the virtual ground end GND of the synchronous Buck controller U1.

[0016] Preferably, the primary side feedback loop comprises a capacitor C2, a capacitor C3, a resistor R3 and a resistor R4; the resistor R3 and the resistor R4 are connected in series as a voltage dividing circuit; the free end of the resistor R3 is connected to the primary winding, and the free end of the resistor R4 is connected to the virtual ground end GND of the synchronous Buck controller U1; the voltage dividing ends of the resistor R3 and the resistor R4 are connected to the feedback end FB of the synchronous Buck controller; the capacitor C3 is connected in parallel with the resistor R3, one end of the C3 is connected to the voltage dividing ends of the resistor R3 and the resistor R4, and the other end is grounded; one end of the capacitor C2 is connected to the primary winding, and the other end is connected to the virtual ground end GND of the synchronous Buck controller U1.

[0017] Preferably, any one of the multi-channel output end rectification and filtering loops comprises a Schottky diode D3, a magnetic bead MB1, a capacitor C6 and a capacitor C7; the cathode of the Schottky diode D3 is connected to one end of the capacitor C6, and the two ends of the secondary winding are respectively connected to the anode of the Schottky diode D3 and the other end of the capacitor C6; the magnetic bead MB1 is connected in series to the positive end of the output V OUT , and the capacitor C7 is connected in parallel to the output V OUT .

[0018] Preferably, the signal conditioning circuit comprises an operational amplifier Op1 and an operational amplifier Op2; the inverting input terminal of the operational amplifier Op1 is connected with the output terminal of the operational amplifier Op1, and the non-inverting input terminal of the operational amplifier Op1 is connected with an input signal; the inverting input terminal of the operational amplifier Op2 and the output terminal of the operational amplifier Op2 are both connected with a virtual ground, and the non-inverting input terminal of the operational amplifier Op2 is connected with a voltage dividing terminal of a voltage reference VREF voltage dividing circuit.

[0019] Preferably, the voltage / digital conversion circuit comprises a summing node SUM1, a summing node SUM2, an integrator I1, an integrator I2, a hysteresis comparator CMP, a voltage reference VREF and a flip-flop FILP; the positive input terminal of the summing node SUM1 is connected with the output terminal of the follower Op1, and the negative input terminal of the summing node SUM1 is connected with the result output terminal of the flip-flop FILP; the output terminal of the summing node SUM1 is connected with the input terminal of the integrator I1; the positive input terminal of the summing node SUM2 is connected with the output terminal of the integrator I1, the negative input terminal of the summing node SUM2 is connected with the result output terminal of the flip-flop FILP, and the output terminal of the summing node SUM2 is connected with the input terminal of the integrator I2; the input terminal of the hysteresis comparator CMP is connected with the output terminal of the integrator I2, and the output terminal of the hysteresis comparator CMP is connected with the input D terminal of the flip-flop FILP; the power supply terminal VCC of the flip-flop FILP is connected with the voltage reference VREF;

[0020] One channel of the digital isolator ISO is connected with a clock signal CLK and inputs the CLK terminal of the flip-flop FILP, and the other channel is connected with a data signal DATA of the flip-flop FILP.

[0021] A multi-channel analog isolation acquisition chip comprises a first layer circuit board, a second layer circuit board, a third layer circuit board and a bottom plate which are fixedly and sequentially stacked;

[0022] The first layer circuit board and the second layer circuit board both comprise the above-described analog isolation conversion circuit;

[0023] The third layer circuit board comprises the above-described multi-channel isolation power supply and FPGA system;

[0024] The spacing between the first layer circuit board, the second layer circuit board, the third layer circuit board and the bottom plate is 0.3-0.5 mm.

[0025] Compared with the prior art, the present application has the following beneficial technical effects:

[0026] The application discloses a multi-channel analog isolation acquisition circuit, which comprises a multi-channel isolation power supply, a multi-channel analog isolation conversion circuit and an FPGA system. IN The input decoupling capacitor C1 in the multi-channel isolation power supply can filter the input voltage V IN The application discloses a multi-channel analog isolation acquisition circuit, which comprises a multi-channel isolation power supply, a multi-channel analog isolation conversion circuit and an FPGA system.

[0027] Further, the under-voltage protection circuit comprises resistors R1 and R2, the voltage dividing ends of the resistors R1 and R2 are connected with the enable end EN of the synchronous Buck controller U1, if the input voltage is too low to reach the enable end opening level, the synchronous Buck controller stops working, and the power supply system can be effectively prevented from working when the input voltage is too low.

[0028] Further, the drive bootstrap circuit is used for providing a floating ground power supply, the Schottky diode D1 charges the capacitor C4 when the Schottky diode D1 is turned on, the voltage at the bootstrap capacitor pin BST of the synchronous Buck controller is higher than the voltage at the SW pin, and the NMOS tube Q1 is turned on.

[0029] Further, the planar transformer adopts multi-layer printed board winding as the transformer winding, and if the number of windings needs to be increased, the number of printed board layers can be increased only.

[0030] Further, the chopper circuit includes NMOS tube Q1 and NMOS tube Q2, and the synchronous Buck controller U1 opens the high-voltage side power NMOS tube Q1 at a fixed frequency, and when the peak current of the high-voltage side NMOS tube Q1 is sensed to rise higher than the internal voltage, the device closes the high-voltage side NMOS tube Q1 and opens the low-voltage side NMOS tube Q2. When the NMOS tube Q2 is turned on, the inductance current decreases. In the next cycle, the low-voltage side NMOS tube Q2 is closed and the high-voltage side NMOS tube Q1 is opened at the rising edge, so as to realize the charging and discharging of the primary winding of the planar transformer.

[0031] Further, the primary side feedback loop includes capacitor C2, capacitor C3, resistor R3 and resistor R4, the resistor R3 and the resistor R4 are used as voltage dividing resistors to feedback the output voltage, the capacitor C3 is used to introduce a pole in the transfer function of the feedback loop, and the capacitor C2 is used as an output capacitor for filtering.

[0032] Further, any loop in the multi-channel output rectification and filtering loop includes Schottky diode D3, magnetic bead MB1, capacitor C6 and capacitor C7, the Schottky diode D3 and the capacitor C6 rectify the output voltage to direct current, and the magnetic bead MB1 and the capacitor C7 are used for filtering the output power supply.

[0033] Further, the signal conditioning circuit includes operational amplifier Op1 and operational amplifier Op2, the inverting terminals of the operational amplifier Op1 and the operational amplifier Op2 are connected to the output to form a follower, the operational amplifier Op1 follows the input signal, and the operational amplifier Op2 follows half of the voltage reference VREF to provide a virtual ground VG.

[0034] A multi-channel analog isolation acquisition chip adopts a printed board space stacking design idea, which can greatly improve the system integration and flexibility, reduce the design complexity of the whole system, reduce the design risk, reduce the development cost, and meet the development trend of miniaturization, lightweight and intelligentization of new generation of aerospace equipment. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0036] Figure 1 Block diagram of the prior art isolated voltage acquisition system;

[0037] Figure 2 Block diagram of the multi-channel analog isolated acquisition circuit in the present application;

[0038] Figure 3 Circuit connection schematic of the isolated power supply in the present application;

[0039] Figure 4 Connection schematic of the analog isolated conversion circuit in the present application;

[0040] Figure 5 Composition schematic of the planar transformer T1 in the present application;

[0041] Figure 6 Block diagram of the FPGA system in the present application;

[0042] Figure 7 Double-DOUT line serial output timing sequence of the interface SPI in the present application;

[0043] Figure 8 Single-board function distribution and circuit integration schematic of the multi-channel analog isolated acquisition chip in the present application;

[0044] Figure 9 Stacked structure schematic of the multi-channel analog isolated acquisition chip in the present application.

[0045] Wherein, 1, first printed board, 11, primary winding, 2, second printed board, 21, secondary winding, 3, planar magnetic core, 4, printed board bottom layer, 41, winding fan-out return line, 1-1, first layer circuit board, 1-2, second layer circuit board, 1-3, third layer circuit board, 1-4, bottom plate, 1-5, positioning pin, 1-6, DB plate. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application claimed, but merely represents selected embodiments of the application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the application, without making creative efforts, fall within the scope of the application claimed.

[0048] It should be noted that similar reference numbers and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0049] In the description of the embodiments of the application, it should be noted that if the terms "upper", "lower", "horizontal", "inner", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed, and are merely for the convenience of describing the application and simplifying the description, and therefore, cannot be understood as indicating or implying that the device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore, cannot be understood as limiting the application. In addition, the terms "first", "second", and the like are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0050] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly inclined. For example, "horizontal" only means that its direction is relatively more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0051] In the description of the embodiments of the application, it should also be noted that unless otherwise explicitly specified and limited, if the terms "arrangement", "installation", "connection", "connection" appear, they should be understood in a broad sense, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, can be electrically connected; can be directly connected, can be indirectly connected through an intermediate medium, or can be connected between two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0052] The application will be further described in detail below with reference to the accompanying drawings:

[0053] The project is based on solving the problem of isolated measurement of multiple groups of non-common-mode analog voltage signals, and provides a multi-channel analog isolated acquisition circuit. The circuit is built-in multi-channel capacitive isolated analog acquisition circuit, multi-channel micro-power isolated power supply and FPGA system. PoP technology adopts the design idea of printed board space stacking, which greatly improves the system integration and flexibility, while also reduces the design complexity of the whole system, reduces the design risk, reduces the development cost, and meets the needs of the new generation of aerospace equipment. In the traditional analog signal isolated acquisition system, according to the different measurement input needs of users, it is necessary to design and customize, which increases the design difficulty and improves the risk. Using PoP technology, the module integrates capacitive isolated analog acquisition circuit, eight-way micro-power isolated power supply and FPGA system. Users only need a single power input, and can receive eight-way serial isolated acquisition data through the module standard SPI interface. This greatly reduces the design risk, improves the accuracy of measurement, the flexibility of design, and the testability of the system. The circuit is designed based on PoP technology, with high integration, and the device occupies a small area. At the same time, it gets rid of the risk brought by traditional complex design, and the digital output interface improves the versatility and flexibility of the circuit, which can realize the demand of tens of analog voltage signal isolation acquisition even hundreds of analog voltage signal isolation acquisition in a small circuit area.

[0054] As shown in Figure 2 A multi-channel analog isolated acquisition circuit, including a multi-channel isolated power supply, i.e. a multi-channel micro-power isolated power supply, a multi-channel analog isolated conversion circuit and an FPGA system; wherein the current output end of the multi-channel isolated power supply is electrically connected one by one with the current input end of the multi-channel analog isolated conversion circuit; the multi-channel analog isolated conversion circuit is connected with the FPGA system for data transmission, and the transmitted data includes a clock signal CLK and a data signal DATA.

[0055] First, for the isolated power supply: the traditional isolated power supply is based on fly-back topology design and relies on the feedback of the secondary side photoelectric coupler, but the photoelectric coupler is large in volume and low in thermal stability. The height of the vertical winding transformer used with it becomes the main reason restricting the integration of the circuit. The winding transformer is usually hand-wound and high in cost, and cannot be consistent between batches. The magnetic circuit is not closed, the leakage inductance is large and electromagnetic interference is easy to produce. It is not conducive to miniaturization and lightweight design. The original side feedback isolation buck-boost topology uses the original side capacitor voltage feedback, keeps the original side output capacitor voltage stable, and uses it as the excitation voltage of the transformer primary winding, abandoning the complex design scheme of output voltage feedback. Under the condition of stable input voltage and continuous current, the output voltage of the secondary side is only related to the turns ratio of the transformer and the load. This topology greatly reduces the complexity of the design.

[0056] As shown in Figure 3As shown, the multi-channel isolated power supply includes an input decoupling capacitor C1, an under-voltage protection circuit, a drive bootstrap circuit, a chopping circuit, a synchronous Buck controller U1, a planar transformer T1, a primary feedback loop, and a multi-channel output end rectification filtering loop; one end of the input decoupling capacitor C1 is connected to the positive end of the input power supply VIN, and the other end is grounded; the synchronous Buck controller U1 is used to realize functions such as loop compensation, gate synchronous driving, overcurrent protection, and over-temperature protection; the under-voltage protection circuit is connected to the positive end of the input power supply VIN and the synchronous Buck controller U1, preventing the power supply system from working when the input voltage is too low; the drive bootstrap circuit is connected to the positive end of the input power supply VIN and the synchronous Buck controller U1, providing a floating ground power supply to enable the NMOS tube Q1 to conduct as needed; the chopping circuit is connected to the synchronous Buck controller U1 and the planar transformer T1, and is used to convert the input DC power supply into an AC pulse power supply; the primary feedback loop is connected to the planar transformer T1 and the synchronous Buck controller U1; and the multi-channel output end rectification filtering loop is connected to the planar transformer T1 and the output V OUT . Among them, the input decoupling capacitor C1, the under-voltage protection circuit, the drive bootstrap circuit, the chopping circuit, the synchronous Buck controller U1, and the primary feedback loop are all primary sides, the planar transformer T1 includes one primary winding and a plurality of secondary windings, and the rectification filtering loop of the output end is also a plurality of rectification filtering loops, which are connected to the plurality of secondary windings one by one. More specifically:

[0057] (1) The input decoupling capacitor C1 is used to filter the input voltage V IN , reducing the noise influence of the input voltage;

[0058] (2) The under-voltage protection circuit is used to prevent the power supply system from working when the input voltage is too low, and specifically includes resistors R1 and R2; the resistors R1 and R2 are connected in series as a voltage dividing circuit; the free end of the resistor R1 is connected to the positive end of the input power supply VIN, the free end of the resistor R2 is connected to the virtual ground end GND of the synchronous Buck controller U1, and the voltage dividing ends of the resistors R1 and R2 are connected to the enable end EN of the synchronous Buck controller U1.

[0059] (3) The drive bootstrap circuit is used to provide a floating ground power supply to enable the NMOS tube Q1 to conduct as needed, and specifically includes a Schottky diode D1 and a capacitor C4; the anode of the Schottky diode D1 is connected to the positive end of the input power supply VIN; the cathode of the Schottky diode D1 is connected to the bootstrap capacitor pin BST of the synchronous Buck controller; one end of the capacitor C4 is connected to the bootstrap capacitor pin BST of the synchronous Buck controller, and the other end is connected to the switching node SW of the synchronous Buck controller.

[0060] (4) As Figure 5As shown, the planar transformer T1 includes a first printed board 1, a plurality of layers of second printed boards 2, and a planar magnetic core 3; the first printed board 1 is provided with a primary winding 11, and each of the plurality of layers of second printed boards 2 is provided with a secondary winding 21; the first printed board 1 and the plurality of layers of second printed boards 2 are stacked, and the planar magnetic core 3 is inserted on both sides of the stacked first printed board 1 and the plurality of layers of second printed boards 2, one side of the planar magnetic core can be a 1 / 2E type planar magnetic core, and the other side is a 1 / 2I type planar magnetic core, and the thickness of the stacked printed board is consistent with the height of the planar magnetic core. The planar transformer T1 further includes a printed board bottom layer 4, and the printed board bottom layer 4 is provided with a winding fan-out return line 41. More preferably, the number of second printed boards 2 is preferably eight layers, forming an eight-channel isolated power supply. The planar transformer T1 adopts multi-layer printed board winding as the transformer winding, and the number of windings can be increased by increasing the number of printed boards. The planar transformer adopts a flat magnetic core, which is directly inserted on both sides of the printed board, and the thickness of the printed board is consistent with the height of the magnetic core, that is, the thickness of the stacked printed board is consistent with the height of the planar magnetic core, effectively reducing the height of the power supply, and facilitating integrated design. The printed board is tightly coupled with small leakage inductance, which eliminates the complex process of manual winding of vertical winding transformer, facilitates batch production, and the planar transformer T1 is used to realize the energy conversion circuit in the power conversion circuit.

[0061] (5) The chopper circuit is used to change the input DC power supply into an AC pulse power supply, and specifically includes an NMOS tube Q1 and an NMOS tube Q2; the gate of the NMOS tube Q1 is connected with the high-voltage opening end HO of the synchronous Buck controller U1, the drain of the NMOS tube Q1 is connected with the positive end of the input voltage VIN, and the source of the NMOS tube Q1 is connected with the drain of the NMOS tube Q2, the switching node SW of the synchronous Buck controller U1, and the primary winding 11; the gate of the NMOS tube Q2 is connected with the low-voltage opening end LO of the synchronous Buck controller, and the source of the NMOS tube Q2 is connected with the virtual ground end GND of the synchronous Buck controller U1.

[0062] (6) The primary feedback loop is used to maintain the effective excitation voltage of the planar transformer T1 unchanged during the chopping process, and specifically includes a capacitor C2, a capacitor C3, a resistor R3, and a resistor R4; the resistor R3 and the resistor R4 are connected in series as a voltage dividing circuit; the free end of the resistor R3 is connected with the primary winding 11, and the free end of the resistor R4 is connected with the virtual ground end GND of the synchronous Buck controller U1; the voltage dividing ends of the resistor R3 and the resistor R4 are connected with the feedback end FB of the synchronous Buck controller; the capacitor C3 is connected in parallel with the resistor R3, one end of the C3 is connected with the voltage dividing end, and the other end is grounded; one end of the capacitor C2 is connected with the primary winding 11, and the other end is connected with the virtual ground end GND of the synchronous Buck controller U1.

[0063] (7) Multi-channel output end rectification filter circuit for maintaining output stability, any of which includes a Schottky diode D3, a magnetic bead MB1, a capacitor C6 and a capacitor C7; the cathode of the Schottky diode D3 is connected to one end of the capacitor C6, and the two ends of the secondary winding 21 are respectively connected to the anode of the Schottky diode D3 and the other end of the capacitor C6; the magnetic bead MB1 is connected in series to the positive end of the output V OUT , and the capacitor C7 is connected in parallel to the output V OUT .

[0064] Secondly, in the isolated acquisition circuit, the traditional optical coupling measurement method is difficult to realize accurate measurement of analog signals due to problems such as linearity and temperature drift. Digital signals only exist in high and low levels, that is, "0" or "1" signals have strong anti-interference in the transmission process. In order to ensure the accuracy of isolated acquisition, the digital signal must be transmitted on the isolation channel. Before isolation, use high-frequency digital signal as carrier wave to modulate low-frequency analog signal. The modulated digital signal contains both high-frequency digital carrier signal and low-frequency analog signal. Through the digital isolator, lossless isolation transmission can be realized. Finally, the signal enters the FPGA, and through the low-pass filter built to filter out the high-frequency digital carrier signal, the original analog signal can be recovered. In this way, the conversion of analog and digital signals is realized before isolation, and the digital signal is transmitted in the form of digital signal in the isolation channel, without signal distortion and attenuation phenomenon, which simplifies the system design difficulty, improves the system acquisition accuracy, and improves the system flexibility and reliability.

[0065] As shown in Figure 2 , in the multi-channel capacitive analog isolation conversion circuit, the analog isolation conversion circuit of a single channel includes a signal conditioning circuit, a voltage / digital conversion circuit and a digital isolator ISO connected in sequence, that is, a signal conditioning circuit composed of two operational amplifiers, two summing nodes SUM1 and SUM2, two integrators I1 and I2 composed of operational amplifiers, a hysteresis comparator CMP, a voltage reference VREF, a D flip-flop FILP and a digital isolator ISO.

[0066] As shown in Figure 4As shown, the signal conditioning circuit comprises an operational amplifier Op1 and an operational amplifier Op2; both of the operational amplifiers are designed in a follow input mode, and the follow mode has the characteristics of high input impedance and low output impedance; the operational amplifier Op1 realizes buffering of the analog input signal; the operational amplifier Op2 outputs a virtual ground signal VG, and can output or absorb current to a certain extent, thereby maintaining the virtual ground signal VG at a constant level. The inverting input end of the operational amplifier Op1 is connected with the output end of the operational amplifier Op1, and the non-inverting input end of the operational amplifier Op1 is connected with the input signal. The inverting input end of the operational amplifier Op2 and the output end of the operational amplifier Op2 are both connected with a virtual ground, and the non-inverting input end of the operational amplifier Op2 is connected with a voltage dividing end of a voltage reference VREF voltage dividing circuit.

[0067] The voltage / digital conversion circuit comprises a summing node SUM1, a summing node SUM2, an integrator I1, an integrator I2, a hysteresis comparator CMP, a voltage reference VREF and a flip-flop FILP; the positive input end of the summing node SUM1 is connected with the output end of the follower Op1, and the negative input end of the summing node SUM1 is connected with the result output end of the flip-flop FILP; the output end of the summing node SUM1 is connected with the input end of the integrator I1; the positive input end of the summing node SUM2 is connected with the output end of the integrator I1, the negative input end of the summing node SUM2 is connected with the result output end of the flip-flop FILP, and the output end of the summing node SUM2 is connected with the input end of the integrator I2; the input end of the hysteresis comparator CMP is connected with the output end of the integrator I2, and the output end of the hysteresis comparator CMP is connected with the input D end of the flip-flop FILP; the power supply end VCC of the flip-flop FILP is connected with the voltage reference VREF;

[0068] The summing node SUM1 subtracts the unipolar positive voltage VOUT and the output signal Q of the flip-flop FILP, i.e. subtracts the output signal of the operational amplifier Op1 and the output signal of the flip-flop FILP, and the obtained result is continuously time-integrated by the integrator I1;

[0069] The summing node SUM2 subtracts the output of the integrator I1 and the output signal Q of the flip-flop FILP, and the obtained result is continuously time-integrated by the integrator I2;

[0070] The hysteresis comparator CMP is used for comparing the output signal of the integrator I2 and the output virtual ground signal VG of Op2; when the output signal of the integrator I2 is higher than the virtual ground signal VG, a digital quantity "1" is output; when the output signal of the integrator I2 is lower than the virtual ground signal VG, a digital quantity "0" is output. Moreover, the comparator has a certain hysteresis range inside, so as to reduce the influence of circuit noise;

[0071] The D flip-flop FILP latches the output signal of the hysteresis comparator CMP under the influence of the input clock CLK, and outputs a digital signal "1" or "0" corresponding to an analog voltage "+VREF" or "0" in a clock cycle of CLK, and inputs the summing nodes SUM1 and SUM2 as a system feedback signal;

[0072] The digital isolator ISO is a double-channel capacitive digital isolator, wherein one channel isolates the clock signal CLK and inputs the CLK end of the flip-flop FILP, and the other channel isolates the data signal DATA of the flip-flop FILP.

[0073] Third, the output of the capacitive isolated analog quantity acquisition circuit is a high-speed low-bit data stream. In order to obtain a high-precision output signal, a digital filter must be connected behind to filter out the noise shaping high-frequency carrier signal and the input signal outside the bandwidth, while the signal rate can be reduced to the Nyquist frequency. The use of a digital filter can easily realize a high-order filter, and the sampled signal after the filter can be directly analyzed and processed in the digital system. The use of a general digital interface such as the SPI interface as the output interface of the entire circuit improves the reliability, universality and flexibility of the system. The use of small packaging and small resource FPGA can easily realize the design of digital filter and SPI interface. The FPGA system block diagram is as follows Figure 6The FPGA system includes an FPGA unit, an SPI FLASH unit, a crystal unit, and a digital power supply unit, which provide required digital 1.2V and 3.3V for the system. The SPI FLASH unit is connected with the FPGA unit; the crystal unit is connected with the FPGA unit; the digital power supply unit is connected with the FPGA unit, the SPI FLASH unit, and the crystal unit; the FPGA unit is sequentially connected with a digital filter, a memory FIFO, and an interface SPI; the digital filter includes a first-stage decimation, a second-stage decimation, and a third-stage decimation. The first stage is a CIC cascaded integrator-comb filter, which realizes 32 times decimation; the second stage is a HBF half-band filter, which realizes 2 times decimation; and the third stage is a FIR filter, which realizes a 2 times decimation filter. The three-stage structure can significantly reduce the operation amount and storage amount of the entire filter, simplify the filter design, and reduce the finite word length effect. The reduction of the sampling frequency is mainly completed by the first-stage CIC filter. Compared with other filter structures, the CIC filter only needs adders and subtractors, and greatly reduces the operation time and resources. The second-stage HBF filter is used to attenuate the signal components and quantization noise components mixed in the baseband after the first-stage CIC filter. The HBF filter is a special linear phase filter, nearly half of the coefficients of which are zero, and the operation amount is reduced by nearly half compared with other FIR filters of the same length. After the first two stages of filters, the signal frequency is reduced by 64 times. To reduce to the Nyquist frequency, the signal needs to be 2 times decimated. The FIR filter is used as the third stage, which can obtain smaller passband ripple and larger stopband attenuation.

[0074] After the digital decimation filter, the output signal is restored to the Nyquist frequency, and the data after 8 channels of decimation is buffered in the FIFO. When the external host device accesses the circuit, the buffered data can be sent through the SPI interface. The timing diagram of the double-DOUT serial interface is as shown in FIG. 6. Figure 7 At this time, the external FPGA is in the Slave mode. After the CS signal is pulled low, DOUTA serially outputs the sampling values of CH1-CH4 in the next 64 clock cycles, and DOUTB serially outputs the sampling values of CH5-CH8 in the 64 clock cycles.

[0075] The multi-channel analog isolation acquisition circuit designed by the application can modulate analog signal input into digital signal of '0' and '1', and realize distortionless and high-precision analog signal isolation conversion through a capacitive digital isolator; meanwhile, the primary side feedback isolation type buck-boost power supply topology and the micro-power isolation power supply of the planar transformer are integrated, only single power input is needed to realize multi-channel isolation output, the design is simple, and the application is very suitable for an isolated signal measurement system; the FPGA system is built-in, and the digital extraction and filtering of the modulated signal are completed in the circuit, and the user can also configure the oversampling rate through the OS[0:2] pin to meet various user needs. The signal extracted and filtered is sent through the double-DOUT line SPI interface in series, and the universality is high, and the use is convenient. The PoP technology is used for integration, the integration degree of the printed board system is improved to the maximum, and problems such as low testability, poor repairability and high process cost caused by the use of bare chips are avoided. The aerospace product based on the PoP technology has been verified by a large amount of verification, and the process is mature and reliable. The application has the characteristics of miniaturization, high integration and high flexibility, and can be widely applied to the fields of aerospace, industrial control and the like.

[0076] The application further discloses a multi-channel analog isolation acquisition chip, as shown in the drawings, comprising a first layer circuit board 1-1, a second layer circuit board 1-2, a third layer circuit board 1-3 and a bottom plate 1-4 which are fixedly arranged in sequence; the first layer circuit board 1-1 and the second layer circuit board 1-2 each comprise the analog isolation conversion circuit in the application, if limited by size, a plurality of circuit boards can be arranged, and a plurality of channel analog isolation conversion circuits are arranged. Figure 8 As shown in the drawings, the first layer circuit board 1-1, the second layer circuit board 1-2, the third layer circuit board 1-3 and the bottom plate 1-4 are arranged in a stacked manner, high-precision positioning holes and a positioning pin 1-5 are used to realize accurate positioning, and a customized DB plate 1-6 with different thicknesses is used to control the height between the plates within a safe interval of 0.3-0.5 mm. The entire circuit uses a DIP32 mode to lead out pins. Figure 9 As shown in the drawings, the first layer circuit board 1-1, the second layer circuit board 1-2, the third layer circuit board 1-3 and the bottom plate 1-4 are arranged in a stacked manner, high-precision positioning holes and a positioning pin 1-5 are used to realize accurate positioning, and a customized DB plate 1-6 with different thicknesses is used to control the height between the plates within a safe interval of 0.3-0.5 mm. The entire circuit uses a DIP32 mode to lead out pins.

[0077] The above is only a preferred embodiment of the application and is not used to limit the application, and the application can have various changes and variations for those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A multi-channel analog isolation acquisition circuit, characterized in that: Including multi-channel isolated power supply, multi-channel analog isolation conversion circuit and FPGA system; The current output terminals of the multi-channel isolated power supply are electrically connected to the current input terminals of the multi-channel analog isolation conversion circuit in a one-to-one correspondence; The multi-channel analog isolation conversion circuit is connected to the FPGA system for data transmission; The multi-channel isolated power supply includes an input decoupling capacitor C1, an undervoltage protection circuit, a drive bootstrap circuit, a chopper circuit, a synchronous Buck controller U1, a planar transformer T1, a primary feedback loop, and a multi-channel output end rectification and filtering loop; One end of the input decoupling capacitor C1 is connected to the positive end of the input power supply VIN, and the other end is grounded; the undervoltage protection circuit is connected to the positive end of the input power supply VIN and the synchronous Buck controller U1; the drive bootstrap circuit is connected to the positive end of the input power supply VIN and the synchronous Buck controller U1; the chopper circuit is connected to the synchronous Buck controller U1 and the planar transformer T1; the primary feedback loop is connected to the planar transformer T1 and the synchronous Buck controller U1; the multi-channel output rectifier filter loop is connected to the planar transformer T1 and the output V OUT Connection settings; The analog isolation conversion circuit of any channel in the multi-channel analog isolation conversion circuit includes a signal conditioning circuit, a voltage / digital conversion circuit and a digital isolator ISO which are connected in sequence; The primary feedback loop includes a capacitor C2, a capacitor C3, a resistor R3, and a resistor R4; the resistor R3 and the resistor R4 are connected in series to form a voltage divider circuit; the free end of the resistor R3 is connected to the primary winding 11, and the free end of the resistor R4 is connected to the virtual ground terminal GND of the synchronous Buck controller U1; the voltage divider end of the resistor R3 and the resistor R4 is connected to the feedback terminal FB of the synchronous Buck controller; the capacitor C3 is arranged in parallel with the resistor R3, one end of the C3 is connected to the voltage divider end of the resistor R3 and the resistor R4, and the other end is grounded; one end of the capacitor C2 is connected to the primary winding 11, and the other end is connected to the virtual ground terminal GND of the synchronous Buck controller U1; The signal conditioning circuit includes an operational amplifier Op1 and an operational amplifier Op2; the inverting input terminal of the operational amplifier Op1 is connected to the output terminal of the operational amplifier Op1, and the non-inverting input terminal of the operational amplifier Op1 is connected to the input signal; the inverting input terminal of the operational amplifier Op2 and the output terminal of the operational amplifier Op2 are both connected to a virtual ground, and the non-inverting input terminal of the operational amplifier Op2 is connected to the voltage divider terminal of the voltage reference VREF voltage divider circuit; The voltage / digital conversion circuit includes a summing node SUM1, a summing node SUM2, an integrator I1, an integrator I2, a hysteresis comparator CMP, a voltage reference VREF, and a flip-flop FILP; the positive input of the summing node SUM1 is connected to the output of the operational amplifier Op1, and the negative input of the summing node SUM1 is connected to the result output of the flip-flop FILP; the output of the summing node SUM1 is connected to the input of the integrator I1; the positive input of the summing node SUM2 is connected to the output of the integrator I1, the negative input of the summing node SUM2 is connected to the result output of the flip-flop FILP, and the output of the summing node SUM2 is connected to the input of the integrator I2; the input of the hysteresis comparator CMP is connected to the output of the integrator I2, and the output of the hysteresis comparator CMP is connected to the input D of the flip-flop FILP; the power supply VCC of the flip-flop FILP is connected to the voltage reference VREF; One channel of the digital isolator ISO isolates the clock signal CLK and connects it to the CLK terminal of the flip-flop FILP, and the other channel isolates the data signal DATA of the flip-flop FILP.

2. A multi-channel analog isolation acquisition circuit according to claim 1, characterized in that: The undervoltage protection circuit includes a resistor R1 and a resistor R2; the resistor R1 and the resistor R2 are connected in series to form a voltage divider circuit; the free end of the resistor R1 is connected to the positive end of the input power supply VIN, the free end of the resistor R2 is connected to the virtual ground terminal GND of the synchronous Buck controller U1, and the voltage divider end of the resistor R1 and the resistor R2 is connected to the enable terminal EN of the synchronous Buck controller U1.

3. The multi-channel analog isolation acquisition circuit according to claim 1, characterized in that: The driving bootstrap circuit includes a Schottky diode D1 and a capacitor C4; the anode of the Schottky diode D1 is connected to the positive terminal of the input power supply VIN; the cathode of the Schottky diode D1 is connected to the bootstrap capacitor pin BST of the synchronous Buck controller; one end of the capacitor C4 is connected to the bootstrap capacitor pin BST of the synchronous Buck controller, and the other end is connected to the switch node SW of the synchronous Buck controller.

4. The multi-channel analog isolation acquisition circuit according to claim 1, characterized in that: The planar transformer T1 includes a first printed circuit board 1, several layers of second printed circuit boards 2, and a planar magnetic core 3; the first printed circuit board 1 is provided with a primary winding 11, and several layers of the second printed circuit boards 2 are provided with secondary windings 21; the first printed circuit board 1 and several layers of the second printed circuit boards 2 are stacked, and the planar magnetic core 3 is inserted on both sides of the stacked first printed circuit board 1 and several layers of the second printed circuit boards 2; After stacking, the thickness of the first printed circuit board 1 and the plurality of layers of second printed circuit boards 2 is consistent with the height of the planar magnetic core 3 .

5. The multi-channel analog isolation acquisition circuit according to claim 1, characterized in that: The chopper circuit includes an NMOS transistor Q1 and an NMOS transistor Q2; the gate of the NMOS transistor Q1 is connected to the high-voltage start-up terminal HO of the synchronous Buck controller U1, the drain of the NMOS transistor Q1 is connected to the positive terminal of the input voltage VIN, and the source of the NMOS transistor Q1 is connected to the drain of the NMOS transistor Q2, the switch node SW of the synchronous Buck controller U1, and the primary winding 11; the gate of the NMOS transistor Q2 is connected to the low-voltage start-up terminal LO of the synchronous Buck controller, and the source of the NMOS transistor Q2 is connected to the virtual ground terminal GND of the synchronous Buck controller U1.

6. The multi-channel analog isolation acquisition circuit according to claim 1, characterized in that: Each of the multi-channel output end rectifier filter circuits includes a Schottky diode D3, a magnetic bead MB1, a capacitor C6, and a capacitor C7; the cathode of the Schottky diode D3 is connected to one end of the capacitor C6, and the two ends of the secondary winding 21 are respectively connected to the anode of the Schottky diode D3 and the other end of the capacitor C6; the magnetic bead MB1 is connected in series to the output V OUT The positive terminal of the capacitor C7 and the output V OUT Parallel setting.

7. A multi-channel analog isolation acquisition chip, characterized in that: It includes a first layer circuit board 1-1, a second layer circuit board 1-2, a third layer circuit board 1-3 and a bottom plate 1-4 which are stacked and fixed in sequence; The first circuit board 1-1 and the second circuit board 1-2 both include the analog isolation conversion circuit described in claim 1; The third layer circuit board 1-3 includes the multi-channel isolated power supply and FPGA system described in claim 1; The spacing between the first layer circuit board 1-1, the second layer circuit board 1-2, the third layer circuit board 1-3 and the bottom plate 1-4 is 0.3-0.5 mm.

Images