p-NiO or p-LiNiO / n-GaN Heterojunction Resonant Tunneling Diode and Preparation Method

Abstract

The present invention discloses a p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode, and its structure includes: a substrate layer; a GaN layer grown on the substrate layer; an n-GaN layer grown on the GaN layer; an n+GaN layer grown on the n-GaN layer; an n++GaN layer grown on the n+GaN layer; a p++NiO layer or a p++LiNiO layer grown on the n++GaN layer; a p+NiO layer grown on the p++NiO layer; or a p+LiNiO layer grown on the p++LiNiO layer; a P-type electrode disposed on the p+LiNiO layer; an N-type electrode disposed on the GaN layer. In the device structure of the present invention, the heavy doping of n++GaN and P++NiO causes the energy band at the pn heterojunction interface to bend, making the valence band of p-NiO higher than the conduction band of n-GaN under zero bias, so as to realize the resonant tunneling of carriers by adjusting the bias voltage.

Description

Technical Field

[0001] The present invention relates to a p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode and a preparation method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] Resonant tunneling diodes have great application potential in the terahertz field, logic circuits and memory circuits. III-V semiconductor materials represented by GaN are preferred materials for preparing high-frequency high-power resonant tunneling diodes due to their advantages such as large bandgap, high carrier mobility and good thermal conductivity. GaN-based p-n junction resonant tunneling diodes are mainly composed of heavily doped p++GaN / n++GaN junctions. When the depletion region width is narrow enough, electrons can tunnel between the conduction band of n-GaN and the valence band of p-GaN at a certain bias voltage at the p-n junction interface. However, since GaN is a wide-bandgap semiconductor material, when using a GaN homojunction p-n junction to prepare a resonant tunneling diode, a large energy band bending needs to be generated at the interface through heavy doping to make the valence band of p-GaN and the conduction band of n-GaN as close as possible at the interface to ensure that carrier tunneling can be achieved at a small bias voltage. This doping concentration often needs to reach 10 20 order of magnitude. However, p-type doping of GaN has always faced the problems of high activation energy of Mg acceptor dopants and low doping efficiency, which seriously affects the preparation of GaN homojunction tunneling diodes. Summary of the Invention

[0003] The purpose of the present invention is to provide a p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode with a type-II energy band alignment, which can reduce the requirement for heavy doping concentration.

[0004] The purpose of the present invention is achieved by the following technical solutions:

[0005] A p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode, the structure of which includes:

[0006] A substrate layer;

[0007] A GaN layer grown on the substrate layer;

[0008] An n-GaN layer grown on the GaN layer;

[0009] An n+GaN layer grown on the n-GaN layer;

[0010] An n++GaN layer grown on the n+GaN layer;

[0011] A p++NiO layer or a p++LiNiO layer grown on the n++GaN layer;

[0012] A p+NiO layer grown on a p++NiO layer throughout its growth; or a p+LiNiO layer grown on a p++LiNiO layer;

[0013] A P-type electrode disposed on the p+NiO or p+LiNiO layer;

[0014] An N-type electrode disposed on the GaN layer.

[0015] Preferably, the thickness of the n-GaN layer is 1 - 3 μm, and the doping concentration is 1×10 19 -1×10 20 cm -3 .

[0016] Preferably, the thickness of the n+GaN layer is 100 - 200 nm, and the doping concentration is 5×10 19 -1×10 20 cm -3 .

[0017] Preferably, the thickness of the n++GaN layer is 10 - 30 nm, and the doping concentration is 2×10 20 -5×10 20 cm -3 .

[0018] Preferably, the thickness of the p++NiO layer or p++LiNiO layer is 10 - 30 nm, and the hole concentration is 2×10 19 -5×10 19 cm -3 .

[0019] Preferably, the thickness of the p+NiO layer or p+LiNiO layer is 100 - 200 nm, and the hole concentration is 5×10 18 -1×10 19 cm -3 .

[0020] The present invention also discloses another structure of a p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode, wherein the GaN layer of the diode is a GaN self-supporting substrate layer, and the N-type electrode is a back electrode.

[0021] The present invention also discloses a method for manufacturing the above-mentioned p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode, and the steps thereof include:

[0022] (1) Growing a GaN layer, an n-GaN layer, an n+GaN layer, and an n++GaN layer on the surface of the substrate in sequence;

[0023] (2) Perform mesa isolation using ICP etching, etch to the n-GaN layer, and fabricate an ohmic contact N-type electrode.

[0024] (3) Grow a p++NiO layer or a p++LiNiO layer on the surface of the n++GaN layer.

[0025] (4) Grow a p+NiO layer on the surface of the p++NiO layer, or grow a p+LiNiO layer on the surface of the p++LiNiO layer.

[0026] (5) Fabricate an ohmic contact P-type electrode on the surface of the p+NiO layer or the p+LiNiO layer.

[0027] The present invention utilizes the characteristics of the staggered arrangement of type-II energy bands. Compared with the GaN homojunction p-n junction, the valence band of p-NiO or p-LiNiO is closer to the conduction band of n-GaN, which is beneficial to the tunneling of carriers, can reduce the requirement for the heavily doped concentration, and p-NiO or p-LiNiO is easier to achieve a higher hole concentration than p-GaN.

[0028] In the device structure of the present invention, the heavy doping of n++GaN and P++NiO causes the energy bands at the pn heterojunction interface to bend, making the valence band of p-NiO (p++NiO layer) higher than the conduction band of n-GaN under zero bias, so as to realize the resonant tunneling of carriers by adjusting the bias voltage. Description of the Drawings

[0029] Figure 1 is a schematic diagram of the device structure obtained in step A of Example 1.

[0030] Figure 2 is a schematic diagram of the device structure obtained in step B of Example 1.

[0031] Figure 3 is a schematic diagram of the device structure obtained in step C of Example 1.

[0032] Figure 4 is a schematic diagram of the device structure obtained in step D of Example 1.

[0033] Figure 5 is the current-voltage curve diagram obtained by testing the device prepared in Example 1.

[0034] Figure 6 is a schematic diagram of the device structure obtained in step A of Example 3.

[0035] Figure 7 is a schematic diagram of the device structure obtained in step B of Example 3.

[0036] Figure 8 is a schematic diagram of the device structure obtained in step C of Example 3.

[0037] Figure 9 It is a schematic diagram of the device structure obtained in step D of Example 3.

[0038] Figure 10 It is a schematic diagram of the device structure obtained in step E of Example 3. Detailed implementation manners

[0039] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0040] Example 1

[0041] Preparation method of p-NiO / n-GaN heterojunction resonant tunneling diode

[0042] A. Use MOCVD or MBE method to grow 2-4 μm of high-resistance GaN on sapphire or Si substrate; the Si doping concentration is 1×10 19 -1×10 20 cm -3 of n-GaN layer with a thickness of 1-3 μm; 100-200 nm of n+GaN with a doping concentration of 5×10 19 -1×10 20 cm -3 ; 10-30 nm thick n++GaN with a doping concentration of 2×10 20 -5×10 20 cm -3 ; Figure 1 It is a schematic diagram of the multi-layer GaN epitaxial structure obtained in step A.

[0043] B. Use ICP etching method for mesa isolation, etch to the n-GaN layer, over-etch 100-300 nm; use electron beam evaporation to prepare n-GaN ohmic contact; Figure 2 It is a schematic diagram of the structure obtained in step B.

[0044] C. Use magnetron sputtering or pulsed laser deposition method to grow p-NiO again. From bottom to top, there are p++NiO with a thickness of 10-30 nm, hole concentration of 2×10 19 -5×10 19 cm -3 ; 100-200 nm of p+NiO, hole concentration of 5×10 18 -1×10 19 cm -3 ;Figure 3 is the device structure obtained in step C.

[0045] D. Prepare the p-type ohmic contact by electron beam evaporation; Figure 4 is the device structure diagram obtained in step D. Test the current-voltage curve of the device, as Figure 5 shown. Under positive gate voltage, the device exhibits obvious negative differential resistance phenomenon, and this phenomenon will not disappear after repeated scanning.

[0046] The above embodiments are the preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent substitution methods and are all included in the protection scope of the present invention.

[0047] Embodiment 2

[0048] A p-NiO / n-GaN heterojunction resonant tunneling diode, the structure of which includes:

[0049] A GaN self-supporting substrate layer;

[0050] An n-GaN layer grown on the GaN layer;

[0051] An n+GaN layer grown on the n-GaN layer;

[0052] An n++GaN layer grown on the n+GaN layer;

[0053] A p++NiO layer grown on the n++GaN layer;

[0054] A p+NiO layer grown on the p++NiO layer;

[0055] A p-type electrode, arranged on the p+NiO layer;

[0056] An n-type electrode, arranged on the back of the GaN self-supporting substrate layer, as the back electrode.

[0057] Embodiment 3

[0058] The diode process flow of Embodiment 2

[0059] A. Grow an n-GaN layer with a Si doping concentration of 1×10 19 -1×10 20 cm -3 on the self-supporting GaN substrate, with a thickness of 1-3 μm; 100-200 nm of n+GaN, with a doping concentration of 5×10 19 -1×10 20 cm -3; n++ GaN with a thickness of 10 - 30 nm and a doping concentration of 2×10 20 -5×10 20 cm -3 ; ( Figure 6 Schematic diagram of the multi-layer GaN epitaxial structure obtained in step A)

[0060] B. Prepare an n-GaN ohmic contact back electrode using electron beam evaporation; ( Figure 7 Schematic diagram of the structure obtained in step B)

[0061] C. Perform mesa isolation using ICP etching, etching down to the n-GaN layer, with an over-etch of 100 - 300 nm; Figure 8 Device structure obtained in step C)

[0062] D. Regrow p-NiO using magnetron sputtering or pulsed laser deposition. From bottom to top, there are p++ NiO with a thickness of 10 - 30 nm, a hole concentration of 2×10 19 -5×10 19 cm -3 ; p+ NiO with a thickness of 100 - 200 nm, a hole concentration of 5×10 18 -1×10 19 cm -3 ; ( Figure 9 Device structure obtained in step D)

[0063] E. Prepare a p-type ohmic contact using electron beam evaporation; ( Figure 10 Device structure diagram obtained in step E).

[0064] Example 4

[0065] Preparation method of p-LiNiO / n-GaN heterojunction resonant tunneling diode

[0066] A. Grow 2 - 4 μm of high-resistance GaN on a sapphire or Si substrate using MOCVD or MBE; The Si doping concentration is 1×10 19 -1×10 20 cm -3 for the n-GaN layer with a thickness of 1 - 3 μm; 100 - 200 nm of n+ GaN with a doping concentration of 5×10 19 -1×10 20 cm -3 ; n++ GaN with a thickness of 10 - 30 nm and a doping concentration of 2×10 20 -5×10 20 cm -3 ; Figure 1 Schematic diagram of the multi-layer GaN epitaxial structure obtained in step A.

[0067] B. Perform mesa isolation using ICP etching, etch to the n-GaN layer, and over-etch by 100 - 300 nm; fabricate n-GaN ohmic contacts using electron beam evaporation; Figure 2 is the structural schematic diagram obtained in step B.

[0068] C. Regrow p-LiNiO using magnetron sputtering or pulsed laser deposition. From bottom to top, it is p++LiNiO with a thickness of 10 - 30 nm, hole concentration of 2×10 19 -5×10 19 cm -3 ; p+LiNiO with a thickness of 100 - 200 nm, hole concentration of 5×10 18 -1×10 19 cm -3 ; Figure 3 is the device structure obtained in step C.

[0069] D. Fabricate p-type ohmic contacts using electron beam evaporation; Figure 4 is the device structure diagram obtained in step D. Test the current-voltage curve of the device. As Figure 5 shown, the device exhibits an obvious negative differential resistance phenomenon under positive gate voltage, and this phenomenon does not disappear after repeated scanning.

[0070] Example 5

[0071] A p-LiNiO / n-GaN heterojunction resonant tunneling diode, whose structure includes:

[0072] A GaN self-supporting substrate layer;

[0073] An n-GaN layer grown on the GaN layer;

[0074] An n+GaN layer grown on the n-GaN layer;

[0075] An n++GaN layer grown on the n+GaN layer;

[0076] A p++LiNiO layer grown on the n++GaN layer;

[0077] A p+LiNiO layer grown on the p++LiNiO layer;

[0078] A p-type electrode, disposed on the p+LiNiO layer;

[0079] An n-type electrode, disposed on the back of the GaN self-supporting substrate layer, serving as a back electrode.

Claims

1. A p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode, the structure of which includes: A substrate layer; A GaN layer grown on the substrate layer; An n-GaN layer grown on the GaN layer; An n+GaN layer grown on the n-GaN layer; An n++GaN layer grown on the n+GaN layer; A p++NiO layer or a p++LiNiO layer grown on the n++GaN layer; A p+NiO layer grown on the p++NiO layer; or a p+LiNiO layer grown on the p++LiNiO layer; A P-type electrode disposed on the p+NiO or p+LiNiO layer; An N-type electrode disposed on the GaN layer.

2. The p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode according to claim 1, characterized in that: The thickness of the n-GaN layer is 1 - 3 μm, and the doping concentration is 1×10 19 -1×10 20 cm -3 .

3. The p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode according to claim 1, characterized in that: The thickness of the n+GaN layer is 100 - 200 nm, and the doping concentration is 5×10 19 -1×10 20 cm -3 .

4. The p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode according to claim 1, characterized in that: The thickness of the n++ GaN layer is 10 - 30 nm, and the doping concentration is 2×10 20 - 5×10 20 cm -3 .

5. The p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode according to any one of claims 1-4, characterized in that: The thickness of the p++NiO layer or p++LiNiO layer is 10 - 30 nm, and the hole concentration is 2×10 19 - 5×10 19 cm -3 .

6. The p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode according to any one of claims 1-4, characterized in that: The thickness of the p+NiO layer or the p+LiNiO layer is 100 - 200 nm, and the hole concentration is 5×10 18 -1×10 19 cm -3 .

7. The p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode according to any one of claims 1-4, characterized in that: The n-GaN layer of the diode is a GaN self-supporting substrate, and the N-type electrode is a back electrode.

8. A method for preparing the p-NiO or p-LiNiO / n-GaN heterojunction resonant tunneling diode according to any one of claims 1-6, the steps of which include: (1) Growing a GaN layer, an n-GaN layer, an n+GaN layer, and an n++GaN layer on the surface of the substrate in sequence; (2) Using ICP etching for mesa isolation, etching to the n-GaN layer, and preparing an ohmic contact N-type electrode; (3) Growing a p++NiO layer or a p++LiNiO layer on the surface of the n++GaN layer; (4) Growing a p+NiO layer on the surface of the p++NiO layer, or growing a p+LiNiO layer on the surface of the p++LiNiO layer; (5) Preparing an ohmic contact P-type electrode on the surface of the p+NiO layer or the p+LiNiO layer.

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