A multi-channel output controlled multiplexer

Abstract

The application discloses a multi-channel output control multiplexer, and relates to the field of electronic circuit design, which can facilitate the cooperative use of multiple groups of output data in signal transmission, and specifically comprises a signal input control device, a selection device and a signal output control device. The principle is that the signal input control device analyzes M input enable signals into N input control signals, which are used for controlling the gating state of N input control units of the selection device; the signal output control device analyzes M output enable signals into N output control signals, which are used for controlling the gating state of N output control units of the selection device; M and N are positive integers greater than 1, and N is less than or equal to 2M. The selection device is connected with input signals at the input end of the N input control units, and the output ends of the N input control units are connected with each other and connected in parallel to the input ends of the N output control units, and the output ends of the N output control units are output signals.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit design, specifically to a multi-channel output control multiplexer that has the function of selecting inputs and controlling outputs of N channels. Background Technology

[0002] A multiplexer can concentrate signals from multiple channels onto a single channel and arbitrarily select one channel for transmission, offering a degree of flexibility and controllability. However, existing multiplexers typically only have N-in, 1-out functionality for channel transmission. In integrated circuit design, especially in signal combination, when it's necessary to sequentially combine signal data from multiple channels into a new data stream and output it to multiple different channels for coordinated use, traditional N-in, 1-out multiplexers cannot directly meet the requirements. For example, in LED driver circuits, when it's necessary to arrange and combine existing input waveforms into multiple sets of different shapes and coordinately output waveforms to control multiple LED outputs to increase visual diversity, traditional N-in, 1-out multiplexers cannot directly meet the requirements, while N-in, N-out multiplexers can easily achieve this.

[0003] This invention discloses a multi-channel output control multiplexer, which has the functions of selecting input and output of multi-channel analog signals; its input enable signal and output enable signal are provided by external devices, which has a high degree of flexibility; its control signal directly controls the transmission gate switch in the control unit, which can enable the input signal to be directly transmitted through the transmission gate, thus ensuring the stability of signal transmission. Summary of the Invention

[0004] This invention discloses a multi-channel output control multiplexer, which has the functions of multi-channel analog signal selection input and multi-channel selection output control (N inputs and N outputs), overcoming at least some of the aforementioned problems. This invention relates to the field of electronic circuit design and specifically includes: a signal input control device, a selection device, and a signal output control device. The circuit principle is as follows: the signal input control device resolves M input enable signals (IEN_1~IEN_M) into N input control signals (ISEL_1~ISEL_N), used to control the selection state of the N input signals (IN_1~IN_N) in the selection device's N input control units (input control unit 1~input control unit N); the signal output control device resolves M output enable signals (OEN_1~OEN_M) into N output control signals (OSEL_1~OSEL_N), used to control the selection state of the N output signals (OUT_1~OUT_N) in the selection device's N output control units (output control unit 1~output control unit N); M and N are positive integers greater than 1, and N≤2. MThe selection device is an execution circuit, and both the input and output of signals are controlled by this device. It consists of N input control units (input control unit 1 to input control unit N) and N output control units (output control unit 1 to output control unit N). The N input control units correspond one-to-one with the N input signals (IN_1 to IN_N) and the N input control signals (ISEL_1 to ISEL_N) output by the signal input control device. The input terminal of the Y-th input control unit Y is connected to the Y-th input signal IN_Y, and the control terminal of the input control unit Y is connected to the Y-th input control signal output by the input control device. The signal ISEL_Y is used to control the selection state of the input control unit Y, where Y = [1, N] and Y is an integer. The N output control units correspond one-to-one with the N output signals (OUT_1~OUT_N) and the N output control signals (OSEL_1~OSEL_N) output by the signal output control device. The input terminal of the Xth output control unit X is connected to the Xth output signal OUT_X, and the control terminal of the output control unit X is connected to the Xth output control signal OSEL_X output by the output control device, used to control the selection state of the output control unit X, where X = [1, N] and X is an integer. The output terminals of the N input control units are connected in parallel, the input terminals of the N output control units are connected in parallel, and the output terminals of the N input control units are connected to the input terminals of the N output control units. The output terminals of the N output control units are the outputs (OUT_1~OUT_N) of the multiplexer.

[0005] The signal input control device receives M input enable signals (IEN_1~IEN_M) and outputs N input control signals (ISEL_1~ISEL_N), where M and N are positive integers greater than 1, and N ≤ 2. M The N input control signals (ISEL_1~ISEL_N) output by the device correspond to the selection states of the N input control units (input control unit 1~input control unit N) in the control selection device. The signal input control device further includes the following: of the N output input control signals (ISEL_1~ISEL_N), only one output is enabled, while the remaining N-1 outputs are disabled.

[0006] The selection device comprises N input control units, each consisting of two inverters and one transmission gate. The transmission gate is composed of a P-channel MOSFET and an N-channel MOSFET connected in parallel, with their sources and drains connected as the input and output terminals (also the input and output terminals of the input control unit). The two inverters are connected in series to coordinate the conduction of the transmission gate. The first inverter performs a phase shift of the input control signal level of the signal input control device; its input terminal is connected to the input control signal of the signal input control device, and its output terminal is connected to the input terminal of the second inverter and the gate control terminal of the P-channel MOSFET in the transmission gate. The second inverter shapes the original signal, and its output terminal is connected to the gate control terminal of the N-channel MOSFET in the transmission gate. The drains and sources of the P-channel and N-channel MOSFETs in the transmission gate are interchangeable, as are their input and output terminals. The signal transmission can be either a digital or analog signal.

[0007] The N output control units in the selection device have the same circuit structure and function as the input control unit, and each unit consists of 2 inverters and 1 transmission gate. The transmission gate is composed of a P-channel MOSFET and an N-channel MOSFET connected in parallel, with their sources and drains connected as the input and output terminals of the transmission gate (which are also the input and output terminals of the output control unit). The two inverters are connected in series to coordinate the conduction of the transmission gate. The first inverter performs a phase shift on the output control signal level of the signal output control device, with its input connected to the output control signal of the signal output control device, and its output connected to the input of the second inverter and the gate control terminal of the P-channel MOSFET in the transmission gate. The second inverter shapes the original signal, and its output is connected to the gate control terminal of the N-channel MOSFET in the transmission gate. The drains and sources of the P-channel and N-channel MOSFETs in the transmission gate are interchangeable, as are their inputs and outputs, allowing for the transmission of both digital and analog signals.

[0008] The signal output control device described herein has the same function and purpose as the signal input control device. The signal output control device receives M output enable signals (OEN_1~OEN_M) and outputs N output control signals (OSEL_1~OSEL_N), where M and N are positive integers greater than 1, and N ≤ 2. MThe N output control signals (OSEL_1~OSEL_N) output by the device correspond to the selection states of the N output control units (output control unit 1~output control unit N) in the control selection device. The signal output control device further includes the following: of the N output control signals (OSEL_1~OSEL_N), only one output is enabled, while the remaining N-1 outputs are disabled. Attached Figure Description

[0009] Figure 1 This diagram illustrates the overall block diagram provided in an embodiment of the present invention. Figure 2 This diagram shows the internal circuit of the selection device provided in an embodiment of the present invention. Figure 3 A schematic diagram showing the internal circuitry of an inverter and the inverter symbol; Figure 4 A schematic diagram showing the internal circuitry of a transmission gate and its symbol is provided. Figure 5 This diagram illustrates the control unit circuit provided in an embodiment of the present invention. Figure 6 This document presents a truth table of the input and output of control signals and transmission signals provided in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions in the embodiments of the present invention will be described in detail below through specific unit circuit examples and accompanying drawings. The example circuits listed in the embodiments are all within the protection scope of the present invention.

[0011] like Figure 1 The diagram illustrates the overall framework of the present invention, which mainly includes a signal input control device, a signal output control device, and a selection device. The principle is as follows: M input enable signals (IEN_1~IEN_M) are parsed by the signal input control device into N input control signals (ISEL_1~ISEL_N). These N input control signals control the selection state of the N input signals (IN_1~IN_N) within the selection device's N input control units (input control unit 1~input control unit N). Similarly, M output enable signals (OEN_1~OEN_M) are parsed by the signal output control device into N output control signals (OSEL_1~OSEL_N). These N output control signals control the selection state of the N output signals (OUT_1~OUT_N) within the selection device's N output control units (output control unit 1~output control unit N). M and N are positive integers greater than 1, and N ≤ 2. MThe selection device is an execution circuit, controlling both signal input and output. Its N input control units have input signals (IN_1~IN_N) connected to their input terminals, and their output terminals are interconnected and connected in parallel to the input terminals of the N output control units. The output terminals of the N output control units are output signals (OUT_1~OUT_N). This results in a multiplexer with N-channel input and N-channel output control.

[0012] The signal input control device in this embodiment of the invention takes M input enable signals (IEN_1~IEN_M) as input and outputs N input control signals (ISEL_1~ISEL_N), where M and N are positive integers greater than 1 and N≤2. M The N input control signals (ISEL_1~ISEL_N) output by this device correspond to the selection states of the N input control units (input control unit 1~input control unit N) in the control selection device. That is, control signal ISEL_1 controls the selection state of input control unit 1 in the selection control circuit, control signal ISEL_2 controls the selection state of input control unit 2 in the selection control circuit, control signal ISEL_N controls the selection state of input control unit N in the selection control circuit, and so on. The signal input control device further includes the following: of the N output input control signals (ISEL_1~ISEL_N), only one output is enabled, while the remaining N-1 outputs are disabled.

[0013] The signal output control device in this embodiment of the invention has the same function and role as the signal input control device. The signal output control device inputs M output enable signals (OEN_1~OEN_M) and outputs N output control signals (OSEL_1~OSEL_N), where M and N are positive integers greater than 1, and N ≤ 2. M The N output control signals (OSEL_1~OSEL_N) output by this device correspond to the selection states of the N output control units (output control unit 1~output control unit N) in the control selection device. That is, control signal OSEL_1 controls the selection state of output control unit 1 in the selection control circuit, control signal OSEL_2 controls the selection state of output control unit 2 in the selection control circuit, control signal OSEL_N controls the selection state of output control unit N in the selection control circuit, and so on. The signal output control device further includes the following: of the N output control signals (OSEL_1~OSEL_N), only one output is enabled, while the remaining N-1 outputs are disabled.

[0014] like Figure 2The diagram shows the internal circuit of the selection device provided in the embodiment of the present invention. The circuit consists of N input control units (input control unit 1 to input control unit N) and N output control units (output control unit 1 to output control unit N). The N input control units correspond one-to-one with the N input signals (IN_1~IN_N) and the N input control signals output by the signal input control device. The input terminal of the Y-th input control unit Y is connected to the Y-th input signal IN_Y, and the control terminal of the input control unit Y is connected to the Y-th input control signal ISEL_Y output by the input control device, used to control the selection state of the input control unit Y. Y = [1, N], where Y is an integer. The N output control units correspond one-to-one with the N output signals (OUT_1~OUT_N) and the N output control signals output by the signal output control device. The input terminal of the X-th output control unit X is connected to the X-th output signal OUT_X, and the control terminal of the output control unit X is connected to the X-th output control signal OSEL_X output by the output control device, used to control the selection state of the output control unit X. X = [1, N], where X is an integer. The outputs of the N input control units are connected in parallel, the inputs of the N output control units are connected in parallel, the outputs of the N input control units are connected to the inputs of the N output control units, and the outputs of the N output control units are the outputs of the multiplexer (OUT_1~OUT_N).

[0015] Optionally, the circuit structure in the selection device is a symmetrical design, the transmitted signal is bidirectional communication, and the signal input control device and the signal output control device have the same function and role, so the signal input and output relationship can be freely defined and switched.

[0016] For ease of circuit analysis, inverters and transmission gates in the circuit diagram are represented using logic gate symbols. The internal circuitry of the inverter is shown below. Figure 3 As shown, the internal circuit of the transmission gate is as follows: Figure 4 As shown. The P-channel MOSFET and N-channel MOSFET in the internal circuit of the transmission gate are connected in parallel. The source of the P-channel MOSFET is connected to the drain of the N-channel MOSFET as the signal input / output transmission interface (defined as the input interface in this embodiment). The drain of the P-channel MOSFET is connected to the source of the N-channel MOSFET, also serving as the signal input / output transmission interface (defined as the output interface in this embodiment). When the control signal ck of the P-channel MOSFET is low and the control signal ckb of the N-channel MOSFET is high (ck and ckb are signals with opposite levels), the transmission gate channel is turned on, and the data at the source and drain terminals are interconnected.

[0017] like Figure 5The control unit circuit in the selection device is shown. The number and structure of the input and output control units are identical, each consisting of two inverters and one transmission gate. The two inverters are connected in series. The first inverter performs a phase shift on the input enable signal, and its output is connected to the control terminal of the P-channel MOSFET in the transmission gate. The second inverter shapes the original enable signal and delays the balanced signal, and its output is connected to the control terminal of the N-channel MOSFET in the transmission gate. The output signals of the two inverters are in binary form, determined by the control signal at the input terminal of the first inverter. A control signal of 1 (high level) indicates enable, and the transmission gate is turned on; a control signal of 0 (low level) indicates disable, and the transmission gate is turned off.

[0018] like Figure 6 The truth table for the input and output of control signals and transmission signals in this embodiment is shown. In this truth table, only one control signal is enabled, and the remaining N-1 control signals are disabled. For example, if the control signal ISEL_1 output by the signal input control device and the control signal OSEL_1 output by the signal output control device are enabled, the input signal IN_1 of the input control unit 1 in the selection device is selected as the input, and then output to OUT_1 by the output control unit 1. That is, the multiplexer will select the input signal IN_1 to output the output signal OUT_1. Similarly, if the input control signal ISEL_2 and the output control signal OSEL_1 are enabled, the selector will select the input signal IN_2 to output the output signal OUT_1; if the input control signal ISEL_1 and the output control signal OSEL_2 are enabled, the selector will select the input signal IN_1 to output the output signal OUT_2; and so on.

[0019] Optionally, in this embodiment, if it is necessary to output one or more input signals to multiple different output channels in a coordinated manner, it is only necessary to control the enable signals of the signal input control device and the signal output control device to be in a dynamically changing state.

[0020] It should be noted that, although embodiments of the present invention have been shown and described, various changes, modifications and substitutions can be made to these embodiments without departing from the principles of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A multiplexer with multi-channel output control, characterized in that, It consists of a signal input control device, a selection device, and a signal output control device. Specifically, the signal input control device resolves M input enable signals (IEN_1~IEN_M) into N input control signals (ISEL_1~ISEL_N), which are used to control the selection state of the N input signals (IN_1~IN_N) in the selection device's N input control units (input control unit 1~input control unit N); the signal output control device resolves M output enable signals (OEN_1~OEN_M) into N output control signals (OSEL_1~OSEL_N), which are used to control the selection state of the N output signals (OUT_1~OUT_N) in the selection device's N output control units (output control unit 1~output control unit N); M and N are positive integers greater than 1, and N≤2. M The selection device is an execution circuit, and the input and output of signals are controlled by this device. It consists of N input control units (input control unit 1 to input control unit N) and N output control units (output control unit 1 to output control unit N) in a symmetrical structure. The N input control units correspond one-to-one with the N input signals (IN_1 to IN_N) and the N input control signals (ISEL_1 to ISEL_N) output by the signal input control device. The input terminal of the Y-th input control unit Y is connected to the Y-th input signal IN_Y, and the control terminal of the input control unit Y is connected to the Y-th input control signal ISEL_Y output by the input control device, which is used to control the selection state of the input control unit Y. Y=[1,N], where Y is an integer. The N output control units are... Each input control unit corresponds one-to-one with N output signals (OUT_1~OUT_N) and N output control signals (OSEL_1~OSEL_N) output by the signal output control device. The input terminal of the Xth output control unit X is connected to the Xth output signal OUT_X, and the control terminal of the output control unit X is connected to the Xth output control signal OSEL_X output by the output control device. This control is used to control the selection state of the output control unit X. X=[1,N], where X is an integer. The output terminals of the N input control units are connected in parallel, the input terminals of the N output control units are connected in parallel, and the output terminals of the N input control units are connected to the input terminals of the N output control units. The output terminals of the N output control units are the outputs (OUT_1~OUT_N) of the multiplexer.

2. The signal input control device as described in claim 1, characterized in that: The device takes M input enable signals (IEN_1~IEN_M) as inputs and outputs N input control signals (ISEL_1~ISEL_N), where M and N are positive integers greater than 1 and N≤2. M The N input control signals (ISEL_1~ISEL_N) output by the device correspond to the selection states of the N input control units (input control unit 1~input control unit N) in the control selection device.

3. The signal input control device as described in claim 2, further comprising: Of the N input control signals (ISEL_1~ISEL_N) output, only one output is enabled, while the remaining N-1 outputs are disabled.

4. The N input control units as described in claim 1, characterized in that: Each input control unit consists of two inverters and one transmission gate. The transmission gate is composed of a P-channel MOSFET and an N-channel MOSFET connected in parallel, with their sources and drains connected as the input and output terminals of the transmission gate (which are also the input and output terminals of the input control unit). The two inverters are connected in series. The input terminal of the first inverter is connected to the input control signal of the signal input control device, and its output terminal is connected to the input terminal of the second inverter and the gate control terminal of the P-channel MOSFET in the transmission gate. The output terminal of the second inverter is connected to the gate control terminal of the N-channel MOSFET in the transmission gate. The drains and sources of the P-channel and N-channel MOSFETs in the transmission gate can be interchanged, as can their input and output terminals. The signal transmission can be either a digital signal or an analog signal.

5. The N output control units as described in claim 1, characterized in that: The output control unit and the input control unit have the same circuit structure, both consisting of two inverters and one transmission gate. The transmission gate is composed of a P-channel MOSFET and an N-channel MOSFET connected in parallel, with their sources and drains connected as the input and output terminals of the transmission gate (which are also the input and output terminals of the output control unit). The two inverters are connected in series. The input terminal of the first inverter is connected to the output control signal of the signal output control device, and its output terminal is connected to the input terminal of the second inverter and the gate control terminal of the P-channel MOSFET in the transmission gate. The output terminal of the second inverter is connected to the gate control terminal of the N-channel MOSFET in the transmission gate. The drains and sources of the P-channel and N-channel MOSFETs in the transmission gate can be interchanged, as can their input and output terminals. The signal transmission can be either a digital signal or an analog signal.

6. The signal output control device as described in claim 1, characterized in that: The signal output control device has the same function and purpose as the signal input control device; the signal output control device inputs M output enable signals (OEN_1~OEN_M) and outputs N output control signals (OSEL_1~OSEL_N), where M and N are positive integers greater than 1, and N≤2. M The N output control signals (OSEL_1~OSEL_N) output by the device correspond to the selection states of the N output control units (output control unit 1~output control unit N) in the control selection device.

7. The signal output control device as described in claim 6, further comprising: Of the N output control signals (OSEL_1~OSEL_N), only one output is enabled, while the remaining N-1 outputs are disabled.

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