A method for manufacturing a power integrated circuit

Abstract

The present invention proposes a method for manufacturing a power integrated circuit, comprising: growing an epitaxial layer of a second type of doped semiconductor with different concentrations on a silicon substrate of a first type of doped semiconductor, and producing a gate oxide layer on the epitaxial layer; determining the doping concentration of the first type of doped semiconductor in different functional areas of the epitaxial layer according to the design of the components and the integrated circuit, performing photolithography and ion implantation on the gate oxide layer according to the doping concentration, defining first type doped semiconductor regions with different concentrations on the epitaxial layer and forming low concentration regions and high concentration regions through annealing, forming a gate pattern on the gate oxide layer through photolithography and etching; depositing a refractory metal layer on the gate oxide layer, and performing photolithography and etching on the refractory metal layer to form ohmic contact windows for different functional areas; forming silicide on the silicon substrate, depositing an ohmic contact metal layer, and photolithography and etching the ohmic contact metal layer to form component and circuit interconnection and circuit isolation of a high-power silicon integrated circuit.

Description

Technical Field

[0001] The invention provides a method for manufacturing a power integrated circuit, belonging to the technical field of microelectronics. Background Art

[0002] In the manufacturing process of semiconductor devices, power devices and large-scale and ultra-large-scale integrated circuits, especially the manufacturing process of integrated circuit modules, how to address the complexity of device performance requirements, including how to combine with integrated circuit and device design to simplify the process flow, improve the adhesion and mechanical strength between multi-layer metals and multi-layer metals and various insulating dielectric layers with different characteristics, reduce device costs, and improve device performance and reliability is a key technical challenge.

[0003] In the existing technical solutions for manufacturing power integrated circuits, either the device functions are incomplete or the device design and manufacturing process are too complicated and the cost is high. In particular, how to integrate semiconductor components, i.e., active components (components), such as metal oxide semiconductor field effect devices, bipolar transistors, etc., with passive components, such as capacitors, resistors, inductors, etc., in a high-efficiency, high-reliability and low-cost manner in the design and manufacture of power integrated circuits. Therefore, the present invention proposes a method for manufacturing power integrated circuits, which forms different functional areas in the epitaxial layer through lithography and etching processes combined with device design and multiple ion implantation and diffusion, performs rapid annealing, and uses multi-layer metal to improve the adhesion between the metal film and the insulating film, so as to integrate the semiconductor components in the power integrated circuit, i.e., active components, such as metal oxide semiconductor field effect devices, etc., and passive components, such as capacitors, resistors, etc., efficiently and reliably, thereby improving the manufacturability of the components and reducing cost consumption, while also improving the performance of the components and enhancing the reliability of the devices. Summary of the Invention

[0004] The present invention provides a method for manufacturing a power integrated circuit, which is used to solve the problem of manufacturing a power integrated circuit:

[0005] The present invention proposes a method for manufacturing a power integrated circuit, comprising: growing an epitaxial layer of a second type of doped semiconductor with different concentrations on a silicon substrate of a first type of doped semiconductor, and producing a gate oxide layer on the epitaxial layer; determining the doping concentration of the first type of doped semiconductor in different functional areas of the epitaxial layer of the second type of doped semiconductor according to the design of the components and the integrated circuit, performing photolithography and ion implantation on the gate oxide layer according to the doping concentration of the first type of doped semiconductor in different functional areas, and defining first type doped semiconductor regions with different concentrations on the epitaxial layer of the second type of doped semiconductor; forming a first type doped semiconductor by annealing. A low-concentration region and a high-concentration region are formed in the region, and a gate pattern is formed on the gate oxide layer by photolithography and etching; a refractory metal layer is deposited on the gate oxide layer, and photolithography and etching are performed on the refractory metal layer to form ohmic contact windows of different functional regions; a silicide is formed on the silicon substrate, an ohmic contact metal layer is deposited, and the ohmic contact metal layer is photolithographically and etched to form components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; and the circuit is the designed circuit of the high-power silicon integrated circuit.

[0006] Furthermore, when depositing a refractory metal layer on the gate oxide layer, the refractory metal layer is photolithographically processed, and functional areas are defined at one time. The functional areas include: a metal oxide semiconductor field effect transistor area, a capacitor area, a resistor area, and a circuit connection area. Silicon nitride film and silicon oxide film are sequentially deposited on the functional areas and the refractory metal layer. After forming ohmic contact windows of different functional areas, the ohmic contact windows of the functional areas are photolithographically processed and etched, and silicide is formed on the corresponding silicon area on the functional area, thereby depositing an ohmic contact metal layer on the silicide.

[0007] Furthermore, the method for manufacturing a power integrated circuit further includes: growing an epitaxial layer of a first type doped semiconductor with different concentrations on a silicon substrate of a second type doped semiconductor, and producing a gate oxide layer on the epitaxial layer; determining the doping concentration of the second type doped semiconductor in different functional areas of the epitaxial layer of the first type doped semiconductor according to the design of the components and the integrated circuit, performing photolithography and ion implantation on the gate oxide layer according to the doping concentration of the second type doped semiconductor in different functional areas, and defining second type doped semiconductor regions with different concentrations on the epitaxial layer of the first type doped semiconductor; forming the second type doped semiconductor regions by annealing. Low-concentration areas and high-concentration areas are formed by photolithography and etching on the gate oxide layer to form a gate pattern; a refractory metal layer is deposited on the gate oxide layer, and photolithography and etching are performed on the refractory metal layer to form ohmic contact windows for different functional areas; silicide is formed on the silicon substrate, an ohmic contact metal layer is deposited, and the ohmic contact metal layer is photolithographically and etched to form component and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are the metal oxide semiconductor field-effect device, input resistor, output resistor, load resistor and filter capacitor; and the circuit is the designed circuit of the high-power silicon integrated circuit.

[0008] Furthermore, the first type of doped semiconductor is a P-type semiconductor, and the second type of doped semiconductor is an N-type semiconductor. The P-type semiconductor is a hole-conducting semiconductor doped with acceptor impurities, and the N-type semiconductor is an electron-conducting semiconductor doped with donor impurities.

[0009] Furthermore, the power integrated circuit, when manufactured, includes:

[0010] For the P-type semiconductor, an epitaxial layer of an N-type semiconductor is sequentially grown on a silicon substrate of the P-type semiconductor, and a photoresist layer is coated on the epitaxial layer of the N-type semiconductor. According to the design of semiconductor components and integrated circuits, the acceptor doping concentrations of different functional regions of the epitaxial layer of the N-type semiconductor are determined. Photolithography and ion implantation are performed on the photoresist layer according to the acceptor doping concentrations of the different functional regions. Acceptor-doped semiconductor regions with different concentrations are defined on the epitaxial layer of the N-type semiconductor. The photoresist is removed, and low-concentration regions and high-concentration regions of the acceptor-doped semiconductor are formed by annealing. A protective oxide layer is grown on the epitaxial layer of the N-type semiconductor, a silicon nitride layer is deposited on the oxide layer, and photolithography and etching are performed on a portion of the silicon nitride layer to form a localized oxide region. The silicon nitride and protective silicon oxide on the localized oxide layer are removed, and a gate oxide layer is grown on the local silicon epitaxial layer from which the silicon nitride and protective silicon oxide have been removed. A polysilicon layer is deposited on the oxide layer; a gate pattern is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, and silicon oxide and silicon nitride are sequentially deposited on the gate oxide layer and the polysilicon layer formed after etching, a gate region side protection structure is formed on the gate oxide layer by photolithography and etching, a polysilicon resistor is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, a silicon nitride film and a capacitor bottom metal are deposited, the capacitor bottom metal is photolithographically and etched, a capacitor dielectric layer is deposited on the capacitor bottom metal, a capacitor dielectric region is defined by photolithography and etching, an ohmic contact and a capacitor top metal layer are deposited, and the ohmic contact and the capacitor top metal layer are photolithographically and etched, thereby forming components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; and the circuit is the designed circuit of the high-power silicon integrated circuit;

[0011] For the N-type semiconductor, an epitaxial layer of a P-type semiconductor is sequentially grown on a silicon substrate of the N-type semiconductor, and a photoresist layer is coated on the epitaxial layer of the P-type semiconductor; according to the design of components and integrated circuits, the donor doping concentrations of different functional areas of the P-type semiconductor epitaxial layer are determined, photolithography and ion implantation are performed on the photoresist layer according to the donor doping concentrations of the different functional areas, and donor-doped semiconductor regions with different concentrations are defined on the P-type semiconductor epitaxial layer; the photoresist is removed, low-concentration regions and high-concentration regions of the donor-doped semiconductor are formed by annealing, a protective oxide layer is grown on the P-type semiconductor epitaxial layer, a silicon nitride layer is deposited on the oxide layer, photolithography and etching are performed on a portion of the silicon nitride layer to form a localized oxide region, the silicon nitride and protective silicon oxide on the localized oxide layer are removed, a gate oxide layer is grown on the local silicon epitaxial layer from which the silicon nitride and protective silicon oxide have been removed, and a gate oxide layer is deposited on the gate oxide layer. A polysilicon layer is deposited on the gate oxide layer; a gate pattern is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, and silicon oxide and silicon nitride are sequentially deposited on the gate oxide layer and the polysilicon layer formed after etching, a gate region side protection structure is formed on the gate oxide layer by photolithography and etching, a polysilicon resistor is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, a capacitor bottom metal is deposited, the capacitor bottom metal is photolithographically and etched, a capacitor dielectric layer is deposited on the capacitor bottom metal, a capacitor dielectric region is defined by photolithography and etching, an ohmic contact and a capacitor top metal layer are deposited, the ohmic contact and the capacitor top metal layer are photolithographically and etched, and components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit are formed, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; and the circuit is the designed circuit of the high-power silicon integrated circuit.

[0012] Furthermore, the photolithography process involves placing a pre-made photomask on a wafer coated with photoresist, and then irradiating the wafer with ultraviolet light or other wavelengths through the photomask for a certain period of time according to the needs of component and integrated circuit design, including:

[0013] S1. Depositing a material for engraving a circuit on a wafer to form a thin film, and depositing a photoresist on the thin film;

[0014] S2. performing photolithography on the wafer by irradiating light according to the circuit design of the mask. When the photolithography process uses positive photoresist, the photoresist exposed to light is removed. When the photolithography process uses negative photoresist, the photoresist exposed to light is retained, and the material to be etched is exposed to the outside of the photoresist not retained.

[0015] S3, removing the exposed etched material by etching, leaving the material required for the wafer and the photoresist attached thereto, and then removing the photoresist by chemical treatment;

[0016] S4. Repeat steps S1 to S3 multiple times until a high-power integrated circuit with a complex structure is obtained.

[0017] Furthermore, the etching includes dry etching and wet etching, which removes the exposed portion of the underlying material in the photoresist micro-pattern after exposure and development, that is, reproduces the same pattern as the photoresist on the underlying material.

[0018] Furthermore, in the high-power silicon integrated circuit, an epitaxial layer of a P-type semiconductor with a resistivity of 8 ohm.cm is grown on the silicon substrate of the N-type semiconductor; the thermal oxidation temperature is 1050°C; the thickness of the gate oxide layer is 0.1 micron; the energy of the photolithography and phosphorus ion implantation of the low-concentration doped semiconductor on the N-type semiconductor is 120 KeV, and the dose is 5×10 13 / cm 3 The energy of the photolithography and phosphorus ion implantation into the high concentration doped semiconductor on the N-type semiconductor is 150 KeV and the dose is 3×10 15 / cm 3 ; Annealing temperature is: 1020℃; Silicon nitride film is: 700 angstroms thick.

[0019] Furthermore, the annealing includes: a first annealing stage, a second annealing stage, and a third annealing stage; wherein the maximum annealing temperature of the first annealing stage is 850°C, the maximum annealing temperature of the second annealing stage is 950°C, and the maximum annealing temperature of the third annealing stage is 1020°C; and, in the first annealing stage, the maximum annealing temperature is set to: a=850°C, and the annealing time is 30 seconds; in the second annealing stage, the annealing time is 180 seconds, and the annealing temperature satisfies the following formula and the maximum value shall not exceed 950°C;

[0020]

[0021] In the above formula, T a1 is the second stage annealing temperature, S 11 is the photolithography temperature from the first stage to the second stage, S 21 is the ion implantation temperature from the first stage to the second stage, S 31 is the vacuum environment temperature from the first stage to the second stage, S 41 is the low concentration semiconductor temperature from the first stage to the second stage, S 51 The high-concentration semiconductor temperature from the first stage to the second stage;

[0022] In the third stage of the annealing, the annealing time is 1000 seconds, the annealing temperature satisfies the following formula and the maximum value shall not exceed 1020° C.;

[0023]

[0024] In the above formula, T a2 is the third stage annealing temperature, S 12 is the photolithography temperature from the second stage to the third stage, S 22 is the ion implantation temperature from the second stage to the third stage, S 32 is the vacuum environment temperature from the second stage to the third stage, S 42 is the low concentration semiconductor temperature from the second stage to the third stage, S 52 It is the high concentration semiconductor temperature from the second stage to the third stage.

[0025] Furthermore, the ohmic contact metal layer includes: a metal layer, an interface between the metal and the semiconductor, and a semiconductor junction; the ohmic contact metal layer includes: ion implantation and epitaxy during its formation, wherein the ion implantation is to generate positively charged impurity ions from the source material, and to give the impurity ions sufficient energy through acceleration by an electric field to obtain impurity ions with sufficient energy, so that the impurity ions with sufficient energy enter the target crystal lattice, and the impurity ions with sufficient energy are activated through thermal annealing, thereby realizing impurity doping of the base material; the epitaxy is to grow a single crystal layer on the substrate, which is divided into solid phase epitaxy, vapor phase epitaxy, and liquid phase epitaxy.

[0026] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0027] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of manufacturing an integrated circuit on an epitaxial layer of an N-type semiconductor on a silicon substrate of a P-type semiconductor in the method for manufacturing a power integrated circuit according to the present invention;

[0029] Figure 2 A schematic diagram of an integrated circuit manufactured on an epitaxial layer of a P-type semiconductor on a silicon substrate of an N-type semiconductor in the method for manufacturing a power integrated circuit according to the present invention;

[0030] Figure 3This is another schematic diagram of manufacturing an integrated circuit on an epitaxial layer of an N-type semiconductor on a silicon substrate of a P-type semiconductor in the manufacturing of a power integrated circuit according to the present invention;

[0031] Figure 4 This is another schematic diagram of an integrated circuit manufactured on an epitaxial layer of a P-type semiconductor on a silicon substrate of an N-type semiconductor in the manufacturing of a power integrated circuit according to the present invention;

[0032] Figure 5 The present invention is a circuit diagram of the method for manufacturing a power integrated circuit. DETAILED DESCRIPTION

[0033] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0034] An embodiment of the present invention provides a method for manufacturing a power integrated circuit, comprising: growing an epitaxial layer of a second type of doped semiconductor with different concentrations on a silicon substrate of a first type of doped semiconductor, and producing a gate oxide layer on the epitaxial layer; determining the doping concentration of the first type of doped semiconductor in different functional areas of the epitaxial layer of the second type of doped semiconductor according to the design of the components and the integrated circuit; performing photolithography and ion implantation on the gate oxide layer according to the doping concentration of the first type of doped semiconductor in different functional areas, and defining first type of doped semiconductor regions with different concentrations on the epitaxial layer of the second type of doped semiconductor; forming the first type of doped semiconductor by annealing. The low-concentration area and the high-concentration area of ​​the conductor area are formed into a gate pattern on the gate oxide layer by photolithography and etching; a refractory metal layer is deposited on the gate oxide layer, and ohmic contact windows of different functional areas are formed by photolithography and etching on the refractory metal layer; silicide is formed on the silicon substrate, an ohmic contact metal layer is deposited, and the ohmic contact metal layer is photolithographically and etched to form the components and circuit interconnection and circuit isolation of the high-power silicon integrated circuit, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; and the circuit is the designed circuit of the high-power silicon integrated circuit.

[0035] The working principle of the above technical solution is as follows: growing an epitaxial layer of a second type of doped semiconductor with different concentrations on a silicon substrate of a first type of doped semiconductor, and producing a gate oxide layer on the epitaxial layer; determining the doping concentration of the first type of doped semiconductor in different functional areas of the epitaxial layer of the second type of doped semiconductor according to the design of the components and integrated circuits; performing photolithography and ion implantation on the gate oxide layer according to the doping concentration of the first type of doped semiconductor in different functional areas, and defining first type of doped semiconductor regions with different concentrations on the epitaxial layer of the second type of doped semiconductor; forming the first type of doped semiconductor regions by annealing. A gate pattern is formed on the gate oxide layer by photolithography and etching in low-concentration areas and high-concentration areas; a refractory metal layer is deposited on the gate oxide layer, and photolithography and etching are performed on the refractory metal layer to form ohmic contact windows for different functional areas; a silicide is formed on the silicon substrate, an ohmic contact metal layer is deposited, and the ohmic contact metal layer is photolithographically and etched to form component and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are metal oxide semiconductor field effect devices, input resistors, output resistors, load resistors and filter capacitors; and the circuit is the design circuit of the high-power silicon integrated circuit.

[0036] The beneficial effects of the above technical solution are as follows: the present invention is a new method based on the existing power integrated circuit component manufacturing process, which combines the design and process of semiconductor components and integrated circuits, and optimizes the design and process, thereby significantly reducing the number of lithography and etching processes, significantly reducing production costs, and improving product performance and reliability. The method can be used not only in the manufacture of silicon components and integrated circuits, but also in the design and manufacture of compound semiconductor components and integrated circuits, such as silicon carbide, gallium nitride, and gallium arsenide. Moreover, the method uses lithography and etching processes combined with component design, forms different functional regions in the epitaxial layer through multiple ion implantation and diffusion, and uses multiple layers of metal to improve the adhesion between the metal film and the insulating film, thereby achieving higher component manufacturability and reliability and reducing costs. It can not only be used to reduce the manufacturing cost and improve the reliability of silicon-based semiconductor power components and integrated circuits, but can also be widely applied to reduce the manufacturing cost and improve the product quality of compound semiconductor power components and integrated circuits. In addition, the method has fewer process steps, saves working time, improves the adhesion of the refractory metal used as a protective conductive layer to the dielectric, and improves stability and reliability. In addition, the present invention reduces the key step that determines the cost of integrated circuit manufacturing, namely the photolithography step, by 40-50%, and will also significantly reduce the steps of the semiconductor process flow, thereby reducing the manufacturing cost of integrated circuits by nearly 50%, and improving the performance and reliability of components by adopting a simplified and reliable process design.

[0037] An embodiment of the present invention proposes a method in which, when a refractory metal layer is deposited on a gate oxide layer, the refractory metal layer is photolithographically processed and functional areas are defined at one time, wherein the functional areas include: a metal oxide semiconductor field effect transistor area, a capacitor area, a resistor area and a circuit connection area, and a silicon nitride film and a silicon oxide film are sequentially deposited on the functional areas and the refractory metal layer. After forming ohmic contact windows of different functional areas, the ohmic contact windows of the functional areas are photolithographically processed and etched, and silicide is formed on the corresponding silicon area on the functional areas, thereby depositing an ohmic contact metal layer on the silicide.

[0038] The working principle of the above technical solution is as follows: when depositing a refractory metal layer on the gate oxide layer, the refractory metal layer is photolithographically processed, and functional areas are defined at one time. A silicon nitride film and a silicon oxide film are sequentially deposited on the functional areas and the refractory metal layer. After forming ohmic contact windows for different functional areas, the ohmic contact windows for the functional areas are photolithographically processed and etched, and silicide is formed on the functional areas for the corresponding silicon areas, thereby depositing an ohmic contact metal layer on the silicide. The functional areas include: a metal oxide semiconductor field effect transistor area, a capacitor area, a resistor area, and a circuit connection area. The capacitor formed here is a metal oxide semiconductor capacitor, and the resistor is the resistor of the low-concentration semiconductor doping area. The value of the capacitor is determined by the thickness of the gate oxide layer and the area of ​​the capacitor, and the size of the resistor is determined by the doping concentration of the low-concentration semiconductor doping area and the shape of the resistor.

[0039] The beneficial effects of the above technical solution are as follows: the present invention is a new method based on the existing power integrated circuit component manufacturing process, in which different functional areas are formed in the epitaxial layer through photolithography and etching processes combined with component design through multiple ion implantation and diffusion, and multi-layer metal is used to improve the adhesion between the metal film and the insulating film, thereby achieving higher component manufacturability and reliability and reducing costs, and the process steps are few, saving working time, improving the adhesion between the refractory metal used as a protective conductive layer and the dielectric, and at the same time improving stability and reliability.

[0040] An embodiment of the present invention provides a method, which further includes: growing an epitaxial layer of a first type doped semiconductor with different concentrations on a silicon substrate of a second type doped semiconductor, and producing a gate oxide layer on the epitaxial layer; determining the doping concentration of the second type doped semiconductor in different functional areas of the epitaxial layer of the first type doped semiconductor according to the design of the components and the integrated circuit, performing photolithography and ion implantation on the gate oxide layer according to the doping concentration of the second type doped semiconductor in different functional areas, and defining second type doped semiconductor regions with different concentrations on the epitaxial layer of the first type doped semiconductor; forming the second type doped semiconductor by annealing. The low-concentration area and the high-concentration area of ​​the semiconductor region are formed into a gate pattern on the gate oxide layer by photolithography and etching; a refractory metal layer is deposited on the gate oxide layer, and ohmic contact windows of different functional areas are formed by photolithography and etching on the refractory metal layer; silicide is formed on the silicon substrate, an ohmic contact metal layer is deposited, and the ohmic contact metal layer is photolithographically and etched to form the components and circuit interconnection and circuit isolation of the high-power silicon integrated circuit, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; and the circuit is the design circuit of the high-power silicon integrated circuit.

[0041] The working principle of the above technical solution is as follows: the method for manufacturing a power integrated circuit further comprises: growing an epitaxial layer of a first type doped semiconductor with different concentrations on a silicon substrate of a second type doped semiconductor, and producing a gate oxide layer on the epitaxial layer; determining the doping concentration of the second type doped semiconductor in different functional areas of the epitaxial layer of the first type doped semiconductor according to the design of the components and the integrated circuit, performing photolithography and ion implantation on the gate oxide layer according to the doping concentration of the second type doped semiconductor in different functional areas, and defining second type doped semiconductor regions with different concentrations on the epitaxial layer of the first type doped semiconductor; forming the second type doped semiconductor regions by annealing. Low-concentration areas and high-concentration areas of the doped semiconductor region are formed into a gate pattern on the gate oxide layer by photolithography and etching; a refractory metal layer is deposited on the gate oxide layer, and photolithography and etching are performed on the refractory metal layer to form ohmic contact windows for different functional areas; silicide is formed on the silicon substrate, an ohmic contact metal layer is deposited, and the ohmic contact metal layer is photolithographically and etched to form component and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are metal oxide semiconductor field effect devices, input resistors, output resistors, load resistors and filter capacitors; and the circuit is the design circuit of the high-power silicon integrated circuit.

[0042] The beneficial effects of the above technical solution are as follows: the present invention is a new method based on the existing power integrated circuit component manufacturing process, in which different functional areas are formed in the epitaxial layer through photolithography and etching processes combined with component design through multiple ion implantation and diffusion, and multi-layer metal is used to improve the adhesion between the metal film and the insulating film, thereby achieving higher component manufacturability and reliability and reducing costs, and the process steps are few, saving working time, improving the adhesion between the refractory metal used as a protective conductive layer and the dielectric, and at the same time improving stability and reliability.

[0043] An embodiment of the present invention proposes a method, wherein the first type of doped semiconductor is a P-type semiconductor, and the second type of doped semiconductor is an N-type semiconductor. The P-type semiconductor is a hole-conducting semiconductor doped with acceptor impurities, and the N-type semiconductor is an electron-conducting semiconductor doped with donor impurities.

[0044] The working principle of the above technical solution is: the first type of doped semiconductor is a P-type semiconductor, and the second type of doped semiconductor is an N-type semiconductor. The P-type semiconductor is a hole-conducting semiconductor doped with acceptor impurities, and the N-type semiconductor is an electron-conducting semiconductor doped with donor impurities.

[0045] The specific process of the method for manufacturing a power integrated circuit is as follows:

[0046] A low-concentration P-type semiconductor epitaxial layer is grown on a silicon substrate of an N-type semiconductor, a gate oxide layer is grown on the low-concentration P-type semiconductor epitaxial layer, and a gate pattern is formed on the gate oxide layer by photolithography and etching, including: performing photolithography on the P-type semiconductor epitaxial layer, etching and ion implantation to define N-type semiconductor regions with different concentrations, and annealing to form a low-concentration region (N-) and a high-concentration region (N+) of the N-type semiconductor; depositing a refractory metal layer on the gate oxide layer, performing photolithography on the refractory metal layer, defining functional regions at one time, and forming a gate pattern on the functional regions. and sequentially depositing a silicon nitride film and a silicon oxide film on the refractory metal layer, photolithography and etching the ohmic contact window of the functional area, forming a silicide in the corresponding silicon area on the functional area, and depositing an ohmic contact metal layer on the silicide; photolithography and etching the ohmic contact metal layer to form components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; the circuit is the designed circuit of the high-power silicon integrated circuit; wherein, Figure 1 As shown, the functional areas include: a metal oxide semiconductor field effect transistor area, a capacitor area, a resistor area, a circuit connection area, and a circuit isolation area.

[0047] A low-concentration N-type semiconductor epitaxial layer is grown on a silicon substrate of a P-type semiconductor, a gate oxide layer is grown on the low-concentration N-type semiconductor epitaxial layer, and a gate pattern is formed on the gate oxide layer by photolithography and etching, including: performing photolithography on the N-type semiconductor epitaxial layer, etching and ion implantation to define P-type semiconductor regions with different concentrations, and annealing to form a low-concentration region (P-) and a high-concentration region (P+) of the P-type semiconductor; depositing a refractory metal layer on the gate oxide layer, performing photolithography on the refractory metal layer, defining functional regions at one time, and forming a gate pattern on the functional regions. and sequentially depositing a silicon nitride film and a silicon oxide film on the refractory metal layer, photolithography and etching the ohmic contact window of the functional area, forming a silicide in the corresponding silicon area on the functional area, and depositing an ohmic contact metal layer on the silicide; photolithography and etching the ohmic contact metal layer to form components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; the circuit is the designed circuit of the high-power silicon integrated circuit; wherein, Figure 2 As shown, the functional areas include: a metal oxide semiconductor field effect transistor area, a capacitor area, a resistor area, a circuit connection area, and a circuit isolation area.

[0048] The beneficial effects of the above technical solution are as follows: the present invention is a new method based on the existing power integrated circuit component manufacturing process, in which different functional areas are formed in the epitaxial layer through photolithography and etching processes combined with component design through multiple ion implantation and diffusion, and multi-layer metal is used to improve the adhesion between the metal film and the insulating film, thereby achieving higher component manufacturability and reliability and reducing costs, and the process steps are few, saving working time, improving the adhesion between the refractory metal used as a protective conductive layer and the dielectric, and at the same time improving stability and reliability.

[0049] An embodiment of the present invention provides a method for manufacturing the power integrated circuit, comprising:

[0050] For the P-type semiconductor, an epitaxial layer of an N-type semiconductor is sequentially grown on a silicon substrate of the P-type semiconductor, and a photoresist layer is coated on the epitaxial layer of the N-type semiconductor. According to the design of semiconductor components and integrated circuits, the acceptor doping concentrations of different functional regions of the epitaxial layer of the N-type semiconductor are determined. According to the acceptor doping concentrations of the different functional regions, photolithography and ion implantation are performed on the photoresist layer to define acceptor-doped semiconductor regions with different concentrations on the epitaxial layer of the N-type semiconductor. The photoresist is removed, and low-concentration regions and high-concentration regions of the acceptor-doped semiconductor are formed by annealing. A protective oxide layer is grown on the epitaxial layer of the N-type semiconductor, a silicon nitride layer is deposited on the oxide layer, and photolithography and etching are performed on a portion of the silicon nitride layer to form a localized oxide region. The silicon nitride and protective silicon oxide on the localized oxide layer are removed. A gate oxide layer is grown on a local silicon epitaxial layer of silicon nitride and protective silicon oxide, and a polysilicon layer is deposited on the gate oxide layer; a gate pattern is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, and silicon oxide and silicon nitride are sequentially deposited on the gate oxide layer and the polysilicon layer formed after etching, a gate region side protection structure is formed on the gate oxide layer by photolithography and etching, a polysilicon resistor is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, a silicon nitride film and a capacitor bottom metal are deposited, the capacitor bottom metal is photolithographically and etched, a capacitor dielectric layer is deposited on the capacitor bottom metal, a capacitor dielectric region is defined by photolithography and etching, an ohmic contact and a capacitor top metal layer are deposited, and the ohmic contact and the capacitor top metal layer are photolithographically and etched, thereby forming component and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein, as Figure 3 As shown, the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; the circuit is the design circuit of the high-power silicon integrated circuit;

[0051] For the N-type semiconductor, an epitaxial layer of a P-type semiconductor is sequentially grown on a silicon substrate of the N-type semiconductor, and a photoresist layer is coated on the epitaxial layer of the P-type semiconductor; according to the design of components and integrated circuits, the donor doping concentrations of different functional areas of the P-type semiconductor epitaxial layer are determined, photolithography and ion implantation are performed on the photoresist layer according to the donor doping concentrations of the different functional areas, and donor-doped semiconductor regions with different concentrations are defined on the P-type semiconductor epitaxial layer; the photoresist is removed, low-concentration regions and high-concentration regions of the donor-doped semiconductor are formed by annealing, a protective oxide layer is grown on the P-type semiconductor epitaxial layer, a silicon nitride layer is deposited on the oxide layer, photolithography and etching are performed on a portion of the silicon nitride layer to form a localized oxide region, the silicon nitride and protective silicon oxide on the localized oxide layer are removed, and after removing the nitride A gate oxide layer is grown on a local silicon epitaxial layer of silicon and protective silicon oxide, and a polysilicon layer is deposited on the gate oxide layer; a gate pattern is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, and silicon oxide and silicon nitride are sequentially deposited on the gate oxide layer and the polysilicon layer formed after etching, a gate region side protection structure is formed on the gate oxide layer by photolithography and etching, a polysilicon resistor is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, a capacitor bottom metal is deposited, the capacitor bottom metal is photolithographically and etched, a capacitor dielectric layer is deposited on the capacitor bottom metal, photolithography and etching are performed to define a capacitor dielectric region, an ohmic contact and a capacitor top metal layer are deposited, and the ohmic contact and the capacitor top metal layer are photolithographically and etched to form component and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein, as Figure 4 As shown, the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; Figure 5 The circuit shown is the design circuit of the high-power silicon integrated circuit.

[0052] The working principle of the above technical solution is as follows: for a P-type semiconductor, an epitaxial layer of an N-type semiconductor is sequentially grown on a silicon substrate of a P-type semiconductor, an epitaxial layer of an N-type semiconductor is sequentially grown on a silicon substrate of a P-type semiconductor, and a photoresist layer is coated on the N-type epitaxial layer; according to the design of components and integrated circuits, the acceptor doping concentration of different functional areas of the epitaxial layer of the N-type semiconductor is determined, and photolithography and ion implantation are performed on the photoresist layer according to the acceptor doping concentration of the different functional areas to define acceptor-doped semiconductor regions with different concentrations; the photoresist is removed, and the acceptor impurities are activated by annealing to form low-concentration and high-concentration regions of the acceptor-doped semiconductor (P-type semiconductor) in the epitaxial layer of the N-type semiconductor; a protective oxide layer is grown on the epitaxial layer of the N-type semiconductor; a silicon nitride layer is deposited on the oxide layer; photolithography and etching are performed on the partially oxidized area on the silicon nitride layer to form a localized oxide region; the silicon nitride and protective silicon oxide on the localized oxide layer are removed; and a gate oxide layer is grown on the local silicon epitaxial layer from which the silicon nitride and protective silicon oxide have been removed. , depositing a polysilicon layer on the gate oxide layer; forming a gate pattern on the gate oxide layer and the polysilicon layer by photolithography and etching, and sequentially depositing silicon oxide and silicon nitride on the gate oxide layer and the polysilicon layer formed after etching; forming a gate region side protection structure on the gate oxide layer by photolithography and etching; depositing a polysilicon resistor, a silicon nitride film and a capacitor bottom metal on the gate oxide layer and the polysilicon layer by photolithography and etching; photolithography and etching the capacitor bottom metal; depositing a capacitor dielectric layer on the capacitor layer metal; defining the capacitor dielectric region and performing photolithography and etching; depositing an ohmic contact and a capacitor top metal layer; photolithography and etching the ohmic contact and the capacitor top metal layer to form components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are metal oxide semiconductor field effect devices, input resistors, output resistors, load resistors and filter capacitors; the resistors are polysilicon resistors, the filter capacitors are metal dielectric metal (MIM) capacitors, and the circuit is the design circuit of the high-power silicon integrated circuit.

[0053] For N-type semiconductors, an epitaxial layer of P-type semiconductor is grown on the silicon substrate of N-type semiconductor in sequence, and a photoresist layer is coated on the P-type epitaxial layer; according to the design of components and integrated circuits, the donor doping concentration of different functional areas of the epitaxial layer of P-type semiconductor is determined, and according to the donor doping concentration of different functional areas, photolithography and ion implantation are performed on the photoresist layer to define donor-doped semiconductor areas with different concentrations; the photoresist is removed, and the donor impurities are activated by annealing to form a donor-doped semiconductor (N-type semiconductor) in the epitaxial layer of P-type semiconductor. A low concentration region (N-) and a high concentration region (N+) of a P-type semiconductor) are formed, a protective oxide layer is grown on the P-type semiconductor epitaxial layer, a silicon nitride layer is deposited on the oxide layer, photolithography and etching are performed on a portion of the silicon nitride layer to form a local oxide region, the silicon nitride and protective silicon oxide on the local oxide layer are removed, a gate oxide layer is grown on the local silicon epitaxial layer from which the silicon nitride and protective silicon oxide are removed, and a polysilicon layer is deposited on the gate oxide layer; a gate pattern is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, and after etching, Silicon oxide and silicon nitride are sequentially deposited on the formed gate oxide layer and polysilicon layer topology. A gate region side protection structure is formed on the gate oxide layer by photolithography and etching. A polysilicon resistor is formed on the gate oxide layer and polysilicon layer by photolithography and etching (the polysilicon resistor can also be formed simultaneously when the gate pattern is formed by simply changing the photolithography mask of the gate pattern). A silicon nitride film and a capacitor bottom metal are deposited. The capacitor bottom metal is photolithographically and etched. A capacitor dielectric layer is deposited on the capacitor bottom metal. Photolithography and etching are performed to define the capacitor dielectric region. An ohmic contact and a capacitor top metal layer are deposited. The ohmic contact and the capacitor top metal layer are the same metal layer. The ohmic contact and the capacitor top metal layer are photolithographically and etched. Components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit are formed. The components are metal oxide semiconductor field effect devices, input resistors, output resistors, load resistors, and filter capacitors. The resistors are polysilicon resistors. The filter capacitors are metal dielectric metal (MIM) capacitors. The circuit is the designed circuit of the high-power silicon integrated circuit.

[0054] The beneficial effects of the above technical solution are as follows: the present invention combines the design of components and integrated circuits, forms functional areas with different doping concentrations in the epitaxial layer through photolithography, etching and ion implantation, forms a gate pattern through photolithography and etching, forms a gate area side protection structure on the gate oxide layer through photolithography and etching, and defines the capacitor dielectric and resistor areas through photolithography and etching. Moreover, only the photolithography mask of the gate pattern needs to be changed, and the polysilicon resistor can also be formed at the same time as the gate pattern is formed, thereby accurately controlling the shape and size of the formed pattern. In addition, the outer contour can be generated at the same time, thereby achieving higher photolithography resolution. By closely integrating the device with integrated circuit design and semiconductor technology, especially with photolithography, ion etching and ion implantation processes, the number of photolithography and etching can be greatly reduced, the process flow can be greatly simplified, and the device performance and reliability can be improved. At the same time, for product manufacturing, the production efficiency is significantly improved, the working time is shortened, and the cost is saved. The photolithography process is simple, the error rate is reduced, and the product yield is improved. The etching has good anisotropy, high selectivity, good controllability, flexibility, and repeatability, and the fine line operation is safe and easy to automate. There is no chemical waste liquid, and the treatment process does not introduce pollution, with high cleanliness.

[0055] An embodiment of the present invention provides a method for photolithography, wherein a pre-made photomask is placed on a wafer coated with photoresist, and then ultraviolet light or a light source of other wavelengths is used to irradiate the wafer through the photomask for a certain period of time according to the requirements of component and integrated circuit design, including:

[0056] S1. Depositing a material for engraving a circuit on a wafer to form a thin film, and depositing a photoresist on the thin film;

[0057] S2. performing photolithography on the wafer by irradiating light according to the circuit design of the mask. When the photolithography process uses positive photoresist, the photoresist exposed to light is removed. When the photolithography process uses negative photoresist, the photoresist exposed to light is retained, and the material to be etched is exposed to the outside of the photoresist not retained.

[0058] S3, removing the exposed etched material by etching, leaving the material required for the wafer and the photoresist attached thereto, and then removing the photoresist by chemical treatment;

[0059] S4. Repeat steps S1 to S3 multiple times until a high-power integrated circuit with a complex structure is obtained.

[0060] The working principle of the above technical solution is as follows: during the photolithography process, a pre-made photomask is placed on a wafer coated with photoresist. Then, according to the needs of the components and integrated circuit design, ultraviolet light or a light source of other wavelengths is used to irradiate the wafer through the photomask for a certain period of time. Specifically, the photolithography steps are as follows: S1. The material used to engrave the circuit is deposited on the wafer to form a thin film, and photoresist is deposited on the thin film; S2. According to the circuit design diagram of the mask, the wafer is photolithographically exposed to light. If the photolithography process uses positive photoresist, the exposed photoresist is removed. If the photolithography process uses negative photoresist, the exposed photoresist is retained, and the material required for etching is exposed to the outside of the photoresist that is not retained;

[0061] S3. Use etching to remove the exposed etched material, leaving the material required for the wafer and the photoresist attached to it, and then remove the photoresist through chemical treatment; S4. Repeat steps S1-S3 multiple times until a complex high-power integrated circuit is obtained.

[0062] The beneficial effects of the above technical solution are as follows: the present invention forms an integrated circuit by applying photoresist, developing, exposing, and etching to remove the photoresist, and finally repeating the above process, thereby accurately controlling the shape and size of the formed graphics. In addition, the outer contour can be generated at the same time, thereby achieving higher photolithography resolution, and at the same time improving the production efficiency of the product, shortening the working time, saving costs, and simplifying the photolithography process, reducing the error rate, and improving the product yield; at the same time, the present invention has good controllability, flexibility, and repeatability, and is safe to operate fine lines, easy to automate, free of chemical waste liquid, and no pollution is introduced during the treatment process. The cleanliness is high, thereby ensuring the product qualification rate.

[0063] The embodiment of the present invention proposes a method, wherein the etching includes dry etching and wet etching, which removes the exposed portion of the underlying material in the photoresist micro-pattern after exposure and development, that is, reproduces the same pattern as the photoresist on the underlying material.

[0064] The working principle of the above-mentioned technical solution is as follows: Etching includes dry etching and wet etching. During etching, the exposed portion of the underlying material in the exposed and developed photoresist micropattern is removed, that is, the same pattern as the photoresist is reproduced on the underlying material. Dry etching is a plasma-based thin film etching technology, generally using particles generated by the plasma to bombard the etched area. Dry etching is an anisotropic etching technology, that is, the etching rate varies in different directions within the etched area. Wet etching is a technology that immerses the etched material in an etching solution and is an isotropic etching method, which uses a chemical reaction process to remove the thin film material in the etched area.

[0065] The beneficial effects of the above technical solution are: by removing the exposed part of the underlying material in the photoresist micro-pattern after exposure and development, and then reproducing the same pattern as the photoresist on the underlying material, it has high repeatability, high selectivity, good uniformity and less damage to the silicon wafer, and improves the automation capability and reduces material consumption, making the cost lower. At the same time, it can achieve anisotropic etching, that is, the longitudinal etching rate is much greater than the lateral etching rate, ensuring the high fidelity of the small pattern after transfer, improving the resolution of the pattern, saving time and improving work efficiency.

[0066] The embodiment of the present invention provides a method, wherein in the high-power silicon integrated circuit, an epitaxial layer of a P-type semiconductor with a resistivity of 8 ohm.cm is grown on a silicon substrate of the N-type semiconductor; the thermal oxidation temperature is 1050°C; the thickness of the gate oxide layer is 0.1 micron; the energy of the photolithography and phosphorus ion implantation of a low-concentration doped semiconductor on the N-type semiconductor is 120 KeV, and the dose is 5×10 13 / cm 3 The energy of the photolithography and phosphorus ion implantation into the high concentration doped semiconductor on the N-type semiconductor is 150 KeV and the dose is 3×10 15 / cm 3 ; Annealing temperature is: 1020℃; Silicon nitride film is: 700 angstroms thick.

[0067] The working principle of the above technical solution is as follows: after chemically cleaning the silicon substrate of the N-type semiconductor, a 3-micron thick epitaxial layer of the P-type semiconductor (P-epitaxial layer) with a resistivity of 8 ohm.cm is grown. Then, a 0.1-micron thick gate silicon oxide layer is formed on the P-epitaxial layer by thermal oxidation at 1050°C for 30 minutes in a dry oxygen and wet oxygen environment. Then, photolithography, ion etching, and phosphorus ion implantation are performed on the gate oxide layer to define a low-concentration N-type semiconductor region. The phosphorus ion implantation energy is 120 KeV and the dose is 5×10 13 / cm 3 , photolithography, ion etching and phosphorus ion implantation are performed on the gate oxide layer to define a high-concentration N-type semiconductor region. The phosphorus ion implantation energy is 150 KeV and the dose is 3×10 15 / cm 3 Both high-concentration and low-concentration phosphorus ion implantation are achieved by penetrating the oxide layer through the photoresist window defined by lithography. The gate oxide layer thickness can be adjusted according to the design performance requirements of high-power integrated circuits, with an adjustment range of 0.02 to 0.3 microns. For the low-concentration N-type semiconductor region on the P-epitaxial layer, the phosphorus ion implantation energy and dose can be adjusted according to the design performance requirements of the component, with an energy adjustment range of 80 to 150 KeV and a dose adjustment range of 3×10 13 -2×10 14 cm3 For the high-concentration N-type semiconductor region on the P-epitaxial layer, the energy and dose of phosphorus ion implantation can be adjusted according to the needs of device design performance. The energy adjustment range is 120 to 1000 KeV, and the dose adjustment range is: 1×10 15 -7×10 15 cm 3 .

[0068] A low-concentration N-type semiconductor region and a high-concentration N-type semiconductor region are formed on the P-epitaxial layer by rapid annealing at a maximum temperature of 1020°C. Utilizing the good adhesion properties of metal molybdenum and silicon oxide, a plasma-enhanced radio frequency sputtering process is used to deposit 500 angstroms of N-type semiconductor. The thickness of the molybdenum metal layer is 1000 angstroms. The molybdenum metal layer is used for photolithography and ion etching to define the metal oxide semiconductor field effect transistor, capacitor, circuit interconnection and circuit isolation and other functional areas. The plasma enhanced chemical vapor deposition process is used to deposit 700 angstroms. The silicon nitride film is then deposited with a thickness of 1.2 microns using the plasma enhanced chemical vapor deposition process, and a tetraethyl orthosilicate silicon oxide film is planarized using chemical mechanical polishing. The ohmic contact windows of each functional area are photoetched and etched, and a 350 angstrom thick silicon nitride film is deposited using the plasma enhanced radio frequency sputtering process. A thick molybdenum metal layer is formed in the corresponding silicon area by a two-step rapid annealing method. The first step is a rapid annealing in nitrogen at a temperature of 850°C for 30 seconds, and the second step is a rapid annealing in nitrogen at a temperature of 950°C for 180 seconds. The plasma-enhanced RF sputtering process is used to deposit 350 angstroms of A titanium nitride metal layer with a thickness of 100 microns and an aluminum metal layer with a thickness of 1.2 microns doped with 0.5 percent copper are used to form ohmic contacts and metal interconnection metal layers. The ohmic contacts and metal interconnection metal layers are photolithographically and etched to complete the components and circuit interconnection and circuit isolation of high-power silicon integrated circuits.

[0069] Similarly, the above method can also be used to design and manufacture high-power P-channel metal oxide semiconductor field effect integrated circuits. For manufacturing high-power P-channel metal oxide semiconductor field effect integrated circuits, the embodiment of the present invention proposes a method for growing an N-type semiconductor epitaxial layer (N-epitaxial layer) with a resistivity of 7 ohm.cm on a P-type semiconductor silicon substrate; the thermal oxidation temperature is: 1080°C; the thickness of the gate silicon oxide layer is: 0.1 micron; the energy of the photolithography and boron ion implantation of the low-concentration doped semiconductor on the P-type semiconductor is: 100 KeV, and the dose is: 3×10 13 / cm 3 The energy of photolithography and boron ion implantation for high-concentration doped semiconductors on P-type semiconductors is 120 KeV and the dose is 5×10 15 / cm 3The annealing temperature is 1000°C, and the silicon nitride film is 700 angstroms thick. The gate oxide layer thickness can be adjusted to meet the design performance requirements of high-power integrated circuits, with an adjustment range of 0.02 to 0.3 microns. The boron ion implantation energy and dose in low-concentration doped semiconductors on P-type semiconductors can be adjusted to meet the design performance requirements of the components, with an energy adjustment range of 80 to 150 KeV and a dose adjustment range of 3×10 13 -2×10 14 cm 3 In high-concentration doped semiconductors on P-type semiconductors, the energy and dose of boron ion implantation can be adjusted according to the needs of device design performance. The energy adjustment range is 120 to 1000 KeV, and the dose adjustment range is: 1×10 15 -7×10 15 cm 3 .

[0070] A low-concentration P-type semiconductor region and a high-concentration P-type semiconductor region are formed on the N-epitaxial layer by rapid annealing at a maximum temperature of 1020°C. Utilizing the good adhesion properties of metal molybdenum and silicon oxide, a plasma-enhanced radio frequency sputtering process is used to deposit 500 angstroms. The thickness of the molybdenum metal layer is 1000 angstroms. The molybdenum metal layer is used for photolithography and ion etching to define the metal oxide semiconductor field effect transistor, capacitor, circuit interconnection and circuit isolation and other functional areas. The plasma enhanced chemical vapor deposition process is used to deposit 700 angstroms. The silicon nitride film is then deposited with a thickness of 1.2 microns using the plasma enhanced chemical vapor deposition process, and a tetraethyl orthosilicate silicon oxide film is planarized using chemical mechanical polishing. The ohmic contact windows of each functional area are photoetched and etched, and a 350 angstrom thick silicon nitride film is deposited using the plasma enhanced radio frequency sputtering process. A thick molybdenum metal layer is formed in the corresponding silicon area by a two-step rapid annealing method. The first step is a rapid annealing in nitrogen at a temperature of 850°C for 30 seconds, and the second step is a rapid annealing in nitrogen at a temperature of 950°C for 180 seconds. The plasma-enhanced RF sputtering process is used to deposit 350 angstroms of A titanium nitride metal layer with a thickness of 100 microns and an aluminum metal layer with a thickness of 1.2 microns doped with 0.5 percent copper are used to form ohmic contacts and metal interconnection metal layers. The ohmic contacts and metal interconnection metal layers are photolithographically and etched to complete the components and circuit interconnection and circuit isolation of high-power silicon integrated circuits.

[0071] The beneficial effects of the above technical solution are as follows: by adopting the process flow layer of the present invention for designing and manufacturing high-power integrated circuits, the components required for the integrated circuit, input resistors, output resistors, load resistors, and filter capacitors can be manufactured with relatively few photolithography and etching processes and simplified and reliable process steps to achieve the required circuit functions. The size of the resistor is controlled by controlling the shape, area, doping concentration and annealing temperature of the resistor element. A plurality of integrated circuit functional regions are formed by one-time photolithography and annealing of a high-concentration doped semiconductor region. The depth and width of the high-concentration doped semiconductor and the electrical characteristics of the corresponding components are controlled by controlling the doping concentration and annealing temperature of the concentration-doped semiconductor region. The metal interconnect reliability of the power integrated circuit is enhanced by using a transition metal layer. According to the needs of the high-power integrated circuit design, the method of the present invention can be used to manufacture semiconductor components and integrated circuits on a first-type semiconductor substrate and a second-type semiconductor epitaxial layer structure, or on a second-type semiconductor substrate and a first-type semiconductor epitaxial layer structure.

[0072] An embodiment of the present invention provides a method, wherein the annealing includes: a first annealing stage, a second annealing stage, and a third annealing stage; wherein the maximum annealing temperature of the first annealing stage is 850°C, the maximum annealing temperature of the second annealing stage is 950°C, and the maximum annealing temperature of the third annealing stage is 1020°C; and, in the first annealing stage, the maximum annealing temperature is set to: a=850°C, and the annealing time is 30 seconds; in the second annealing stage, the annealing time is 180 seconds, and the annealing temperature satisfies the following formula and the maximum value shall not exceed 950°C;

[0073]

[0074] In the above formula, T a1 is the second stage annealing temperature, S 11 is the photolithography temperature from the first stage to the second stage, S 21 is the ion implantation temperature from the first stage to the second stage, S 31 is the vacuum environment temperature from the first stage to the second stage, S 41 is the low concentration semiconductor temperature from the first stage to the second stage, S 51 The high-concentration semiconductor temperature from the first stage to the second stage;

[0075] In the third stage of the annealing, the annealing time is 1000 seconds, the annealing temperature satisfies the following formula and the maximum value shall not exceed 1020° C.;

[0076]

[0077] In the above formula, T a2 is the third stage annealing temperature, S12 is the photolithography temperature from the second stage to the third stage, S 22 is the ion implantation temperature from the second stage to the third stage, S 32 is the vacuum environment temperature from the second stage to the third stage, S 42 is the low concentration semiconductor temperature from the second stage to the third stage, S 52 It is the high concentration semiconductor temperature from the second stage to the third stage.

[0078] The working principle of the above technical solution is as follows: the annealing includes: complete annealing, incomplete annealing, stress relief annealing, diffusion annealing, spheroidizing annealing and recrystallization annealing; according to the heating temperature, it is divided into: phase change recrystallization annealing above the critical temperature and annealing below the critical temperature; phase change recrystallization annealing above the critical temperature includes: complete annealing, diffusion annealing, incomplete annealing and spheroidizing annealing; annealing below the critical temperature includes: recrystallization annealing and stress relief annealing; the annealing process is divided into the first annealing stage, the second annealing stage and the third annealing stage; in the first annealing stage, the maximum annealing temperature is 850°C, in the second annealing stage, the maximum annealing temperature is 950°C, and in the third annealing stage, the maximum annealing temperature is 1020°C; and, in the first stage of annealing, the maximum annealing temperature is set to: a=850°C, and the annealing time is 30 seconds; in the second stage of annealing, the annealing time is 180 seconds, the annealing temperature satisfies the following formula and the maximum value shall not exceed 950°C;

[0079]

[0080] In the above formula, T a1 is the second stage annealing temperature, S 11 is the photolithography temperature from the first stage to the second stage, S 21 is the ion implantation temperature from the first stage to the second stage, S 31 is the vacuum environment temperature from the first stage to the second stage, S 41 is the low concentration semiconductor temperature from the first stage to the second stage, S 51 The high-concentration semiconductor temperature from the first stage to the second stage;

[0081] In the third stage of annealing, the annealing time is 1000 seconds, the annealing temperature satisfies the following formula and the maximum value shall not exceed 1020°C;

[0082]

[0083] In the above formula, T a2 is the third stage annealing temperature, S 12 is the photolithography temperature from the second stage to the third stage, S 22 is the ion implantation temperature from the second stage to the third stage, S32 is the vacuum environment temperature from the second stage to the third stage, S 42 is the low concentration semiconductor temperature from the second stage to the third stage, S 52 The high-concentration semiconductor temperature from the second stage to the third stage;

[0084] In particular, the photolithography temperature is the substrate temperature during the photolithography process, the ion implantation temperature is the wafer temperature during the ion implantation process, the low-concentration semiconductor temperature is the temperature of the low-concentration semiconductor region during the process, and the high-concentration semiconductor temperature is the temperature of the low-concentration semiconductor region during the process.

[0085] The beneficial effects of the above technical solution are as follows: the annealing stage at different temperatures adopted by the present invention controls the size of the resistance by controlling different photolithography temperatures, ion implantation temperatures, vacuum environment temperatures and temperatures of semiconductors with different concentrations, thereby forming the low-concentration and high-concentration regions of the doped semiconductor. The annealing stage simplifies the calculation process and has high accuracy, saving working time. Without affecting the construction period, the annealing stage improves the working efficiency of the manufacturing of the power integrated circuit, further optimizes the working steps, improves accuracy, and also improves the yield of the product, reduces costs, and improves product quality.

[0086] An embodiment of the present invention provides a method, wherein the ohmic contact metal layer includes: a metal layer, an interface between the metal and the semiconductor, and a semiconductor junction; the ohmic contact metal layer is formed by: ion implantation and epitaxy, wherein the ion implantation generates positively charged impurity ions from a source material, imparts sufficient energy to the impurity ions through acceleration by an electric field, obtains impurity ions with sufficient energy, allows the impurity ions with sufficient energy to enter a target crystal lattice, and activates the impurity ions with sufficient energy through thermal annealing, thereby achieving impurity doping of the substrate material;

[0087] Epitaxy is the process of growing a single crystal layer on a substrate, which is divided into solid phase epitaxy, vapor phase epitaxy and liquid phase epitaxy.

[0088] The working principle of the above technical solution is: the ohmic contact metal layer includes: a metal layer, an interface between the metal and the semiconductor, and a semiconductor junction, and the ohmic contact metal layer must be subjected to ion implantation and epitaxy during its formation, wherein ion implantation is to generate positively charged impurity ions from the source material, and to give the impurity ions sufficient energy through acceleration by an electric field to obtain impurity ions with sufficient energy, so that the impurity ions with sufficient energy enter the target crystal lattice, and are activated by thermal annealing to achieve impurity doping of the substrate material; epitaxy is divided into solid phase epitaxy, vapor phase epitaxy, and liquid phase epitaxy, which is to grow a single crystal layer on a substrate.

[0089] The beneficial effects of the above technical solution are as follows: the present invention is a new method based on the existing power integrated circuit component manufacturing process. In this method, different functional areas are formed in the epitaxial layer through multiple ion implantation and diffusion processes combined with component design, and multiple layers of metal are used to improve the adhesion between the metal film and the insulating film, thereby achieving higher component manufacturability and reliability and reducing costs. In addition, the process steps are reduced, which saves working time, and the adhesion between the refractory metal used as a protective conductive layer and the dielectric is improved, while also improving stability and reliability.

[0090] The process of the present invention can reduce the key step that determines the cost of integrated circuit production, namely the photolithography step, by 40-50%. It will also significantly reduce the steps of the semiconductor process flow, thereby reducing the manufacturing cost of integrated circuits by nearly 50%, and improve the performance and reliability of components by adopting a simplified and reliable process design.

[0091] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A method for manufacturing a power integrated circuit, characterized in that: The method for manufacturing a power integrated circuit includes: growing an epitaxial layer of a second type of doped semiconductor with different concentrations on a silicon substrate of a first type of doped semiconductor, and producing a gate oxide layer on the epitaxial layer; determining the doping concentration of the first type of doped semiconductor in different functional areas of the epitaxial layer of the second type of doped semiconductor according to the design of the components and the integrated circuit; performing photolithography and ion implantation on the gate oxide layer according to the doping concentration of the first type of doped semiconductor in different functional areas, and defining first type of doped semiconductor regions with different concentrations on the epitaxial layer of the second type of doped semiconductor; forming a low concentration of the first type of doped semiconductor region by annealing. region and a high-concentration region, forming a gate pattern on the gate oxide layer by photolithography and etching; depositing a refractory metal layer on the gate oxide layer, and performing photolithography and etching on the refractory metal layer to form ohmic contact windows of different functional regions; forming silicide on the silicon substrate, depositing an ohmic contact metal layer, and photolithography and etching the ohmic contact metal layer to form components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; and the circuit is the designed circuit of the high-power silicon integrated circuit; When depositing a refractory metal layer on the gate oxide layer, the refractory metal layer is photolithographically processed, and functional areas are defined at one time. The functional areas include: a metal oxide semiconductor field effect transistor area, a capacitor area, a resistor area, and a circuit connection area. Silicon nitride film and silicon oxide film are sequentially deposited on the functional areas and the refractory metal layer. After forming ohmic contact windows of different functional areas, the ohmic contact windows of the functional areas are photolithographically processed and etched, and silicide is formed on the functional areas for the corresponding silicon areas, thereby depositing an ohmic contact metal layer on the silicide.

2. The method for manufacturing a power integrated circuit according to claim 1, wherein: The first type of doped semiconductor is a P-type semiconductor, and the second type of doped semiconductor is an N-type semiconductor. The P-type semiconductor is a hole-conducting semiconductor doped with acceptor impurities, and the N-type semiconductor is an electron-conducting semiconductor doped with donor impurities.

3. The method for manufacturing a power integrated circuit according to claim 2, wherein: The power integrated circuit, when manufactured, includes: For the P-type semiconductor, an epitaxial layer of an N-type semiconductor is sequentially grown on a silicon substrate of the P-type semiconductor, and a photoresist layer is coated on the epitaxial layer of the N-type semiconductor. According to the design of semiconductor components and integrated circuits, the acceptor doping concentrations of different functional regions of the epitaxial layer of the N-type semiconductor are determined. Photolithography and ion implantation are performed on the photoresist layer according to the acceptor doping concentrations of the different functional regions, and acceptor-doped semiconductor regions with different concentrations are defined on the epitaxial layer of the N-type semiconductor. The photoresist is removed, and low-concentration regions and high-concentration regions of the acceptor-doped semiconductor are formed by annealing. A protective oxide layer is grown on the epitaxial layer of the N-type semiconductor, a silicon nitride layer is deposited on the oxide layer, and photolithography and etching are performed on a portion of the silicon nitride layer to form a localized oxide region. The silicon nitride and protective silicon oxide on the localized oxide layer are removed, and a gate oxide layer is grown on the localized silicon epitaxial layer from which the silicon nitride and protective silicon oxide have been removed. A polysilicon layer is deposited on the gate oxide layer; a gate pattern is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, and silicon oxide and silicon nitride are sequentially deposited on the gate oxide layer and the polysilicon layer formed after etching, a gate region side protection structure is formed on the gate oxide layer by photolithography and etching, a polysilicon resistor is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, a silicon nitride film and a capacitor bottom metal are deposited, the capacitor bottom metal is photolithographically and etched, a capacitor dielectric layer is deposited on the capacitor bottom metal, a capacitor dielectric region is defined by photolithography and etching, an ohmic contact and a capacitor top metal layer are deposited, and the ohmic contact and the capacitor top metal layer are photolithographically and etched, thereby forming components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; and the circuit is the designed circuit of the high-power silicon integrated circuit.

4. The method for manufacturing a power integrated circuit according to claim 1, wherein: The first type of doped semiconductor is an N-type semiconductor, and the second type of doped semiconductor is a P-type semiconductor.

5. The method for manufacturing a power integrated circuit according to claim 4, wherein: The power integrated circuit, when manufactured, includes: For the N-type semiconductor, an epitaxial layer of a P-type semiconductor is sequentially grown on a silicon substrate of the N-type semiconductor, and a photoresist layer is coated on the epitaxial layer of the P-type semiconductor; according to the design of components and integrated circuits, the donor doping concentrations of different functional areas of the P-type semiconductor epitaxial layer are determined, photolithography and ion implantation are performed on the photoresist layer according to the donor doping concentrations of the different functional areas, and donor-doped semiconductor regions with different concentrations are defined on the P-type semiconductor epitaxial layer; the photoresist is removed, low-concentration regions and high-concentration regions of the donor-doped semiconductor are formed by annealing, a protective oxide layer is grown on the P-type semiconductor epitaxial layer, a silicon nitride layer is deposited on the oxide layer, photolithography and etching are performed on a portion of the silicon nitride layer to form a local oxide region, the silicon nitride and protective silicon oxide on the local oxide layer are removed, a gate oxide layer is grown on the local silicon epitaxial layer from which the silicon nitride and protective silicon oxide are removed, and a gate oxide layer is deposited on the gate oxide layer. A polysilicon layer is deposited on the gate oxide layer; a gate pattern is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, and silicon oxide and silicon nitride are sequentially deposited on the gate oxide layer and the polysilicon layer formed after etching, a gate region side protection structure is formed on the gate oxide layer by photolithography and etching, a polysilicon resistor is formed on the gate oxide layer and the polysilicon layer by photolithography and etching, a capacitor bottom metal is deposited, the capacitor bottom metal is photolithographically and etched, a capacitor dielectric layer is deposited on the capacitor bottom metal, a capacitor dielectric region is defined by photolithography and etching, an ohmic contact and a capacitor top metal layer are deposited, the ohmic contact and the capacitor top metal layer are photolithographically and etched, and components and circuit interconnection and circuit isolation of a high-power silicon integrated circuit are formed, wherein the components are the metal oxide semiconductor field effect device, input resistor, output resistor, load resistor and filter capacitor; and the circuit is the designed circuit of the high-power silicon integrated circuit.

6. The method for manufacturing a power integrated circuit according to claim 1, wherein: The photolithography process involves placing a pre-made photomask on a wafer coated with photoresist, and then irradiating the wafer with ultraviolet light or other wavelengths of light through the photomask for a certain period of time according to the needs of component and integrated circuit design. The process includes: S1. Depositing a material for engraving a circuit on a wafer to form a thin film, and depositing a photoresist on the thin film; S2. performing photolithography on the wafer by irradiating light according to the circuit design of the mask. When the photolithography process uses positive photoresist, the photoresist exposed to light is removed. When the photolithography process uses negative photoresist, the photoresist exposed to light is retained, and the material to be etched is exposed to the outside of the photoresist not retained. S3, removing the exposed etched material by etching, leaving the material required for the wafer and the photoresist attached thereto, and then removing the photoresist by chemical treatment; S4. Repeat steps S1 to S3 multiple times until a high-power integrated circuit with a complex structure is obtained.

7. The method for manufacturing a power integrated circuit according to claim 1, wherein: The etching includes dry etching and wet etching, which removes the exposed part of the lower layer material in the photoresist micro-pattern after exposure and development, that is, reproduces the same pattern as the photoresist on the lower layer material.

8. The method for manufacturing a power integrated circuit according to claim 2, wherein: In the high-power silicon integrated circuit, an epitaxial layer of a P-type semiconductor with a resistivity of 8 ohm.cm is grown on the silicon substrate of the N-type semiconductor; the thermal oxidation temperature is 1050°C; the thickness of the gate oxide layer is 0.1 micron; the energy of the photolithography and phosphorus ion implantation of the low-concentration doped semiconductor on the N-type semiconductor is 120 KeV, and the dose is 5×10 13 / cm 3 The energy of the photolithography and phosphorus ion implantation into the high concentration doped semiconductor on the N-type semiconductor is 150 KeV and the dose is 3×10 15 / cm 3 ; Annealing temperature is: 1020℃; Silicon nitride film is: 700 angstroms thick.

9. The method for manufacturing a power integrated circuit according to claim 1, wherein: The annealing includes: a first annealing stage, a second annealing stage and a third annealing stage; wherein the maximum annealing temperature of the first annealing stage is 850° C., the maximum annealing temperature of the second annealing stage is 950° C., and the maximum annealing temperature of the third annealing stage is 1020° C.; and, in the first annealing stage, the maximum annealing temperature is set to: , the annealing time is 30 seconds; in the second stage of the annealing, the annealing time is 180 seconds, the annealing temperature satisfies the following formula and the maximum value shall not exceed 950°C; In the above formula, is the second stage annealing temperature, is the photolithography temperature from the first stage to the second stage, is the ion implantation temperature from the first stage to the second stage, is the vacuum environment temperature from the first stage to the second stage, is the low concentration semiconductor temperature from the first stage to the second stage, The high-concentration semiconductor temperature from the first stage to the second stage; In the third stage of the annealing, the annealing time is 1000 seconds, the annealing temperature satisfies the following formula and the maximum value shall not exceed 1020° C.; In the above formula, is the third stage annealing temperature, is the photolithography temperature from the second stage to the third stage, is the ion implantation temperature from the second stage to the third stage, is the vacuum environment temperature from the second stage to the third stage, is the low concentration semiconductor temperature from the second stage to the third stage, It is the high concentration semiconductor temperature from the second stage to the third stage.

10. The method for manufacturing a power integrated circuit according to claim 1, wherein: The ohmic contact metal layer includes: a metal layer, an interface between the metal and the semiconductor, and a semiconductor junction; the ohmic contact metal layer includes: ion implantation and epitaxy during its formation, wherein the ion implantation is to generate positively charged impurity ions from the source material, and to give the impurity ions sufficient energy through acceleration by an electric field to obtain impurity ions with sufficient energy, so that the impurity ions with sufficient energy enter the target crystal lattice, and the impurity ions with sufficient energy are activated through thermal annealing, thereby realizing impurity doping of the base material; the epitaxy is to grow a single crystal layer on the substrate, which is divided into solid phase epitaxy, vapor phase epitaxy, and liquid phase epitaxy.

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