FPGA routing method considering maximum latency optimization

Abstract

The application relates to an FPGA wiring method considering maximum time delay optimization, which comprises the following steps: step S1: adopting a layout optimization algorithm driven by wiring, circuit design is divided into subareas with smaller system time delay; step S2: adopting a TDM ratio initial allocation method based on a Lagrange relaxation method, optimal TDM ratio allocation results are obtained; step S3: a TDM ratio legalization algorithm based on actual constraint conditions is used to perform legalization operation on the TDM ratio allocation results; and step S4: a maximum time delay optimization algorithm based on negotiation exchange is used to further reduce the TDM ratio and reduce the system time delay. The application can effectively improve the availability of a multi-FPGA prototype system and improve wiring efficiency.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit computer-aided design, and particularly relates to an FPGA wiring method considering maximum time delay optimization. BACKGROUND

[0002] Logic verification plays an important role in the physical design automation of Very Large Scale Integration (VLSI). With the rapid increase of the size of VLSI, the time for implementing logic verification is getting longer and the cost of replication is getting higher. Therefore, for modern advanced VLSI, an effective and scalable logic verification method is needed. The existing VLSI logic verification methods are divided into the following three categories: (1) software simulation method, (2) hardware simulation method and (3) Field Programmable Gate Array (FPGA) prototyping method. The software-based simulator is visualized and provides debugging capabilities for VLSI developers. However, such a simulator needs to simulate all logic gates one by one on a single processor, so its running time is too long for large VLSI designs. Compared with software simulation, the hardware simulation method greatly speeds up the generation process of the circuit, but the implementation cost will be greatly increased. Now with the development of integrated circuit technology, the chip size used is getting larger and larger, and the disadvantages of the two verification methods described above are becoming more and more obvious.

[0003] At present, Field Programmable Gate Array has been widely used in cloud computing, deep learning in artificial intelligence and FPGA prototyping system. Unlike the methods of logic simulation and hardware simulation, the FPGA prototyping method spends less on cost and running time, so it has been widely used in industry. For FPGA prototyping design, if it is a very small scale circuit, logic verification can be performed on a single FPGA. However, the size of the current VLSI design is huge, and it is difficult for the FPGA prototyping system to design in only one FPGA. Therefore, people have developed a multi-FPGA prototyping system, which divides the given VLSI design into sub-circuits, and each sub-circuit can be implemented in a single FPGA. Due to the physical limitations of a single FPGA, the number of I / O pins between circuits is usually exceeded. Therefore, the Timing Division Multiplexing (TDM) technology is proposed to solve the problem of insufficient number of I / O pins. The TDM technology effectively improves the signal transmission capability of the FPGA prototyping system. However, since the timing division multiplexing prolongs the signal delay between FPGAs, the clock frequency of the system is greatly reduced, and how to optimize the TDM ratio is still an important problem. SUMMARY

[0004] Therefore, the present application aims to provide an FPGA routing method considering maximum latency optimization, which aims to optimize system running time and optimize maximum latency, and effectively improves the availability of multi-FPGA prototype system.

[0005] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0006] An FPGA routing method considering maximum latency optimization, comprising the following steps:

[0007] Step S1: using a routing-driven layout optimization algorithm, the circuit design is divided into sub-regions with smaller system latency;

[0008] Step S2: using a TDM ratio initial allocation method based on the Lagrange relaxation method, the optimal TDM ratio allocation result is obtained;

[0009] Step S3: the TDM ratio allocation result is legalized by a TDM ratio legalization algorithm based on actual constraint conditions;

[0010] Step S4: using a maximum latency optimization algorithm based on negotiation exchange, further reducing the TDM ratio and reducing the system latency.

[0011] Further, the routing-driven layout optimization algorithm specifically comprises:

[0012] (1) providing an initial position for each logic element, and adjusting the area of the logic element;

[0013] (2) packing the logic element into a basic logic element based on constraints;

[0014] (3) congestion-driven global layout, providing a global layout result for legalization;

[0015] (4) determining the exact position of each logic element;

[0016] (5) using an improved greedy algorithm for detailed layout.

[0017] Further, the step S2 specifically comprises:

[0018] Step S21: according to the constraint condition, the TDM allocation problem is modeled as formula (1), formula (1) is as follows:

[0019]

[0020] Where, at sink is the system latency to the target node, at i is the system latency to node i, xi is the TDM ratio on the ith edge, p i is the number of edges on the ith connection pair;

[0021] where the second constraint in formula (1) can be expanded to formula (2) as follows:

[0022]

[0023] Step S22: Relax the constraints shown in formula (2), and introduce a non-negative Lagrange multiplier variable for each constraint condition;

[0024] Step S23: Solve the constraint optimization problem based on the Lagrange relaxation method to obtain the optimal TDM ratio allocation result.

[0025] Further, the step S22 is specifically:

[0026] λ i is introduced for each FPGA, and μ p，q is introduced for the constraint on each edge e p，q , and the relaxed formula is as follows:

[0027]

[0028] Based on the above, the Lagrange relaxation sub-problem (LRS) related to the Lagrange multipliers μ and λ is defined as:

[0029]

[0030] Further, the step S23 is specifically:

[0031] Under the KKT condition, the optimal solution of PP is also the optimal solution of the Lagrange relaxation sub-problem, therefore, μ and λ must satisfy the KKT condition and When solving the (μ, λ) of the Lagrange dual problem (LDP), only those multipliers satisfying these conditions are considered, and this also indicates the optimality condition of the multipliers, as shown in formula (5):

[0032]

[0033] Therefore, x can be obtained through (μ, λ), as shown in formula (6):

[0034]

[0035] Since μ and λ are two groups of non-negative variables, the optimal value of LRS / (μ, λ) is not greater than the objective value of PP, if the L μ，λthe minimum of LDP

[0036] By iteratively updating μ and λ, L μ，λ the lower bound of LDP will be closer to the optimal solution of PP, and finally converge. Let Q(μ, λ) denote the optimal value of LRS / (μ, λ), the formula of LDP is as follows:

[0037]

[0038] When optimizing LDP, only (μ, λ) in the solution space Ω defined by formula (7) needs to be considered; previous work usually uses arbitrarily assigned multipliers as initial Lagrange multipliers, and then iteratively updates the multipliers; in order to update the multipliers,

[0039] μ p，q is initialized to be proportional to the number of TDM edges that affect at p，q ; the initial assignment of μ p，q is obtained by making μ p，q proportional to the number of TDM edges that affect at i，sink .

[0040] Further, the initialization method of λ is as follows:

[0041]

[0042] After solving LRS / (μ, λ), μ is updated according to the time critical value of each edge, and formula (9) is used to control the convergence speed and quality;

[0043]

[0044] where i is the current iteration number;

[0045] Further, a greedy algorithm is used to update μ, first, the μ i，sink of the target node is updated, as shown in formula (10):

[0046] μ′ i,sink = μ i,sink ·(1+r), if at i,sink ≥ c·at sink (10)

[0047] Then, the Lagrange multiplier of the intermediate node is updated; when the Lagrange multiplier of the output edge of a node g p is updated, the wiring diagram will appear to violate the constraint.

[0048] The violation of the constraint can be divided into two cases: (1) and (2) The first case infers that at pat p to improve at sink The difference between the output edge and the input edge is evenly distributed to the edge {e i，p |at i，p ≥c·at p} where c is a constant as shown in equation (12):

[0049]

[0050] In case (2), update with g p The Lagrange multiplier on the edge as the output node; in order to minimize at sink , first only for all j∈{k|at k，p <at p} to reduce the multiplier μ j，p ; when the constraints can not be met by only reducing these multipliers, the difference between the Lagrange multiplier on each edge is reduced in proportion; however, when the arrival time of each input edge is equal to at p , the Lagrange multiplier on each edge will be updated by equation (12); after updating μ, λ is still updated in the manner of equation (8).

[0051] Further, the step S3 is specifically: first, traverse each net on each edge and make the allocated TDM ratio legal by rounding up; then, if the result is odd, increase them by 1 to make them even; since the increase of a number reduces its reciprocal, the above operation ensures that the reciprocal of the TDM ratio on each edge is less than 1.

[0052] Further, the maximum latency optimization algorithm based on negotiation exchange is specifically: judge whether the maximum TDM ratio is reduced by exchanging the TDM ratios of the edges between two FPGAs, if the maximum TDM ratio is reduced, exchange the TDM ratios of the two edges; if exchange is performed in the last iteration and the result is improved compared with the previous pre-set iteration, it is considered that there is room for improvement in the system clock cycle.

[0053] Compared with the prior art, the present application has the following beneficial effects:

[0054] The present application effectively optimizes system running time and optimizes maximum latency, and improves the usability of a multi-FPGA prototype system. BRIEF DESCRIPTION OF DRAWINGS

[0055] Figure 1 is a method flowchart of the present application;

[0056] Figure 2 is an algorithm flowchart for solving the LDP problem in an embodiment of the present application. Detailed Implementation

[0057] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0058] Please refer to Figure 1 This invention provides an FPGA routing method that considers maximum delay optimization, comprising the following steps:

[0059] Step S1: Use a routing-driven layout optimization algorithm to divide the circuit design into partitions with smaller system latency;

[0060] Step S2: Use the initial TDM ratio allocation method based on the Lagrange relaxation method to obtain the optimal TDM ratio allocation result;

[0061] Step S3: The TDM ratio allocation result is legalized using the TDM ratio legalization algorithm based on actual constraints;

[0062] Step S4: Based on the maximum delay optimization algorithm of negotiation and switching, further reduce the TDM ratio and reduce system latency.

[0063] In this embodiment, for a multi-FPGA prototype system, an efficient routing method is needed for initial routing between FPGA chips to determine which FPGAs are interconnected. Using FPGA routing diagrams, net lists, and net group information as input, considering the criticality of net groups at this stage is crucial because optimizing the TDM ratio is limited by the routing topology. All nets are first routed based on the KMB algorithm, a Steiner tree approximation algorithm. Then, de-routing and rerouting are performed to further improve the routing results. Specifically, the routing order is evaluated based on the net group size, and shortest path algorithms are used sequentially to find the path for each required connection pair. Finally, the routed nets are evaluated, and poorly routed nets are rerouted to improve the routing results and complete the routing generation.

[0064] Preferably, in this embodiment, a routing-driven layout optimization algorithm is used to perform the layout operation. The algorithm includes the following five stages: (1) partitioning, providing an initial position for each logical element and adjusting the area of ​​the logical elements; (2) packing, packing the logical elements into basic logical elements (BLE) based on constraints; (3) congestion-driven global layout, providing global layout results for legalization; (4) legalization, determining the exact position of each logical element; and (5) detailed layout, improving the layout of the greedy algorithm.

[0065] Preferably, in this embodiment, the initial allocation of the TDM ratio specifically includes:

[0066] (1) Problem modeling and conversion

[0067] The TDM allocation problem is modeled and converted to get an optimal TDM ratio to reduce the system latency. First, the problem is modeled as formula (1) according to the constraints, which is shown as follows:

[0068]

[0069] where at sink is the system latency to the target node, at i is the system latency to node i, x i is the TDM ratio on the ith edge, p i is the number of edges on the ith connection pair.

[0070] where the second constraint in formula (1) can be expanded to formula (2) as follows:

[0071]

[0072] (2) Lagrangian relaxation method

[0073] The Lagrangian relaxation (LR) method is an approximate optimization method for solving constrained optimization problems. This algorithm has applications in many aspects. In the process of Lagrangian relaxation, the constraints that are difficult to solve in the problem can be transferred to the optimization objective. LR is a general framework for solving constrained optimization problems. By binarizing the difficult constraints in the primal problem (PP), a Lagrangian relaxation subproblem (LRS) can be obtained. LRS is a problem that is easier to solve. For a minimization problem, the optimal solution of LRS is a lower bound on PP. The constraints violated in PP are penalized by the Lagrangian multipliers (LMs) in LRS. In addition, the problem of maximizing the lower bound on LMs is called the Lagrangian dual problem (LDP). Since it is often difficult to find the optimal LM of PP, an iterative method is used to update the LM.

[0074] This embodiment proposes a new updating strategy to reduce the number of iterative updates. First, the constraints shown in formula (2) are relaxed. For each constraint, a non-negative Lagrangian multiplier variable is introduced, so that any violation of these constraints will be penalized, thereby avoiding the generation of a worse TDM ratio allocation result.

[0075] Specifically, λ i is introduced for each FPGA p，q , and μ p，q is introduced for each constraint on edge e

[0076]

[0077] Therefore, the Lagrangian relaxation subproblem (LRS) with respect to the Lagrange multipliers μ and λ is defined as:

[0078]

[0079] (3) Solving the Lagrangian relaxation subproblem

[0080] Under the KKT conditions, the optimal solution of PP is also the optimal solution of the Lagrangian relaxation subproblem. Therefore, μ and λ must satisfy the KKT conditions and When solving the Lagrangian dual problem (LDP) for (μ, λ), only those multipliers that satisfy these conditions are considered. At the same time, this also indicates the optimality conditions on the multipliers, as shown in equation (5).

[0081]

[0082] Therefore, x can be obtained from (μ, λ), as shown in equation (6):

[0083]

[0084] (4) Solving the Lagrangian dual problem

[0085] Since μ and λ are two sets of non-negative variables, the optimal value of LRS / (μ, λ) is not greater than the objective value of PP. Therefore, if the minimum value of L μ，λ is maximized, a tighter lower bound of PP can be obtained. By iteratively updating μ and λ, the lower bound of L μ，λ will be closer to the optimal solution of PP, eventually converging. Let Q(μ, λ) represent the optimal value of LRS / (μ, λ). The formula for LDP is as follows:

[0086]

[0087] When optimizing LDP, only (μ, λ) in the solution space Ω defined by Equation (7) needs to be considered. Previous works typically use arbitrarily assigned multipliers as initial Lagrange multipliers and then update the multipliers through iterative updates. To update the multipliers, subgradient formula optimization is usually employed. However, this invention starts by finding a good initial assignment for the multipliers in the solution space Ω, and then updates the multipliers using a novel method as shown, taking into account the KKT conditions during the update.

[0088] refer to Figure 2 This is a flowchart for solving LDP.

[0089] μ p，q initial value and influence at p，q The number of TDM edges is related by μ p，q With influence at p，q The initial allocation of μ is proportional to the number of TDM edges. Furthermore, λ is initialized as follows:

[0090]

[0091] After solving LRS / (μ,λ), μ is updated based on the time critical value of each edge. Formula (9) is used to control the convergence speed and quality.

[0092]

[0093] Where i is the current iteration number.

[0094] In this embodiment, a greedy algorithm is applied to update μ, attempting to reduce the TDM ratio on the critical path in each iteration, thereby reducing the maximum system latency. First, the μ of the target node is updated. i，sink As shown in formula (10):

[0095] μ′ i,sink =μ i,sink ·(1+r),if at i,sink ≥c·at sink (10)

[0096] Then, the Lagrange multipliers of the intermediate nodes are updated. When a node g p After updating the Lagrange multiplier of the output edge, the wiring diagram may exhibit constraint violations. Constraint violations can be categorized into two types: (1) and (2) The first case infers at p At least on one critical path, at needs to be reduced p To improve at sink Therefore, this invention distributes the difference between the output edge and the input edge evenly to the edge {e}.i，p |at i，p ≥c·at p}. Where c is a constant with value 0.95. As shown in equation (12):

[0097]

[0098] In case (2), although node g p is less critical than before, it can still be on a critical path. Therefore, the Lagrange multiplier on the edge leading to g p is updated. To minimize at sink , first only the j∈{k|at k，p < at p} are reduced by the multiplier μ j，p . When the constraint cannot be satisfied by reducing these multipliers alone, the difference in the Lagrange multiplier on each edge is reduced proportionally. However, when the arrival time of each input edge equals at p , the Lagrange multiplier on each edge is updated by equation (12).

[0099] After updating μ, λ is still updated as in equation (8).

[0100] Preferably, in this embodiment, TDM rate legalization includes: since the continuous solver optimizes the TDM rate in a global manner, the result should be respected in the discretization process. Since the result obtained by the continuous solver is a continuous solution, it does not satisfy the constraint that the TDM rate should be even. Therefore, the TDM rate needs to be legalized. First, traverse each net on each edge and make the allocated TDM rate legal by rounding up. Then, if the result is odd, increase them by 1 to make them even. Since the increase of a number reduces its reciprocal, the above operation guarantees that the reciprocal of the TDM rate on each edge and is less than 1.

[0101] Preferably, in this embodiment, TDM rate optimization includes: swap-based TDM rate optimization algorithm. For example, given a continuous solution at p = 8, at m = 16, delay p，q = 16 and delay m，n = 8. It can be known that the optimal result of the displacement of these two edges is 0. But when considering the discretization result of other edges in the timing graph, the values of at p and at q are changed to 15 and 9. If the TDM rates of e p，q and e m，n are swapped, max(atn , at q ) can be improved by 6. The specific algorithm is to judge whether the maximum TDM ratio is reduced by exchanging the TDM ratios of two edges between FPGAs, and if the maximum TDM ratio is reduced, the TDM ratios of the two edges are exchanged to improve the system clock period. If the exchange is made in the last iteration and the result is improved compared with the previous 10 iterations, it is considered that there is room for improvement of the system clock period. If a TDM line network net j is considered as a candidate of net i if it satisfies the following two constraint conditions: (1) the TDM ratio of net i is less than that of net j . (2) ResSlack of net j should be greater than 0. ResSlack j is the maximum slack of net i after exchanging with net j . In the optimization stage, the TDM ratio of the edge with greater ResSlack j is first tried to be exchanged, and it is more likely to reduce the system clock period by this exchange.

[0102] The above only describes the preferred embodiments of the present application, and any equivalent changes and modifications made within the scope of the present application should be included in the scope of the present application.

Claims

1. A method for FPGA routing considering maximum latency optimization, comprising: The method comprises the following steps: Step S1: using a wiring-driven layout optimization algorithm to divide the circuit design into partitions with smaller system latency; Step S2: using a TDM ratio initial allocation method based on the Lagrange relaxation method to obtain an optimal TDM ratio allocation result; Step S3: using a TDM ratio legalization algorithm based on actual constraint conditions to legalize the TDM ratio allocation result; Step S4: using a maximum latency optimization algorithm based on negotiation exchange to reduce the TDM ratio and reduce the system latency. The wiring-driven layout optimization algorithm specifically comprises: (1) providing an initial position for each logic element and adjusting the area of the logic element; (2) packing the logic element into a basic logic element based on constraints; (3) congestion-driven global layout, providing a global layout result for legalization; (4) determining the exact position of each logic element; (5) using an improved greedy algorithm for detailed layout. The step S2 specifically comprises: Step S21: modeling the TDM allocation problem as formula (1) according to the constraint conditions, and formula (1) is as follows: where at sink is the system delay to reach the target node, at p and at q are the system delays to reach nodes p and q, respectively, x j is the TDM ratio on the jth edge, p i is the number of edges on the ith connection pair; Wherein, the second constraint condition in formula (1) is expanded to obtain formula (2), and formula (2) is as follows: Step S22: relaxing the constraint shown in formula (2), and introducing a non-negative Lagrange multiplier variable for each constraint condition; Step S23: solving the constraint optimization problem based on the Lagrange relaxation method to obtain the optimal TDM ratio allocation result.

2. The FPGA routing method with maximum latency optimization according to claim 1, wherein, The step S22 specifically comprises: λ was introduced for each FPGA i And for each edge e p,q The constraint introduced on μ p,q The relaxed formula is shown below: In summary, the Lagrangian relaxation subproblem (LRS) related to the Lagrangian multipliers μ, λ will be defined as: .

3. The FPGA routing method with maximum latency optimization according to claim 1, wherein, The step S23 specifically comprises: Under the KKT conditions, the optimal solution of the PP is also the optimal solution of the Lagrangian relaxation subproblem, therefore, μ and λ must satisfy the KKT conditions and In solving the Lagrangian dual problem (LDP) for (μ, λ), only those multipliers satisfying these conditions are considered, while this also indicates the optimality conditions on the multipliers, as shown in equation (5): Therefore, x is obtained through (μ, λ), as shown in formula (6): Since μ and λ are two sets of nonnegative variables, the optimal value of LRS / (μ, λ) is not greater than the PP target value, if maximizing L μ,λ The minimum value of LRS / (μ, λ) gives a tighter lower bound of PP By iteratively updating μ and λ, L μ,λ The lower bound of LDP will be closer to the optimal solution of PP, and eventually converge. Let Q(μ, λ) represent the optimal value of LRS / (μ, λ), and the formula of LDP is as follows: When optimizing the LDP, only (μ, λ) in the solution space Ω defined by formula (7) needs to be considered; previous work uses an arbitrarily assigned multiplier as the initial Lagrange multiplier, and then updates the multiplier through continuous iteration; in order to update the multiplier; The initial value of μ p,q is linked to the number of TDM edges that affect at p,q , and the initial allocation of μ is obtained by making μ p,q proportional to the number of TDM edges that affect at p,q .

4. The FPGA routing method with maximum latency optimization according to claim 3, wherein, The initialization method of λ is as follows: After solving the LRS / (μ, λ), μ is updated according to the time critical value of each edge, and formula (9) is used to control the convergence speed and quality; Wherein, n is the current iteration number.

5. The FPGA routing method with maximum latency optimization according to claim 3, wherein, The greedy algorithm is used to update μ, first, update the target node's μ i,sink As shown in equation (10): μ' k,sink = μ k,sink • (1 + r), if at k,sink ≥ c • at sink (10) Then, the Lagrange multipliers of the intermediate nodes are updated; when a node g p After the Lagrange multipliers of the output edges are updated, the wiring diagram may violate the constraints; Violations of the constraints can be divided into two cases: (1) and (2) The first case infers that at p at least on one critical path, at p to improve at sink The difference between the output edges and the input edges is evenly distributed to the edges {e i,p ∣at i,p ≥ c · at p}; where c is a constant value such as equation (12) As shown: In case (2), update with g p the Lagrange multiplier on the edge that is the output node; to minimize at sink , first only for all j e {k \ at k,p <at p} reduce the multipliers μ j,p ; when the constraints cannot be satisfied by only reducing these multipliers, reduce the difference of the Lagrange multipliers on each edge proportionally; however, when the arrival time of each input edge equals at p , update the Lagrange multiplier on each edge by formula (12); after updating μ, λ is still updated as formula (8).

6. The FPGA routing method with maximum latency consideration optimization of claim 1, wherein, The step S3 specifically comprises: first, traversing each net on each edge and making the allocated TDM ratio legal through the upward rounding method; then, if the result obtained is odd, they are increased by 1 to make them even; since the increase of a number reduces its reciprocal, it is ensured that the reciprocal of the TDM ratio on each edge is less than 1.

7. The FPGA routing method with maximum latency optimization according to claim 1, wherein, The maximum latency optimization algorithm based on negotiation exchange specifically comprises: judging whether the maximum TDM ratio is reduced by exchanging the TDM ratios of the edges between two FPGAs, if the maximum TDM ratio is reduced, exchanging the TDM ratios of the two edges; if the exchange is performed in the last iteration, and the result is improved compared with the previous pre-set iteration, it is considered that there is room for improvement in the system clock cycle.

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