A low earth orbit satellite phased array antenna calibration device

Abstract

The application discloses a low-orbit satellite phased array antenna calibration device, wherein the calibration antenna is connected with a transmitting calibration component and a receiving calibration component through a duplexer; a first calibration integrated circuit is connected with a first test circuit in series through a power divider and the calibration antenna to form a closed loop, and the first calibration integrated circuit is connected with a first reference circuit in series through the power divider to form a closed loop; the first calibration integrated circuit is used for calculating compensation amplitude and phase values according to comparison of amplitudes and phases between the first test circuit and the first reference circuit; a second calibration integrated circuit is connected with a second test circuit in series through a power divider and the calibration antenna to form a closed loop, and the first calibration integrated circuit is connected with a second reference circuit in series through the power divider to form a closed loop; and the second calibration integrated circuit is used for calculating compensation amplitude and phase values according to comparison of amplitudes and phases between the second test circuit and the second reference circuit.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of satellite wireless communication, in particular to a low-orbit satellite phased array antenna calibration device. BACKGROUND

[0002] In recent years, the world has gradually increased the research investment in low-orbit satellite constellations, and foreign companies have launched thousands of low-orbit satellites, preliminarily opening low-orbit satellite internet services, and domestic research is still in the initial stage. The low-orbit satellites largely use phased array technology, which can quickly adjust the beam pointing to serve specific areas on the ground. In the phased array antenna, in order to accurately point the antenna beam, the phase and amplitude consistency of each channel must be strictly controlled, which requires calibration of each channel to meet the accuracy requirements of beam pointing.

[0003] The traditional DBF calibration device uses a calibration source to generate a calibration signal, the calibration signal is divided into N paths, and is sequentially fed into N T / R channels through a switch. The switch is turned to the calibration source, and a first sampling is performed to obtain the amplitude and phase information of the calibration source. The switch is turned back to the T / R channel, and a second sampling is performed. The amplitude and phase errors between channels are calculated using the AD converted data, and a calibration coefficient is generated. This calibration method requires an independent calibration source device during calibration, and the calibration source needs to be divided into N paths, which is relatively complex in a large-scale DBF phased array antenna system and is difficult to integrate into the phased array antenna. The calibration operation conditions are relatively high, and it is difficult to realize after the antenna is shipped, especially after being launched into orbit.

[0004] In the traditional technology, the calibration device is composed of a signal processing system and a near-field signal source. The signal processing system includes a plurality of phase-locked loops and mixers, and the number of phase-locked loops is the same as the number of mixers. N channels require N phase-locked loops. Since the phase of the phase-locked loop after power-on is random, the phase of the N phase-locked loops after power-on is randomly distributed, and the last calibration data cannot be used. After power-on, it needs to be calibrated again. It takes a long time to calibrate after each power-on, which is tedious and time-consuming. For low-orbit satellites, the time cost is too high. SUMMARY

[0005] The technical problem to be solved by the application is that the signal generated by the traditional calibration signal source is complex and has high cost, and it is difficult to integrate into a large-scale DBF phased array antenna. The purpose is to provide a low-orbit satellite phased array antenna calibration device, which solves the problem that the traditional technology is difficult to apply to a large-scale phased array antenna due to the complexity and high cost of the device when calibrating the signals of each channel of the phased array antenna.

[0006] The application is implemented through the following technical solutions:

[0007] A low-orbit satellite phased array antenna calibration device, comprising a calibration antenna, a duplexer, a transmitting calibration component and a receiving calibration component;

[0008] The calibration antenna is connected with the transmitting calibration component and the receiving calibration component through the duplexer respectively;

[0009] The transmitting calibration component comprises a first calibration integrated circuit, a first test circuit and a first reference circuit;

[0010] The first calibration integrated circuit is connected with the first test circuit and the first reference circuit through the power divider to form a closed loop, and the first calibration integrated circuit is used to compare the amplitude and phase between the first test circuit and the first reference circuit;

[0011] The receiving calibration component comprises a second calibration integrated circuit, a second test circuit and a second reference circuit;

[0012] The second calibration integrated circuit is connected with the second test circuit and the second reference circuit through the power divider to form a closed loop, and the second calibration integrated circuit is used to compare the amplitude and phase between the second test circuit and the second reference circuit.

[0013] In the scheme, the calibration antenna is connected with the transmitting calibration component and the receiving calibration component through the duplexer, and the transmitting calibration component and the receiving calibration component share the same calibration antenna, which reduces the cost and simplifies the device.

[0014] The first calibration integrated circuit is used to transmit a radio frequency calibration signal, the radio frequency calibration signal is divided into two signals through the power divider, one of the two signals is a test signal, the test signal is sent to the first test circuit through the calibration antenna, the first test circuit receives the test signal to test the phase and amplitude of the transmitting channel in the phased array technology, the first calibration integrated circuit and the first test circuit are connected in series to form a closed loop, and the first test circuit sends the test signal of the phase and amplitude of the transmitting channel to the first calibration integrated circuit;

[0015] The other signal of the radio frequency calibration signal divided by the power divider is transported to the first reference circuit, the other signal is a reference signal, the first reference circuit receives the reference signal, the first reference circuit is used to self-calibrate the reference signal to form a standard signal of the transmitting channel in the phased array technology, the standard signal is an accurate amplitude and phase, the first reference circuit and the first calibration integrated circuit are connected in series to form a closed loop, and the first reference circuit sends the standard signal to the first calibration integrated circuit;

[0016] The first calibration integrated circuit compares the standard signal with the amplitude and phase of the transmitting channel in the phased array technology, and calculates the compensation amplitude and phase value needed to compensate for the transmitting channel in the phased array technology.

[0017] The second calibration integrated circuit transmits a radio frequency calibration signal, which is divided into two signals by a power divider. One of the two signals is a test signal, which is transmitted to the second test circuit through a calibration antenna. The second test circuit receives the test signal to test the phase and amplitude of the receiving channel in the phased array technology. The second calibration integrated circuit and the second test circuit form a closed loop in series. The second test circuit transmits the test signal of the phase and amplitude of the receiving channel to the second calibration integrated circuit.

[0018] The other signal of the radio frequency calibration signal transmitted to the second reference circuit through the power divider is a reference signal. The second reference circuit receives the reference signal. The second reference circuit is used to calibrate the reference signal to form a standard signal of the receiving channel in the phased array technology. The standard signal is accurate in amplitude and phase. The second reference circuit and the second calibration integrated circuit form a closed loop in series. The second reference circuit transmits the standard signal to the second calibration integrated circuit.

[0019] The second calibration integrated circuit compares the standard signal with the amplitude and phase of the receiving channel in the phased array technology, and calculates the compensation amplitude and phase value needed to compensate for the receiving channel in the phased array technology.

[0020] The first calibration integrated circuit compares the first test circuit and the first reference circuit, calculates the compensation amplitude and phase value of the transmitting channel, and repeats the above process to obtain the amplitude and phase of all transmitting channels, and then performs normalization processing. The second calibration integrated circuit compares the second test circuit and the second reference circuit, calculates the compensation amplitude and phase value of the receiving channel, and repeats the above process to obtain the amplitude and phase of all receiving channels, and then performs normalization processing. The structure is simple, easy to integrate into a large-scale DBF phased array antenna, and solves the problem of complex structure, high cost, and difficulty in integrating into a large-scale phased array antenna in the traditional technology.

[0021] In some implementable solutions, a low-orbit satellite phased array antenna calibration device, the first calibration integrated circuit includes a first processor with FPGA as the core.

[0022] In this scheme, the FPGA is a programmable gate array, which is a semi-custom circuit in the field of application-specific integrated circuits. It solves the shortcomings of custom circuits and overcomes the limitation of the number of gate circuits in the original programmable device.

[0023] In some embodiments, a low-orbit satellite phased array antenna calibration device, the first calibration integrated circuit further comprises a first signal source chip and a first analog-to-digital converter;

[0024] One end of the first signal source chip is electrically connected with a frequency divider in the first processor, and the other end is electrically connected with a power divider, the first processor is used to generate a calibration signal by driving the first signal source chip, and the calibration signal is sent into the first test circuit and the first reference circuit through the power divider;

[0025] One end of the first analog-to-digital converter is connected with the first processor, and the other end is connected with a first switch, the first switch is used to select the first test circuit or the first reference circuit according to the first processor.

[0026] In this scheme, the first processor is a first processor with FPGA as the core, the first processor is built-in with a frequency divider, the frequency divider is a DDS direct digital synthesizer, the frequency divider is connected with the first signal source chip, and the frequency divider in the first processor drives the first signal source chip to generate a calibration signal, the calibration signal is divided into two paths through a power divider, one path is a test signal sent into the first test circuit, and the other path is a reference signal sent into the first reference circuit.

[0027] The first processor is connected with a first analog-to-digital converter, the first analog-to-digital converter is connected with a first switch, the first switch is used to select the first test circuit or the first reference circuit according to the first processor, the first analog-to-digital converter is used to process the test signal transmitted by the first test circuit or the reference signal transmitted by the first reference circuit, and the first analog-to-digital converter converts the test signal or the reference signal into a digital signal and transmits it to the first processor.

[0028] In some embodiments, a low-orbit satellite phased array antenna calibration device, the first test circuit comprises a transmitting channel;

[0029] One end of the transmitting channel is connected with a power divider, and the other end is connected with a transmitting array element; the transmitting array element is wirelessly connected with a calibration antenna; the calibration antenna is electrically connected with a first digital control attenuator, and the first digital control attenuator is electrically connected with a first switch.

[0030] The scheme, the first test circuit includes a transmit channel, the transmit channel is used for receiving the test signal split by the first processor through the power divider, the test signal enters the transmit channel for sampling the amplitude and phase of the transmit channel; the transmit channel is connected with a transmit array element, the transmit channel transmits the test signal to the transmit array element, the transmit array element is a transmit antenna, the transmit array element radiates through an antenna, and the calibration antenna receives the test signal radiated by the transmit array element; the first digital attenuator is connected with the first switch, and the first digital attenuator is used for adjusting the size of the test signal; the first digital attenuator is electrically connected with the first switch, and the first digital attenuator transmits the test signal to the first processor through the first switch and the first analog-to-digital converter.

[0031] In some implementable schemes, a low-orbit satellite phased array antenna calibration device, the first reference circuit includes a first attenuator for adjusting the size of the signal, one end of the first attenuator is connected with the power divider, and the other end is electrically connected with the first switch.

[0032] The scheme, the first reference circuit receives the reference signal split by the power divider, and the reference signal is self-calibrated by the first attenuator; the first reference circuit is connected with the first processor through the first switch and the first analog-to-digital converter, and the self-calibrated reference signal is transmitted to the first processor through the first switch.

[0033] In some implementable schemes, a low-orbit satellite phased array antenna calibration device, the second calibration integrated circuit includes a second processor with FPGA as the core.

[0034] The scheme, the FPGA is a programmable gate array, which is a semi-custom circuit in the field of application-specific integrated circuit, that is, it solves the shortcomings of custom circuits and overcomes the limitation of the number of gate circuits of the original programmable device.

[0035] In some implementable schemes, a low-orbit satellite phased array antenna calibration device, the second calibration integrated circuit further includes a second signal source chip and a second analog-to-digital converter;

[0036] One end of the second signal source chip is electrically connected with a frequency divider in the second processor, and the other end is electrically connected with the power divider; the second processor is used for generating a calibration signal by driving the second signal source chip, and sending the calibration signal into the second test circuit and the second reference circuit through the power divider;

[0037] One end of the second analog-to-digital converter is connected with the second processor, and the other end is connected with a second switch, and the second switch is used for selecting the second test circuit or the second reference circuit according to the second processor.

[0038] In the scheme, the second processor is an FPGA-based second processor, the second processor is internally provided with a frequency divider, the frequency divider is connected with a second signal source chip, the frequency divider in the second processor drives the second signal source chip to generate a calibration signal, the calibration signal is divided into two paths by a power divider, one path is a test signal sent to a second test circuit, and the other path is a reference signal sent to a second reference circuit.

[0039] The second processor is connected with a second analog-to-digital converter, the second analog-to-digital converter is connected with a second switch, the second switch is used to select connection with the second test circuit or the second reference circuit according to the second processor, the second analog-to-digital converter is used to process a test signal transmitted by the second test circuit or a reference signal transmitted by the second reference circuit, and the second analog-to-digital converter converts the test signal or the reference signal into a digital signal and transmits the digital signal to the second processor.

[0040] In some implementable schemes, a low-orbit satellite phased array antenna calibration device, the second test circuit includes a second digital attenuator,

[0041] One end of the second digital attenuator is connected with the power divider, and the other end is connected with a calibration antenna, the calibration antenna is wirelessly connected with a receiving array element, the receiving array element is electrically connected with a receiving channel, the receiving channel is connected with a third digital attenuator, and the third digital attenuator is electrically connected with the second switch.

[0042] In the scheme, the second test circuit includes a second digital attenuator, a test signal divided by the power divider is sent to the second digital attenuator, the second digital attenuator is used to adjust the power size of the test signal, the second digital attenuator is connected with the calibration antenna, the attenuated test signal is transmitted to the calibration antenna by the second digital attenuator, the calibration antenna transmits the test signal to the receiving array element through antenna radiation, the receiving array element is a receiving antenna, the receiving array element is electrically connected with a receiving channel, the test signal passes through the receiving channel to sample the amplitude and phase of the receiving channel, the receiving channel is connected with a third digital attenuator, the third digital attenuator is used to adjust the signal size entering the second analog-to-digital converter, the third digital attenuator is electrically connected with the second switch, and the third digital attenuator transmits the test signal to the second processor through the second switch and the second analog-to-digital converter.

[0043] In some implementable schemes, a low-orbit satellite phased array antenna calibration device, the second reference circuit includes a second attenuator for adjusting the signal size, one end of the second attenuator is connected with the power divider, and the other end is electrically connected with the second switch.

[0044] In the scheme, the second reference circuit receives a reference signal branched from the power divider, and the reference signal is subjected to self-calibration of the reference signal by the second attenuator; the second reference circuit is connected with the second processor through the second switch and the second analog-to-digital converter, and the self-calibrated reference signal is transmitted to the second processor through the second switch.

[0045] In some implementable schemes, a low-orbit satellite phased array antenna calibration device, the first calibration integrated circuit is multiplexed by a baseband FPGA, and the first calibration integrated circuit is connected in series with the second test circuit through the power divider to form a closed loop.

[0046] The first calibration integrated circuit is connected in series with the second reference circuit through the power divider to form a closed loop; and the first calibration integrated circuit is configured to calculate compensation amplitude and phase values according to comparison of amplitudes and phases between the second test circuit and the second reference circuit.

[0047] In the scheme, the first calibration integrated circuit comprises a first processor with an FPGA as a core, a first signal source chip and a first analog-to-digital converter; the first test circuit and the second test circuit are both connected with the first calibration integrated circuit to form a closed loop; and the first test circuit and the second test circuit share the first processor, the first signal source chip and the first analog-to-digital converter, thereby saving device cost.

[0048] The first reference circuit and the second reference circuit are both connected with the second calibration integrated circuit to form a closed loop; and the first reference circuit and the second reference circuit share the first processor, the first signal chip and the first analog-to-digital converter, thereby saving device cost.

[0049] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0050] The calibration antenna is connected with the transmitting calibration assembly and the receiving calibration assembly through the diplexer respectively; and the transmitting calibration assembly and the receiving calibration assembly share the same calibration antenna, thereby reducing cost and simplifying the device.

[0051] The first calibration integrated circuit compares the first test circuit and the first reference circuit to calculate compensation amplitude and phase values of the transmitting channel, and the above process is repeated to obtain amplitudes and phases of all transmitting channels and then perform normalization processing; the second calibration integrated circuit compares the second test circuit and the second reference circuit to calculate compensation amplitude and phase values of the receiving channel, and the above process is repeated to obtain amplitudes and phases of all receiving channels and then perform normalization processing; the structure is simple, easy to integrate into a large-scale DBF phased array antenna, and solves the problem of complex structure, high cost and difficulty in integration into a large-scale phased array antenna in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor. In the drawings:

[0053] Fig. 1 A schematic diagram of a transmitting calibration component of a low-orbit satellite phased array antenna calibration device is provided for Embodiment 1;

[0054] Fig. 2 A flowchart of a transmitting calibration component of a low-orbit satellite phased array antenna calibration device is provided for Embodiment 1;

[0055] Fig. 3 A schematic diagram of a common calibration antenna of a low-orbit satellite phased array antenna calibration device is provided for Embodiment 1;

[0056] Fig. 4 A schematic diagram of a receiving calibration component of a low-orbit satellite phased array antenna calibration device is provided for Embodiment 2;

[0057] Fig. 5 A flowchart of a transmitting calibration component of a low-orbit satellite phased array antenna calibration device is provided for Embodiment 2;

[0058] Fig. 6 A flowchart of a common first processor of a low-orbit satellite phased array antenna calibration device is provided for Embodiment 2.

[0059] Markings in the drawings and corresponding names of parts:

[0060] 1 - transmitting array element, 2 - duplexer, 3 - transmitting calibration component, 31 - first calibration integrated circuit, 311 - first processor, 312 - first signal source chip, 313 - first analog-to-digital converter, 314 - first switch, 32 - first test circuit, 321 - transmitting channel, 322 - first digitally controlled attenuator, 33 - first reference circuit, 331 - first attenuator, 4 - receiving calibration component, 41 - second calibration integrated circuit, 411 - second processor, 412 - second signal source chip, 413 - second analog-to-digital converter, 414 - second switch, 42 - second test circuit, 421 - second digitally controlled attenuator, 422 - receiving channel, 423 - third digitally controlled attenuator, 43 - second reference circuit, 431 - second attenuator, 5 - receiving array element, 6 - calibration antenna. DETAILED DESCRIPTION

[0061] In order to make the objects, technical solutions and advantages of the present application clearer, further detailed description will be made to the present application in combination with embodiments and drawings, the illustrative embodiments and the description thereof are only used to explain the present application, and do not limit the present application.

[0062] Embodiment 1

[0063] As Figs. 1-3 Embodiment 1 provides a low-orbit satellite phased array antenna calibration device, which comprises a calibration antenna 6, a diplexer, a transmitting calibration component 3 and a receiving calibration component 4.

[0064] The calibration antenna 6 is connected with the transmitting calibration component 3 and the receiving calibration component 4 through the diplexer 2.

[0065] The transmitting calibration component 3 comprises a first calibration integrated circuit 31, a first test circuit 32 and a first reference circuit 33.

[0066] The first calibration integrated circuit 31 is connected with the first test circuit 32 in series through the power divider and the calibration antenna 6 to form a closed loop, and the first calibration integrated circuit 31 is connected with the first reference circuit 33 in series through the power divider to form a closed loop; the first calibration integrated circuit 31 is used to calculate compensation amplitude and phase values according to comparison of amplitudes and phases between the first test circuit 32 and the first reference circuit 33.

[0067] The first calibration integrated circuit 31 comprises a first processor 311 with FPGA as the core.

[0068] The first calibration integrated circuit 31 further comprises a first signal source chip 312 and a first analog-to-digital converter 313; one end of the first signal source chip 312 is electrically connected with a frequency divider in the first processor 311, and the other end is electrically connected with the power divider; the first processor 311 is used to generate a calibration signal through driving the first signal source chip 312, and send the calibration signal into the first test circuit 32 and the first reference circuit 33 through the power divider; one end of the first analog-to-digital converter 313 is connected with the first processor 311, and the other end is connected with a first switch 314; the first switch 314 is used to select connection with the first test circuit 32 or the first reference circuit 33 according to the first processor 311.

[0069] The first test circuit 32 comprises a transmitting channel 321; one end of the transmitting channel 321 is connected with the power divider, and the other end is connected with a transmitting array element 1; the transmitting array element 1 is wirelessly connected with the calibration antenna 6; the calibration antenna 6 is electrically connected with a first digital control attenuator 322; the first digital control attenuator 322 is electrically connected with the first switch 314.

[0070] The first reference circuit 33 comprises a first attenuator 331 for adjusting the signal size, one end of which is connected with the power divider, and the other end is electrically connected with the first switch 314.

[0071] In a specific embodiment, the calibration antenna 6 is connected with the transmitting calibration component 3 and the receiving calibration component 4 through the duplexer 2, and the transmitting calibration component 3 and the receiving calibration component 4 share the same calibration antenna 6, which reduces the cost and simplifies the device.

[0072] The first processor 311 is an FPGA-based first processor 311, which is internally provided with a frequency divider, the frequency divider is a DDS (Direct Digital Synthesizer), the frequency divider is controlled by programming the first processor 311, the frequency divider is connected with the first signal source chip 312, the first signal source is an ADRV9009 analog-to-digital converter, the frequency divider in the first processor 311 drives the TX2 channel DAC of the ADRV9009 to generate a single-tone signal as a calibration signal, the calibration signal is divided into two paths by the power divider, one path is a test signal sent to the first test circuit 32, and the other path is a reference signal sent to the first reference circuit 33.

[0073] The test signal is sent to the first test circuit 32, the test signal passes through the transmitting channel 321 and is radiated to the calibration antenna 6 through the transmitting array element 1, the single-tone calibration signal received by the calibration antenna 6 passes through the duplexer 2, the first digital attenuator 322, the first switch 314 and the first analog-to-digital converter 313 in turn, wherein the first switch 314 is used to select the ADC signal entering the RX1 channel of the first analog-to-digital converter 313, the switching of the first reference circuit 33 and the first test circuit 32 is performed in time, the first digital attenuator 322 is used to adjust the power size of the test signal, the first digital attenuator 322 is connected with the first analog-to-digital converter 313, and the first analog-to-digital converter 313 samples the test signal sent by the test circuit to the first calibration integrated circuit 31 for processing.

[0074] The reference signal is sent to the first reference circuit 33 for self-calibration and then sent to the first calibration integrated circuit 31 for processing.

[0075] The first calibration integrated circuit 31 calculates the amplitude and phase of the transmitting channel 321 by comparing the received test signal and the reference signal, and repeatedly calculates until the amplitudes and phases of all transmitting channels 321 are obtained, and then performs normalization processing to obtain the compensation amplitude and phase values of each transmitting channel 321.

[0076] Embodiment 2

[0077] As Figs. 4-6, embodiment 2 provides a receiving calibration component 4 of a low-orbit satellite phased array antenna calibration device on the basis of embodiment 1, and the second calibration integrated circuit 41 comprises a second processor 411 taking FPGA as a core.

[0078] The second calibration integrated circuit 41 further comprises a second signal source chip 412 and a second analog-to-digital converter 413.

[0079] One end of the second signal source chip 412 is electrically connected with a frequency divider in the second processor 411, and the other end is electrically connected with a power divider; the second processor 411 is used for generating a calibration signal by driving the second signal source chip 412, and sending the calibration signal into the second test circuit 42 and the second reference circuit 43 through the power divider.

[0080] One end of the second analog-to-digital converter 413 is connected with the second processor 411, and the other end is connected with a second switch 414; the second switch 414 is used for selecting to be connected with the second test circuit 42 or the second reference circuit 43 according to the second processor 411.

[0081] The second test circuit 42 comprises a first digital attenuator 322.

[0082] One end of the second digital attenuator 421 is connected with the power divider, and the other end is connected with a calibration antenna 6; the calibration antenna 6 is wirelessly connected with a receiving array element 5; the receiving array element 5 is electrically connected with a receiving channel 422; the receiving channel 422 is connected with a third digital attenuator 423; and the third digital attenuator 423 is electrically connected with the second switch 414.

[0083] The second reference circuit 43 comprises a second attenuator 431 for adjusting signal size; one end of the second attenuator 431 is connected with the power divider, and the other end is electrically connected with the second switch 414.

[0084] In a specific embodiment, the second processor 411 is an FPGA-based second processor 411. The FPGA is a programmable gate array, which is a kind of semi-custom circuit in the field of application-specific integrated circuit, that is, it solves the shortcomings of custom circuits and overcomes the limitation of the number of gate circuits of the original programmable device. The second processor 411 has a frequency divider built-in. The frequency divider is a DDS direct digital frequency synthesizer. The frequency divider is connected with the second signal source chip 412. The second signal source is an ADRV9009 analog-to-digital converter. The frequency divider in the second processor 411 drives the TX1 channel DAC of the ADRV9009 to generate a calibration signal, and converts the calibration signal into an analog signal. The calibration signal is divided into two paths by a power divider. One path is a test signal sent to the second test circuit 42, and the other path is a reference signal sent to the second reference circuit 43.

[0085] The test signal converted into an analog signal by the TX1 channel of the second signal source is radiated outward to the receiving array element 5 through the second digital attenuator 421 and the calibration antenna 6. The receiving array element 5 sequentially passes the received test signal through the receiving channel 422, the third digital attenuator 423, the second switch 414, and the second analog-to-digital converter 413 to the second processor 411. The second switch 414 is used to select the ADC signal of the RX1 channel entering the second analog-to-digital converter 413, and switch the second reference circuit 43 and the second test circuit 42 in time. The second digital attenuator 421 is used to adjust the power of the test signal. The third digital attenuator 423 is used to adjust the size of the signal entering the second analog-to-digital converter 413.

[0086] The reference signal enters the second reference circuit 43 for self-calibration and is sent to the second calibration integrated circuit 41 for processing.

[0087] The second calibration integrated circuit 41 calculates the amplitude and phase of the receiving channel 422 by comparing the received test signal and the reference signal, and repeats the calculation multiple times until the amplitudes and phases of all receiving channels 422 are obtained. After normalization processing, the compensation amplitude and phase values of each receiving channel 422 are obtained.

[0088] The first calibration integrated circuit 31 is multiplexed by a baseband FPGA. The first calibration integrated circuit 31 is connected in series with the second test circuit 42 through a power divider to form a closed loop.

[0089] The first calibration integrated circuit 31 is connected in series with the second reference circuit 43 through a power divider to form a closed loop. The first calibration integrated circuit 31 is used to calculate the compensation amplitude and phase values according to the comparison of the amplitudes and phases between the second test circuit 42 and the second reference circuit 43.

[0090] In a specific embodiment, the first calibration integrated circuit 31 comprises a first processor 311 with a FPGA core, a first signal source chip 312, and a first analog-to-digital converter 313; the first test circuit 32 and the second test circuit 42 form a closed loop with the first calibration integrated circuit 31; the first test circuit 32 and the second test circuit 42 share the first processor 311, the first signal source chip 312, and the first analog-to-digital converter 313; and the device cost is saved.

[0091] The first reference circuit 33 and the second reference circuit 43 form a closed loop with the second calibration integrated circuit 41; the first reference circuit 33 and the second reference circuit 43 share the first processor 311, the first signal source chip 312, and the first analog-to-digital converter 313; and the device cost is saved.

[0092] The above detailed description of the specific embodiments has further detailed the purposes, technical solutions, and beneficial effects of the present application. It should be understood that the above detailed description is only a specific embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A low earth orbit satellite phased array antenna calibration apparatus, characterized by, The calibration antenna (6), the duplexer (2), the transmitting calibration component (3) and the receiving calibration component (4) are included. The calibration antenna (6) is connected with the transmitting calibration component (3) and the receiving calibration component (4) through the duplexer (2), and the transmitting calibration component (3) and the receiving calibration component (4) share the calibration antenna (6). The transmitting calibration component (3) includes a first calibration integrated circuit (31), a first test circuit (32) and a first reference circuit (33). The first calibration integrated circuit (31) takes FPGA as a core, and forms a closed loop by being connected with the first reference circuit (33) and the first test circuit (32) through a power divider, the first reference circuit (33) includes a first attenuator (331) for self-calibrating a reference signal to form a standard signal, and the first calibration integrated circuit (31) is used for comparing the amplitude and the phase between the first test circuit (32) and the first reference circuit (33). The receiving calibration component (4) includes a second calibration integrated circuit (41), a second test circuit (42) and a second reference circuit (43). The second calibration integrated circuit (41) takes FPGA as a core, and forms a closed loop by being connected with the second reference circuit (43) and the second test circuit (42) through a power divider, the second reference circuit (43) includes a second attenuator (431) for self-calibrating a reference signal to form a standard signal, and the second calibration integrated circuit (41) is used for comparing the amplitude and the phase between the second test circuit (42) and the second reference circuit (43). The first calibration integrated circuit (31) is multiplexed through a baseband FPGA, and the first calibration integrated circuit (31) is connected with the second test circuit (42) and the second reference circuit (43) through a power divider to form a closed loop.

2. The low earth orbit satellite phased array antenna calibration apparatus of claim 1, wherein, The first calibration integrated circuit (31) includes a first processor (311) taking FPGA as a core.

3. The low earth orbit satellite phased array antenna calibration apparatus of claim 2, wherein, The first calibration integrated circuit (31) further includes a first signal source chip (312) and a first analog-to-digital converter (313). One end of the first signal source chip (312) is electrically connected with a frequency divider in the first processor (311), and the other end is electrically connected with a power divider, the first processor (311) is used for generating a calibration signal by driving the first signal source chip (312), and the calibration signal is sent into the first test circuit (32) and the first reference circuit (33) through the power divider. The first analog-to-digital converter (313) is connected with the first processor (311) at one end, and is connected with a first switch (314) at the other end, the first switch (314) is used for selecting to be connected with the first test circuit (32) or the first reference circuit (33) according to the first processor (311).

4. The low earth orbit satellite phased array antenna calibration apparatus of claim 3, wherein, The first test circuit (32) includes a transmitting channel (321). The transmitting channel (321) is connected with the power divider at one end and connected with the transmitting array element (1) at the other end; the transmitting array element (1) is wirelessly connected with the calibration antenna (6); the calibration antenna (6) is electrically connected with the first digital control attenuator (322), and the first digital control attenuator (322) is electrically connected with the first switch (314).

5. The low earth orbit satellite phased array antenna calibration apparatus of claim 4, wherein, The first attenuator (331) is connected with the power divider at one end and electrically connected with the first switch (314) at the other end.

6. The low earth orbit satellite phased array antenna calibration apparatus of claim 1, wherein, The second calibration integrated circuit (41) comprises a second processor (411) taking FPGA as the core.

7. The low earth orbit satellite phased array antenna calibration apparatus of claim 6, wherein, The second calibration integrated circuit (41) further comprises a second signal source chip (412) and a second analog-to-digital converter (413). The second signal source chip (412) is electrically connected with the frequency divider in the second processor (411) at one end and electrically connected with the power divider at the other end; the second processor (411) is used to generate the calibration signal by driving the second signal source chip (412) and send the calibration signal into the second test circuit (42) and the second reference circuit (43) through the power divider; The second analog-to-digital converter (413) is connected with the second processor (411) at one end and connected with the second switch (414) at the other end, and the second switch (414) is used to select the connection with the second test circuit (42) or the second reference circuit (43) according to the second processor (411).

8. The low earth orbit satellite phased array antenna calibration apparatus of claim 7, wherein, The second test circuit (42) comprises a second digital control attenuator (421). The second digital control attenuator (421) is connected with the power divider at one end and connected with the calibration antenna (6) at the other end; the calibration antenna (6) is wirelessly connected with the receiving array element (5), the receiving array element (5) is electrically connected with the receiving channel (422), the receiving channel (422) is connected with the third digital control attenuator (423), and the third digital control attenuator (423) is electrically connected with the second switch (414).

9. The low earth orbit satellite phased array antenna calibration apparatus of claim 8, wherein, The second attenuator (431) is connected with the power divider at one end and electrically connected with the second switch (414) at the other end.

10. The low earth orbit satellite phased array antenna calibration apparatus of claim 5, wherein, The first calibration integrated circuit (31) is used to compare the amplitude and phase between the second test circuit (42) and the second reference circuit (43) and calculate the compensation amplitude and phase value.

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