A method of forming a semiconductor device

Abstract

The application discloses a forming method of a semiconductor device, which comprises the following steps: providing a substrate, a surface of the substrate comprises an oxidation layer and a non-oxidation layer arranged around the oxidation layer; bombarding: bombarding the surface of the oxidation layer by using a bombarding ion to form Si-O dangling bonds on the surface; depositing: inputting an etching gas, the etching gas forms a bonding layer on the surface of the oxidation layer and the Si-O dangling bonds, and forms a fluorocarbon polymer layer on the surface of the non-oxidation layer; and cleaning: inputting a bombarding gas, and using the energy provided by the bombarding gas to make the Si-O dangling bonds in the bonding layer react with the precursor of the etching gas to form a volatile gas. The method provided by the application improves the etching selectivity ratio of silicon oxide to silicon nitride and polysilicon, the formed fluorocarbon polymer layer can protect the silicon nitride and the polysilicon from being damaged by ion bombardment, meanwhile, the precise control of the etching morphology is realized, and the method is suitable for etching the silicon oxide at different positions of a 3D NAND memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a forming method of a semiconductor device. BACKGROUND

[0002] NAND flash is a kind of storage device. At present, the planar structure NAND flash is close to the limit of practical expansion, in order to further improve the storage capacity and reduce the storage cost per bit, the 3D NAND memory with 3D structure is proposed.

[0003] The forming process of the existing 3D NAND memory generally includes: alternately depositing silicon nitride and silicon oxide on the substrate to form a stack layer, etching a through hole in the stack layer, filling silicon nitride, polysilicon and silicon oxide in the through hole, and finally replacing the silicon nitride with metal.

[0004] According to the requirements of circuit connection, it is necessary to etch the silicon oxide located in the through hole or the silicon oxide located on the surface of the stack layer in the periphery of the through hole, without damaging the silicon nitride and polysilicon in the through hole. The traditional planar structure NAND is formed by stacking silicon oxide, silicon nitride and polysilicon along the horizontal direction, and it is easy to realize the etching of silicon oxide by passing in macromolecular C4F6. However, the silicon nitride and polysilicon of the 3D NAND memory are arranged along the vertical direction, and directly passing in fluorocarbon gas to etch silicon oxide will expose a large area of silicon nitride and polysilicon to the etching gas, causing strong ion bombardment, resulting in device damage and affecting its electrical performance. Wet etching can achieve high etching selectivity of silicon oxide to silicon nitride and polysilicon, without causing strong bombardment to silicon nitride and polysilicon, but it is difficult to achieve precise control of the device topography in etching. SUMMARY

[0005] The purpose of the present application is to improve the high etching selectivity of silicon oxide to silicon nitride and polysilicon, while reducing the damage caused by etching to silicon nitride and polysilicon.

[0006] In order to achieve the above purpose, the present application provides a forming method of a semiconductor device, comprising:

[0007] providing a substrate, the surface of the substrate comprising an oxide layer and a non-oxide layer arranged around the oxide layer;

[0008] bombardment: using a bombardment ion to bombard the surface of the oxide layer to form Si-O dangling bonds on the surface thereof;

[0009] deposition: passing in etching gas, the etching gas forming a bonding layer on the surface of the oxide layer and the Si-O dangling bonds, and forming a fluorocarbon polymer layer on the surface of the non-oxide layer;

[0010] Cleaning: the bombardment gas is introduced, and the Si-O dangling bonds in the bonding layer react with the precursor in the etching gas to form a volatile gas by using the energy provided by the bombardment gas.

[0011] Optionally, the substrate comprises a stack layer, a dielectric layer on the surface of the stack layer, and a through hole penetrating through the stack layer and the dielectric layer, and from the center to the outside of the through hole, the silicon oxide layer, the polysilicon layer, the silicon oxide layer, the silicon nitride layer and the silicon oxide layer are arranged in sequence in the circumferential direction; the material of the dielectric layer is silicon oxide.

[0012] Optionally, the thickness of the silicon oxide layer is equal to the depth of the through hole; the surface of the silicon oxide layer and the dielectric layer forms the Si-O dangling bond.

[0013] Optionally, the thickness of the silicon oxide layer is less than the depth of the through hole, a groove is formed above the silicon oxide layer, and the polysilicon layer is formed in the groove; the dielectric layer is the oxide layer.

[0014] Optionally, the method for forming the Si-O dangling bond comprises: introducing a bombardment gas to the surface of the substrate, the bombardment gas forms bombardment positive ions under the action of radio frequency power, the bombardment positive ions bombard the surface of the oxide layer to form the Si-O dangling bond.

[0015] Optionally, the bombardment gas is an inert gas.

[0016] Optionally, the inert gas is one or more of Ar, Kr or Xe.

[0017] Optionally, after the etching gas is introduced, the etching gas is decomposed into a precursor, and the precursor forms a fluorocarbon polymer on the surface of the oxide layer and the non-oxide layer.

[0018] Optionally, the etching gas is a fluorocarbon gas C x F y , wherein x and y represent the number of carbon and fluorine atoms, and x≥2.

[0019] Optionally, the fluorocarbon gas comprises one or more of C2F4, C2F6, C3F6, C3F8, C4F6 or C4F8.

[0020] Optionally, the etching gas does not contain hydrogen element.

[0021] Optionally, the volatile gas comprises SiF4 and CO.

[0022] Optionally, when the fluorocarbon polymer is formed, the dilution gas is introduced; the dilution gas comprises an inert gas.

[0023] Optionally, the deposition and removal constitute a cycle, and the method for forming the semiconductor device comprises several cycles.

[0024] Optionally, the conditions for exciting the formation of the bombardment positive ions and the decomposition of the etching gas into the precursor are: pressure 15-30 mTorr, frequency 40 Mhz-100 Mhz, and radio frequency power 500 w-700 w.

[0025] Optionally, the flow rate of the bombardment gas is 700 sccm-1000 sccm.

[0026] Optionally, the operation time of the bombardment process is 4-8 s.

[0027] Optionally, the etching gas is composed of several gaseous pure substances, and the flow rate of any gaseous pure substance is 0-5 sccm.

[0028] Optionally, the ratio of the operation time of the deposition and removal process is (0.3-0.75):1.

[0029] Optionally, the flow rate ratio of the etching gas and the dilution gas is: 1:200-1:500.

[0030] Compared with the prior art, the present application has the following beneficial effects:

[0031] The method for forming the semiconductor device provided by the present application first bombards the surface of the oxide layer with bombardment ions to form Si-O dangling bonds on the surface, then the etching gas is introduced, the precursor of the etching gas combines with the Si-O dangling bonds to form a combination layer, and the etching gas forms a fluorocarbon polymer on the surface of the non-oxide layer, and then the Si-O dangling bonds in the combination layer react with the precursor of the etching gas to form a volatile gas under the energy provided by the bombardment gas, so that the oxide layer is exposed, the oxide layer is etched by the bombardment gas, and the fluorocarbon polymer on the surface of the non-oxide layer is difficult to remove and is used to protect the surface of the non-oxide layer, so that the non-oxide layer is not etched by the bombardment gas. It can be seen that the oxide layer and the non-oxide layer have a strong etching selectivity, and the etching morphology can be accurately controlled. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a schematic diagram of a 3D NAND memory structure.

[0033] Figure 2 It is a flow chart of the method for forming the semiconductor device provided by the present application.

[0034] Figure 3 It is a schematic diagram of the forming process of the semiconductor device provided by the present application.

[0035] Figure 4A schematic diagram of a semiconductor device according to Embodiment 1 of the present application.

[0036] Figure 5 A schematic diagram of a semiconductor device according to Embodiment 2 of the present application.

[0037] Figure 6 A schematic diagram of an etching effect of a semiconductor device obtained by using the method according to Embodiment 2 of the present application.

[0038] Figure 7 A schematic diagram of an etching effect of a semiconductor device obtained by using the method according to the comparative example of the present application.

[0039] In the figure, 1 is a dielectric layer, 2 is a stack layer, 3 is a memory cell, 31 is a silicon oxide layer, 310 is a central silicon oxide layer, 311 is a peripheral silicon oxide layer, 3111 is a first peripheral silicon oxide layer, 3112 is a second peripheral silicon oxide layer, 32 is a polysilicon layer, 33 is a silicon nitride layer, 4 is an oxide layer, 6 is a bombardment gas, 7 is an etching gas, 81 is a fluorocarbon polymer layer, 82 is a bonding layer, and 9 is a groove. DETAILED DESCRIPTION

[0040] The technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0041] As shown in Figure 1 , a 3D NAND memory is composed of a dielectric layer 1, a stack layer 2, and a memory cell 3. The stack layer 2 includes silicon oxide and silicon nitride alternately stacked in sequence, the dielectric layer 1 is located on the surface of the stack layer 2, and the material of the dielectric layer 1 is silicon oxide. A via hole is etched in the direction perpendicular to the dielectric layer 1 and the stack layer 2, and the via hole is filled with silicon nitride, polysilicon, and silicon oxide as the memory cell 3. Figure 1 In an embodiment as shown in , the memory cell 3 is composed of a silicon oxide layer 31, a polysilicon layer 32, a silicon oxide layer 31, a silicon nitride layer 33, and a silicon oxide layer 31 arranged in sequence from the center of the via hole to the inner sidewall of the via hole. In an embodiment, the silicon oxide layer 31 at the center position of the dielectric layer 1 or the memory cell 3 of the 3D NAND memory needs to be etched.

[0042] Figure 2 and Figure 3 , the method for forming a semiconductor device provided by the present application includes the following steps:

[0043] Step S1, bombardment: introducing a bombardment gas 6 to bombard the surface of the silicon oxide, and forming Si-O dangling bonds on the surface of the silicon oxide.

[0044] In some embodiments, the bombardment gas 6 is excited to form a plasma, the bombardment gas 6 forms bombardment positive ions, the Si-O-Si bonds on the surface of the silicon oxide are bombarded by the bombardment positive ions, the Si-O-Si bonds are broken, and a large number of Si-O dangling bonds are formed; the conditions for exciting the bombardment gas 6 to form a plasma containing bombardment positive ions are: pressure 15-30 mTorr, frequency 40-100 Mhz, and radio frequency power 500-700 w.

[0045] In some embodiments, the bombardment gas 6 is an inert gas, which can be selected from one or more of Ar, Kr, or Xe.

[0046] In some embodiments, the operation time of the bombardment process of S1 is 4-8 s.

[0047] In step S2, deposition: the bombardment gas 6 is continuously introduced, and the etching gas 7 is also introduced; the precursor of the etching gas 7 first combines with the Si-O dangling bonds on the surface of the silicon oxide to form a combination layer 82, and then the precursor of the etching gas 7 forms a fluorocarbon polymer layer 81 on the surface of the combination layer 82; the fluorocarbon polymer layer 81 is deposited on the surfaces of the polysilicon and the silicon nitride.

[0048] In some embodiments, the etching gas 7 is a fluorocarbon gas C x F y , wherein x and y represent the number of carbon and fluorine atoms, and x≥2; the fluorocarbon gas is excited to form a plasma to provide energy for the fluorocarbon gas, so that the fluorocarbon gas is decomposed into short-chain fluorocarbon precursors C m F n , wherein m and n represent the number of carbon and fluorine atoms, and 0 m F n , respectively, on the surfaces of the silicon oxide, the silicon nitride, and the polysilicon; the C m F n combines with the Si-O dangling bonds to form the combination layer 82; the C m F n forms the fluorocarbon polymer layer 81, covering the polysilicon and the silicon nitride to protect the polysilicon and the silicon nitride from the subsequent cleaning step.

[0049] In some embodiments, the fluorocarbon gas contains one or more of C2F4, C2F6, C3F6, C3F8, C4F6, or C4F8.

[0050] In some embodiments, the etching gas 7 does not contain hydrogen. Etching gas containing hydrogen may combine with silicon nitride to form cyanide, causing damage to the silicon nitride layer.

[0051] In some embodiments, the etching gas 7 is composed of a plurality of pure gaseous substances, and the flow rate of any of the pure gaseous substances is 0-5 sccm.

[0052] In one embodiment, when forming the fluorocarbon polymer, the dilution gas is also introduced; the dilution gas includes an inert gas. The flow ratio of the etching gas to the dilution gas is: 1:200 to 1:500. The larger the flow of the dilution gas, the more conducive it is to fully dilute the etching gas to form a bonding layer 82 and a fluorocarbon polymer layer 81 with uniform thickness; the smaller the flow of the etching gas, the less likely it is to form a fluorocarbon polymer layer 81 that is too thick, which is conducive to the energy provided by the subsequent bombardment gas to be transferred to the bonding layer 82, and to the Si-O dangling bonds in the bonding layer 82 and the fluorocarbon precursor C m F n Reacts to form volatile gases.

[0053] Step S3, clearing: stop the introduction of etching gas 7 and continue to introduce bombardment gas 6, using the energy provided by bombardment gas 6 to make the Si-O dangling bonds in the bonding layer 82 and the carbon fluorine precursor C m F n Reacts to form volatile gases.

[0054] In some embodiments, the bombardment gas 6 is excited into plasma to form bombardment positive ions. The conditions for exciting the bombardment gas 6 to form plasma containing bombardment positive ions are: pressure 15-30 mTorr, frequency 40-100 MHz, and RF power 500-700 W.

[0055] The bombarding positive ions carry energy, which is transferred to the bonding layer 82 through the fluorocarbon polymer layer 81, causing the C m F n After being physically bombarded, the Si-O dangling bonds receive the energy transferred by the bombarding positive ions and react to form volatile gases. The volatile gases include SiF4 and CO. The bonding layer 82 on the surface of the silicon oxide is removed, and the fluorocarbon polymer layer 81 on the bonding layer 82 also falls off and is removed. The silicon oxide is bombarded and removed by the bombarding positive ions. In the above step S2, the fluorocarbon polymer layer 81 covering the surface of the polysilicon and silicon nitride is not removed. Therefore, the polysilicon and silicon nitride can be protected from the physical bombardment of the bombarding positive ions. Utilizing the protective effect of the fluorocarbon polymer 81, the silicon oxide has a higher etching selectivity to the polysilicon and silicon nitride.

[0056] In some embodiments, the deposition step S2 and the cleaning step S3 are alternately performed for multiple cycles to precisely control the etching profile and etching depth of the oxide layer, and the operation time ratio of the deposition and cleaning processes is (0.3-0.75):1.

[0057] The above steps S1, S2 and S3 always keep a large flow rate of the bombardment gas 6; the bombardment gas 6 can continuously provide energy for the Si-O-Si bond breakage to form Si-O dangling bonds in steps S1, S2 and S3, in addition, the bombardment gas can also play a role in diluting the etching gas 7 in step S2, and can also provide energy for the mutual combination of the fluorocarbon polymer and the Si-O dangling bond in step S3 to form a volatile gas, thereby achieving the purpose of etching the oxide layer; optionally, the flow rate of the bombardment gas 6 is always kept at 700-1000sccm.

[0058] Embodiment 1

[0059] As shown in Figure 4 , the embodiment provides a method for etching a center silicon oxide layer 310 of a 3D NAND memory cell 3 to obtain a semiconductor device.

[0060] Step S1, bombardment: Ar gas is introduced as a bombardment gas at a flow rate of 800sccm, and the Ar gas is excited into a plasma under the conditions of a pressure of 20mTorr, a frequency of 60Mhz and a radio frequency power of 600w, the plasma contains Ar positive ions, and the Si-O-Si bonds on the surface of the center silicon oxide layer 310 are bombarded by the Ar positive ions to form Si-O dangling bonds on the surface of the silicon oxide layer 31.

[0061] Step S2, deposition: continue to introduce Ar gas as a dilution gas at a flow rate of 800sccm, and introduce C4F8 as an etching gas at a flow rate of 3sccm, excite the Ar gas and C4F8 into a plasma under the conditions of a pressure of 20mTorr, a frequency of 60Mhz and a radio frequency power of 600w, the etching gas C4F8 can be decomposed into short-chain fluorocarbon precursors, the fluorocarbon precursors are deposited on the center silicon oxide layer 310, combined with the Si-O dangling bonds to form a combined layer, and then deposited on the surface of the combined layer to form a fluorocarbon polymer layer; the fluorocarbon precursors are deposited on the surfaces of the polysilicon layer 32 and the silicon nitride layer 33 to form a fluorocarbon polymer layer.

[0062] Step S3, clearing: stop introducing C4F8 and continue to introduce Ar gas at a flow rate of 800sccm. Under the conditions of pressure 20mTorr, frequency 60MHz, and RF power 600W, the Ar gas is excited into plasma. After receiving the energy provided by the physical bombardment of the Ar gas, the precursor of the etching gas C4F8 in the bonding layer forms volatile gases SiF4 and CO with the Si-O dangling bonds, and the bonding layer is removed. The fluorocarbon polymer layer on the bonding layer also falls off and is removed, so that the silicon oxide layer 31 is etched.

[0063] In the above process, step S1 is first executed for 6 seconds, and then steps S2 and S3 are alternately executed in a cycle with an operating time ratio of 0.5:1 until the etching depth of the central silicon oxide layer 310 in the vertical direction reaches the set requirement.

[0064] The purpose of this embodiment is to etch the central silicon oxide layer 310 of the memory cell 3. Since the dielectric layer 1 also contains silicon oxide, the surface of the dielectric layer 1 will also form Si-O dangling bonds and combine with the carbon fluorine precursor, and then receive the bombardment energy of the Ar gas to form volatile gases. Therefore, in the initial stage of the cycle of steps S2 and S3, the silicon oxide on the surface of the dielectric layer 1 will inevitably be thinned at the same etching rate as the silicon oxide layer 31 at the center of the memory cell 3; as the number of cycles increases, a groove 9 will be formed in the silicon oxide layer 31 at the center of the memory cell 3. Compared with the surface of the dielectric layer 1, the silicon oxide on the inner side wall of the groove 9 has a higher surface area than that of the dielectric layer 1. The area is larger, so that the thickness of the fluorocarbon polymer layer formed on the central silicon oxide layer 310 is smaller than the thickness of the fluorocarbon polymer layer on the edge dielectric layer 1. Then, the fluorocarbon polymer layer of the central silicon oxide layer 310 is easier to remove than the fluorocarbon polymer layer on the dielectric layer 1, so that the central silicon oxide layer 310 is easy to be exposed, while the fluorocarbon polymer layer on the dielectric layer 1 is not easy to be removed. Therefore, the etching speed at the central silicon oxide layer 310 will become faster and faster, so that the etching depth of the central silicon oxide layer 310 can quickly reach the requirement, thereby reducing the loss of silicon oxide on the surface of the dielectric layer 1.

[0065] The silicon oxide layer 31 in the memory cell 3 includes a central silicon oxide layer 310 and a peripheral silicon oxide layer 311. Since a fluorocarbon polymer layer will continuously accumulate on the surface of the polysilicon layer 32 and the silicon nitride layer 33, and the thickness of the polysilicon layer 32 and the silicon nitride layer 33 is relatively thin, when the fluorocarbon polymer layer accumulated on them reaches a certain height, it will overflow to both sides and spread to the surface of the peripheral silicon oxide layer 311, so that a higher fluorocarbon polymer layer is also accumulated on the peripheral silicon oxide layer 311, and the peripheral silicon oxide layer 311 is not easily etched. Furthermore, for the fluorocarbon gas C x F yThe smaller the values of x and y, the shorter the carbon chain, the more active the carbon fluoride gas, and the stronger the ability to combine with the Si-O dangling bond. Therefore, in the initial stage of the cycle of steps S2 and S3, a carbon fluoride gas with a longer carbon chain can be selected as the etching gas in step S2; and as the cycle number increases, the etching gas can be replaced by a carbon fluoride gas with a shorter carbon chain to improve the etching depth.

[0066] Embodiment 2

[0067] As shown in Figure 5 , the embodiment provides a method for etching a 3D NAND memory medium layer 1 (as shown in Figure 1 ) to obtain a semiconductor device.

[0068] Before the process is run, the recess 9 corresponding to the silicon oxide layer 31 is filled with polysilicon to protect the silicon oxide layer 31 at the center position from being etched.

[0069] Step S1, bombardment: Kr gas is introduced as a bombardment gas at a flow rate of 900 sccm, and the Kr gas is excited into a plasma under the conditions of a pressure of 30 mTorr, a frequency of 70 Mhz, and a radio frequency power of 500 w, the plasma containing Kr positive ions, and the Si-O-Si bonds on the surface of the medium layer 1 are bombarded by the Kr positive ions to form Si-O dangling bonds on the surface of the medium layer 1.

[0070] Step S2, deposition: Kr gas is continuously introduced as a dilution gas at a flow rate of 900 sccm, and a mixed gas of C4F6 and C4F8 is introduced as an etching gas, the flow rate of C4F6 being 4 sccm and the flow rate of C4F8 being 4 sccm, and the Kr gas, C4F6 and C4F8 are excited into a plasma under the conditions of a pressure of 30 mTorr, a frequency of 70 Mhz, and a radio frequency power of 500 w, the etching gas C4F6 and C4F8 being able to be decomposed into short-chain carbon fluoride precursors, the carbon fluoride precursors being deposited on the medium layer 1, combining with the Si-O dangling bonds to form a combination layer, and then being deposited on the surface of the combination layer to form a carbon fluoride polymer layer; and the surfaces of the polysilicon layer 32 and the silicon nitride layer 33 are deposited with the carbon fluoride polymer layer.

[0071] Step S3, cleaning: the introduction of C4F6 and C4F8 is stopped, and Kr gas is continuously introduced at a flow rate of 900 sccm, and the Kr gas is excited into a plasma under the conditions of a pressure of 30 mTorr, a frequency of 70 Mhz, and a radio frequency power of 500 w, after the combination layer receives the energy provided by the physical bombardment of the Kr gas, the precursors of the etching gas C4F6 and C4F8 in the combination layer form volatile gases SiF4 and CO with the Si-O dangling bonds, the combination layer is removed, and the carbon fluoride polymer layer on the combination layer also falls off and is removed, so that the medium layer 1 is etched.

[0072] In the above steps, first, step S1 is run for 8 seconds, and then steps S2 and S3 are alternately run in a cycle with a run time of 0.6:1 until the medium layer 1 is completely etched.

[0073] The peripheral silicon oxide layer 311 includes a first peripheral silicon oxide layer 3111 disposed between the polysilicon layer 32 and the silicon nitride layer 33 and a second peripheral silicon oxide layer 3112 disposed at the outermost side of the memory cell 3. As described above, due to the overflow of the fluorocarbon polymer layer on the surfaces of the polysilicon layer 32 and the silicon nitride layer 33, the surfaces of the first peripheral silicon oxide layer 3111 and the second peripheral silicon oxide layer 3112 will also accumulate the overflowed fluorocarbon polymer layer. However, as the medium layer 1 is thinned by etching, the sidewall of the second peripheral silicon oxide layer 3112 is exposed to the etching environment, the binding layer formed on the sidewall is subjected to the energy of the Kr gas, forms a volatile gas and is etched, and the etching depth of the second peripheral silicon oxide layer 3112 is close to the etching depth of the medium layer 1. Therefore, after the etching depth of the medium layer 1 reaches the required value, the second peripheral silicon oxide layer 3112 can be further filled as needed.

[0074] The 3D NAND memory medium layer 1 is etched by using the conventional CCP method, which is a comparative example (as shown in FIG. 6). Figure 7 The method used in the comparative example is as follows: the etching gas composed of C4F6, O2 and Ar is introduced into the 3D NAND, and is excited into plasma to etch the medium layer 1 until the medium layer 1 is etched to a specified thickness.

[0075] Figure 6 The schematic diagram of the memory cell 3 after the medium layer 1 is etched by using the method provided in Example 2 is shown in FIG. 5. Figure 6 As shown in FIG. 5, after the etching is completed, the height of the memory cell 3 almost does not change (the dashed line on the upper side in the figure is the height of the memory cell 3 before the etching process starts), which indicates that the polysilicon and the silicon nitride on the top and the sidewall of the memory cell 3 are perfectly protected and do not have obvious defects.

[0076] Figure 7 The schematic diagram of the memory cell 3 after the medium layer 1 is etched by using the existing method is shown in FIG. 6. Figure 7 As shown in FIG. 6, compared with before the etching, the height of the memory cell 3 is reduced due to the etching, and there are obvious depressions on both sides of the memory cell 3, which indicates that the polysilicon and the silicon nitride on the top and the sidewall of the memory cell 3 are damaged to a great extent.

[0077] In summary, the present application provides a method for forming a semiconductor device, by introducing the bombardment gas and the etching gas, the etching selectivity of the silicon oxide to the silicon nitride and the polysilicon is improved, the fluorocarbon polymer layer formed can protect the silicon nitride and the polysilicon from being damaged by ion bombardment, and at the same time, the etching morphology is accurately controlled, which is suitable for etching the silicon oxide at different positions of the 3D NAND memory.

[0078] While the application has been described in detail by reference to preferred embodiments thereof, it is to be understood that the description is not to be construed as limiting the scope of the application. Various modifications and changes can occur to those skilled in the art, once they learn of the basic concept of the application. Therefore, the scope of the application is to be defined by the appended claims, rather than by the description of the preferred embodiments.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, wherein a surface of the substrate comprises an oxide layer and a non-oxide layer disposed around the oxide layer; Bombardment: bombarding the surface of the oxide layer with a bombarding ion to form Si-O dangling bonds on the surface; the bombarding ion is formed by an inert gas under the action of radio frequency power; Deposition: introducing an etching gas, wherein the etching gas forms a bonding layer with Si-O dangling bonds on the surface of the oxide layer and forms a fluorocarbon polymer layer on the surface of the non-oxide layer; Cleaning: introducing bombardment gas, and utilizing the energy provided by the bombardment gas to cause the Si-O dangling bonds in the bonding layer to react with the precursor of the etching gas to form volatile gas; the bombardment gas is an inert gas.

2. The method for forming a semiconductor device according to claim 1, wherein: The substrate includes: a stacked layer, a dielectric layer located on the surface of the stacked layer, and a through hole penetrating the stacked layer and the dielectric layer. A silicon oxide layer, a polysilicon layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are arranged in sequence from the center to the outside in the through hole; the material of the dielectric layer is silicon oxide.

3. The method for forming a semiconductor device according to claim 2, wherein: The thickness of the silicon oxide layer is equal to the depth of the through hole; the Si-O dangling bonds are formed on the surfaces of the silicon oxide layer and the dielectric layer.

4. The method for forming a semiconductor device according to claim 2, wherein: The thickness of the silicon oxide layer is smaller than the depth of the through hole. A groove is formed above the silicon oxide layer, and a polysilicon layer is formed in the groove. The dielectric layer is the oxide layer.

5. The method for forming a semiconductor device according to claim 3 or 4, wherein: The method for forming the Si-O dangling bonds includes: introducing a bombarding gas into the surface of the substrate, wherein the bombarding gas forms bombarding positive ions under the action of radio frequency power, and the bombarding positive ions bombard the surface of the oxide layer to form the Si-O dangling bonds.

6. The method for forming a semiconductor device according to claim 1, wherein: The inert gas is one or more of Ar, Kr or Xe.

7. The method for forming a semiconductor device according to claim 1, wherein: After the etching gas is introduced, the method further comprises the step of decomposing the etching gas into precursors, wherein the precursors form the fluorocarbon polymer on the surfaces of the oxide layer and the non-oxide layer, and the fluorocarbon polymer on the oxide layer is located on the surface of the bonding layer.

8. The method for forming a semiconductor device according to claim 1, wherein: The etching gas is a carbon fluorine gas C x F y , where x and y represent the number of carbon and fluorine atoms, and x≥2.

9. The method for forming a semiconductor device according to claim 8, wherein: The carbon fluorine gas includes one or more of C2F4, C2F6, C3F6, C3F8, C4F6 or C4F8.

10. The method for forming a semiconductor device according to claim 1, wherein: The etching gas does not contain hydrogen element.

11. The method for forming a semiconductor device according to claim 1, wherein: The volatile gases include SiF4 and CO.

12. The method for forming a semiconductor device according to claim 1, wherein: When forming the fluorocarbon polymer, a dilution gas is also introduced; the dilution gas includes an inert gas.

13. The method for forming a semiconductor device according to claim 1, wherein: The deposition and removal constitute a cycle, and the method for forming a semiconductor device includes several of the cycles.

14. The method for forming a semiconductor device according to claim 1, wherein: Pressure 15-30mTorr, frequency 40Mhz-100Mhz, RF power 500w-700w.

15. The method for forming a semiconductor device according to claim 1, wherein: The flow rate of the bombardment gas is 700 sccm-1000 sccm.

16. The method for forming a semiconductor device according to claim 1, wherein: The bombardment process takes 4-8 seconds.

17. The method for forming a semiconductor device according to claim 1, wherein: The etching gas is composed of a plurality of gaseous pure substances, and the flow rate of any of the gaseous pure substances is 0-5 sccm.

18. The method for forming a semiconductor device according to claim 1, wherein: The operation time ratio of the deposition and removal processes is (0.3-0.75):

1.

19. The method for forming a semiconductor device according to claim 12, wherein: The flow ratio of the etching gas to the dilution gas is 1:200 to 1:500.

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