An automatic layout method for circuit schematics

Abstract

This invention discloses an automatic layout method for circuit schematics, belonging to the field of electronic information, which improves the efficiency and accuracy of circuit schematic inversion engineering. The invention includes the following steps: First, it reads in netlist information and component library information and performs data conversion; then, it clusters all components based on their pin and connection information; next, it performs local layout for each sub-partition, mainly including directed graph transformation, logic swap column positioning, logic row positioning, and physical expansion positioning; finally, it outputs the placement coordinates and rotation angle of each component. This solves the problems of slow speed and high error rate in current manual circuit schematic inversion methods.

Description

Technical Field

[0001] This invention belongs to the field of electronic information, and in particular relates to an automatic layout method for circuit schematics. Background Technology

[0002] The deterioration of electronic devices is an inevitable process, and their increasingly widespread use has led to a growing accumulation of faulty devices. Due to limitations imposed by intellectual property protection and technology patents, electronic devices are often sold without their circuit diagrams, or the diagrams are damaged or lost. This creates significant obstacles to independent repair and maintenance of electronic devices.

[0003] Despite breakthroughs in electronic equipment repair technology, the lack of circuit diagrams remains a significant obstacle, preventing timely repairs of faulty electronic devices. It's common to see expensive electronic equipment left idle or operating with faults, leading to increasing resource waste and environmental pollution. Extensive equipment repair experience demonstrates that a large proportion of these faulty electronic devices are easily repairable if their circuit diagrams are available. From a repair perspective, circuit diagrams are crucial for operational procedures. With a circuit diagram, testing and repair plans can be developed under existing conditions, the causes of faults can be analyzed, and repairs can be carried out.

[0004] Domestic research and development also exist for PCB circuit reconstruction technology, typically consisting of a measurement station, a path detector, and a local area network. From the perspective of circuit reconstruction steps and implementation principles, it is divided into two parts: front-end probing and back-end logic synthesis. Front-end probing measures and records the connectivity between all component pins on the circuit board to generate a measurement netlist; back-end logic synthesis uses the measurement netlist for reverse analysis to reconstruct the circuit schematic. This manual inversion technique has certain limitations in practical application, requiring physical testing, and is also known as "contact inversion." According to relevant reports, the most typical research in this field abroad involves PCB testing instruments. More advanced instruments can generate netlist files in universal formats, but their schematic inversion is very poor, serving no reference purpose whatsoever, let alone practical use.

[0005] Cadence's OrCAD schematic design component, Capture CIS, is considered an excellent schematic design software in the industry due to its beautiful interface, ease of use, and powerful simulation capabilities. However, this type of software can only be used for manual schematic drawing and cannot automatically process and draw related schematics. In practice, using this software for manual schematic drawing not only results in a large workload, low design efficiency, and a lot of repetitive work, but also fails to guarantee the consistency of design data across different design stages, making it prone to errors. Therefore, schematic drawing software like Capture CIS cannot meet the requirements of the schematic reverse engineering process. Summary of the Invention

[0006] This invention proposes an automatic layout method for circuit schematics, which solves the problems of circuit division and automatic layout in current circuit schematic inversion engineering.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] An automatic placement algorithm for circuit schematics includes the following steps:

[0009] (1) Circuit partitioning process: The complete circuit diagram corresponding to a netlist is quite complex. It is necessary to first perform reasonable clustering of all components. This method uses the network intersection-union ratio based on the network connection relationship to partition the overall circuit. Then, based on the obtained initial partition group, some minimal partitions are merged twice.

[0010] (2) Directed graph conversion process: For each group, the pin redirection operation is performed. Although the drawing is generally done from left to right according to the current direction when drawing manually, due to the large number of feedback circuits, the layout is not strictly from left to right according to the current direction. Therefore, this step is mainly based on the network relationship to redirect the direction of the pins to consider the relationship between the components as a whole.

[0011] (3) Logical ring-breaking column positioning process: First, the ring-breaking operation is to break the loops in the directed network obtained in the above steps. Then, based on a directed graph without loops, the column position of each group of components is determined. At this time, the column position is the logical position, without considering the left and right spacing and the length and width of the components.

[0012] (4) Logical row positioning process: First, the position of each column of components is adjusted based on the independent fan-in set strategy, and then the logical row position of the components is adjusted based on the center of gravity rule.

[0013] (5) Physical expansion and positioning process: This involves calculating the actual coordinate information based on the logical row and column positions obtained from the above steps. First, based on the principle of prioritizing the longest column, the longest column in the group is expanded. Then, the remaining columns are expanded forward and backward from the longest column. When calculating the row position, pins that meet the conditions are strictly aligned based on the pin alignment principle, which is beneficial to the aesthetics of subsequent wiring. In addition, if the corresponding conditions for pin alignment are not met, the centroid rule is used to calculate the row position.

[0014] Of the steps described above, step (2) specifically includes the following steps:

[0015] (21) First, identify the power amplifier structure in each subdivision and bind the dual-ended components that are fully connected to the power amplifier components to the power amplifier components according to the pin direction. Then, delete the dual-ended components that are bound to the power amplifier structure from the subdivision. That is, the dual-ended components that are bound to the power amplifier components are temporarily not considered, which also simplifies the network in the schematic diagram to a certain extent.

[0016] (22) Next, extract all networks with external connections for the sub-partition, and select one network as the input network. The network selection principle is: the number of pins of the largest component contained in the network is the smallest compared with other networks. If the number of pins is the same, the network with the smallest number of components is selected.

[0017] (23) Then, the selected input network is traversed in breadth-first order according to the principle of left-in and right-out. During the traversal, only the output nodes of each network are pushed into the queue. The input nodes are only assigned pin attributes and are not pushed into the queue to be traversed. That is, it only extends from left to right and backward, and does not extend forward or backward. In addition, the power network and ground network are not considered during the traversal. That is, the network including the power and ground networks is included. During the traversal, the input pin attributes are set to input and the other pins are set to output. The traversal continues with the other pins and follows the principle of left-in and right-out. The principle is to rotate some components to ensure that the input is on the left and the output is on the right, but components with more than 4 pins will not be rotated; components with 1 pin are always assigned as output nodes; if all nodes in a network are determined to be input or output nodes, and the network has external connections, then the network is determined to be the output or input network of the entire subdivision, and all nodes are either input or output nodes; if the network has no external connections, then the smallest unvisited component is selected and flipped.

[0018] (24) Then continue to process the remaining networks with external connections. For the remaining networks, if all nodes in the network have been visited, the network is deleted and no longer processed separately. Then select a network to continue breadth-first traversal search. After each traversal, the set of networks must be reduced.

[0019] (25) Then process all power networks. If the number of pins of the power network connection node is less than 3, rotate according to the specific situation and traverse the remaining ends backward. If the number of pins is greater than 3, only traverse downward for the components whose pins are at the left or upper end of the component connected to the power. If they are at the right or lower end, do not continue traversing. The nodes that have been processed before will not be modified during traversal.

[0020] (26) Then process the previously bound power amplifier structure and dual-ended structure, that is, process the pin attributes and angles of the dual-ended components bound to it according to the angle of the power amplifier components.

[0021] (27) Redefine the network based on the new pin directions determined above and convert it into a directed graph.

[0022] Step (3) specifically includes the following steps:

[0023] (31) First, place all components without internal inputs in the first column;

[0024] (32) Then, identify all feedback loops based on the connection relationship between the components. Then, calculate the loop breaking coefficient and break the loops in descending order of the number of feedback loops. Then, place the components according to the placement rules. The placement rules are as follows: traverse all the previous connected node positions of the current node and place the current component in the column after the largest column of all previous connected nodes. For the remaining unplaced components, if all their previous connected nodes have been placed, place them according to the placement rules; otherwise, place them later.

[0025] Step (4) specifically includes the following steps:

[0026] (41) Traverse all nodes, find all existing independent fan-in sets, and adjust all components in the fan-in set to the beginning of each column. The definition of an independent fan-in set is as follows: take the current component as the root node and search forward until there are no previous connected nodes. If the backward connections of the previous connected nodes all belong to one point, then it is an independent fan-in set.

[0027] (42) Then calculate the center of gravity value of each component and adjust its position: calculate the center of gravity position based on the position of the previous connected node and the connection weight of each node to rearrange the order of the components in each column.

[0028] Step (5) specifically includes the following steps:

[0029] (51) First, perform row expansion. Based on the component height, perform basic row expansion on each column. Then, prioritize the layout of the longest column and proceed backwards based on the longest column. The layout rules are as follows: a. If the current component has only one front-connecting component, calculate the physical position of the component according to the pin alignment principle. The pin alignment principle is to strictly align the corresponding connecting pins of the two components in the figure based on the component height, rotation angle, and pin position. b. If the current component has multiple front-connecting components, calculate the physical position based on the first front-connecting component in the previous column of the current component according to the pin alignment principle. c. Sort according to the calculated physical positions and place them in order from top to bottom. If there is overlap of components, move the position of the next component down.

[0030] (52) Then, based on the longest column and the already laid-out columns, the layout is performed forward. The layout rules for components with subsequent connections are as follows: a. Traverse all subsequent connections of the component and determine whether they meet the pin alignment principle, and calculate the physical position based on the topmost subsequent connection component of the nearest column that meets the condition; b. If there is no subsequent connection component that meets the pin alignment, calculate the physical position based on the position of the subsequent connection component of the nearest column according to the centroid calculation rule; The layout rules for components without subsequent connections are as follows: a. First, lay out the components that are not laid out continuously from the first row downwards. The position calculation rule is that each component is within the specified range. a. Calculate the physical position without overlapping with the next component; b. Then lay out the remaining components without subsequent connections. The position calculation rule is that if the previous component has been laid out, calculate the physical position without overlapping with the previous component. If the previous component has not been laid out, the current component is placed after the previous component. Finally, sort according to the calculated physical positions. If the position of the smallest component is less than 0, all laid-out components need to be moved down to ensure that the position of the smallest component is 1. Then place the components in this column in order from top to bottom. If there is an overlap of components, move the position of the next component down.

[0031] (53) Finally, from front to back, select the maximum component width of each column as the width of the column for physical column expansion.

[0032] Beneficial Effects: This invention proposes an automatic layout algorithm for circuit schematics. It divides the overall circuit diagram into circuit parts using a clustering algorithm based on network intersection-exchange ratio (COP). It transforms the original many-to-many undirected network graph into a directed graph with a sequence. It locates the column logic positions of components by breaking down feedback loops and using a breadth-first search algorithm. It further adjusts the row logic positions of each column of components by identifying independent fan-in sets. Finally, it obtains the actual coordinate positions of each component by physically expanding backward and forward based on the longest column, using the obtained logic positions and the alignment principle. Attached Figure Description

[0033] Figure 1 This is an overall flowchart of an embodiment of the present invention;

[0034] Figure 2 This is a flowchart of step 2 in an embodiment of the present invention;

[0035] Figure 3 This is an example diagram of the power amplifier structure in step 2 of this embodiment of the invention;

[0036] Figure 4 This is an example diagram of the double-ended connection structure in step 2 of this embodiment of the invention;

[0037] Figure 5 This is a schematic diagram of the generation result in an embodiment of the present invention. Detailed Implementation

[0038] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments:

[0039] like Figure 1 As shown, an automatic placement algorithm for circuit schematics includes the following steps:

[0040] Step 1: Based on the network connection relationship, the network crossover and parallelism ratio is used to divide the overall circuit. Then, based on the obtained initial division groups, a secondary merging is performed to handle some very small division groups.

[0041] Step 2: Perform pin redirection and directed graph transformation on each partition group obtained after Step 1;

[0042] Step 3: Decompose the loops in the directed network, and then determine the column positions of the components in each group based on a loop-free directed graph. At this time, the column positions are logical positions, without considering the left and right spacing and the length and width of the components.

[0043] Step 4: Adjust the row position of the components in each column based on the independent fan-in set strategy, and then adjust the logical row position of the components based on the center of gravity rule.

[0044] Step 5: Calculate the actual coordinate information based on the logical row and column positions obtained from the above steps.

[0045] In the steps described above, step 1 specifically includes: First, each component in the circuit is assumed to be a subset. Then, the association weight between different subsets is evaluated using a weight evaluation function based on the network intersection-union ratio. Finally, the two subsets with the largest association weights are selected and merged based on the connection weights between the subsets. The weight evaluation function is as follows:

[0046]

[0047] Where: n i n is the number of networks containing subset i; ij n is the number of networks in which subsets i and j are both present. j The number of networks containing subset j;

[0048] The relevant constraints in the clustering process are as follows:

[0049] (11) The intersection-union ratio threshold is 0.5, that is, the association weight of one of the two merged subsets is not less than 0.5;

[0050] (12) Two components with more than 20 pins are not allowed to be in the same group; components with more than 40 pins and components with more than 3 pins are not allowed to be in the same group.

[0051] After the initial clustering is completed, a second merging is performed on the smallest subgroups. The smallest subgroups refer to subgroups with fewer than 8 components and each component has 3 or fewer pins. During the second merging, the smallest subgroups are merged with the smallest subgroups that do not contain large components.

[0052] like Figure 2 As shown, the specific steps of step 2 are as follows:

[0053] Step 201: Identify the power amplifier structure within each sub-partition and bind the dual-ended components that are fully connected to the power amplifier components to the power amplifier components according to the pin direction. Then, delete the dual-ended components bound to the power amplifier structure from the sub-partition. That is, the dual-ended components that are bound to the power amplifier components are temporarily disregarded. This also simplifies the network in the schematic diagram to some extent.

[0054] Step 202: Extract all networks with external connections for the sub-partition, and select one network as the input network. The network selection principle is: the number of pins of the largest component contained in the network is the smallest compared with other networks. If the number of pins is the same, the network with the smallest number of components is selected.

[0055] Step 203: Perform a breadth-first traversal of the components using the selected input network according to the principle of left-in and right-out. During the traversal, only the output nodes of each network are pushed into the queue. The input nodes are only reset with their pin attributes and are not pushed into the traversal queue. That is, the traversal extends from left to right and backward, and does not extend forward or backward. Furthermore, the traversal does not consider power and ground networks, i.e., networks that include power and ground. During traversal, the input pins are set to input, and the remaining pins are set to output. Traversal continues from the remaining pins, and some components are rotated according to the principle of left-in and right-out to ensure that the input is on the left and the output is on the right. However, components with more than 4 pins are not rotated. Components with 1 pin are consistently assigned as output nodes. If all nodes in a network are identified as inputs or outputs, and the network has external connections, then the network is identified as either the input or output network of the entire subdivision, and all nodes are either input or output nodes. If the network has no external connections, then the smallest unvisited component is selected and flipped.

[0056] Step 204: Continue processing the remaining networks with external connections. First, reduce the number of networks. For networks where all nodes have been visited, delete them and do not process them separately. Then, select a network to continue breadth-first traversal search. After each traversal, reduce the number of networks in the set.

[0057] Step 205: Process all power networks. If the number of pins of a power network connection node is less than 3, rotate it according to the specific situation and traverse the remaining ends backward. If the number of pins is greater than 3, only traverse downward for components whose pins are at the left or top of the component connected to the power supply. If they are at the right or bottom, do not continue traversing. Nodes that have been processed before will not be modified during traversal.

[0058] Step 206: Process the previously bound power amplifier structure and dual-ended structure, that is, set the pin attributes and angles of the dual-ended components bound to it according to the angle of the power amplifier components.

[0059] Step 207: Redefine the network according to the new pin orientation and convert it into a directed graph;

[0060] Figure 3 and Figure 4 The power amplifier structures and dual-ended fully connected structures that are individually identified and preprocessed in step 2 are presented.

[0061] The specific steps for step 3 are as follows:

[0062] Step 301: Set all components without internal inputs to column 1.

[0063] Step 302: Identify all feedback loops based on the connection relationships between components, then calculate the loop-breaking coefficients and break the loops sequentially. Next, place the components according to the placement rules, which are as follows: Traverse all previous connected node positions of the current node and place the current component in the column following the largest column of all previous connected nodes; for any unplaced components encountered during the traversal, if all their previous connected nodes have been placed, place them according to the placement rules; otherwise, place them later. The loop-breaking coefficient p... i The calculation formula is as follows:

[0064]

[0065]

[0066] In the formula: n is the total number of nodes in the feedback loop; dis(i,j) represents the distance between node i and node j in the loop, indegree i The in-degree and out-degree of node i are represented by the number of nodes i. i The out-degree of node i is indicated by isOutnode(i), which indicates whether node i is an output node. An output node is a node that is connected to other networks in addition to the current ring network.

[0067] The specific steps for step 4 are as follows:

[0068] Step 401: Identify all existing independent fan-in sets and adjust all components in the fan-in set to the beginning of each column; the definition of an independent fan-in set is as follows: with the current component as the root node, perform a depth-first search forward until there are no previous connected nodes. If the backward connections of the previous connected nodes all converge to one point, then it is an independent fan-in set.

[0069] Step 402: Calculate the centroid position based on the positions of the preceding connected nodes and the connection weights of each node, and rearrange the component order of each column. The centroid value calculation formula is as follows:

[0070]

[0071] In the formula, c represents the total number of preceding connected nodes of node i, weight(i,j) represents the number of nodes connected between node i and node j, and row(j) represents the row number of node j;

[0072] The specific steps for step 5 are as follows:

[0073] Step 501: Perform basic row expansion on each column based on the component height, and then lay out the components backwards using the longest column as the reference. The layout rules are as follows: a. If the current component has only one preceding connected component, calculate the physical position of the component according to the pin alignment principle. The pin alignment principle means strictly aligning the corresponding connecting pins of two components in the diagram based on the component height, rotation angle, and pin position. b. If the current component has multiple preceding connected components, calculate the physical position based on the first preceding connected component in the previous column of the current component according to the pin alignment principle. c. Sort the components according to their calculated physical positions and place them sequentially from top to bottom. If there is overlap between components, move the next component down.

[0074] Step 502: Layout forward based on the longest column and already laid-out columns. The layout rules for components with subsequent connections are as follows: a. Traverse all subsequent connections of the component and determine whether they meet the pin alignment principle. Calculate the physical position based on the topmost subsequent connection component in the nearest column that meets the condition; b. If there is no subsequent connection component that meets the pin alignment principle, calculate the physical position based on the position of the subsequent connection component in the nearest column according to the centroid calculation rule. The centroid calculation rule here is similar to that in Step 4. The layout rules for components without subsequent connections are as follows: a. First, lay out the components that are not yet laid out consecutively from the first row downwards. The position calculation rules are as follows: Calculate the physical position of each component while ensuring it does not overlap with the next component; b. Then lay out the remaining components without subsequent connections. The position calculation rule is that if the previous component has been laid out, calculate the physical position while ensuring it does not overlap with the previous component. If the previous component has not been laid out, the current component will be laid out later; finally, sort according to the calculated physical positions. If the minimum component position is less than 0, all laid-out components need to be moved down as a whole to ensure that the minimum row position of the component is 1. Then place the components in the column in order from top to bottom. If there is an overlap of components, move the position of the next component down.

[0075] Step 503: Select the maximum component width of each column from front to back as the width of that column and expand the physical columns accordingly.

[0076] Figure 5 The results of generating partial schematic diagrams using Cadence software and the method of this invention have been verified to meet the needs of practical engineering.

[0077] The above embodiments are merely illustrative of preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concepts proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. An automatic layout method for circuit schematics, characterized in that, Includes the following steps: Step 1: Based on network connectivity, the overall circuit is divided using the network intersection-union ratio (CIU). Then, a secondary merging is performed based on the initial partitions. Specifically, this includes: first, assuming each component in the circuit as a subset; then, evaluating the correlation weight between different subsets using a weight evaluation function based on the CIU; and finally, merging the two subsets with the highest correlation weights based on the connection weights between the subsets. The weight evaluation function is as follows: ， In the formula: The number of networks containing subset i; Let be the number of networks in which both subset i and subset j are present. The number of networks containing subset j; After the initial merging is completed, a second merging is performed on the smallest partition group. During the second merging, the smallest partition group is merged with the smallest partition group that does not contain large components. Step 2: Perform pin redirection and directed graph transformation for each partition group; Step 3: Decompose the loops in the directed network, and then determine the column positions of the components in each group based on a loop-free directed graph. At this time, the column positions are logical positions, without considering the left and right spacing and the length and width of the components. Step 4: Adjust the row position of the components in each column based on the independent fan-in set strategy, and then adjust the logical row position of the components based on the center of gravity rule. Step 5: Calculate the actual coordinate information based on the logical row and column positions obtained from the above steps.

2. The automatic layout method for circuit schematics according to claim 1, characterized in that, The restrictions in the merging process are as follows: the crossover ratio threshold is 0.5, that is, the association weight of one of the two merged subsets is not less than 0.5; two components with more than 20 pins are not allowed to be in the same group; components with more than 40 pins and components with more than 3 pins are not allowed to be in the same group.

3. The automatic layout method for circuit schematics according to claim 1, characterized in that, Step 2 specifically includes the following steps: Step 201: Identify the power amplifier structure within each sub-division and bind the dual-ended components that are fully connected to the power amplifier components to the power amplifier components according to the pin direction. Then, delete the dual-ended components that are bound to the power amplifier structure from the sub-division. Step 202: Extract all externally connected networks for the sub-partition, and select one network as the input network. Step 203: Perform a breadth-first traversal of the selected input network according to the principle of left-in and right-out, and reset the corresponding pin attributes; Step 204: Continue processing the remaining networks with external connections. First, reduce the number of networks. For networks where all nodes have been visited, delete them and do not process them separately. Then, select a network to continue breadth-first traversal. After each traversal, reduce the number of networks in the set. Step 205: Process all power networks. If the number of pins of a power network connection node is less than 3, rotate it according to the specific situation and traverse the remaining ends backward. If the number of pins is greater than 3, only traverse downward for components whose pins are at the left or top of the component connected to the power supply. If they are at the right or bottom, do not continue traversing. Nodes that have been processed before will not be modified during traversal. Step 206: Process the previously bound power amplifier structure and dual-ended structure, that is, set the pin attributes and angles of the dual-ended components bound to it according to the angle of the power amplifier components. Step 207: Redefine the network according to the new pin orientation and convert it into a directed graph.

4. The automatic layout method for circuit schematics according to claim 3, characterized in that, In step 203, during traversal, the input pin attribute is set to "input", and the remaining pins are set to "output". Traversal continues with the remaining pins, and some components are rotated according to the principle of left-in and right-out to ensure that the input is on the left and the output is on the right. However, components with more than 4 pins are not rotated. Components with 1 pin are consistently assigned as output nodes. If all nodes in a network are identified as inputs or outputs, and the network has external connections, then the network is identified as either the input network or the output network of the entire subdivision, and all nodes are either input nodes or output nodes. If the network has no external connections, then the smallest unvisited component is selected and flipped.

5. The automatic layout method for circuit schematics according to claim 1, characterized in that, Step 3 specifically includes the following steps: Step 301: Set all components without internal inputs to column 1; Step 302: Identify all feedback loops based on the connection relationships between components, then calculate the loop breaking coefficients and break the loops sequentially. Then, place the components according to the placement rules, which are: traverse all the previous connected node positions of the current node and place the current component in the column after the largest column of all previous connected nodes; for unplaced components encountered during the traversal, if all their previous connected nodes have been placed, place them according to the placement rules, otherwise place them later.

6. The automatic layout method for circuit schematics according to claim 5, characterized in that, The ring-removal coefficient in step 302 The calculation formula is as follows: ， ， In the formula: n is the total number of nodes in the feedback loop; This represents the distance between nodes i and j in the ring. Indicates the in-degree of node i. Indicates the out-degree of a node.

7. The automatic layout method for circuit schematics according to claim 1, characterized in that, Step 4 specifically includes the following steps: Step 401: Identify all existing independent fan-in sets and adjust all components within each fan-in set to the top of each column; Step 402: Calculate the centroid position based on the positions of the preceding connected nodes and the connection weights of each node, and rearrange the component order of each column. The centroid value calculation formula is as follows: ， In the formula, n represents the total number of preceding connected nodes of node i. This indicates the number of disciplines connected to node i and node j. This indicates the row number of node j.

8. The automatic layout method for circuit schematics according to claim 1, characterized in that, Step 5 specifically includes the following steps: Step 501: Perform basic row expansion on each column based on the component height, and then lay out the components backwards using the longest column as the reference. The layout rules are as follows: If the current component has only one preceding connected component, calculate the physical position of the component according to the pin alignment principle. The pin alignment principle is to strictly align the corresponding connecting pins of two components in the diagram based on information including component height, rotation angle, and pin position. If the current component has multiple preceding connected components, calculate the physical position based on the first preceding connected component in the previous column of the current component according to the pin alignment principle. Sort the components according to the calculated physical positions and place them sequentially from top to bottom. If there is overlap of components, move the position of the next component down. Step 502: Lay out the columns backwards, using the longest column and already laid out columns as a reference; Step 503: From front to back, select the maximum component width of each column as the width of that column and expand the physical columns accordingly.

9. The automatic layout method for circuit schematics according to claim 8, characterized in that, In step 502, the layout rules for components with subsequent connections are as follows: traverse all subsequent connections of the component and determine whether they meet the pin alignment principle, and calculate the physical position based on the topmost subsequent connection component in the nearest column that meets the condition; if there is no subsequent connection component that meets the pin alignment, calculate the physical position based on the position of the subsequent connection component in the nearest column according to the centroid calculation rules in step 4; the layout rules for components without subsequent connections are as follows: first, lay out the components that are not laid out continuously from the first row downwards, and the position calculation rule is that each component ensures that it does not overlap with the next component. Calculate the physical position when components overlap; then lay out the remaining components without subsequent connections. The position calculation rule is that if the previous component has been laid out, calculate the physical position while ensuring that it does not overlap with the previous component. If the previous component has not been laid out, the current component will be laid out later. Finally, sort according to the calculated physical position. If the minimum component position is less than 0, all laid-out components need to be moved down as a whole to ensure that the minimum row position of the component is 1. Then, place the components in the column in order from top to bottom. If there is an overlap of components, move the position of the next component down.

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