Gate driving circuit and display panel

Abstract

The application discloses a kind of gate drive circuit and display panel.Therein, gate drive circuit includes output control module, first transistor, second transistor and voltage regulation module;Output control module is used to control first transistor and second transistor alternate conduction, to first output signal and second output signal are alternately transmitted to the output end of gate drive circuit;At least one of first transistor and second transistor is double-gate transistor, the first gate of double-gate transistor is connected with output control module;Voltage regulation module is connected with the second gate of double-gate transistor, for adjusting the second gate voltage of double-gate transistor.The technical scheme of the application is helpful to improve the waveform distortion problem of gate drive signal, so as to improve the display effect of display panel.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a gate driving circuit and a display panel. BACKGROUND

[0002] With the continuous development of display technology, people have higher and higher requirements for the performance of display panels. The display panel includes a gate driving circuit for generating a gate driving signal. At present, the waveform of the gate driving signal output by the existing gate driving circuit is distorted, which affects the display effect of the display panel. SUMMARY

[0003] Embodiments of the present application provide a gate driving circuit and a display panel to improve the waveform distortion problem of the gate driving signal, thereby improving the display effect of the display panel.

[0004] In a first aspect, embodiments of the present application provide a gate driving circuit, comprising:

[0005] an output control module, a first transistor, and a second transistor, the output control module being connected to the gate of the first transistor and the gate of the second transistor, the first electrode of the first transistor being connected to a first output signal, the second electrode of the first transistor being connected to an output end of the gate driving circuit, the first electrode of the second transistor being connected to a second output signal, the second electrode of the second transistor being connected to the output end of the gate driving circuit, the output control module being configured to control the first transistor and the second transistor to conduct alternately, so as to transmit the first output signal and the second output signal to the output end of the gate driving circuit alternately; wherein at least one of the first transistor and the second transistor is a double-gate transistor, and the first gate of the double-gate transistor is connected to the output control module.

[0006] at least one voltage adjusting module connected to the second gate of the double-gate transistor, and configured to adjust the voltage of the second gate of the double-gate transistor.

[0007] Optionally, the voltage adjusting module is configured to adjust the voltage of the second gate of the double-gate transistor when the double-gate transistor is turned on, so as to improve the driving capability of the double-gate transistor, and / or adjust the voltage of the second gate of the double-gate transistor when the double-gate transistor is turned off, so as to suppress the leakage current of the double-gate transistor.

[0008] Optionally, a control terminal of the voltage regulating module is connected to a first control signal, a first terminal of the voltage regulating module is connected to a first level signal, and a second terminal of the voltage regulating module is connected to a second gate of the double-gate transistor, and the voltage regulating module is configured to transmit the first level signal to the second gate of the double-gate transistor when the double-gate transistor is turned off in response to the first control signal, so as to suppress a leakage current of the double-gate transistor.

[0009] Preferably, the voltage regulating module comprises a third transistor, a gate of the third transistor is connected to the first control signal, a first pole of the third transistor is connected to the first level signal, and a second pole of the third transistor is connected to the second gate of the double-gate transistor.

[0010] Optionally, a control terminal of the voltage regulating module is connected to a second control signal, a first terminal of the voltage regulating module is connected to a preset signal, and a second terminal of the voltage regulating module is connected to a second gate of the double-gate transistor, and the voltage regulating module is configured to adjust the voltage of the second gate of the double-gate transistor by the preset signal when the double-gate transistor is turned on in response to the second control signal, so as to improve a driving capability of the double-gate transistor.

[0011] Preferably, the voltage regulating module comprises a fourth transistor, a gate of the fourth transistor is connected to the second control signal, a first pole of the fourth transistor is connected to the preset signal, and the fourth transistor is configured to transmit a signal related to the preset signal to the second gate of the double-gate transistor in response to the second control signal.

[0012] Optionally, the voltage regulating module further comprises a first capacitor connected between a second pole of the fourth transistor and the second gate of the double-gate transistor.

[0013] Optionally, the voltage regulating module further comprises a fifth transistor, the second control signal is connected to the gate of the fourth transistor through the fifth transistor, and the fifth transistor is kept in an open state.

[0014] Optionally, the voltage regulating module comprises:

[0015] a first voltage regulating unit, a control terminal of the first voltage regulating unit is connected to a first control signal, a first terminal of the first voltage regulating unit is connected to a first level signal, and a second terminal of the first voltage regulating unit is connected to a second gate of the double-gate transistor, and the first voltage regulating unit is configured to transmit the first level signal to the second gate of the double-gate transistor when the double-gate transistor is turned off in response to the first control signal;

[0016] a second voltage regulating unit, a control end of the second voltage regulating unit being connected to a second control signal, a first end of the second voltage regulating unit being connected to a preset signal, and a second end of the second voltage regulating unit being connected to the second gate of the double-gate transistor, the second voltage regulating unit being configured to, in response to the second control signal, regulate the voltage of the second gate of the double-gate transistor by the preset signal when the double-gate transistor is turned on.

[0017] The level of the first level signal comprises a first level, and the level of the preset signal comprises a second level, one of the first level and the second level being a preset high level and the other being a preset low level.

[0018] Optionally, the first voltage regulating unit comprises a third transistor, and the second voltage regulating unit comprises a fourth transistor.

[0019] The gate of the third transistor is connected to the first control signal, the first pole of the third transistor is connected to the first level signal, and the second pole of the third transistor is connected to the second gate of the double-gate transistor.

[0020] The gate of the fourth transistor is connected to the second control signal, the first pole of the fourth transistor is connected to the preset signal, and the fourth transistor is configured to, in response to the second control signal, transmit a signal related to the preset signal to the second gate of the double-gate transistor.

[0021] Preferably, the second voltage regulating unit further comprises a first capacitor connected between the second electrode of the fourth transistor and the second gate of the double-gate transistor.

[0022] Preferably, in the case where the double-gate transistor is an N-type transistor, the first level is a preset low level, and the second level is a preset high level.

[0023] In the case where the double-gate transistor is a P-type transistor, the first level is a preset high level, and the second level is a preset low level.

[0024] Optionally, the first control signal comprises a first clock signal, and the preset signal comprises a second clock signal, the phases of the first clock signal and the second clock signal being opposite.

[0025] Optionally, the third transistor is a double-gate transistor.

[0026] The first gate of the third transistor is connected to the first control signal, and the second gate of the third transistor is connected to the first level signal; or

[0027] The second gate of the third transistor is connected to the first control signal, and the first gate of the third transistor is connected to the first level signal.

[0028] Optionally, in the case that the first transistor is the double-gate transistor, the voltage adjusting module comprises a first voltage adjusting module connected to the second gate of the first transistor.

[0029] In the case that the second transistor is the double-gate transistor, the voltage adjusting module comprises a second voltage adjusting module connected to the second gate of the second transistor.

[0030] Optionally, the first transistor and the second transistor are both double-gate transistors.

[0031] The second gate of the first transistor is connected to the first voltage adjusting module, and the second gate of the second transistor is connected to the second voltage adjusting module.

[0032] Optionally, the first transistor and the second transistor are both double-gate transistors.

[0033] The second gate of one of the first transistor and the second transistor is connected to a first level signal line, and the second gate of the other of the first transistor and the second transistor is connected to the voltage adjusting module; or,

[0034] The first gate and the second gate of one of the first transistor and the second transistor are connected, and the second gate of the other of the first transistor and the second transistor is connected to the voltage adjusting module.

[0035] Optionally, the output control module comprises:

[0036] An input unit connected to the first node, the second node and the input end of the gate drive circuit, for controlling the signals of the first node and the second node according to the first clock signal, the second level signal and the signal of the input end of the gate drive circuit;

[0037] A first output control unit connected to the first node and the second node, for controlling the signal of the first node according to the signal of the second node and the first clock signal;

[0038] A second output control unit connected to the first node and the second node, for controlling the signal of the second node according to the signal of the first node, the second clock signal and the third level signal; wherein the first node is connected to the gate of the first transistor, and the signal of the second node is transmitted to the gate of the second transistor.

[0039] wherein the third level signal is multiplexed as the first output signal, and the second clock signal is multiplexed as the second output signal;

[0040] Preferably, the output control module further comprises a sixth transistor connected between a third node and the second node, the sixth transistor maintaining an open state, the third node being connected to the gate of the second transistor, and the signal of the second node being transmitted to the gate of the second transistor through the sixth transistor;

[0041] Preferably, in the case that the first transistor is the double-gate transistor, the voltage adjustment module comprises a first voltage adjustment module connected to the second gate of the first transistor; and in the case that the second transistor is the double-gate transistor, the voltage adjustment module comprises a second voltage adjustment module connected to the second gate of the second transistor;

[0042] Preferably, the signal of the second node, the signal of the third node, or the first clock signal is multiplexed as a first control signal in the first voltage adjustment module; the signal of the first node is multiplexed as a second control signal in the first voltage adjustment module; the second clock signal or the second level signal is multiplexed as a preset signal in the first voltage adjustment module and the second voltage adjustment module; the signal of the first node or the first clock signal is multiplexed as a first control signal in the second voltage adjustment module, and the signal of the second node or the signal of the third node is multiplexed as a second control signal in the second voltage adjustment module.

[0043] Optionally, the first output control unit comprises a seventh transistor, the gate of the seventh transistor being connected to the second node, the first pole of the seventh transistor being connected to the first clock signal, and the second pole of the seventh transistor being connected to the first node;

[0044] The second output control unit comprises an eighth transistor and a ninth transistor, the gate of the eighth transistor being connected to the first node, the first pole of the eighth transistor being connected to the third level signal, the second pole of the eighth transistor being connected to the first pole of the ninth transistor, the gate of the ninth transistor being connected to the second clock signal, and the second pole of the ninth transistor being connected to the second node;

[0045] Preferably, the seventh transistor is a double-gate transistor, the first gate of the seventh transistor being connected to the second node, and the second gate of the seventh transistor being connected to the first level signal; and / or,

[0046] The eighth transistor and the ninth transistor are both double-gate transistors, the first gate of the eighth transistor is connected to the first node, the first gate of the ninth transistor is connected to the second clock signal, and the second gate of the eighth transistor and the second gate of the ninth transistor are both connected to the first level signal.

[0047] Optionally, the output control module comprises:

[0048] The input unit is connected to the first node, the second node and the input end of the gate drive circuit, and is configured to control the signals of the first node and the second node according to the first clock signal, the third level signal and the signal of the input end of the gate drive circuit.

[0049] The first output control unit is connected to the third node, the first node and the second node, and is configured to control the signal of the third node according to the second clock signal, the signal of the first node, the signal of the second node and the third level signal; wherein the third node is connected to the gate of the first transistor.

[0050] The second output control unit is connected to the fourth node and the third node, and is configured to control the signal of the fourth node according to the signal of the third node, the signal of the fourth node, the third level signal and the second clock signal; wherein the fourth node is connected to the gate of the second transistor, and the signal of the second node is transmitted to the gate of the second transistor.

[0051] The third level signal is multiplexed as the first output signal, and the second level signal is multiplexed as the second output signal.

[0052] Preferably, the output control module further comprises a tenth transistor connected between the second node and the fourth node, the tenth transistor maintains an open state, and the signal of the second node is transmitted to the gate of the second transistor through the tenth transistor.

[0053] Preferably, in the case that the first transistor is the double-gate transistor, the voltage adjustment module comprises a first voltage adjustment module connected to the second gate of the first transistor; in the case that the second transistor is the double-gate transistor, the voltage adjustment module comprises a second voltage adjustment module connected to the second gate of the second transistor.

[0054] Preferably, the first clock signal is multiplexed as a first control signal in the first voltage regulation module and the second voltage regulation module; the signal of the first node is multiplexed as a second control signal in the first voltage regulation module; the second clock signal or the second level signal is multiplexed as a preset signal in the first voltage regulation module and the second voltage regulation module; the signal of the second node or the signal of the fourth node is multiplexed as a second control signal in the second voltage regulation module.

[0055] Optionally, the output control module comprises: an input unit connected to the first node, the second node and an input end of the gate drive circuit, configured to control the signals of the first node and the second node according to the first clock signal, the second level signal and the signal of the input end of the gate drive circuit;

[0056] a first output control unit connected to the first node and the second node, configured to control the signal of the first node according to the signal of the second node and the first clock signal;

[0057] a second output control unit connected to the third node and the fourth node, configured to control the signal of the fourth node according to the signal of the third node and the second clock signal; wherein the signal of the first node is transmitted to the third node, and the signal of the fourth node is transmitted to the gate of the first transistor;

[0058] a third output control unit connected to the fifth node and the sixth node, configured to control the signal of the sixth node according to the signal of the fifth node, the signal of the sixth node, a third level signal and the second clock signal; wherein the signal of the first node is transmitted to the fifth node, the signal of the second node is transmitted to the sixth node, and the sixth node is connected to the gate of the second transistor;

[0059] a fourth output control unit connected to the seventh node and the second node, configured to control the signal of the seventh node according to the signal of the second node and the third level signal; wherein the signal of the fourth node is transmitted to the seventh node, and the seventh node is connected to the gate of the first transistor;

[0060] wherein the third level signal is multiplexed as the first output signal, and the second level signal is multiplexed as the second output signal;

[0061] Preferably, the output control module further comprises an eleventh transistor, a first pole of the eleventh transistor is connected to the first node, a second pole of the eleventh transistor is connected to the third node, the eleventh transistor keeps an open state, and the signal of the first node is transmitted to the third node through the eleventh transistor;

[0062] The output control module further comprises a twelfth transistor connected between the fourth node and the seventh node, the twelfth transistor being kept in an always-on state, and the signal of the fourth node being transmitted to the gate of the first transistor through the twelfth transistor;

[0063] The output control module further comprises a thirteenth transistor, a first pole of the thirteenth transistor being connected to a second pole of the eleventh transistor, a second pole of the thirteenth transistor being connected to the fifth node, the thirteenth transistor being kept in an always-on state, and the signal of the first node being transmitted to the fifth node through the thirteenth transistor;

[0064] The output control module further comprises a fourteenth transistor connected between the second node and the sixth node, the fourteenth transistor being kept in an always-on state, and the signal of the second node being transmitted to the sixth node through the fourteenth transistor;

[0065] Preferably, in the case that the first transistor is the double-gate transistor, the voltage adjustment module comprises a first voltage adjustment module connected to the second gate of the first transistor; in the case that the second transistor is the double-gate transistor, the voltage adjustment module comprises a second voltage adjustment module connected to the second gate of the second transistor;

[0066] Preferably, the first clock signal is multiplexed as a first control signal in the first voltage adjustment module and the second voltage adjustment module; the signal of the first node, the signal of the third node or the signal of the fifth node is multiplexed as a second control signal in the first voltage adjustment module; the second clock signal or the second level signal is multiplexed as a preset signal in the first voltage adjustment module and the second voltage adjustment module; the signal of the second node or the signal of the sixth node is multiplexed as a second control signal in the second voltage adjustment module.

[0067] Optionally, in the case that the double-gate transistor is an N-type transistor, the potential of the first level signal is less than or equal to the minimum potential in the first output signal and the second output signal; in the case that the double-gate transistor is a P-type transistor, the potential of the first level signal is greater than or equal to the maximum potential in the first output signal and the second output signal.

[0068] In a second aspect, an embodiment of the present application provides a display panel comprising a plurality of gate drive circuits as described in the first aspect, and the plurality of gate drive circuits are connected in cascade.

[0069] The gate drive circuit and the display panel provided by the embodiment of the present application can control the first transistor and the second transistor to be turned on alternately by the output control module, so as to alternately transmit the first output signal and the second output signal to the output end of the gate drive circuit as the gate drive signal. By setting at least one of the first transistor and the second transistor as a double-gate transistor, the threshold voltage of the double-gate transistor can be adjusted by the voltage adjustment module when the double-gate transistor is turned on, so as to improve the driving capability of the double-gate transistor, thereby improving the driving capability of the gate drive signal output by the gate drive circuit, and improving the waveform distortion problem of the gate drive signal. In addition, the threshold voltage of the double-gate transistor can be adjusted by the voltage adjustment module when the double-gate transistor is turned off, so as to suppress the leakage current of the double-gate transistor, thereby reducing the power consumption of the double-gate transistor caused by the leakage current, and further improving the waveform distortion problem of the gate drive signal, which is helpful to improve the display effect of the display panel.

[0070] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0072] Figure 1 is a structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0073] Figure 2 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application;

[0074] Figure 3 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application;

[0075] Figure 4 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application;

[0076] Figure 5 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application;

[0077] Figure 6 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application;

[0078] Figure 7 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0079] Figure 8 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0080] Figure 9 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0081] Figure 10 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0082] Figure 11 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0083] Figure 12 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0084] Figure 13 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0085] Figure 14 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0086] Figure 15 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0087] Figure 16 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0088] Figure 17 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0089] Figure 18 is a driving timing schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0090] Figure 19 is a comparison diagram of a drain current and a gate drive signal waveform provided by an embodiment of the present application;

[0091] Figure 20 is a comparison diagram of a gate drive signal waveform provided by an embodiment of the present application;

[0092] Figure 21 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0093] Figure 22is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application;

[0094] Figure 23 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application;

[0095] Figure 24 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0096] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the person of ordinary skill in the art without creative labor should belong to the scope of protection of the present application.

[0097] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0098] As described in the background, the existing gate driving signal waveform output by the gate driving circuit is distorted, which affects the display effect of the display panel. The inventor has found that the reasons for the above problems are as follows: in the existing gate driving circuit, two output transistors, for example, a first output transistor and a second output transistor, connected to the gate driving signal output end of the gate driving circuit are usually provided, the first electrode of the first output transistor can be connected to a low-level signal, the first electrode of the second output transistor can be connected to a high-level signal, the second electrode of the first output transistor and the second electrode of the second output transistor are both connected to the gate driving signal output end of the gate driving circuit, and by controlling the first output transistor and the second output transistor to be turned on alternately, the gate driving signal output end of the gate driving circuit can alternately output high level and low level. However, the output transistor generally has a large leakage current, for example, when N-type indium gallium zinc oxide (IGZO) is used as the output transistor, the threshold voltage is relatively negative, the output transistor cannot be completely turned off and has a large leakage problem, thereby generating power consumption, and the waveform of the gate driving signal is distorted. For example, when the second output transistor is turned off and the first output transistor is turned on and transmits a low-level signal to the gate driving signal output end, if the second output transistor has a leakage current, the potential of the low-level signal output by the gate driving signal output end will be affected, thereby affecting the waveform of the gate driving signal, and the second output transistor generates power consumption due to the leakage current. In addition, the output transistor also has the problem of insufficient driving capacity, which causes the level signal transmitted by the output transistor to the gate driving signal output end of the gate driving circuit to be distorted, which also causes the waveform of the gate driving signal to be distorted, and ultimately affects the display effect of the display panel.

[0099] To solve the above problems, the embodiment of the present application provides a gate driving circuit. Figure 1 is a structural schematic diagram of a gate driving circuit provided by the embodiment of the present application. Referring to Figure 1 The gate driving circuit comprises an output control module 10, a first transistor T1, a second transistor T2 and at least one voltage adjusting module 20.

[0100] The output control module 10 is connected to the gate of the first transistor T1 and the gate of the second transistor T2, the first electrode of the first transistor T1 is connected to the first output signal, the second electrode of the first transistor T1 is connected to the output end O1 of the gate drive circuit, the first electrode of the second transistor T2 is connected to the second output signal, and the second electrode of the second transistor T2 is connected to the output end O1 of the gate drive circuit. The output control module 10 is used to control the first transistor T1 and the second transistor T2 to conduct alternately, so as to alternately transmit the first output signal and the second output signal to the output end O1 of the gate drive circuit. Among them, at least one of the first transistor T1 and the second transistor T2 is a double-gate transistor, and the first gate of the double-gate transistor is connected to the output control module 10.

[0101] The voltage adjustment module 20 is connected to the second gate of the double-gate transistor, and the voltage adjustment module 20 is used to adjust the voltage of the second gate of the double-gate transistor.

[0102] Specifically, one of the first output signal and the second output signal contains a relatively low level, and the other contains a relatively high level. Figure 1 Taking the third level signal VGL as the first output signal and the second level signal VGH as the second output signal as an example, one of the third level signal VGL and the second level signal VGH contains a relatively low level, and the other contains a relatively high level. By controlling the first transistor T1 and the second transistor T2 to conduct alternately through the output control module 10, the first transistor T1 and the second transistor T2 can alternately transmit signals to the output end O1 of the gate drive circuit, so that the output end O1 of the gate drive circuit outputs the gate drive signal with high level and low level alternately.

[0103] At least one of the first transistor T1 and the second transistor T2 is a dual-gate transistor, which can be a dual-gate transistor including a top gate and a bottom gate. The first gate of the dual-gate transistor can be one of the top gate and the bottom gate, and the second gate can be the other one of the top gate and the bottom gate. For example, the first gate of the dual-gate transistor can be the top gate, and the second gate can be the bottom gate. When the first transistor T1 is a dual-gate transistor, the first gate of the first transistor T1 is connected to the output control module 10, and the second gate of the first transistor T1 is connected to the voltage adjustment module 20, so that the first gate voltage of the first transistor T1 is controlled by the output control module 10 to control the conduction or non-conduction of the first transistor T1, and the second gate voltage of the first transistor T1 is adjusted by the voltage adjustment module 20. Similarly, when the second transistor T2 is a dual-gate transistor, the first gate of the second transistor T2 is connected to the output control module 10, and the second gate of the second transistor T2 is connected to the voltage adjustment module 20, so that the first gate voltage of the second transistor T2 is controlled by the output control module 10 to control the conduction or non-conduction of the second transistor T2, and the second gate voltage of the second transistor T2 is adjusted by the voltage adjustment module 20.

[0104] According to the characteristics of the dual-gate transistor, the threshold voltage of the dual-gate transistor is affected by the potential of the second gate. When the dual-gate transistor is an N-type transistor, the more positive the potential of the second gate is, the more negative the threshold voltage of the dual-gate transistor is, and the more negative the potential of the second gate is, the more positive the threshold voltage of the dual-gate transistor is. When the dual-gate transistor is a P-type transistor, the more positive the potential of the second gate is, the more negative the threshold voltage of the dual-gate transistor is, and the more negative the potential of the second gate is, the more positive the threshold voltage of the dual-gate transistor is.

[0105] In the case where the first transistor T1 is a dual-gate transistor, the voltage adjustment module 20 can include a first voltage adjustment module 20a connected to the second gate of the first transistor T1. In the case where the second transistor T2 is a dual-gate transistor, the voltage adjustment module 20 can include a second voltage adjustment module 20b connected to the second gate of the second transistor T2. In an embodiment, as shown in FIG. 2, the first transistor T1 and the second transistor T2 can both be dual-gate transistors, the second gate of the first transistor T1 is connected to the first voltage adjustment module 20a, and the second gate of the second transistor T2 is connected to the second voltage adjustment module 20b. In other embodiments, when any one of the first transistor T1 and the second transistor T2 is a dual-gate transistor, only the voltage adjustment module 20 connected to the dual-gate transistor can be provided, and when both the first transistor T1 and the second transistor T2 are dual-gate transistors, only the voltage adjustment module 20 connected to one of the dual-gate transistors can be provided. Figure 1 ​

[0106] Optionally, the voltage adjusting module 20 is configured to adjust the second gate voltage of the double-gate transistor to improve the driving capability of the double-gate transistor when the double-gate transistor is turned on, and / or to suppress the leakage current of the double-gate transistor when the double-gate transistor is turned off.

[0107] The working principle of the gate driving circuit shown in FIG. 1 will be described below with the first transistor T1 and the second transistor T2 being N-type transistors, and the third-level signal VGL containing a low level and the second-level signal VGH containing a high level as examples. Figure 1

[0108] When the output control module 10 controls the first transistor T1 to be turned off and the second transistor T2 to be turned on, the second-level signal VGH is transmitted to the output end O1 of the gate driving circuit through the second transistor T2, and the gate driving signal output by the gate driving circuit is a high-level signal. The voltage adjusting module 20 corresponding to the second transistor T2 can transmit a potential greater than 0V to the second gate of the second transistor T2 when the second transistor T2 is turned on, so as to raise the second gate voltage of the second transistor T2 and make the threshold voltage of the second transistor T2 more negative. In the case where the first gate voltage of the second transistor T2 is unchanged, the more negative the threshold voltage of the second transistor T2, the greater the current of the second transistor T2, and thus the driving capability of the second transistor T2 can be improved to improve the waveform distortion problem of the gate driving signal. Meanwhile, the voltage adjusting module 20 corresponding to the first transistor T1 can transmit a potential less than 0V to the second gate of the first transistor T1 when the first transistor T1 is turned off, so as to lower the second gate voltage of the first transistor T1 and make the threshold voltage of the first transistor T1 more positive. In the case where the first gate voltage of the first transistor T1 is unchanged, the more positive the threshold voltage of the first transistor T1, the less negative the first gate voltage required for turning off the first transistor T1, so as to avoid the situation that the first transistor T1 is not turned off, i.e., the first transistor T1 is still in the sub-threshold region or in the on state when the first gate voltage of the first transistor T1 is not low enough. Therefore, when the first transistor T1 is turned off, the voltage adjusting module 20 corresponding to the first transistor T1 transmits a potential less than 0V to the second gate of the first transistor T1 to lower the second gate voltage of the first transistor T1 and make the threshold voltage of the first transistor T1 more positive, which can make the first transistor T1 more easily turned off, thus helping to avoid the leakage problem caused by the failure of the first transistor T1 to be completely turned off, so as to suppress the leakage current of the first transistor T1, further improve the waveform distortion problem of the gate driving signal, and help to reduce the power consumption of the first transistor T1 caused by the leakage current.

[0109] ​Similarly, when the output control module 10 controls the second transistor T2 to be turned off and the first transistor T1 to be turned on, the third level signal VGL is transmitted to the output end O1 of the gate drive circuit through the first transistor T1, and the gate drive signal output by the gate drive circuit is a low level signal. The voltage adjusting module 20 corresponding to the first transistor T1 can transmit a potential greater than 0V to the second gate of the first transistor T1 when the first transistor T1 is turned on, so as to raise the second gate voltage of the first transistor T1, so that the threshold voltage of the first transistor T1 is negatively biased, thereby improving the driving capability of the first transistor T1 and improving the waveform distortion problem of the gate drive signal. At the same time, the voltage adjusting module 20 corresponding to the second transistor T2 can transmit a potential less than 0V to the second gate of the second transistor T2 when the second transistor T2 is turned off, so as to lower the second gate voltage of the second transistor T2, so that the threshold voltage of the second transistor T2 is positively biased, which helps to avoid the leakage problem caused by the failure of the second transistor T2 to be completely turned off, so as to suppress the leakage current of the second transistor T2, thereby further improving the waveform distortion problem of the gate drive signal and helping to reduce the power consumption of the second transistor T2 caused by the leakage current.

[0110] In other embodiments, when the first transistor T1 and the second transistor T2 are both P-type transistors, the voltage adjusting module 20 can transmit a potential less than 0V to the second gate of the corresponding double-gate transistor (i.e. the first transistor T1 or the second transistor T2) when the double-gate transistor is turned on, so as to lower the second gate voltage of the double-gate transistor, so that the threshold voltage of the double-gate transistor is positively biased, thereby improving the driving capability of the double-gate transistor and improving the waveform distortion problem of the gate drive signal. The voltage adjusting module 20 can transmit a potential greater than 0V to the second gate of the double-gate transistor when the double-gate transistor is turned off, so as to raise the second gate voltage of the double-gate transistor, so that the threshold voltage of the double-gate transistor is negatively biased, thereby suppressing the leakage current of the double-gate transistor, reducing the power consumption of the double-gate transistor caused by the leakage current, and further improving the waveform distortion problem of the gate drive signal.

[0111] It should be noted that the above embodiment is only described by taking the case that the voltage adjustment module 20 adjusts the second gate voltage of the double-gate transistor to improve the driving capability of the double-gate transistor when the corresponding double-gate transistor is turned on, and the voltage adjustment module 20 adjusts the second gate voltage of the double-gate transistor to suppress the leakage current of the double-gate transistor when the corresponding double-gate transistor is turned off as an example. In other embodiments, only the voltage adjustment module 20 can be arranged to adjust the second gate voltage of the double-gate transistor to improve the driving capability of the double-gate transistor when the corresponding double-gate transistor is turned on, or only the voltage adjustment module 20 can be arranged to adjust the second gate voltage of the double-gate transistor to suppress the leakage current of the double-gate transistor when the corresponding double-gate transistor is turned off. Both of the above two arrangements can help to improve the gate driving signal waveform distortion problem of the gate driving circuit.

[0112] In summary, the technical scheme of the embodiment of the present application, by the output control module controls the first transistor and the second transistor to turn on alternately, so as to alternately transmit the first output signal and the second output signal to the output end of the gate driving circuit as the gate driving signal, by setting at least one of the first transistor and the second transistor as a double-gate transistor, so that the voltage adjustment module can be used to adjust the threshold voltage of the double-gate transistor by adjusting the second gate voltage of the double-gate transistor when the double-gate transistor is turned on, so as to improve the driving capability of the double-gate transistor, thereby improving the driving capability of the gate driving signal output by the gate driving circuit, and improving the waveform distortion problem of the gate driving signal, and the voltage adjustment module can also be used to adjust the threshold voltage of the double-gate transistor by adjusting the second gate voltage of the double-gate transistor when the double-gate transistor is turned off, so as to suppress the leakage current of the double-gate transistor, thereby reducing the power consumption of the double-gate transistor due to the leakage current, and further improving the waveform distortion problem of the gate driving signal, which helps to improve the display effect of the display panel.

[0113] Figure 2 is another structural schematic diagram of a gate driving circuit provided by the embodiment of the present application. Referring to Figure 2 In an embodiment, the control end of the voltage adjustment module 20 can be connected to the first control signal, the first end of the voltage adjustment module 20 can be connected to the first level signal VGLL, and the second end of the voltage adjustment module 20 can be connected to the second gate of the double-gate transistor. The voltage adjustment module 20 is used to transmit the first level signal VGLL to the second gate of the double-gate transistor in response to the first control signal when the double-gate transistor is turned off, so as to suppress the leakage current of the double-gate transistor.

[0114] Exemplarily, when the first transistor T1 is a double-gate transistor, a first voltage adjusting module 20a corresponding to the first transistor T1 can be arranged, a control terminal of the first voltage adjusting module 20a is connected to the first control signal A1-1, and a second terminal of the first voltage adjusting module 20a is connected to the second gate of the first transistor T1. When the first transistor T1 is turned off, the first voltage adjusting module 20a is turned on in response to the first control signal A1-1, the first level signal VGLL is transmitted to the second gate of the first transistor T1 through the first voltage adjusting module 20a, the voltage of the second gate of the first transistor T1 is adjusted by the first level signal VGLL, the threshold voltage of the first transistor T1 is adjusted, and the complete turn-off of the first transistor T1 is ensured, thereby inhibiting the leakage current of the first transistor T1. Similarly, when the second transistor T2 is a double-gate transistor, a second voltage adjusting module 20b corresponding to the second transistor T2 can be arranged, a control terminal of the second voltage adjusting module 20b is connected to the first control signal A1-2, and a second terminal of the second voltage adjusting module 20b is connected to the second gate of the second transistor T2. When the second transistor T2 is turned off, the second voltage adjusting module 20b is turned on in response to the first control signal A1-2, the first level signal VGLL is transmitted to the second gate of the second transistor T2 through the second voltage adjusting module 20b, the voltage of the second gate of the second transistor T2 is adjusted by the first level signal VGLL, the threshold voltage of the second transistor T2 is adjusted, and the complete turn-off of the second transistor T2 is ensured, thereby inhibiting the leakage current of the second transistor T2. Optionally, when the first transistor T1 or the second transistor T2 is an N-type double-gate transistor, the potential of the first level signal VGLL can be a potential less than 0V.

[0115] Continuing to refer to Figure 2 Further, the voltage adjusting module 20 comprises a third transistor, a gate of the third transistor is connected to the first control signal, a first pole of the third transistor is connected to the first level signal VGLL, and a second pole of the third transistor is connected to the second gate of the double-gate transistor. Exemplarily, when the first transistor T1 is a double-gate transistor, the first voltage adjusting module 20a can be arranged to comprise a third transistor T3-1, a gate of the third transistor T3-1 is connected to the first control signal A1-1, a first pole of the third transistor T3-1 is connected to the first level signal VGLL, and a second pole of the third transistor T3-1 is connected to the second gate of the first transistor T1. When the second transistor T2 is a double-gate transistor, the second voltage adjusting module 20b can be arranged to comprise a third transistor T3-2, a gate of the third transistor T3-2 is connected to the first control signal A1-2, a first pole of the third transistor T3-2 is connected to the first level signal VGLL, and a second pole of the third transistor T3-2 is connected to the second gate of the second transistor T2.

[0116] In another embodiment, a clock signal can be used to replace the first level signal VGLL, the clock signal including a signal with high level and low level alternately, for example, the clock signal including a high level greater than 0V and a low level less than 0V. In the case that the double-gate transistor connected with the voltage adjustment module 20 is an N-type transistor, the low level less than 0V in the clock signal can be transmitted to the second gate of the double-gate transistor by the voltage adjustment module 20 (or the third transistor) when the double-gate transistor is off, so as to adjust the threshold voltage of the double-gate transistor, and to help ensure that the double-gate transistor is completely off, thereby suppressing the leakage current of the double-gate transistor; in the case that the double-gate transistor connected with the voltage adjustment module 20 is a P-type transistor, the high level greater than 0V in the clock signal can be transmitted to the second gate of the double-gate transistor by the voltage adjustment module 20 (or the third transistor) when the double-gate transistor is off, so as to adjust the threshold voltage of the double-gate transistor, and to help ensure that the double-gate transistor is completely off, thereby suppressing the leakage current of the double-gate transistor.

[0117] In another embodiment, a clock signal can be used to replace the first level signal VGLL, and a capacitor can be arranged between the second electrode of the third transistor and the second gate of the double-gate transistor, for example, when the first transistor T1 is a double-gate transistor, a capacitor can be arranged between the second electrode of the third transistor T3-1 in the first voltage adjustment module 20a and the second gate of the first transistor T1, so as to control the third transistor T3-1 to transmit the clock signal to the capacitor when the first transistor T1 is off, and to couple the voltage of the second gate of the first transistor T1 according to the jump of the clock signal through the capacitor, so as to adjust the threshold voltage of the first transistor T1, thereby ensuring that the first transistor T1 is completely off, so as to suppress the leakage current of the first transistor T1. Similarly, when the second transistor T2 is a double-gate transistor, a capacitor can be arranged between the second electrode of the third transistor T3-2 in the second voltage adjustment module 20b and the second gate of the second transistor T2, and a clock signal can be used to replace the first level signal VGLL.

[0118] Figure 3 is another structure diagram of a gate drive circuit provided by an embodiment of the present application. Referring to Figure 3 In an embodiment, the control end of the voltage adjustment module 20 can be connected to the second control signal, the first end of the voltage adjustment module 20 can be connected to the preset signal, and the second end of the voltage adjustment module 20 can be connected to the second gate of the double-gate transistor. The voltage adjustment module 20 is configured to adjust the voltage of the second gate of the double-gate transistor by the preset signal when the double-gate transistor is turned on in response to the second control signal, so as to improve the driving capability of the double-gate transistor.

[0119] The preset signal can be a fixed level signal or a jumping level signal, where the jumping level signal refers to a signal whose level jumps between a high level and a low level, such as a clock signal.

[0120] Exemplarily, the second level signal VGH can be used as the preset signal. When the first transistor T1 is a double-gate transistor, a first voltage adjustment module 20a corresponding to the first transistor T1 can be provided, a control end of the first voltage adjustment module 20a is connected to the second control signal A2-1, and a second end of the first voltage adjustment module 20a is connected to the second gate of the first transistor T1. When the first transistor T1 is turned on, the first voltage adjustment module 20a is turned on in response to the second control signal A2-1, so that the second level signal VGH is transmitted to the second gate of the first transistor T1 through the first voltage adjustment module 20a, and the second gate voltage of the first transistor T1 is adjusted through the second level signal VGH, so as to adjust the threshold voltage of the first transistor T1, thereby improving the driving capability of the first transistor T1. Similarly, when the second transistor T2 is a double-gate transistor, a second voltage adjustment module 20b corresponding to the second transistor T2 can be provided, a control end of the second voltage adjustment module 20b is connected to the second control signal A2-2, and a second end of the second voltage adjustment module 20b is connected to the second gate of the second transistor T2. When the second transistor T2 is turned on, the second voltage adjustment module 20b is turned on in response to the second control signal A2-2, so that the second level signal VGH is transmitted to the second gate of the second transistor T2 through the second voltage adjustment module 20b, and the second gate voltage of the second transistor T2 is adjusted through the second level signal VGH, so as to adjust the threshold voltage of the second transistor T2, thereby improving the driving capability of the second transistor T2. Optionally, when the first transistor T1 or the second transistor T2 is an N-type double-gate transistor, the potential of the second level signal VGH can be a potential greater than 0V.

[0121] Continuing to refer to Figure 3Further, the voltage adjusting module 20 comprises a fourth transistor, a gate of the fourth transistor is connected to the second control signal, a first pole of the fourth transistor is connected to the preset signal, and the fourth transistor is configured to transmit the preset signal to the second gate of the double-gate transistor in response to the second control signal. For example, when the first transistor T1 is a double-gate transistor, the first voltage adjusting module 20a can be configured to comprise a fourth transistor T4-1, a gate of the fourth transistor T4-1 is connected to the second control signal A2-1, a first pole of the fourth transistor T4-1 is connected to the second level signal VGH, and a second pole of the fourth transistor T4-1 is connected to the second gate of the first transistor T1. When the second transistor T2 is a double-gate transistor, the second voltage adjusting module 20b can be configured to comprise a fourth transistor T4-2, a gate of the fourth transistor T4-2 is connected to the second control signal A2-2, a first pole of the fourth transistor T4-2 is connected to the second level signal VGH, and a second pole of the fourth transistor T4-2 is connected to the second gate of the second transistor T2.

[0122] Figure 4 is another structural schematic diagram of a gate driving circuit provided by an embodiment of the present application. Referring to Figure 4On the basis of the above-mentioned embodiments, the voltage regulating module 20 further comprises a first capacitor connected between the second electrode of the fourth transistor and the second gate of the double-gate transistor. Specifically, when the first transistor T1 is a double-gate transistor, the first voltage regulating module 20a can be configured to further comprise a first capacitor C1-1 connected between the second electrode of the fourth transistor T4-1 and the second gate of the first transistor T1. In the case where the preset signal is a clock signal, for example, the second clock signal CK2, and the first transistor T1 is an N-type transistor, the fourth transistor T4-1 can be turned on in response to the second control signal A2-1 when the first transistor T1 is turned on, so that the second clock signal CK2 is transmitted to the first capacitor C1-1 through the fourth transistor T4-1, so as to couple the potential of the second gate of the first transistor T1 through the first capacitor C1-1 when the level of the second clock signal CK2 jumps from low to high, so as to raise the voltage of the second gate of the first transistor T1, so as to bias the threshold voltage of the first transistor T1 to be negative, thereby improving the driving capability of the first transistor T1. In addition, when the level of the second clock signal CK2 is low, there is a voltage difference between the second gate of the first transistor T1 and the first electrode of the fourth transistor T4-1, and by arranging the first capacitor C1-1 between the second electrode of the fourth transistor T4-1 and the second gate of the first transistor T1, the current transmission path between the second electrode of the fourth transistor T4-1 and the second gate of the first transistor T1 is blocked through the first capacitor C1-1, so as to avoid the low level in the second clock signal CK2 from being transmitted to the second gate of the first transistor T1, thereby affecting the working state of the first transistor T1. Similarly, when the second transistor T2 is a double-gate transistor, the second voltage regulating module 20b can be configured to further comprise a first capacitor C1-2 connected between the second electrode of the fourth transistor T4-2 and the second gate of the second transistor T2. The first capacitor C1-2 and the first capacitor C1-1 have similar functions, which will not be described here.

[0123] Figure 5 is another structure schematic diagram of a gate drive circuit provided by an embodiment of the present application. Referring to Figure 5Optionally, the voltage adjustment module 20 further comprises a fifth transistor connected between the gate of the fourth transistor and the second control signal end, and the fifth transistor keeps open state. Specifically, when the first transistor T1 is a double-gate transistor, the first voltage adjustment module 20a can be configured to further comprise a fifth transistor T5-1 connected between the gate of the fourth transistor T4-1 and the second control signal end, and the second control signal A2-1 is input to the gate of the fourth transistor T4-1 through the fifth transistor T5-1. The fifth transistor T5-1 helps to block the extremely low / high potential in the second control signal A2-1, so as to avoid the extremely low / high potential in the second control signal A2-1 from being transmitted to the fourth transistor T4-1, thereby avoiding damage to the fourth transistor T4-1 and affecting the normal work of the fourth transistor T4-1. Similarly, when the second transistor T2 is a double-gate transistor, the second voltage adjustment module 20b can be configured to further comprise a fifth transistor T5-2 connected between the gate of the fourth transistor T4-2 and the second control signal end, and the second control signal A2-2 is input to the gate of the fourth transistor T4-2 through the fifth transistor T5-2. The fifth transistor T5-2 and the fifth transistor T5-1 have similar functions, and will not be described here.

[0124] Figure 6 is another structure diagram of a gate drive circuit provided by an embodiment of the present application. Referring to Figure 6 Optionally, in another embodiment, the voltage adjustment module 20 can also be configured to comprise a first voltage adjustment unit 210 and a second voltage adjustment unit 220. The control end of the first voltage adjustment unit 210 is connected to the first control signal, the first end of the first voltage adjustment unit 210 is connected to the first level signal VGLL, and the second end of the first voltage adjustment unit 210 is connected to the second gate of the double-gate transistor. The first voltage adjustment unit 210 is configured to transmit the first level signal VGLL to the second gate of the double-gate transistor in response to the first control signal when the double-gate transistor is turned off. The control end of the second voltage adjustment unit 220 is connected to the second control signal, the first end of the second voltage adjustment unit 220 is connected to the preset signal, and the second end of the second voltage adjustment unit 220 is connected to the second gate of the double-gate transistor. The second voltage adjustment unit 220 is configured to adjust the second gate voltage of the double-gate transistor through the preset signal when the double-gate transistor is turned on in response to the second control signal.

[0125] Exemplarily, in a case that the first transistor T1 is a double-gate transistor, the voltage adjustment module 20 can be configured to include a first voltage adjustment module 20a connected to the second gate of the first transistor T1. In the first voltage adjustment module 20a: the control end of the first voltage adjustment unit 210 is connected to the first control signal A1-1, the second end of the first voltage adjustment unit 210 is connected to the second gate of the first transistor T1, the control end of the second voltage adjustment unit 220 is connected to the second control signal A2-1, and the second end of the second voltage adjustment unit 220 is connected to the second gate of the first transistor T1. In this way, when the output control module 10 controls the first transistor T1 to be off, the first voltage adjustment unit 210 can transmit a first-level signal VGLL to the second gate of the first transistor T1 in response to the first control signal A1-1, and the second gate voltage of the first transistor T1 is adjusted by the first-level signal VGLL to adjust the threshold voltage of the first transistor T1, so as to suppress the leakage current of the first transistor T1. When the output control module 10 controls the first transistor T1 to be on, the second voltage adjustment unit 220 can transmit a signal related to a preset signal to the second gate of the first transistor T1 in response to the second control signal A2-1, and the second gate voltage of the first transistor T1 is adjusted by the preset signal to adjust the threshold voltage of the first transistor T1, so as to improve the driving capability of the first transistor T1.

[0126] Similarly, in a case that the second transistor T2 is a double-gate transistor, the voltage adjustment module 20 can be configured to include a second voltage adjustment module 20b connected to the second gate of the second transistor T2. In the second voltage adjustment module 20b: the control end of the first voltage adjustment unit 210 is connected to the first control signal A1-2, the second end of the first voltage adjustment unit 210 is connected to the second gate of the second transistor T2, the control end of the second voltage adjustment unit 220 is connected to the second control signal A2-2, and the second end of the second voltage adjustment unit 220 is connected to the second gate of the second transistor T2. The working principles of the first voltage adjustment unit 210 and the second voltage adjustment unit 220 in the second voltage adjustment module 20b are similar to those of the first voltage adjustment unit 210 and the second voltage adjustment unit 220 in the first voltage adjustment module 20a, and will not be described herein again.

[0127] Figure 7 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. Referring to Figure 7On the basis of the above-mentioned embodiments, optionally, the first voltage adjusting unit 210 comprises a third transistor, and the second voltage adjusting unit 220 comprises a fourth transistor. The gate of the third transistor is connected to the first control signal, the first pole of the third transistor is connected to the first level signal VGLL, and the second pole of the third transistor is connected to the second gate of the double-gate transistor. The gate of the fourth transistor is connected to the second control signal, the first pole of the fourth transistor is connected to the preset signal, and the fourth transistor is configured to transmit a signal related to the preset signal to the second gate of the double-gate transistor in response to the second control signal.

[0128] Specifically, in the case where the first transistor T1 is a double-gate transistor, the first voltage adjusting module 20a can be configured to connect to the second gate of the first transistor T1. In the first voltage adjusting module 20a: the gate of the third transistor T3-1 is connected to the first control signal A1-1, the first pole of the third transistor T3-1 is connected to the first level signal VGLL, and the second pole of the third transistor T3-1 is connected to the second gate of the first transistor T1. The gate of the fourth transistor T4-1 is connected to the second control signal A2-1, the first pole of the fourth transistor T4-1 is connected to the preset signal, and the fourth transistor T4-1 is configured to transmit a signal related to the preset signal to the second gate of the first transistor T1 in response to the second control signal A2-1. In the case where the second transistor T2 is a double-gate transistor, the second voltage adjusting module 20b can be configured to connect to the second gate of the second transistor T2. In the second voltage adjusting module 20b: the gate of the third transistor T3-2 is connected to the first control signal A1-2, the first pole of the third transistor T3-2 is connected to the first level signal VGLL, and the second pole of the third transistor T3-2 is connected to the second gate of the second transistor T2. The gate of the fourth transistor T4-2 is connected to the second control signal A2-2, the first pole of the fourth transistor T4-2 is connected to the preset signal, and the fourth transistor T4-2 is configured to transmit a signal related to the preset signal to the second gate of the second transistor T2 in response to the second control signal A2-2.

[0129] Continuing to refer to Figure 7Further, in an embodiment, the second voltage adjusting unit 220 further comprises a first capacitor connected between the second electrode of the fourth transistor and the second gate of the double-gate transistor. For example, in the case that the first transistor T1 is a double-gate transistor, the first voltage adjusting module 20a can further comprise a first capacitor C1-1 connected between the second electrode of the fourth transistor T4-1 and the second gate of the first transistor T1, and the preset signal inputted to the first electrode of the fourth transistor T4-1 can be a clock signal, for example, the second clock signal CK2. In the case that the second transistor T2 is a double-gate transistor, the second voltage adjusting module 20b can further comprise a first capacitor C1-2 connected between the second electrode of the fourth transistor T4-2 and the second gate of the second transistor T2, and the preset signal inputted to the first electrode of the fourth transistor T4-2 can also be a clock signal, for example, the second clock signal CK2.

[0130] In another embodiment, when the first capacitor C1-1 is not arranged in the first voltage adjusting module 20a, and the second electrode of the fourth transistor T4-1 is directly connected to the second gate of the first transistor T1, the preset signal inputted to the first electrode of the fourth transistor T4-1 can be the second level signal VGH. Similarly, when the first capacitor C1-2 is not arranged in the second voltage adjusting module 20b, and the second electrode of the fourth transistor T4-2 is directly connected to the second gate of the second transistor T2, the preset signal inputted to the first electrode of the fourth transistor T4-2 can also be the second level signal VGH.

[0131] On the basis of the above embodiments, optionally, the level of the first level signal VGLL comprises a first level; the level of the preset signal comprises a second level, one of the first level and the second level is a preset high level, and the other is a preset low level. Specifically, the preset high level refers to a high level opposite to the preset low level, and the voltage corresponding to the preset high level can be a voltage corresponding to a high level for normally controlling the transistor to be turned on or turned off, for example, the voltage corresponding to the preset high level can be a voltage of about 3.5V to 5V, and the voltage corresponding to the preset low level can be a voltage corresponding to a low level for normally controlling the transistor to be turned on or turned off, for example, the voltage corresponding to the preset low level can be a voltage of about -5V to -7V.

[0132] Further, in the case that the double-gate transistor in the first transistor T1 and the second transistor T2 is an N-type transistor, the first level included in the first level signal VGLL is a preset low level, and the second level included in the preset signal is a preset high level. Taking the case that the first transistor T1 is a double-gate transistor and the first transistor T1 is an N-type transistor as an example, when the first transistor T1 is turned off, by transmitting the first level signal VGLL, i.e., the preset low level signal, to the second gate of the first transistor T1, the voltage at the second gate of the first transistor T1 can be reduced, so as to make the threshold voltage of the first transistor T1 positive bias, which helps to ensure that the first transistor T1 is completely turned off, thereby inhibiting the leakage current of the first transistor T1. The second level signal VGH or the second clock signal CK2 in the above embodiment can be used as the preset signal. When the first transistor T1 is turned on, by adjusting the voltage at the second gate of the first transistor T1 through the preset high level in the second level signal VGH or the second clock signal CK2, the voltage at the second gate of the first transistor T1 can be raised, so as to make the threshold voltage of the first transistor T1 negative bias. In the case that the voltage at the first gate of the first transistor T1 is unchanged, the more negative the threshold voltage of the first transistor T1 is, the greater the current of the first transistor T1 is, thereby improving the driving capability of the first transistor T1.

[0133] In the case that the double-gate transistor in the first transistor T1 and the second transistor T2 is a P-type transistor, the first level included in the first level signal VGLL is a preset high level, and the second level included in the preset signal is a preset low level. The specific principle is the same as before, and will not be described again.

[0134] It should be noted that, Figures 1 to 7 In the above embodiments, the case that the first transistor T1 and the second transistor T2 are both double-gate transistors, and the voltage adjustment module 20 includes the first voltage adjustment module 20a and the second voltage adjustment module 20b is taken as an example for illustration. In other embodiments, when any one of the first transistor T1 and the second transistor T2 is a double-gate transistor, only the voltage adjustment module 20 connected to the double-gate transistor can be provided. When the first transistor T1 and the second transistor T2 are both double-gate transistors, only the voltage adjustment module 20 connected to one of the double-gate transistors can be provided.

[0135] Figure 4 、 Figure 5 and Figure 7The first capacitor (i.e. C1-1 or C1-2) is included in the voltage adjustment module 20 and connected between the second electrode of the fourth transistor and the second gate electrode of the corresponding double-gate transistor. In other embodiments, the voltage adjustment module 20 can not include the first capacitor, the first electrode of the fourth transistor is connected to the second clock signal CK2, and the second electrode of the fourth transistor is directly connected to the second gate electrode of the corresponding double-gate transistor. For example, refer to Figure 7 The first capacitor C1-1 in the voltage adjustment module 20 can be removed, so that the first electrode of the fourth transistor T4-1 is connected to the second clock signal CK2, and the second electrode of the fourth transistor T4-1 is directly connected to the second gate electrode of the first transistor T1. In this way, when the first transistor T1 is an N-type transistor, the fourth transistor T4-1 can transmit a preset high level in the second clock signal CK2 to the second gate electrode of the first transistor T1 to raise the voltage of the second gate electrode of the first transistor T1 when the first transistor T1 is turned on, so as to offset the threshold voltage of the first transistor T1 to negative, thereby improving the driving capability of the first transistor T1. Similarly, the first capacitor C1-2 in the voltage adjustment module 20 can also be removed, so that the first electrode of the fourth transistor T4-2 is connected to the second clock signal CK2, and the second electrode of the fourth transistor T4-2 is directly connected to the second gate electrode of the second transistor T2.

[0136] Figure 8 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. Figure 9 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. Refer to Figure 8 and Figure 9 Optionally, the third transistor in the voltage adjustment module 20 can also be a double-gate transistor. In an embodiment, the first gate electrode of the third transistor is connected to the first control signal, and the second gate electrode of the third transistor is connected to the first level signal VGLL.

[0137] Exemplarily, when the second transistor T2 is a double-gate transistor, the third transistor T3-2 in the second voltage adjusting module 20b can be a double-gate transistor, the first gate of the third transistor T3-2 is connected to the first control signal A1-2, and the second gate of the third transistor T3-2 is connected to the first pole of the third transistor T3-2 to access the first level signal VGLL. In the case that the second transistor T2 is an N-type transistor, the first level included in the first level signal VGLL is a preset low level, when the output control module 10 controls the second transistor T2 to be turned on, the fourth transistor T4-2 is turned on in response to the second control signal A2-2, so that the second clock signal CK2 is transmitted to the first capacitor C1-2 through the fourth transistor T4-2, so as to couple the potential of the second gate of the second transistor T2 through the first capacitor C1-2 when the level of the second clock signal CK2 jumps from low level to high level, so as to raise the second gate voltage of the second transistor T2, so as to make the threshold voltage of the second transistor T2 be negatively biased, thereby improving the driving capability of the second transistor T2. Since the second gate voltage of the second transistor T2 is high, and the voltage of the first level signal VGLL is low, there is a voltage difference between the two ends of the third transistor T3-2, by setting the second gate of the third transistor T3-2 to access the first level signal VGLL, the potential of the second gate of the third transistor T3-2 is low, which helps to make the threshold voltage of the third transistor T3-2 be positively biased, and ensures that the third transistor T3-2 is in the off state under the condition that the voltage of the first gate of the third transistor T3-2 is unchanged, so as to avoid that the third transistor T3-2 is not in the completely off state, thereby there is a large leakage current, which affects the second gate voltage of the second transistor T2, thereby affecting the driving capability of the second transistor T2.

[0138] Similarly, when the first transistor T1 is a double-gate transistor, and the voltage adjusting module 20 includes the first voltage adjusting module 20a corresponding to the first transistor T1, the third transistor in the first voltage adjusting module 20a can also be a double-gate transistor, and the first gate of the third transistor is connected to the first control signal, and the second gate of the third transistor is connected to the first pole of the third transistor, so that the second gate of the third transistor accesses the first level signal VGLL.

[0139] Figure 10 is another structure diagram of a gate drive circuit provided by an embodiment of the present application. Referring to Figure 10 Optionally, in another embodiment, when the third transistor in the voltage adjusting module 20 is a double-gate transistor, the second gate of the third transistor can also be connected to the first control signal, and the first gate of the third transistor is connected to the first pole of the third transistor.

[0140] Exemplarily, when the second transistor T2 is a double-gate transistor, the third transistor T3-2 in the second voltage adjusting module 20b can be a double-gate transistor, the second gate of the third transistor T3-2 is connected to the first control signal A1-2, and the first gate of the third transistor T3-2 is connected to the first pole of the third transistor T3-2 to access the first level signal VGLL. The following still takes the second transistor T2 as an N-type transistor and the first level included in the first level signal VGLL as a preset low level as an example for description. As described in the above embodiment, when the output control module 10 controls the second transistor T2 to be turned on, in order to improve the driving capability of the second transistor T2, it is needed to raise the second gate voltage of the second transistor T2, so that there is a voltage difference between the two ends of the third transistor T3-2. By setting the first gate of the third transistor T3-2 to access the first level signal VGLL, the threshold voltage of the third transistor T3-2 can be positively biased, and in the case that the second gate voltage of the third transistor T3-2 is unchanged, the third transistor T3-2 is ensured to be in the off state, so as to avoid that the third transistor T3-2 is not in the completely off state, and then there is a large leakage current which affects the second gate voltage of the second transistor T2, thereby affecting the driving capability of the second transistor T2. In addition, since the second gate of the third transistor T3-2 accesses the first control signal A1-2, by controlling the second gate voltage of the third transistor T3-2, the turn-on and turn-off of the third transistor T3-2 can also be controlled, so that the third transistor T3-2 can still be turned on in response to the first control signal A1-2 when the second transistor T2 is turned off, the first level signal VGLL is transmitted to the second gate of the second transistor T2 through the third transistor T3-2, the second gate voltage of the second transistor T2 is adjusted by the first level signal VGLL, the threshold voltage of the second transistor T2 is adjusted, which helps to ensure that the second transistor T2 is completely turned off, thereby suppressing the leakage current of the second transistor T2.

[0141] Similarly, when the first transistor T1 is a double-gate transistor and the voltage adjusting module 20 includes the first voltage adjusting module 20a corresponding to the first transistor T1, the third transistor in the first voltage adjusting module 20a can also be set as a double-gate transistor, and the second gate of the third transistor accesses the first control signal, and the first gate of the third transistor is connected to the first pole of the third transistor to access the first level signal VGLL.

[0142] Figure 11 is another structure schematic diagram of a gate driving circuit provided by an embodiment of the present application. Referring to Figures 8 to 11When the first transistor T1 and the second transistor T2 are both double-gate transistors, the second gate of one of the first transistor T1 and the second transistor T2 can be connected to the first-level signal line 30, and the first-level signal line 30 is connected to the first-level signal VGLL, and the second gate of the other of the first transistor T1 and the second transistor T2 is connected to the voltage adjustment module 20.

[0143] For example, the second gate of the first transistor T1 is connected to the first-level signal line 30, and the second gate of the second transistor T2 is connected to the voltage adjustment module 20. When the first transistor T1 and the second transistor T2 are both N-type transistors, the first level included in the first-level signal VGLL is a preset low level. The first-level signal line 30 can transmit the first-level signal VGLL to the second gate of the first transistor T1 to reduce the second gate voltage of the first transistor T1, which helps to avoid the leakage problem caused by the failure of the first transistor T1 to completely turn off, thereby suppressing the leakage current of the first transistor T1. The third transistor T3-2 in the voltage adjustment module 20 can transmit the first-level signal VGLL to the second gate of the second transistor T2 when the second transistor T2 is turned off, which helps to ensure that the second transistor T2 is completely turned off, thereby suppressing the leakage current of the second transistor T2. The fourth transistor T4-2 can transmit the second clock signal CK2 to the first capacitor C1-2 when the second transistor T2 is turned on, so as to raise the second gate voltage of the second transistor T2 through the coupling effect of the first capacitor C1-2, so as to bias the threshold voltage of the second transistor T2 to be negative, thereby improving the driving capability of the second transistor T2.

[0144] When the first transistor T1 and the second transistor T2 are both P-type transistors, the first level included in the first-level signal VGLL is a preset high level. Transmitting the first-level signal VGLL to the second gate of the first transistor T1 through the first-level signal line 30 also helps to suppress the leakage current of the first transistor T1. Moreover, by providing the voltage adjustment module 20, it also helps to suppress the leakage current of the second transistor T2 when the second transistor T2 is turned off, and to improve the driving capability of the second transistor T2 when the second transistor T2 is turned on.

[0145] In other embodiments, when the first transistor T1 and the second transistor T2 are both double-gate transistors, the first gate and the second gate of one of the first transistor T1 and the second transistor T2 can be connected, and the second gate of the other of the first transistor T1 and the second transistor T2 is connected to the voltage adjustment module 20.

[0146] Exemplarily, the first gate and the second gate of the first transistor T1 are connected, and the second gate of the second transistor T2 is connected with the voltage adjustment module 20. When the output control module 10 transmits a high-level signal to the first gate and the second gate of the first transistor T1 in the case that the first transistor T1 is an N-type transistor, the electric potential of the first gate and the second gate of the first transistor T1 is high, so as to control the first transistor T1 to be turned on. The first gate and the second gate of the first transistor T1 are connected, so as to increase the gate control ability of the first transistor T1 and improve the driving ability of the first transistor T1. When the output control module 10 transmits a low-level signal to the first gate and the second gate of the first transistor T1, the electric potential of the first gate and the second gate of the first transistor T1 is low, so as to control the first transistor T1 to be turned off. The first gate and the second gate of the first transistor T1 are connected, so as to increase the gate control ability of the first transistor T1 and help to ensure that the first transistor T1 is completely turned off, thereby inhibiting the leakage current of the first transistor T1. Similarly, in the case that the first transistor T1 is a P-type transistor, when the output control module 10 transmits a low-level signal to the first gate and the second gate of the first transistor T1, the first transistor T1 can be controlled to be turned on and the driving ability of the first transistor T1 can be improved. When the output control module 10 transmits a high-level signal to the first gate and the second gate of the first transistor T1, the first transistor T1 can be controlled to be turned off and the leakage current of the first transistor T1 can be inhibited. By setting the voltage adjustment module 20, the leakage current of the second transistor T2 can be inhibited when the second transistor T2 is turned off, and the driving ability of the second transistor T2 can be improved when the second transistor T2 is turned on.

[0147] In the technical solution of the present application, the specific structure of the output control module in the gate drive circuit can be various, and in combination with the different structures of the voltage adjustment module and the like described in the above embodiments, various gate drive circuits can be formed. Several of them are taken as examples for description below.

[0148] Referring to Figure 8In an embodiment, the output control module 10 in the gate drive circuit can include an input unit 110, a first output control unit 120 and a second output control unit 130. The input unit 110 is connected to the first node N1, the second node N2 and the input end of the gate drive circuit, and is configured to control the signals of the first node N1 and the second node N2 according to the first clock signal CK1, the second level signal VGH and the signal of the input end of the gate drive circuit, i.e., the start signal IN. The first output control unit 120 is connected to the first node N1 and the second node N2, and is configured to control the signal of the first node N1 according to the signal of the second node N2 and the first clock signal CK1. The second output control unit 130 is connected to the first node N1 and the second node N2, and is configured to control the signal of the second node N2 according to the signal of the first node N1, the second clock signal CK2 and the third level signal VGL. The first node N1 is connected to the gate of the first transistor T1, and the signal of the second node N2 is transmitted to the gate of the second transistor T2. The third level signal VGL is multiplexed as the first output signal, and the second clock signal CK2 is multiplexed as the second output signal.

[0149] Specifically, one of the second level signal VGH and the third level signal VGL is a high-level signal, and the other is a low-level signal. The input end of the gate drive circuit is connected to the start signal IN. The input unit 110 controls the signals of the first node N1 and the second node N2 according to the first clock signal CK1, the second level signal VGH and the signal of the input end of the gate drive circuit, i.e., the start signal IN, which means that the input unit 110 transmits the second level signal VGH to the first node N1 in response to the first clock signal CK1, and transmits the start signal IN to the second node N2 in response to the first clock signal CK1. The first output control unit 120 controls the signal of the first node N1 according to the signal of the second node N2 and the first clock signal CK1, which means that the first output control unit 120 can transmit the first clock signal CK1 to the first node N1 in response to the signal of the second node N2. The second output control unit 130 controls the signal of the second node N2 according to the signal of the first node N1, the second clock signal CK2 and the third level signal VGL, which means that the second output control unit 130 can transmit the third level signal VGL to the second node N2 in response to the signal of the first node N1 and the second clock signal CK2.

[0150] When the third level signal VGL is a low level signal, by setting the output control module 10 to include the input unit 110, the first output control unit 120 and the second output control unit 130, the signals of the first node N1 and the second node N2 can be controlled, so as to control the first transistor T1 and the second transistor T2 to be turned on alternately. When the first transistor T1 is turned on, the third level signal VGL is transmitted to the output end O1 of the gate drive circuit through the first transistor T1, so that the gate drive signal output by the gate drive circuit is a low level signal. When the second transistor T2 is turned on, the high level signal in the second clock signal CK2 is transmitted to the output end O1 of the gate drive circuit through the second transistor T2, so that the gate drive signal output by the gate drive circuit is a high level signal. Similarly, when the third level signal VGL is a high level signal, by setting the output control module 10 to include the input unit 110, the first output control unit 120 and the second output control unit 130, the signals of the first node N1 and the second node N2 can be controlled, so as to control the first transistor T1 and the second transistor T2 to be turned on alternately. When the first transistor T1 is turned on, the third level signal VGL is transmitted to the output end O1 of the gate drive circuit through the first transistor T1, so that the gate drive signal output by the gate drive circuit is a high level signal. When the second transistor T2 is turned on, the low level signal in the second clock signal CK2 is transmitted to the output end O1 of the gate drive circuit through the second transistor T2, so that the gate drive signal output by the gate drive circuit is a low level signal.

[0151] Referring to Figures 8 to 11 Further, in an embodiment, the output control module 10 can further include a sixth transistor T6, the sixth transistor T6 is connected between the third node N3 and the second node N2, the sixth transistor T6 keeps an open state, and the third node N3 is connected to the gate of the second transistor T2, so that the signal of the second node N2 is transmitted to the gate of the second transistor T2 through the sixth transistor T6. In other embodiments, the second node N2 can be directly connected to the gate of the second transistor T2, so that the signal of the second node N2 can be directly transmitted to the gate of the second transistor T2.

[0152] Referring to Figures 9 to 11On the basis of the above-mentioned embodiment, the first output control unit 120 comprises a seventh transistor T7 optionally, the gate of the seventh transistor T7 is connected with the second node N2, the first electrode of the seventh transistor T7 is connected with the first clock signal CK1, and the second electrode of the seventh transistor T7 is connected with the first node N1. The second output control unit 130 comprises an eighth transistor T8 and a ninth transistor T9, the gate of the eighth transistor T8 is connected with the first node N1, the first electrode of the eighth transistor T8 is connected with the third level signal VGL, the second electrode of the eighth transistor T8 is connected with the first electrode of the ninth transistor T9, the gate of the ninth transistor T9 is connected with the second clock signal CK2, and the second electrode of the ninth transistor T9 is connected with the second node N2. The input unit 110 comprises a fifteenth transistor T15 and a sixteenth transistor T16, the gate of the fifteenth transistor T15 and the gate of the sixteenth transistor T16 are both connected with the first clock signal CK1, the first electrode of the fifteenth transistor T15 is connected with the second level signal VGH, the second electrode of the fifteenth transistor T15 is connected with the first node N1, the first electrode of the sixteenth transistor T16 can be connected with the start signal IN as the input end of the gate drive circuit, and the second electrode of the sixteenth transistor T16 is connected with the second node N2. The gate drive circuit further comprises a second capacitor C2 and a third capacitor C3, the second capacitor C2 is connected between the first gate and the first electrode of the first transistor T1, and the third capacitor C3 is connected between the first gate and the second electrode of the second transistor T2.

[0153] Referring to Figure 9 and Figure 10 Optionally, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are all double-gate transistors, the first gate of the seventh transistor T7 is connected with the second node N2, the first gate of the eighth transistor T8 is connected with the first node N1, the first gate of the ninth transistor T9 is connected with the second clock signal CK2, and the second gate of the seventh transistor T7, the second gate of the eighth transistor T8 and the second gate of the ninth transistor T9 are all connected with the first level signal VGLL.

[0154] Specifically, when the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are all N-type transistors, the first level signal VGLL is a preset low level signal, the second gate of the seventh transistor T7, the second gate of the eighth transistor T8 and the second gate of the ninth transistor T9 are all connected to the first level signal VGLL, which can reduce the second gate voltage of the seventh transistor T7, the second gate voltage of the eighth transistor T8 and the second gate voltage of the ninth transistor T9, so that the threshold voltages of the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are all positive, which helps to avoid the leakage problem caused by the failure of the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 to completely turn off, so as to suppress the leakage current of the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9, thereby avoiding the influence on the potentials of the first node N1, the second node N2 and the third node N3, and helping to ensure the normal work of the first transistor T1 and the second transistor T2.

[0155] Figure 9 and Figure 10 It is shown that the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are all double-gate transistors, and in another embodiment, only the seventh transistor T7 can be set as a double-gate transistor, the first gate of the seventh transistor T7 is connected to the second node N2, and the second gate of the seventh transistor T7 is connected to the first level signal VGLL, because in the working process of the gate drive circuit, the seventh transistor T7 is in the off state for a long time, which helps to improve the leakage problem caused by the failure of the seventh transistor T7 to completely turn off, so as to avoid the influence on the potential of the first node N1, and help to ensure the normal work of the first transistor T1. In another embodiment, only the eighth transistor T8 and the ninth transistor T9 can be set as double-gate transistors, the first gate of the eighth transistor T8 is connected to the first node N1, the first gate of the ninth transistor T9 is connected to the second clock signal CK2, and the second gate of the eighth transistor T8 and the second gate of the ninth transistor T9 are both connected to the first level signal VGLL, so as to improve the leakage problem caused by the failure of the eighth transistor T8 and the ninth transistor T9 to completely turn off, so as to avoid the influence on the potentials of the second node N2 and the third node N3, and help to ensure the normal work of the second transistor T2.

[0156] Figure 12 is another structure schematic diagram of a gate drive circuit provided by the embodiment of the present application. Referring to Figure 12Optionally, in the case that the first transistor T1 is a double-gate transistor, the voltage adjustment module 20 comprises a first voltage adjustment module 20a, and in the case that the second transistor T2 is a double-gate transistor, the voltage adjustment module 20 comprises a second voltage adjustment module 20b. The first output signal can be a fixed voltage signal, and the second output signal can be a second clock signal CK2. The first output signal and the first level signal VGLL can have the same polarity, and the absolute value of the first level signal VGLL is greater than or equal to the absolute value of the first output signal. The signal of the first gate of the second transistor T2, or a signal synchronous with the high-low change of the signal of the first gate of the second transistor T2 or a first clock signal CK1 can be multiplexed as a first control signal A1-1 in the first voltage adjustment module 20a. The signal of the second node N2, the signal of the third node N3 or the first clock signal CK1 is multiplexed as the first control signal A1-1 in the first voltage adjustment module 20a. The signal of the first gate of the first transistor T1, or a signal synchronous with the high-low change of the signal of the first gate of the first transistor T1 can be multiplexed as a second control signal A2-1 in the first voltage adjustment module 20a. The signal of the first node N1 is multiplexed as the second control signal A2-1 in the first voltage adjustment module 20a. The second clock signal CK2 or a second level signal VGH is multiplexed as a preset signal in the first voltage adjustment module 20a and the second voltage adjustment module 20b. The signal of the first gate of the first transistor T1, or a signal synchronous with the high-low change of the signal of the first gate of the first transistor T1 or a first clock signal CK1 can be multiplexed as a first control signal A1-2 in the second voltage adjustment module 20b. The signal of the first node N1 or the first clock signal CK1 is multiplexed as the first control signal A1-2 in the second voltage adjustment module 20b. The signal of the first gate of the second transistor T2, or a signal synchronous with the high-low change of the signal of the first gate of the second transistor T2 can be multiplexed as a second control signal A2-2 in the second voltage adjustment module 20b. The signal of the second node N2 or the signal of the third node N3 is multiplexed as the second control signal A2-2 in the second voltage adjustment module 20b. Multiplexing the first control signal and the second control signal with the signal on the signal line connected with the output control module 10 or the signal of the node in the output control module 10 can reduce the number of signal lines introduced from the external chip.

[0157] The transistors in the gate drive circuit can be N-type transistors or P-type transistors. For example, when the transistors in the gate drive circuit are N-type transistors, the first-level signal VGLL is a preset low-level signal, the second-level signal VGH is a preset high-level signal, and the third-level signal VGL is a low-level signal. When the output control module 10 controls the first transistor T1 to be off and the second transistor T2 to be on, the high-level signal in the second clock signal CK2 is transmitted to the output end O1 of the gate drive circuit through the second transistor T2, and the gate drive signal output by the gate drive circuit is a high-level signal. The signal at the first node N1 is a low-level signal, and the signals at the second node N2 and the third node N3 are high-level signals. The third transistor T3-1 in the first voltage adjustment module 20a is turned on in response to the high-level signal in the second clock signal CK2 or the signals at the second node N2 and the third node N3, so that the first-level signal VGLL is transmitted to the second gate of the first transistor T1 through the third transistor T3-1, the second gate voltage of the first transistor T1 is reduced, the threshold voltage of the first transistor T1 is positively biased, and the first transistor T1 is completely turned off, thereby inhibiting the leakage current of the first transistor T1, reducing the power consumption of the first transistor T1 caused by the leakage current, and improving the waveform distortion problem of the gate drive signal.

[0158] When the output control module 10 controls the first transistor T1 to be on and the second transistor T2 to be off, the third-level signal VGL is transmitted to the output end O1 of the gate drive circuit through the first transistor T1, and the gate drive signal output by the gate drive circuit is a low-level signal. The signal at the first node N1 is a high-level signal, and the signals at the second node N2 and the third node N3 are low-level signals. The fourth transistor T4-1 in the first voltage adjustment module 20a is turned on in response to the signal at the first node N1, so that the second clock signal CK2 is transmitted to the first capacitor C1-1 through the fourth transistor T4-1. When the level of the second clock signal CK2 jumps from a low level to a high level, the potential of the second gate of the first transistor T1 is coupled through the first capacitor C1-1 to raise the second gate voltage of the first transistor T1, negatively bias the threshold voltage of the first transistor T1, and improve the driving capability of the first transistor T1 and the waveform distortion problem of the gate drive signal.

[0159] Similarly, the second voltage adjustment module 20b has an effect on the second transistor T2 similar to that of the first voltage adjustment module 20a on the first transistor T1, and can be understood with reference to the above embodiments, which will not be described again. In addition, when the transistors in the gate drive circuit are P-type transistors, the first-level signal VGLL can be set as a preset high-level signal, the second-level signal VGH can be set as a preset low-level signal, and the third-level signal VGL can be set as a high-level signal, and the principle is the same as before.

[0160] Figure 13 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. Referring to Figure 13 In another embodiment, the output control module 10 in the gate drive circuit can include an input unit 110, a first output control unit 120, and a second output control unit 130. The input unit 110 is connected to the first node N1, the second node N2, and the input end of the gate drive circuit, and is configured to control the signals of the first node N1 and the second node N2 according to the first clock signal CK1, the third level signal VGL, and the signal of the input end of the gate drive circuit, i.e., the start signal IN. The first output control unit 120 is connected to the third node N3, the first node N1, and the second node N2, and is configured to control the signal of the third node N3 according to the second clock signal CK2, the signal of the first node N1, the signal of the second node N2, and the third level signal VGL. The third node N3 is connected to the gate of the first transistor T1. The second output control unit 130 is connected to the fourth node N4 and the third node N3, and is configured to control the signal of the fourth node N4 according to the signal of the third node N3, the signal of the fourth node N4, the third level signal VGL, and the second clock signal CK2. The fourth node N4 is connected to the gate of the second transistor T2, and the signal of the second node N2 is transmitted to the gate of the second transistor T2. The third level signal VGL is multiplexed as the first output signal, and the second level signal VGH is multiplexed as the second output signal.

[0161] Specifically, one of the second level signal VGH and the third level signal VGL is a high-level signal, and the other is a low-level signal. The input end of the gate drive circuit is connected to the start signal IN. The input unit 110 controls the signals of the first node N1 and the second node N2 according to the first clock signal CK1, the third level signal VGL, and the signal of the input end of the gate drive circuit, i.e., the start signal IN. The meaning can be that the input unit 110 transmits the third level signal VGL to the first node N1 in response to the start signal IN, and transmits the start signal IN to the second node N2 in response to the first clock signal CK1. The first output control unit 120 controls the signal of the third node N3 according to the second clock signal CK2, the signal of the first node N1, the signal of the second node N2, and the third level signal VGL, which means that the first output control unit 120 can transmit the second clock signal CK2 to the third node N3 in response to the signal of the first node N1, and transmit the third level signal VGL to the third node N3 in response to the signal of the second node N2. The second output control unit 130 controls the signal of the fourth node N4 according to the signal of the third node N3, the signal of the fourth node N4, the third level signal VGL, and the second clock signal CK2, which means that the second output control unit 130 can control the signal of the fourth node N4 through the third level signal VGL and the second clock signal CK2 in response to the signals of the third node N3 and the fourth node N4.

[0162] By setting the output control module 10 to include the input unit 110, the first output control unit 120 and the second output control unit 130, the signals of the first node N1, the second node N2, the third node N3 and the fourth node N4 can be controlled, so that the first transistor T1 and the second transistor T2 are alternately turned on, so that when the first transistor T1 is turned on, the third level signal VGL is transmitted to the output end O1 of the gate drive circuit through the first transistor T1, and when the second transistor T2 is turned on, the second level signal VGH is transmitted to the output end O1 of the gate drive circuit through the second transistor T2, so that the gate drive circuit outputs the gate drive signal with high level and low level alternately.

[0163] Continuing to refer to Figure 13 On the basis of the above-mentioned embodiments, optionally, the output control module 10 further includes a tenth transistor T10, the tenth transistor T10 is connected between the second node N2 and the fourth node N4, and the tenth transistor T10 keeps an open state, so that the signal of the second node N2 is transmitted to the gate of the second transistor T2 through the tenth transistor T10. In other embodiments, the second node N2 can also be directly connected to the gate of the second transistor T2, so that the signal of the second node N2 can be directly transmitted to the gate of the second transistor T2.

[0164] Figure 14 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the application. Figure 15 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the application. Referring to Figure 14 and Figure 15On the basis of the above-mentioned embodiment, optionally, the input unit 110 comprises a seventeenth transistor T17 and an eighteenth transistor T18. The gate of the seventeenth transistor T17 and the first electrode of the eighteenth transistor T18 are connected to the start signal IN as the input end of the gate driving circuit, the first electrode of the seventeenth transistor T17 is connected to the third level signal VGL, the second electrode of the seventeenth transistor T17 is connected to the first node N1, the gate of the eighteenth transistor T18 is connected to the first clock signal CK1, and the second electrode of the eighteenth transistor T18 is connected to the second node N2. The first output control unit 120 comprises a nineteenth transistor T19, a twentieth transistor T20 and a fourth capacitor C4. The gate of the nineteenth transistor T19 is connected to the first node N1, the first electrode of the nineteenth transistor T19 is connected to the second clock signal CK2, and the second electrode of the nineteenth transistor T19 is connected to the third node N3. The gate of the twentieth transistor T20 is connected to the second node N2, the first electrode of the twentieth transistor T20 is connected to the third level signal VGL, and the second electrode of the twentieth transistor T20 is connected to the third node N3. The fourth capacitor C4 is connected between the gate and the first electrode of the nineteenth transistor T19. The second output control unit 130 comprises a twenty-first transistor T21, a twenty-second transistor T22 and a fifth capacitor C5. The gate of the twenty-first transistor T21 is connected to the third node N3, the first electrode of the twenty-first transistor T21 is connected to the third level signal VGL, the gate of the twenty-second transistor T22 is connected to the fourth node N4, the first electrode of the twenty-second transistor T22 is connected to the second clock signal CK2, and the second electrode of the twenty-second transistor T22 is connected to the second electrode of the twenty-first transistor T21. The fifth capacitor C5 is connected between the gate and the second electrode of the twenty-second transistor T22.

[0165] Referring to Figure 15 Optionally, in the case that the first transistor T1 is a double-gate transistor, the voltage adjusting module 20 comprises a first voltage adjusting module 20a, and in the case that the second transistor T2 is a double-gate transistor, the voltage adjusting module 20 comprises a second voltage adjusting module 20b. The first clock signal CK1 is multiplexed as the first control signal A1-1 in the first voltage adjusting module 20a and the first control signal A1-2 in the second voltage adjusting module 20b. The signal of the first node N1 is multiplexed as the second control signal A2-1 in the first voltage adjusting module 20a. The second clock signal CK2 or the second level signal VGH is multiplexed as a preset signal in the first voltage adjusting module 20a and the second voltage adjusting module 20b. The signal of the second node N2 or the fourth node N4 is multiplexed as the second control signal A2-2 in the second voltage adjusting module 20b.

[0166] The transistors in the gate drive circuit can be N-type transistors or P-type transistors. For example, when the transistors in the gate drive circuit are N-type transistors, the first-level signal VGLL is a preset low-level signal, the second-level signal VGH is a preset high-level signal, and the third-level signal VGL is a low-level signal. When the output control module 10 controls the first transistor T1 to be off and the second transistor T2 to be on, the second-level signal VGH is transmitted to the output end O1 of the gate drive circuit through the second transistor T2, and the gate drive signal output by the gate drive circuit is a high-level signal. The signals of the second node N2 and the fourth node N4 are high-level signals, and the fourth transistor T4-2 in the second voltage adjustment module 20b is turned on in response to the signals of the second node N2 or the fourth node N4, so that the second clock signal CK2 is transmitted to the first capacitor C1-2 through the fourth transistor T4-2. When the level of the second clock signal CK2 jumps from a low level to a high level, the potential of the second gate of the second transistor T2 is coupled through the first capacitor C1-2 to raise the second gate voltage of the second transistor T2, so that the threshold voltage of the second transistor T2 is negatively biased, thereby improving the driving capability of the second transistor T2 and the waveform distortion problem of the gate drive signal.

[0167] When the output control module 10 controls the first transistor T1 to be on and the second transistor T2 to be off, the third-level signal VGL is transmitted to the output end O1 of the gate drive circuit through the first transistor T1, and the gate drive signal output by the gate drive circuit is a low-level signal. The signals of the second node N2 and the fourth node N4 are low-level signals, and the third transistor T3-2 in the second voltage adjustment module 20b is turned on in response to the high-level signal in the first clock signal CK1, so that the first-level signal VGLL is transmitted to the gate of the second transistor T2 through the third transistor T3-2 to reduce the second gate voltage of the second transistor T2, so that the threshold voltage of the second transistor T2 is positively biased, which helps to ensure that the second transistor T2 is completely turned off, thereby suppressing the leakage current of the second transistor T2, reducing the power consumption of the second transistor T2 due to the leakage current, and improving the waveform distortion problem of the gate drive signal.

[0168] Similarly, the first voltage adjustment module 20a has the same effect on the first transistor T1 as the second voltage adjustment module 20b has on the second transistor T2, and the specific understanding can be made with reference to the above embodiments, which will not be described here. In addition, when the transistors in the gate drive circuit are P-type transistors, the first-level signal VGLL can be set as a preset high-level signal, the second-level signal VGH can be set as a preset low-level signal, and the third-level signal VGL can be set as a high-level signal, and the principle is the same as before.

[0169] Figure 16is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. Referring to Figure 16 In another embodiment, the output control module 10 in the gate drive circuit can include an input unit 110, a first output control unit 120, a second output control unit 130, a third output control unit 140, and a fourth output control unit 150. The input unit 110 is connected to the first node N1, the second node N2, and the input end of the gate drive circuit, and is configured to control the signals of the first node N1 and the second node N2 according to the first clock signal CK1, the second level signal VGH, and the signal of the input end of the gate drive circuit, i.e., the start signal IN. The first output control unit 120 is connected to the first node N1 and the second node N2, and is configured to control the signal of the first node N1 according to the signal of the second node N2 and the first clock signal CK1. The second output control unit 130 is connected to the third node N3 and the fourth node N4, and is configured to control the signal of the fourth node N4 according to the signal of the third node N3 and the second clock signal CK2. The signal of the first node N1 is transmitted to the third node N3, and the signal of the fourth node N4 is transmitted to the gate of the first transistor T1. The third output control unit 140 is connected to the fifth node N5 and the sixth node N6, and is configured to control the signal of the sixth node N6 according to the signal of the fifth node N5, the signal of the sixth node N6, the third level signal VGL, and the second clock signal CK2. The signal of the first node N1 is transmitted to the fifth node N5, the signal of the second node N2 is transmitted to the sixth node N6, and the sixth node N6 is connected to the gate of the second transistor T2. The fourth output control unit 150 is connected to the seventh node N7 and the second node N2, and is configured to control the signal of the seventh node N7 according to the signal of the second node N2 and the third level signal VGL. The signal of the fourth node N4 is transmitted to the seventh node N7, and the seventh node N7 is connected to the gate of the first transistor T1. The third level signal VGL is multiplexed as the first output signal, and the second level signal VGH is multiplexed as the second output signal.

[0170] Specifically, one of the second level signal VGH and the third level signal VGL is a high level signal, and the other is a low level signal. The input end of the gate drive circuit is connected to the start signal IN. The input unit 110 controls the signals of the first node N1 and the second node N2 according to the first clock signal CK1, the second level signal VGH and the signal of the input end of the gate drive circuit, which means that the input unit 110 transmits the second level signal VGH to the first node N1 in response to the first clock signal CK1, and transmits the start signal IN to the second node N2 in response to the first clock signal CK1. The first output control unit 120 controls the signal of the first node N1 according to the signal of the second node N2 and the first clock signal CK1, which means that the first output control unit 120 can transmit the first clock signal CK1 to the first node N1 in response to the signal of the second node N2. The second output control unit 130 controls the signal of the fourth node N4 according to the signal of the third node N3 and the second clock signal CK2, which means that the second output control unit 130 can control the signal of the fourth node N4 through the second clock signal CK2 in response to the signals of the third node N3 and the fourth node N4. The third output control unit 140 controls the signal of the sixth node N6 according to the signal of the fifth node N5, the signal of the sixth node N6, the third level signal VGL and the second clock signal CK2, which means that the third output control unit 140 can control the signal of the sixth node N6 through the third level signal VGL and the second clock signal CK2 in response to the signals of the fifth node N5 and the sixth node N6. The fourth output control unit 150 controls the signal of the seventh node N7 according to the signal of the second node N2 and the third level signal VGL, which means that the fourth output control unit 150 can transmit the third level signal VGL to the seventh node N7 in response to the signal of the second node N2.

[0171] Continuing to refer to Figure 16 On the basis of the above-mentioned embodiments, optionally, the output control module 10 further comprises an eleventh transistor T11, the first electrode of the eleventh transistor T11 is connected to the first node N1, the second electrode of the eleventh transistor T11 is connected to the third node N3, and the eleventh transistor T11 keeps an open state to make the signal of the first node N1 transmitted to the third node N3 through the eleventh transistor T11. In other embodiments, the first node N1 can be directly connected to the third node N3 to make the signal of the first node N1 directly transmitted to the third node N3.

[0172] Further, the output control module 10 further comprises a twelfth transistor T12, the twelfth transistor T12 is connected between the fourth node N4 and the seventh node N7, the twelfth transistor T12 keeps open state, so that the signal of the fourth node N4 is transmitted to the gate of the first transistor T1 through the twelfth transistor T12. In other embodiments, the fourth node N4 can also be directly connected to the gate of the first transistor T1, so that the signal of the fourth node N4 can be directly transmitted to the gate of the first transistor T1.

[0173] Further, the output control module 10 further comprises a thirteenth transistor T13, the first pole of the thirteenth transistor T13 is connected to the second pole of the eleventh transistor T11, the second pole of the thirteenth transistor T13 is connected to the fifth node N5, the thirteenth transistor T13 keeps open state, so that the signal of the first node N1 is transmitted to the fifth node N5 through the thirteenth transistor T13. In other embodiments, the first node N1 can also be directly connected to the fifth node N5, so that the signal of the first node N1 can be directly transmitted to the fifth node N5.

[0174] Further, the output control module 10 further comprises a fourteenth transistor T14, the fourteenth transistor T14 is connected between the second node N2 and the sixth node N6, the fourteenth transistor T14 keeps open state, so that the signal of the second node N2 is transmitted to the sixth node N6 through the fourteenth transistor T14. In other embodiments, the second node N2 can also be directly connected to the sixth node N6, so that the signal of the second node N2 can be directly transmitted to the sixth node N6.

[0175] Figure 17 is another structure schematic diagram of the gate drive circuit provided by the embodiment of the present application. Referring to Figure 17On the basis of the above-mentioned embodiment, optionally, the input unit 110 comprises a twenty-third transistor T23 and a twenty-fourth transistor T24. The gate of the twenty-third transistor T23 is connected to the first clock signal CK1, the first electrode of the twenty-third transistor T23 is connected to the second level signal VGH, and the second electrode of the twenty-third transistor T23 is connected to the first node N1. The gate of the twenty-fourth transistor T24 is connected to the first clock signal CK1, the first electrode of the twenty-fourth transistor T24 is connected to the start signal IN, and the second electrode of the twenty-fourth transistor T24 is connected to the second node N2. The first output control unit 120 comprises a twenty-fifth transistor T25, the gate of the twenty-fifth transistor T25 is connected to the second node N2, the first electrode of the twenty-fifth transistor T25 is connected to the first clock signal CK1, and the second electrode of the twenty-fifth transistor T25 is connected to the first node N1. The second output control unit 130 comprises a twenty-sixth transistor T26 and a sixth capacitor C6. The gate of the twenty-sixth transistor T26 is connected to the third node N3, the first electrode of the twenty-sixth transistor T26 is connected to the second clock signal CK2, the second electrode of the twenty-sixth transistor T26 is connected to the fourth node N4, and the sixth capacitor C6 is connected between the third node N3 and the fourth node N4. The third output control unit 140 comprises a twenty-seventh transistor T27, a twenty-eighth transistor T28 and a seventh capacitor C7. The gate of the twenty-seventh transistor T27 is connected to the fifth node N5, the first electrode of the twenty-seventh transistor T27 is connected to the third level signal VGL, the gate of the twenty-eighth transistor T28 is connected to the sixth node N6, the first electrode of the twenty-eighth transistor T28 is connected to the second clock signal CK2, and the second electrode of the twenty-eighth transistor T28 is connected to the second electrode of the twenty-seventh transistor T27. The seventh capacitor C7 is connected between the gate and the second electrode of the twenty-eighth transistor T28. The fourth output control unit 150 comprises a twenty-ninth transistor T29, the gate of the twenty-ninth transistor T29 is connected to the second node N2, the first electrode of the twenty-ninth transistor T29 is connected to the third level signal VGL, and the second electrode of the twenty-ninth transistor T29 is connected to the seventh node N7.

[0176] When the twenty-sixth transistor T26 is turned on in response to the high-level signal of the third node N3, the second clock signal CK2 is transmitted to the fourth node N4 through the twenty-sixth transistor T26, and due to the coupling effect of the sixth capacitor C6, the signal of the third node N3 can be coupled according to the level jump of the second clock signal CK2 of the fourth node N4, and the signal level of the third node N3 is coupled to an extremely high level higher than the high level, so as to increase the on degree of the twenty-sixth transistor T26, and ensure that the twenty-sixth transistor T26 transmits the second clock signal CK2 to the fourth node N4, thereby controlling the first gate voltage of the first transistor T1 and making the first transistor T1 work normally. By arranging the eleventh transistor T11 and the thirteenth transistor T13, the extremely high level of the third node N3 is blocked through the eleventh transistor T11, so as to avoid the transmission of the extremely high level of the third node N3 to the twenty-third transistor T23 and the twenty-fifth transistor T25, thereby affecting the work of the twenty-third transistor T23 and the twenty-fifth transistor T25, and the extremely high level of the third node N3 is blocked through the thirteenth transistor T13, so as to avoid the transmission of the extremely high level of the third node N3 to the fifth node N5, thereby damaging the twenty-seventh transistor T27 and affecting the work of the twenty-seventh transistor T27. In addition, when the output control module 10 controls the second transistor T2 to be turned on, the signal of the sixth node N6 is a high-level signal, so that the twenty-eighth transistor T28 is turned on, and the second clock signal CK2 is transmitted to the seventh capacitor C7 through the twenty-eighth transistor T28. Due to the coupling effect of the seventh capacitor C7, the signal of the sixth node N6 can be coupled according to the level jump of the second clock signal CK2 of the second pole of the twenty-eighth transistor T28, and the signal level of the sixth node N6 is coupled to an extremely high level higher than the high level, so as to increase the on degree of the second transistor T2, and ensure that the second level signal VGH can be transmitted to the output end O1 of the gate drive circuit through the second transistor T2. By arranging the fourteenth transistor T14, the extremely high level of the sixth node N6 is blocked through the fourteenth transistor T14, so as to avoid the transmission of the extremely high level of the sixth node N6 to the twenty-fourth transistor T24, the twenty-eighth transistor T28 and the twenty-ninth transistor T29, thereby affecting the work of the twenty-fourth transistor T24, the twenty-eighth transistor T28 and the twenty-ninth transistor T29. In the case that all the transistors in the gate drive circuit are P-type transistors, the above-mentioned transistors and capacitors can also achieve similar effects, and the specific principles are not described again.

[0177] Continuing to refer to Figure 17Optionally, the first control signal includes a first clock signal CK1, and the preset signal includes a second clock signal CK2. The first clock signal CK1 and the second clock signal CK2 have the same frequency but opposite phase. Further, when the first transistor T1 is a dual-gate transistor, the voltage regulation module 20 includes a first voltage regulation module 20a; when the second transistor T2 is a dual-gate transistor, the voltage regulation module 20 includes a second voltage regulation module 20b. The first clock signal CK1 is multiplexed into the first control signal A1-1 in the first voltage regulation module 20a and the first control signal A1-2 in the second voltage regulation module 20b. The signal of the first node N1, the signal of the third node N3, or the signal of the fifth node N5 is multiplexed into the second control signal A2-1 in the first voltage regulation module 20a. The second clock signal CK2 or the second level signal VGH is multiplexed into the preset signal in the first voltage regulation module 20a and the second voltage regulation module 20b. The signal of the first gate of the second transistor T2, or a signal synchronized with the high / low change of the signal of the first gate of the second transistor T2, is multiplexed into the second control signal A2-2 in the second voltage regulation module 20b. The signal from the second node N2 or the signal from the sixth node N6 is multiplexed into the second control signal A2-2 in the second voltage regulation module 20b.

[0178] Figure 18 This is a schematic diagram of the driving timing of a gate driving circuit according to an embodiment of the present invention. This driving timing can be applied to driving... Figure 16 and Figure 17 The gate drive circuit shown is working. The following section combines... Figure 17 and Figure 18 Taking an example where all transistors in the gate drive circuit are N-type transistors, the working principle of the gate drive circuit is explained. Here, the first level signal VGLL is a preset low-level signal, the second level signal VGH is a preset high-level signal, and the third level signal VGL is a low-level signal.

[0179] At the t0 stage, the start signal IN is a high level signal, the first transistor T1 is off, the second transistor T2 is on, the second level signal VGH is transmitted to the output end O1 of the gate driving circuit through the second transistor T2, and the gate driving signal Vout output by the gate driving circuit is a high level signal. The signals of the second node N2 and the sixth node N6 are both high level signals. The fourth transistor T4-2 in the second voltage adjusting module 20b is turned on in response to the signals of the second node N2 or the sixth node N6, so that the second clock signal CK2 is transmitted to the first capacitor C1-2 through the fourth transistor T4-2, so as to couple the potential of the second gate of the second transistor T2 through the first capacitor C1-2 when the level of the second clock signal CK2 jumps from low level to high level, so as to raise the second gate voltage of the second transistor T2, make the threshold voltage of the second transistor T2 deviate negatively, thereby improving the driving capability of the second transistor T2 and improving the waveform distortion problem of the gate driving signal.

[0180] At the t1 stage, the first transistor T1 remains off, the second transistor T2 remains on, and the gate driving signal Vout output by the gate driving circuit is still a high level signal. The falling edge of the start signal IN and the rising edge of the first clock signal CK1 come, the twenty-third transistor T23 and the third transistor T3-1 in the first voltage adjusting module 20a are turned on, the first level signal VGLL is transmitted to the BGU node through the third transistor T3-1, the voltage of the BGU node is reset, the first node N1, the third node N3 and the fifth node N5 input the second level signal VGH, the signals of the first node N1, the third node N3 and the fifth node N5 are all high level signals, the fourth transistor T4-1 in the first voltage adjusting module 20a is turned on in response to the signals of the first node N1, the third node N3 or the fifth node N5, and the low level in the second clock signal CK2 is transmitted to the first capacitor C1-1 in the first voltage adjusting module 20a. The first electrode voltage of the first capacitor C1-1 is reset.

[0181] In the t2 stage, the start signal IN is a low signal, the second transistor T2 changes from the on state to the off state, the first transistor T1 changes from the off state to the on state, the third level signal VGL is transmitted to the output end O1 of the gate driving circuit through the first transistor T1, and the gate driving signal Vout output by the gate driving circuit changes from the high signal to the low signal. After the first transistor T1 is turned on, the signals of the first node N1, the third node N3 and the fifth node N5 are all high signals, the fourth transistor T4-1 in the first voltage adjusting module 20a is turned on in response to the signals of the first node N1, the third node N3 or the fifth node N5, and the second clock signal CK2 is transmitted to the first electrode of the first capacitor C1-1. When the third transistor T3-1 in the first voltage adjusting module 20a is turned off in response to the low level in the first clock signal CK1, the second clock signal CK2 jumps from the low level to the high level, and the first capacitor C1-1 can respond to the level jump of the second clock signal CK2 to couple the potential of the BGU node to raise the voltage of the BGU node, so as to bias the threshold voltage of the first transistor T1 to negative, thereby improving the driving capability of the first transistor T1, so that the gate driving signal Vout output by the gate driving circuit rapidly decreases from the high signal to the low signal, which helps to reduce the waveform delay of the gate driving signal Vout, thereby improving the waveform distortion problem of the gate driving signal. At the same time, the signals of the second node N2 and the sixth node N6 are both low signals. The fourth transistor T4-2 in the second voltage adjusting module 20b is turned off in response to the signals of the second node N2 or the sixth node N6, and when the third transistor T3-2 is turned on in response to the high level in the first clock signal CK1, the first level signal VGLL is transmitted to the BGD node through the third transistor T3-2 and maintained by the first capacitor C1-2 to reduce the voltage of the second gate of the second transistor T2, so as to bias the threshold voltage of the second transistor T2 to positive, which helps to ensure that the second transistor T2 is completely turned off, thereby suppressing the leakage current of the second transistor T2, reducing the power consumption of the second transistor T2 due to the leakage current, and improving the waveform distortion problem of the gate driving signal.

[0182] At the t3 stage, the rising edge of the start signal IN and the rising edge of the first clock signal CK1 arrive, the twenty-fourth transistor T24 and the third transistor T3-2 in the second voltage adjusting module 20b are turned on, the first level signal VGLL is transmitted to the BGD node through the third transistor T3-2, the voltage of the BGD node is reset, the second node N2 and the sixth node N6 input the second level signal VGH, the signals of the second node N2 and the sixth node N6 are both high level signals, the fourth transistor T4-2 in the second voltage adjusting module 20b is turned on in response to the signals of the second node N2 or the sixth node N6, and the low level in the second clock signal CK2 is transmitted to the first electrode of the first capacitor C1-2 to reset the voltage of the first electrode of the first capacitor C1-2.

[0183] In the t4 stage, the start signal IN is a high-level signal, the first transistor T1 changes from the on state to the off state, the second transistor T2 changes from the off state to the on state, the second voltage level signal VGH is transmitted to the output end O1 of the gate drive circuit through the second transistor T2, and the gate drive signal Vout output by the gate drive circuit changes from the low-level signal to the high-level signal. After the second transistor T2 is turned on, the signals of the second node N2 and the sixth node N6 are both high-level signals, the fourth transistor T4-2 in the second voltage adjustment module 20b is turned on in response to the signals of the second node N2 or the sixth node N6, and the second clock signal CK2 is transmitted to the first electrode of the first capacitor C1-2. When the third transistor T3-2 in the second voltage adjustment module 20b is turned off in response to the low level in the first clock signal CK1, the second clock signal CK2 jumps from the low level to the high level, and the first capacitor C1-2 can couple the potential of the BGD node in response to the level jump of the second clock signal CK2 to raise the voltage of the BGD node, so that the threshold voltage of the second transistor T2 is negatively biased, thereby improving the driving capability of the second transistor T2, so that the gate drive signal Vout output by the gate drive circuit rapidly rises from the low-level signal to the high-level signal, which helps to reduce the waveform delay of the gate drive signal Vout, thereby improving the waveform distortion problem of the gate drive signal. At the same time, the signals of the first node N1, the third node N3 and the fifth node N5 are all low-level signals, the fourth transistor T4-1 in the first voltage adjustment module 20a is turned off in response to the signals of the first node N1, the third node N3 or the fifth node N5, and when the third transistor T3-1 is turned on in response to the high level in the first clock signal CK1, the first voltage level signal VGLL is transmitted to the BGU node through the third transistor T3-1 and maintained by the first capacitor C1-1, so that the first voltage level signal VGLL is transmitted to the second gate of the first transistor T1 to reduce the second gate voltage of the first transistor T1, so that the threshold voltage of the first transistor T1 is positively biased, which helps to ensure that the first transistor T1 is completely turned off, thereby suppressing the leakage current of the first transistor T1, reducing the power consumption of the first transistor T1 caused by the leakage current, and improving the waveform distortion problem of the gate drive signal.

[0184] When each transistor in the gate drive circuit is a P-type transistor, the first voltage level signal VGLL is a preset high-level signal, the second voltage level signal VGH is a preset low-level signal, and the third voltage level signal VGL is a high-level signal. The specific working principle of the gate drive circuit is similar to that of the above-mentioned embodiments, and will not be described here.

[0185] Figure 19 is a leakage current and gate drive signal waveform comparison chart provided by an embodiment of the application.

[0186] Wherein, the horizontal axis of the coordinate represents time t, and the vertical axis of the coordinate respectively represents leakage current Id and gate drive signal Vout output by the output end of the gate drive circuit, the unit of leakage current Id is ampere A, and the unit of gate drive signal Vout is volt V. In combination with Figure 17 and Figure 19 , Id1 represents the leakage current of the first transistor T1 in the technical scheme of the present application, and Id2 represents the leakage current of the output transistor of the gate drive circuit in the prior art. When the first transistor T1 and the output transistor of the gate drive circuit in the prior art are both N-type transistors, the threshold voltage of the output transistor of the gate drive circuit in the prior art is negative, and its leakage current is large, while the leakage current Id1 of the first transistor T1 in the technical scheme of the present application can be greatly reduced. Vout1 represents the high-level signal in the gate drive signal output by the gate drive circuit in the technical scheme of the present application, and Vout2 represents the high-level signal in the gate drive signal output by the gate drive circuit in the prior art. It can be seen that, compared with the prior art, the high-level signal output by the gate drive circuit provided in the embodiment of the present application is more stable.

[0187] Figure 20 is a comparison diagram of gate drive signal waveforms provided in the embodiment of the present application. Wherein, the horizontal axis of the coordinate represents time t, and the vertical axis of the coordinate represents gate drive signal Vout output by the output end of the gate drive circuit, Vout1' represents the falling edge waveform of the gate drive signal output by the gate drive circuit in the technical scheme of the present application, and Vout2' represents the falling edge waveform of the gate drive signal output by the gate drive circuit in the prior art. In Vout1', the time t01 required for the voltage of the gate drive signal to decrease from V2 to V1 is approximately 374.18 ns, and in Vout2', the time t02 required for the voltage of the gate drive signal to decrease from V2 to V1 is approximately 373.89 ns. It can be seen that the falling edge delay of the gate drive signal output by the gate drive circuit in the embodiment of the present application is close to that of the gate drive circuit in the prior art. While reducing the leakage currents of the first transistor T1 and the second transistor T2, the driving capability of the first transistor T1 and the second transistor T2 is ensured.

[0188] On the basis of the above-mentioned embodiments, in the case that the double-gate transistor in the first transistor T1 and the second transistor T2 is an N-type transistor, the potential of the first-level signal VGLL is less than or equal to the minimum potential in the first output signal and the second output signal. One of the first output signal and the second output signal is a high-level signal, and the other is a low-level signal, and the minimum potential in the first output signal and the second output signal is the potential of the low-level signal. Exemplarily, see Figure 17When the third level signal VGL is as the first output signal and the second level signal VGH is as the second output signal, the potential of the third level signal VGL is lower than the potential of the second level signal VGH, and the potential of the first level signal VGLL is less than or equal to the potential of the third level signal VGL. The level corresponding to the third level signal VGL can be a low level for normally controlling the on or off of the transistor, for example, the voltage of the third level signal VGL can be about -5V to -7V. The level of the first level signal VGLL, i.e., the preset low level, can be a more negative low level than the level of the third level signal VGL, for example, the voltage of the first level signal VGLL can be about 0.5V to 5V lower than the voltage of the third level signal VGL. The reason for such setting is that when the second gate voltage of the double-gate transistor in the first transistor T1 and the second transistor T2 is adjusted by the first level signal VGLL, the lower the level of the first level signal VGLL, the more positive the threshold voltage of the double-gate transistor can be, which helps to ensure that the double-gate transistor is completely turned off, thereby suppressing the leakage current of the double-gate transistor. In other embodiments, the potential of the first level signal VGLL can also be equal to the potential of the third level signal VGL, so that the third level signal VGL can be multiplexed as the first level signal VGLL, thereby reducing the number of signal terminals in the display panel.

[0189] Similarly, in the case where the double-gate transistor in the first transistor T1 and the second transistor T2 is a P-type transistor, the potential of the first-level signal VGLL is greater than or equal to the maximum potential in the first output signal and the second output signal. One of the first output signal and the second output signal is a high-level signal, and the other is a low-level signal, and the maximum potential in the first output signal and the second output signal is the potential of the high-level signal. For example, when the third-level signal VGL is the first output signal and the second-level signal VGH is the second output signal, the potential of the third-level signal VGL is higher than the potential of the second-level signal VGH, and the potential of the first-level signal VGLL is greater than or equal to the potential of the third-level signal VGL. The level corresponding to the third-level signal VGL can be a high level for normally controlling the on or off of the transistor, for example, the voltage of the third-level signal VGL can be a voltage of about 3.5 V to 5 V. The level of the first-level signal VGLL, that is, the preset high level, can be a higher high level than the level of the third-level signal VGL, for example, the voltage of the first-level signal VGLL can be about 0.5 V to 5 V higher than the voltage of the third-level signal VGL. In this way, when the second gate voltage of the double-gate transistor in the first transistor T1 and the second transistor T2 is adjusted by the first-level signal VGLL, it is also helpful to ensure that the double-gate transistor is completely turned off, thereby suppressing the leakage current of the double-gate transistor. In other embodiments, the potential of the first-level signal VGLL can also be equal to the potential of the third-level signal VGL, so that the third-level signal VGL can be multiplexed as the first-level signal VGLL, thereby reducing the number of signal terminals in the display panel.

[0190] Figure 21 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. Referring to Figure 21 In the gate drive circuit, the first voltage adjustment module 20a further includes a fifth transistor T5-1, and the second voltage adjustment module 20b further includes a fifth transistor T5-2. By arranging the fifth transistor T5-1 in a normally open state between the gate of the fourth transistor T4-1 and the corresponding second control signal terminal (i.e., the first node N1, the third node N3, or the fifth node N5), it is helpful to block the extremely high level in the first node N1, the third node N3, and the fifth node N5 from being transmitted to the fourth transistor T4-1, thereby affecting the operation of the fourth transistor T4-1. By arranging the fifth transistor T5-2 in a normally open state between the gate of the fourth transistor T4-2 and the corresponding second control signal terminal (i.e., the second node N2 or the sixth node N6), it is helpful to block the extremely high level in the second node N2 and the sixth node N6 from being transmitted to the fourth transistor T4-2, thereby affecting the operation of the fourth transistor T4-2.

[0191] Figure 22is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. Referring to Figure 22 In the gate drive circuit, the third transistor T3-1 in the first voltage adjustment module 20a is a double-gate transistor, the first gate of the third transistor T3-1 is connected to the first control signal A1-1, and the second gate of the third transistor T3-1 is connected to the first pole of the third transistor T3-1 to connect to the first level signal VGLL. The third transistor T3-2 in the second voltage adjustment module 20b is a double-gate transistor, the first gate of the third transistor T3-2 is connected to the first control signal A1-2, and the second gate of the third transistor T3-2 is connected to the first pole of the third transistor T3-2 to connect to the first level signal VGLL. By connecting the second gate of the third transistor T3-1 to the first level signal VGLL, the second gate potential of the third transistor T3-1 can be adjusted to adjust the threshold voltage of the third transistor T3-1, and in the case that the first gate voltage of the third transistor T3-1 is unchanged, the third transistor T3-1 is ensured to be in an off state to avoid the third transistor T3-1 not being in a completely off state, and then there is a large leakage current to affect the second gate voltage of the first transistor T1, thereby affecting the driving capability of the first transistor T1. Similarly, by connecting the second gate of the third transistor T3-2 to the first level signal VGLL, the second gate potential of the third transistor T3-2 can be adjusted to adjust the threshold voltage of the third transistor T3-2, and in the case that the first gate voltage of the third transistor T3-2 is unchanged, the third transistor T3-2 is ensured to be in an off state to avoid the third transistor T3-2 not being in a completely off state, and then there is a large leakage current to affect the second gate voltage of the second transistor T2, thereby affecting the driving capability of the second transistor T2.

[0192] Figure 23 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. Figure 23 Compared with the gate drive circuit shown in Figure 17 The difference is that the seventh capacitor C7 does not need to be arranged in the third output control unit 140, the gate of the twenty-eighth transistor T28 is connected to the second clock signal CK2, and the first pole of the twenty-eighth transistor T28 is connected to the second node N2 to transmit the third level signal VGL to the second node N2 through the third output control unit 140 in response to the signal of the fifth node N5 and the second clock signal CK2. In addition, the gate drive circuit further comprises an eighth capacitor C8, the first pole of the eighth capacitor C8 is connected to the second clock signal CK2, the second pole of the eighth capacitor C8 is connected to the sixth node N6, and the eighth capacitor C8 can couple the signal of the sixth node N6 according to the level jump of the second clock signal CK2.

[0193] Figure 24This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 24 and Figure 23 Compared to the gate drive circuits shown, the difference lies in that the third transistor T3-1 in the first voltage regulation module 20a is a dual-gate transistor. The first gate of the third transistor T3-1 is connected to the first control signal A1-1, and the second gate of the third transistor T3-1 is connected to the first terminal of the third transistor T3-1 to connect to the first level signal VGLL. Similarly, the third transistor T3-2 in the second voltage regulation module 20b is a dual-gate transistor. The first gate of the third transistor T3-2 is connected to the first control signal A1-2, and the second gate of the third transistor T3-2 is connected to the first terminal of the third transistor T3-2 to connect to the first level signal VGLL. By setting the second gate of the third transistor T3-1 to connect to the first level signal VGLL, the second gate potential of the third transistor T3-1 can be adjusted to regulate its threshold voltage. This ensures that the third transistor T3-1 is in a turned-off state while its first gate voltage remains unchanged, preventing leakage current that could affect the second gate voltage of the first transistor T1 and thus its driving capability. Similarly, by connecting the second gate of the third transistor T3-2 to the first level signal VGLL, the second gate potential of the third transistor T3-2 can be adjusted to regulate the threshold voltage of the third transistor T3-2. With the first gate voltage of the third transistor T3-2 remaining unchanged, the third transistor T3-2 is kept in the off state to avoid the third transistor T3-2 not being in a fully off state, which would result in a large leakage current that would affect the second gate voltage of the second transistor T2 and thus affect the driving capability of the second transistor T2.

[0194] This invention also provides a display panel, including the gate driving circuits described in any of the above embodiments, and the number of gate driving circuits is multiple, cascaded together. The display panel can be an Organic Light-Emitting Diode (OLED) display panel or a Micro-LED display panel, etc. Multiple gate driving circuits are cascaded; for example, the input terminal of the first-stage gate driving circuit is connected to a start signal, and the output terminal of the previous-stage gate driving circuit is connected to the input terminal of the next-stage gate driving circuit. In this way, the output signal of the previous-stage gate driving circuit can be used as the input signal of the next-stage gate driving circuit, and the multiple-stage gate driving circuits can output gate driving signals with sequentially shifted timings.

[0195] The display panel comprises a plurality of pixel circuits and light emitting devices, the pixel circuit can be composed of a thin film transistor and a storage capacitor, the thin film transistor comprises a driving transistor and a switching transistor, when the switching transistor in the pixel circuit is turned on, the data voltage can be transmitted to the storage capacitor, the data voltage is stored through the storage capacitor, so that the driving transistor can generate driving current according to the data voltage stored in the storage capacitor, and then drive the light emitting device to emit light and display. The gate driving signal output by the gate driving circuit can be used to drive the switching transistor in the pixel circuit to work.

[0196] The display panel provided by the embodiment of the present application comprises the gate driving circuit in any embodiment of the present application, and therefore has the corresponding function modules and beneficial effects of the gate driving circuit, which will not be described herein.

[0197] It should be understood that the steps can be reordered, added or deleted using various forms of flow shown above. For example, each step described in the present application can be executed in parallel, sequentially or in different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0198] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A gate driving circuit, characterized in that, include: The system includes an output control module, a first transistor, and a second transistor. The output control module is connected to the gates of the first transistor and the second transistor. A first output signal is connected to the first terminal of the first transistor, and a second terminal of the first transistor is connected to the output terminal of the gate driving circuit. A second output signal is connected to the first terminal of the second transistor, and a second terminal of the second transistor is also connected to the output terminal of the gate driving circuit. The output control module controls the first transistor and the second transistor to conduct alternately, so as to alternately transmit the first output signal and the second output signal to the output terminal of the gate driving circuit. At least one of the first transistor and the second transistor is a dual-gate transistor, and the first gate of the dual-gate transistor is connected to the output control module. At least one voltage regulation module is connected to the second gate of the dual-gate transistor; The voltage regulation module is used to adjust the second gate voltage of the dual-gate transistor when the dual-gate transistor is turned on, so as to improve the driving capability of the dual-gate transistor, and to adjust the second gate voltage of the dual-gate transistor when the dual-gate transistor is turned off, so as to suppress the leakage current of the dual-gate transistor. The voltage regulation module includes: A first voltage regulation unit, wherein the control terminal of the first voltage regulation unit is connected to a first control signal, the first terminal of the first voltage regulation unit is connected to a first level signal, and the second terminal of the first voltage regulation unit is connected to the second gate of the dual-gate transistor, and the first voltage regulation unit is used to respond to the first control signal and transmit the first level signal to the second gate of the dual-gate transistor when the dual-gate transistor is turned off. The second voltage regulation unit has a control terminal connected to a second control signal, a first terminal connected to a preset signal, and a second terminal connected to the second gate of the dual-gate transistor. The second voltage regulation unit is used to respond to the second control signal and adjust the second gate voltage of the dual-gate transistor by the preset signal when the dual-gate transistor is turned on. Wherein, the level of the first level signal includes a first level; the level of the preset signal includes a second level, one of the first level and the second level is a preset high level, and the other is a preset low level.

2. The gate driving circuit according to claim 1, characterized in that, The control terminal of the voltage regulation module is connected to a first control signal, the first terminal of the voltage regulation module is connected to a first level signal, and the second terminal of the voltage regulation module is connected to the second gate of the dual-gate transistor. The voltage regulation module is used to respond to the first control signal and transmit the first level signal to the second gate of the dual-gate transistor when the dual-gate transistor is turned off, so as to suppress the leakage current of the dual-gate transistor.

3. The gate driving circuit according to claim 1, characterized in that, The voltage regulation module includes a third transistor, the gate of which is connected to the first control signal, the first terminal of which is connected to the first level signal, and the second terminal of which is connected to the second gate of the dual-gate transistor.

4. The gate driving circuit according to claim 1, characterized in that, The control terminal of the voltage regulation module is connected to a second control signal, the first terminal of the voltage regulation module is connected to a preset signal, and the second terminal of the voltage regulation module is connected to the second gate of the dual-gate transistor. The voltage regulation module is used to respond to the second control signal and adjust the second gate voltage of the dual-gate transistor through the preset signal when the dual-gate transistor is turned on, so as to improve the driving capability of the dual-gate transistor.

5. The gate driving circuit according to claim 1, characterized in that, The voltage regulation module includes a fourth transistor, the gate of which is connected to the second control signal, and the first terminal of which is connected to the preset signal. The fourth transistor is used to transmit a signal related to the preset signal to the second gate of the dual-gate transistor in response to the second control signal.

6. The gate driving circuit according to claim 5, characterized in that, The voltage regulation module further includes a first capacitor connected between the second terminal of the fourth transistor and the second gate of the dual-gate transistor.

7. The gate driving circuit according to claim 5, characterized in that, The voltage regulation module further includes a fifth transistor, through which the second control signal is connected to the gate of the fourth transistor, and the fifth transistor remains in a normally open state.

8. The gate driving circuit according to claim 1, characterized in that, The first voltage regulation unit includes a third transistor, and the second voltage regulation unit includes a fourth transistor; The gate of the third transistor is connected to the first control signal, the first terminal of the third transistor is connected to the first level signal, and the second terminal of the third transistor is connected to the second gate of the dual-gate transistor. The gate of the fourth transistor is connected to the second control signal, and the first terminal of the fourth transistor is connected to the preset signal. The fourth transistor is used to transmit a signal related to the preset signal to the second gate of the dual-gate transistor in response to the second control signal.

9. The gate driving circuit according to claim 8, characterized in that, The second voltage regulation unit further includes a first capacitor connected between the second electrode of the fourth transistor and the second gate of the dual-gate transistor.

10. The gate driving circuit according to claim 1, characterized in that, When the dual-gate transistor is an N-type transistor, the first level is a preset low level and the second level is a preset high level; When the dual-gate transistor is a P-type transistor, the first level is a preset high level and the second level is a preset low level.

11. The gate driving circuit according to claim 1, characterized in that, The first control signal includes a first clock signal, and the preset signal includes a second clock signal, wherein the first clock signal and the second clock signal are out of phase.

12. The gate driving circuit according to claim 3 or 8, characterized in that, The third transistor is a dual-gate transistor; The first gate of the third transistor is connected to the first control signal, and the second gate of the third transistor is connected to the first level signal; or, The second gate of the third transistor is connected to the first control signal, and the first gate of the third transistor is connected to the first level signal.

13. The gate driving circuit according to any one of claims 1-11, characterized in that, When the first transistor is the dual-gate transistor, the voltage regulation module includes a first voltage regulation module connected to the second gate of the first transistor; When the second transistor is the dual-gate transistor, the voltage regulation module includes a second voltage regulation module connected to the second gate of the second transistor.

14. The gate driving circuit according to claim 13, characterized in that, Both the first transistor and the second transistor are dual-gate transistors; The second gate of the first transistor is connected to the first voltage regulation module, and the second gate of the second transistor is connected to the second voltage regulation module.

15. The gate driving circuit according to any one of claims 1-11, characterized in that, Both the first transistor and the second transistor are dual-gate transistors; The second gate of one of the first transistors and the second transistor is connected to a first level signal line, and the second gate of the other of the first transistors and the second transistor is connected to the voltage regulation module; or, The first gate and the second gate of one of the first transistor and the second transistor are connected, and the second gate of the other of the first transistor and the second transistor is connected to the voltage regulation module.

16. The gate driving circuit according to claim 1, characterized in that, The output control module includes: An input unit, connected to the first node, the second node, and the input terminal of the gate driving circuit, is used to control the signals of the first node and the second node according to the first clock signal, the second level signal, and the signal at the input terminal of the gate driving circuit. A first output control unit, connected to the first node and the second node, is used to control the signal of the first node according to the signal of the second node and the first clock signal; A second output control unit is connected to the first node and the second node, and is used to control the signal of the second node according to the signal of the first node, the second clock signal and the third level signal; wherein, the first node is connected to the gate of the first transistor, and the signal of the second node is transmitted to the gate of the second transistor; The third level signal is multiplexed as the first output signal, and the second clock signal is multiplexed as the second output signal.

17. The gate driving circuit according to claim 16, characterized in that, The output control module further includes a sixth transistor connected between the third node and the second node. The sixth transistor is kept in a normally open state. The third node is connected to the gate of the second transistor, and the signal from the second node is transmitted to the gate of the second transistor through the sixth transistor.

18. The gate driving circuit according to claim 17, characterized in that, When the first transistor is the dual-gate transistor, the voltage regulation module includes a first voltage regulation module connected to the second gate of the first transistor; when the second transistor is the dual-gate transistor, the voltage regulation module includes a second voltage regulation module connected to the second gate of the second transistor.

19. The gate driving circuit according to claim 18, characterized in that, The signal from the second node, the signal from the third node, or the first clock signal are multiplexed into a first control signal in the first voltage regulation module; the signal from the first node is multiplexed into a second control signal in the first voltage regulation module. The second clock signal or the second level signal is multiplexed into a preset signal in the first voltage regulation module and the second voltage regulation module; The signal of the first node or the first clock signal is multiplexed into the first control signal in the second voltage regulation module, and the signal of the second node or the signal of the third node is multiplexed into the second control signal in the second voltage regulation module.

20. The gate driving circuit according to claim 16, characterized in that, The first output control unit includes a seventh transistor, the gate of which is connected to the second node, the first terminal of which is connected to the first clock signal, and the second terminal of which is connected to the first node; The second output control unit includes an eighth transistor and a ninth transistor. The gate of the eighth transistor is connected to the first node, the first terminal of the eighth transistor is connected to the third level signal, the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor, the gate of the ninth transistor is connected to the second clock signal, and the second terminal of the ninth transistor is connected to the second node.

21. The gate driving circuit according to claim 20, characterized in that, The seventh transistor is a dual-gate transistor, with its first gate connected to the second node and its second gate connected to the first level signal; And / or, Both the eighth transistor and the ninth transistor are dual-gate transistors. The first gate of the eighth transistor is connected to the first node, the first gate of the ninth transistor is connected to the second clock signal, and the second gates of both the eighth transistor and the ninth transistor are connected to the first level signal.

22. The gate driving circuit according to claim 1, characterized in that, The output control module includes: An input unit, connected to the first node, the second node, and the input terminal of the gate driving circuit, is used to control the signals of the first node and the second node according to the first clock signal, the third level signal, and the signal at the input terminal of the gate driving circuit. A first output control unit, connected to a third node, a first node, and a second node, is used to control the signal of the third node according to a second clock signal, the signal of the first node, the signal of the second node, and the third level signal; wherein, the third node is connected to the gate of the first transistor; The second output control unit is connected to the fourth node and the third node, and is used to control the signal of the fourth node according to the signal of the third node, the signal of the fourth node, the third level signal and the second clock signal; wherein, the fourth node is connected to the gate of the second transistor, and the signal of the second node is transmitted to the gate of the second transistor; The third level signal is multiplexed to become the first output signal, and the second level signal is multiplexed to become the second output signal.

23. The gate driving circuit according to claim 22, characterized in that, The output control module further includes a tenth transistor, which is connected between the second node and the fourth node. The tenth transistor is kept in a normally open state, and the signal from the second node is transmitted to the gate of the second transistor through the tenth transistor.

24. The gate driving circuit according to claim 23, characterized in that, When the first transistor is the dual-gate transistor, the voltage regulation module includes a first voltage regulation module connected to the second gate of the first transistor; when the second transistor is the dual-gate transistor, the voltage regulation module includes a second voltage regulation module connected to the second gate of the second transistor.

25. The gate driving circuit according to claim 24, characterized in that, The first clock signal is multiplexed into a first control signal in the first voltage regulation module and the second voltage regulation module; the signal of the first node is multiplexed into a second control signal in the first voltage regulation module; The second clock signal or the second level signal is multiplexed into a preset signal in the first voltage regulation module and the second voltage regulation module; The signal from the second node or the signal from the fourth node is multiplexed into the second control signal in the second voltage regulation module.

26. The gate driving circuit according to claim 1, characterized in that, The output control module includes an input unit connected to the first node, the second node, and the input terminal of the gate driving circuit, used to control the signals of the first node and the second node according to the first clock signal, the second level signal, and the signal of the input terminal of the gate driving circuit; A first output control unit, connected to the first node and the second node, is used to control the signal of the first node according to the signal of the second node and the first clock signal; The second output control unit is connected to the third node and the fourth node, and is used to control the signal of the fourth node according to the signal of the third node and the second clock signal; wherein the signal of the first node is transmitted to the third node, and the signal of the fourth node is transmitted to the gate of the first transistor; A third output control unit, connected to the fifth node and the sixth node, is used to control the signal of the sixth node according to the signal of the fifth node, the signal of the sixth node, the third level signal and the second clock signal; wherein, the signal of the first node is transmitted to the fifth node, the signal of the second node is transmitted to the sixth node, and the sixth node is connected to the gate of the second transistor; A fourth output control unit, connected to the seventh node and the second node, is used to control the signal of the seventh node according to the signal of the second node and the third level signal; wherein the signal of the fourth node is transmitted to the seventh node, and the seventh node is connected to the gate of the first transistor; The third level signal is multiplexed to become the first output signal, and the second level signal is multiplexed to become the second output signal.

27. The gate driving circuit according to claim 26, characterized in that, The output control module further includes an eleventh transistor, the first terminal of which is connected to the first node, the second terminal of which is connected to the third node, the eleventh transistor is kept in a normally open state, and the signal from the first node is transmitted to the third node through the eleventh transistor. The output control module further includes a twelfth transistor, which is connected between the fourth node and the seventh node. The twelfth transistor is kept normally open, and the signal from the fourth node is transmitted to the gate of the first transistor through the twelfth transistor. The output control module also includes a thirteenth transistor, the first terminal of which is connected to the second terminal of the eleventh transistor, the second terminal of which is connected to the fifth node, the thirteenth transistor is kept in a normally open state, and the signal from the first node is transmitted to the fifth node through the thirteenth transistor; The output control module further includes a fourteenth transistor connected between the second node and the sixth node. The fourteenth transistor is kept normally open, and the signal from the second node is transmitted to the sixth node through the fourteenth transistor.

28. The gate driving circuit according to claim 27, characterized in that, When the first transistor is the dual-gate transistor, the voltage regulation module includes a first voltage regulation module connected to the second gate of the first transistor; when the second transistor is the dual-gate transistor, the voltage regulation module includes a second voltage regulation module connected to the second gate of the second transistor.

29. The gate driving circuit according to claim 28, characterized in that, The first clock signal is multiplexed into a first control signal in the first voltage regulation module and the second voltage regulation module; the signal of the first node, the signal of the third node, or the signal of the fifth node is multiplexed into a second control signal in the first voltage regulation module; The second clock signal or the second level signal is multiplexed into a preset signal in the first voltage regulation module and the second voltage regulation module; The signal from the second node or the signal from the sixth node is multiplexed into a second control signal in the second voltage regulation module.

30. The gate driving circuit according to claim 3, characterized in that, When the dual-gate transistor is an N-type transistor, the potential of the first level signal is less than or equal to the minimum potential of the first output signal and the second output signal; When the dual-gate transistor is a P-type transistor, the potential of the first level signal is greater than or equal to the maximum potential of the first output signal and the second output signal.

31. A display panel, characterized in that, It includes multiple gate drive circuits as described in any one of claims 1-30, and the multiple gate drive circuits are cascaded together.

Images