Semiconductor device and manufacturing method thereof

Abstract

The present application discloses a semiconductor device comprising: a substrate including a first surface and a second surface opposing each other; a gate located on the first surface of the substrate; a source region and a drain region in the substrate located on either side of the gate; and an anti-punchthrough structure in the substrate, the anti-punchthrough structure including a third surface and a fourth surface opposing each other, the third surface being adjacent to and lower than the first surface, the anti-punchthrough structure being located between the source region and the drain region. By providing the anti-punchthrough structure between the source region and the drain region in the substrate, the present application can reduce or avoid the effects of short channel effects, thereby improving device performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, the size of semiconductor devices such as field-effect transistors has continued to shrink. When the channel length is reduced to a certain extent, a series of secondary physical effects known as short-channel effects occur. For example, when the depletion region generated by the drain region of a transistor contacts or is closely adjacent to the opposing depletion region generated by the source region of an opposing transistor, punchthrough of the depletion region can cause charge to move between the source and drain regions without being affected by the voltage applied to the gate. Therefore, transistors affected by punchthrough may be unable to shut down. Therefore, finding a semiconductor device that is resistant to punchthrough is a challenge that those skilled in the art need to address. Summary of the Invention

[0003] In view of this, an embodiment of the present application provides a semiconductor device to solve at least one problem existing in the background technology.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] According to an embodiment of the present application, a semiconductor device is provided, including:

[0006] A substrate comprising a first surface and a second surface opposite to each other; a gate located on the first surface of the substrate; a source region and a drain region in the substrate located on both sides of the gate; and an anti-punchthrough structure located in the substrate, the anti-punchthrough structure comprising a third surface and a fourth surface opposite to each other, the third surface being close to and lower than the first surface, and the anti-punchthrough structure being located between the source region and the drain region.

[0007] In some exemplary embodiments of the present application, the anti-punch-through structure is located below the gate, and the distance between the anti-punch-through structure and the source region is equal to the distance between the anti-punch-through structure and the drain region.

[0008] In some exemplary embodiments of the present application, the anti-punch-through structure is T-shaped, and the width of the third surface of the anti-punch-through structure is greater than the width of the fourth surface.

[0009] In some exemplary embodiments of the present application, the semiconductor device includes:

[0010] Two anti-punch-through structures are located below the gate, and the distance between the anti-punch-through structure near the source region and the source region is equal to the distance between the anti-punch-through structure near the drain region and the drain region.

[0011] In some exemplary embodiments of the present application, the semiconductor device includes:

[0012] A plurality of anti-punch-through structures are symmetrically distributed relative to a central axis of the gate, and a distance between the anti-punch-through structures and the first surface increases successively along the direction from the central axis to the source region or the drain region.

[0013] In some exemplary embodiments of the present application, a distance between the third surface of the anti-punch-through structure and the first surface of the substrate is greater than 50 angstroms.

[0014] In some exemplary embodiments of the present application, the material of the anti-punch-through structure includes an insulating material.

[0015] The present invention also provides a method for manufacturing a semiconductor device, including:

[0016] A substrate is provided, the substrate including a first surface and a second surface opposite to each other; an anti-punchthrough structure is formed in the substrate, the anti-punchthrough structure including a third surface and a fourth surface opposite to each other, the third surface being close to the first surface and lower than the first surface; a gate is formed on the first surface of the substrate; and a source region and a drain region are formed in the substrate on both sides of the gate, the anti-punchthrough structure being located between the source region and the drain region.

[0017] In some exemplary embodiments of the present application, forming an anti-punch-through structure in the substrate includes:

[0018] A patterned mask layer is formed on the second surface of the substrate, the mask layer exposing an area on the substrate; the substrate is etched using the patterned mask layer as a mask to form an opening; and an insulating material is filled in the opening to form an anti-punch-through structure.

[0019] In some exemplary embodiments of the present application, the anti-punch-through structure is located below the gate, and the distance between the anti-punch-through structure and the source region is equal to the distance between the anti-punch-through structure and the drain region.

[0020] In some exemplary embodiments of the present application, the anti-punch-through structure is T-shaped, and the width of the third surface of the anti-punch-through structure is greater than the width of the fourth surface.

[0021] In some exemplary embodiments of the present application, forming an anti-punch-through structure in the substrate includes:

[0022] Two anti-punchthrough structures are formed in the substrate. The two anti-punchthrough structures are located below the gate, and the distance between the anti-punchthrough structure near the source region and the source region is equal to the distance between the anti-punchthrough structure near the drain region and the drain region.

[0023] In some exemplary embodiments of the present application, forming an anti-punch-through structure in the substrate includes:

[0024] A plurality of anti-punch-through structures are formed in the substrate, the plurality of anti-punch-through structures are symmetrically distributed relative to the central axis of the gate, and the distance between the anti-punch-through structures and the first surface increases successively along the direction from the central axis to the source region or the drain region.

[0025] In some exemplary embodiments of the present application, a distance between the third surface of the anti-punch-through structure and the first surface of the substrate is greater than 50 angstroms.

[0026] An embodiment of the present application further provides a memory comprising the semiconductor device described in any of the above embodiments.

[0027] An embodiment of the present application provides a semiconductor device, comprising: a substrate including a first surface and a second surface opposing each other; a gate located on the first surface of the substrate; a source region and a drain region in the substrate located on either side of the gate; and an anti-punchthrough structure in the substrate, the anti-punchthrough structure including a third surface and a fourth surface opposing each other, the third surface being adjacent to and lower than the first surface, the anti-punchthrough structure being located between the source region and the drain region. Providing the anti-punchthrough structure between the source region and the drain region in the substrate can reduce or avoid the effects of short channel effects, thereby improving device performance.

[0028] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1a A schematic cross-sectional view of a semiconductor device of related art;

[0030] Figure 1b A schematic cross-sectional view of a semiconductor device of related art;

[0031] Figure 1c A schematic cross-sectional view of a semiconductor device of related art;

[0032] Figure 2 A schematic cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0033] Figure 3a-3b A schematic cross-sectional view of a semiconductor device provided in another embodiment of the present application;

[0034] Figure 4 A schematic cross-sectional view of a semiconductor device provided in another embodiment of the present application;

[0035] Figure 5 A schematic cross-sectional view of a semiconductor device provided in another embodiment of the present application;

[0036] Figure 6 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0037] Figures 7a to 7d A schematic diagram of the device structure during the preparation process of the semiconductor device provided in an embodiment of the present application.

[0038] Figures 8a to 8c A schematic diagram of the device structure during the preparation process of the semiconductor device provided in an embodiment of the present application.

[0039] Figures 9a to 9b A schematic diagram of the device structure during the preparation process of the semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0041] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0042] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0043] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0044] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0047] Attachment Figure 1a The cross-sectional view of a semiconductor device of related art is shown, which includes: a substrate 101; a gate 103 located on the substrate; a source region 105 and a drain region 107 located in the substrate on both sides of the gate. With the continuous development of integrated circuit manufacturing technology, the size of the device is also continuously reduced. Figure 1a As shown in the figure, the depletion layers of the source and drain regions are getting closer. When voltage is applied to the drain end, the drain end depletion layer 111 widens and gradually merges with the source end depletion layer 109, causing serious surface punch-through current. The current improvement method in the industry is to implant more channel ion implantation (IMP) in the channel surface area to reduce the width of the surface depletion layer. However, as the channel length is further reduced, the depletion layers below the source and drain regions are still at risk of contact, causing body punch-through current, as shown in the attached figure. Figure 1b If more well ion implantation (WELL IMP) is performed here, problems such as body effect, well isolation, and latch-up will occur, so other more advanced improvement methods are needed. Silicon on insulator (SOI) structure, as shown in the attached figure, Figure 1c As shown, the silicon layer is very thin, and the oxide layer 113 in the middle can isolate the depletion layer, which can effectively reduce the punch-through leakage. However, this structure is complex and cannot be compatible with the process of general semiconductor devices such as dynamic random access memory (DRAM).

[0048] Based on this, the embodiment of the present application provides a semiconductor device, Figure 2 Schematic diagram of the cross section of the semiconductor device provided in the embodiment of the present application. Figure 2The semiconductor device includes: a substrate 101, the substrate 101 including a first surface 213 and a second surface 215 opposite to each other; a gate 103 located on the first surface 213 of the substrate 101; a source region 105 and a drain region 107 located in the substrate 101 on either side of the gate 103; and an anti-punchthrough structure 217 located in the substrate. The anti-punchthrough structure 217 includes a third surface 219 and a fourth surface 221 opposite to each other, the third surface 219 being close to and lower than the first surface 213, and the anti-punchthrough structure 217 being located between the source region 105 and the drain region 107. The anti-punchthrough structure 217 can block the lateral expansion of the drain-end depletion layer 111 and the source-end depletion layer 109. Thus, providing the anti-punchthrough structure between the source and drain regions in the substrate can reduce or avoid the impact of the short channel effect and improve device performance.

[0049] In actual operation, the substrate 101 may be silicon, silicon germanium, germanium, or other suitable semiconductors. The source region 105 and the drain region 107 may be formed into an N-type doped region by doping with an n-type dopant such as phosphorus, arsenic, other n-type dopant, or a combination thereof; and may be formed into a P-type doped region by doping with a p-type dopant such as boron, indium, other p-type dopant, or a combination thereof. The source region 105 and the drain region 107 may also include a lightly doped region (LDD) and a Halo implanted region. The gate 103 includes a gate dielectric layer and a gate metal layer. For example, the gate dielectric layer may be silicon oxynitride, silicon oxide, or a high-K material, and the gate metal layer may be polysilicon, tungsten metal, titanium nitride, or the like.

[0050] In one embodiment, the distance between the third surface 219 of the anti-punchthrough structure 217 and the first surface 213 of the substrate 101 is greater than 50 angstroms. In this case, the anti-punchthrough structure 217 can block most of the lateral diffusion of the drain depletion layer 111 and the source depletion layer 109 without significantly affecting the formation of the channel.

[0051] In one embodiment, the fourth surface 221 of the anti-punchthrough structure 217 is flush with the second surface 215 of the substrate 101. If the fourth surface 221 is higher than the second surface 215, the drain depletion layer 111 and the source depletion layer 109 may bypass the anti-punchthrough structure 217 from below the fourth surface 221, thereby causing undesirable leakage. This effectively prevents the depletion layer from bypassing the fourth surface of the anti-punchthrough structure and causing a punchthrough effect.

[0052] In one embodiment, the material of the anti-punch-through structure 217 may include insulating materials such as silicon dioxide (SiO 2 ), silicon nitride, and silicon oxynitride.

[0053] In one embodiment, the expansion coefficient of the anti-punch-through structure 217 is smaller than the expansion coefficient of the substrate 101; and / or the elastic modulus of the anti-punch-through structure 217 is greater than the elastic modulus of the substrate 101. In this way, by selecting a suitable anti-punch-through structure material, the stress effect caused by adding the anti-punch-through structure can be minimized.

[0054] Although not shown in the figures, when multiple semiconductor devices according to embodiments of the present application are manufactured simultaneously, shallow trench isolation (STI) may be performed between the multiple semiconductor devices.

[0055] In some embodiments of the present application, as shown in the attached Figure 2 As shown, the anti-punchthrough structure 217 is located below the gate 103, and the distance W1 between the anti-punchthrough structure 217 and the source region 105 is equal to the distance W2 between the anti-punchthrough structure 217 and the drain region 107. Compared to an anti-punchthrough structure offset to one side, an anti-punchthrough structure located in the center of the device can prevent punchthrough without affecting the direction of the depletion layer, while also ensuring uniform stress distribution across the device.

[0056] In some embodiments of the present application, as shown in the attached Figure 3a As shown, the anti-punchthrough structure 217 is T-shaped, and the width W3 of the third surface 219 of the anti-punchthrough structure 217 is greater than the width W4 of the fourth surface 221. As device integration increases and channel length shortens, in a single anti-punchthrough structure with uniform width, the depletion layer at the source and drain ends may bypass the anti-punchthrough structure and contact each other from above the anti-punchthrough structure, causing a punchthrough effect. The T-shaped structure can greatly reduce the probability of the depletion layer bypassing the third surface of the anti-punchthrough structure, thereby improving device reliability.

[0057] In the above embodiment, the third surface 219 of the anti-punch-through structure is parallel to the substrate surface. However, the above solution is only an example of an embodiment. It should be understood that other structures can be used to implement the present application and should not be limited by the specific embodiment described here. Figure 3b As shown, the third surface 219 of the anti-punch-through structure can be concave in a circular arc shape toward the gate, which is conducive to filling with insulating material, simplifies the filling process, and reduces production costs.

[0058] In some embodiments of the present application, as shown in the attached Figure 4As shown, the semiconductor device includes: two punch-through prevention structures 217. The two punch-through prevention structures 217 are located below the gate 103, and the distance W5 between the punch-through prevention structure 217 close to the source region 105 and the source region 105 is equal to the distance W6 between the punch-through prevention structure 217 close to the drain region 107 and the drain region 107. Since the process of setting the T-shaped punch-through prevention structure is relatively complex, and the effect of a single punch-through prevention structure in blocking the punch-through of the depletion layer is limited. Therefore, in the embodiment of the present application, punch-through prevention structures 217 are provided at both the source end and the drain end. The punch-through prevention structure 217 close to the source region 105 can block the diffusion of the source-end depletion layer 109 towards the drain end, and the punch-through prevention structure 217 close to the drain region 107 can block the diffusion of the drain-end depletion layer 111 towards the source end, thereby effectively reducing the body punch-through effect of the short-channel device.

[0059] In some embodiments of the present application, as shown in the appendix Figure 5 As shown, the semiconductor device includes: a plurality of punch-through prevention structures. The plurality of punch-through prevention structures are symmetrically distributed with respect to the central axis 523 of the gate, and the distance between the punch-through prevention structure and the first surface 213 increases sequentially along the direction of the central axis 523 to the source region or the drain region.

[0060] In actual operation, as shown in the appendix Figure 5 As shown, taking 5 punch-through prevention structures as an example, the above solution will be specifically described. The 5 punch-through prevention structures are symmetrically distributed with respect to the central axis 523 of the gate. Among them, the punch-through prevention structure 217-1 is located at the central axis 523, and the distance between the punch-through prevention structure 217-1 and the first surface 213 is W7. The punch-through prevention structures 217-2 are symmetrically distributed on both sides of the punch-through prevention structure 217-1, and the distance between the punch-through prevention structure 217-2 and the first surface 213 is W8. The punch-through prevention structures 217-3 are symmetrically distributed on the outermost sides of the punch-through prevention structure 217-1, and the distance between the punch-through prevention structure 217-3 and the first surface 213 is W9. The distance between the punch-through prevention structure and the first surface 213 increases sequentially along the direction of the central axis 523 to the source region or the drain region, that is, W7 < W8 < W9. Although setting punch-through prevention structures at both the source end and the drain end can effectively inhibit the punch-through of the depletion layer, this structure forcibly changes the direction of the depletion layer, and the physical model requires this area to balance charges. In this embodiment, the effect of preventing punch-through is achieved as much as possible without affecting the depletion layer region. For example, as the source-end depletion layer 109 gradually expands, the punch-through prevention structure 217-3 set on the outermost side first will play a blocking role and delay its migration towards the drain end. As the source-end depletion layer 109 further expands, the punch-through prevention structure 217-2 will play a blocking role, thereby preventing the depletion layer from bypassing the central punch-through prevention structure 217-1 above.

[0061] The present invention also provides a method for manufacturing a semiconductor device. Figure 6 , as shown in the figure, the method includes:

[0062] Step 601: providing a substrate, wherein the substrate comprises a first surface and a second surface opposite to each other;

[0063] Step 602: forming an anti-punch-through structure in the substrate, wherein the anti-punch-through structure includes a third surface and a fourth surface opposite to each other, wherein the third surface is close to the first surface and lower than the first surface;

[0064] Step 603: forming a gate on the first surface of the substrate;

[0065] Step 604: forming a source region and a drain region in the substrate on both sides of the gate, with the anti-punch-through structure being located between the source region and the drain region.

[0066] The manufacturing method of the semiconductor device provided in the embodiment of the present application is further described in detail below with reference to specific embodiments.

[0067] Figures 7a to 7d A schematic diagram of the device structure during the preparation process of the semiconductor device provided in an embodiment of the present application.

[0068] First, execute step 601, see Figure 7a , providing a substrate 101, wherein the substrate 101 includes a first surface 213 and a second surface 215 opposite to each other. The substrate 101 may be silicon, silicon germanium, germanium or other suitable semiconductors.

[0069] Next, see Figure 7b , perform step 602 to form an anti-punch-through structure 217 in the substrate 101, the anti-punch-through structure 217 includes a third surface 219 and a fourth surface 221 opposite to each other, the third surface 219 is close to the first surface 213 and lower than the first surface 213.

[0070] In actual operation, as shown in the attached Figures 8a-8c As shown, an anti-punch-through structure 217 is formed in the substrate 101, including: forming a patterned mask layer 801 on the second surface 215 of the substrate 101, the mask layer 801 exposing an area on the substrate 101; etching the substrate 101 using the patterned mask layer 801 as a mask to form an opening 805; filling the opening 805 with an insulating material to form an anti-punch-through structure.

[0071] Specifically, as attached Figure 8aAs shown, the substrate 101 is first turned over, and a mask layer 801 is formed on the second surface 215 of the substrate 101. Then, the mask layer 801 is patterned using a photomask 803 to form a shape corresponding to the pattern to be etched. The mask layer 801 can be patterned by a photolithography process, for example, by steps such as exposure, development, and stripping.

[0072] Next, see the attached Figure 8b The substrate 101 is etched using the patterned mask layer 801 as a mask to form an opening 805 having a certain depth according to the groove pattern to be etched. Here, for example, a wet or dry etching process can be used to form the opening 805. In actual operation, the distance between the bottom surface of the opening 805 and the first surface 213 of the substrate 101 is greater than 50 angstroms.

[0073] Then, see Figure 8c The opening 805 is filled with an insulating material to form an anti-punch-through structure 217. The insulating material may include insulating materials such as silicon dioxide (SiO2), silicon nitride, and silicon oxynitride. For example, after depositing SiO2, chemical mechanical polishing (CMP) is performed to remove the SiO2 deposited on the substrate surface.

[0074] Next, see Figure 7c , step 603 is performed to form a gate 103 on the first surface 213 of the substrate. The gate 103 includes a gate dielectric layer and a gate metal layer. For example, the gate dielectric layer may be silicon oxynitride, silicon oxide, or a high-K material, and the gate metal layer may be polysilicon, tungsten metal, titanium nitride, or the like.

[0075] In one embodiment, the expansion coefficient of the anti-punch-through structure is smaller than the expansion coefficient of the substrate; and / or the elastic modulus of the anti-punch-through structure is larger than the elastic modulus of the substrate. In this way, by selecting a suitable anti-punch-through structure material, the stress impact caused by the addition of the anti-punch-through structure can be minimized.

[0076] Finally, referring to FIG7 d , step 604 is performed to form a source region 105 and a drain region 107 in the substrate 101 on both sides of the gate 103 , with the anti-punch-through structure 217 located between the source region 105 and the drain region 107 .

[0077] Thus, providing an anti-punchthrough structure between the source and drain regions in the substrate can reduce or avoid the impact of the short channel effect and improve device performance. In actual operation, the source region 105 and the drain region 107 can be doped with n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof to form n-type doped regions; and can be doped with p-type dopants such as boron, indium, other p-type dopants, or combinations thereof to form p-type doped regions. The source and drain regions may also include lightly doped regions (LDDs) and Halo implanted regions.

[0078] Although not shown in the figures, when multiple semiconductor devices according to embodiments of the present application are manufactured simultaneously, shallow trench isolation (STI) may be performed between the multiple semiconductor devices.

[0079] In one embodiment, the fourth surface 221 of the anti-punch-through structure 217 is flush with the second surface 215 of the substrate 217 .

[0080] In some embodiments of the present application, the anti-punch-through structure is located below the gate, and the distance between the anti-punch-through structure and the source region is equal to the distance between the anti-punch-through structure and the drain region.

[0081] In another embodiment, the anti-punch-through structure is T-shaped, and the width of the third surface of the anti-punch-through structure is greater than the width of the fourth surface. Figure 9a As shown, a first substrate 901 and a second substrate 903 may be provided, a first trench 905 may be formed in the first substrate 901, the bottom of the first trench 905 forming the third surface 219 of the T-shaped anti-punch-through structure, a second trench 907 may be formed in the second substrate 903, and the second trench 907 may penetrate the second substrate 903. Figure 9b As shown, the first substrate 901 and the second substrate 903 are bonded together, and a T-shaped opening 911 is formed by the first trench 905 and the second trench 907. Then, an insulating material is filled into the T-shaped opening 911 to form an anti-punch-through structure. In some preferred embodiments, the bottom surface of the first trench 905 can be an arc surface, and the upper surface of the resulting T-shaped anti-punch-through structure can also be an arc surface.

[0082] In another embodiment, the semiconductor device includes: two anti-punch-through structures, the two anti-punch-through structures are located below the gate, and the distance between the anti-punch-through structure near the source region and the source region is equal to the distance between the anti-punch-through structure near the drain region and the drain region.

[0083] In some embodiments, the semiconductor device includes: multiple anti-punchthrough structures, the multiple anti-punchthrough structures are symmetrically distributed with respect to the central axis of the gate, and the distance between the anti-punchthrough structures and the first surface increases in a direction from the central axis to the source region or the drain region. In actual operation, multiple mask etching processes can be performed, and the etching time can be controlled to obtain openings of varying depths that decrease in a direction from the central axis to the source region or the drain region. Subsequently, an insulating material is filled into the openings to form the anti-punchthrough structures.

[0084] The present application also provides a memory device including the semiconductor device described in the above solution. The memory device may be a computing memory (e.g., DRAM, SRAM, DDR3 SDRAM, DDR2 SDRAM, DDR SDRAM, etc.), a consumer memory (e.g., DDR3 SDRAM, DDR2 SDRAM, DDR SDRAM, SDRS DRAM, etc.), a graphics memory (e.g., DDR3 SDRAM, GDDR3 SDRAM, GDDR4 SDRAM, GDDR5 SDRAM, etc.), a mobile memory, etc. The beneficial effects thereof can be referred to the above description of the semiconductor device and its manufacturing method, which will not be repeated here.

[0085] In summary, the anti-punchthrough structure can block the lateral diffusion of the drain and source depletion layers. Providing an anti-punchthrough structure between the source and drain regions in the substrate can reduce or avoid the impact of the short channel effect and improve device performance.

[0086] It should be noted that the semiconductor device and its manufacturing method provided by the embodiments of the present invention can be applied to any integrated circuit including the structure. The technical features in the technical solutions described in the embodiments can be combined arbitrarily if they do not conflict.

[0087] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor device, characterized in that: include: a substrate comprising a first surface and a second surface opposite to each other; a gate located on the first surface of the substrate; a source region and a drain region in the substrate respectively located on both sides of the gate; A plurality of anti-punch-through structures are located in the substrate, the anti-punch-through structures include a third surface and a fourth surface opposite to each other, the third surface is close to the first surface and lower than the first surface, and the anti-punch-through structure is located between the source region and the drain region; the plurality of anti-punch-through structures are symmetrically distributed relative to the central axis of the gate, and the distance between the anti-punch-through structure and the first surface increases successively along the direction from the central axis to the source region or the drain region.

2. The semiconductor device according to claim 1, wherein The anti-punch-through structure is T-shaped, and the width of the third surface of the anti-punch-through structure is greater than the width of the fourth surface.

3. The semiconductor device according to claim 1, wherein A distance between the third surface of the anti-punch-through structure and the first surface of the substrate is greater than 50 angstroms.

4. The semiconductor device according to claim 1, wherein The material of the anti-punch-through structure includes insulating material.

5. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate comprising a first surface and a second surface opposite to each other; forming an anti-punch-through structure in the substrate, the anti-punch-through structure comprising a third surface and a fourth surface opposite to each other, the third surface being close to the first surface and lower than the first surface; forming a gate on the first surface of the substrate; forming a source region and a drain region in the substrate on both sides of the gate, wherein the anti-punch-through structure is located between the source region and the drain region; Wherein, forming an anti-punch-through structure in the substrate includes: A plurality of anti-punch-through structures are formed in the substrate, the plurality of anti-punch-through structures are symmetrically distributed relative to the central axis of the gate, and the distance between the anti-punch-through structures and the first surface increases successively along the direction from the central axis to the source region or the drain region.

6. The manufacturing method according to claim 5, wherein: forming an anti-punch-through structure in the substrate, comprising: forming a patterned mask layer on the second surface of the substrate, wherein the mask layer exposes an area on the substrate; etching the substrate using the patterned mask layer as a mask to form an opening; The opening is filled with insulating material to form an anti-punch-through structure.

7. The manufacturing method according to claim 5, wherein: The anti-punch-through structure is T-shaped, and the width of the third surface of the anti-punch-through structure is greater than the width of the fourth surface.

8. The manufacturing method according to claim 5, wherein: A distance between the third surface of the anti-punch-through structure and the first surface of the substrate is greater than 50 angstroms.

9. A memory, characterized in that: A semiconductor device comprising any one of claims 1 to 4.

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