A RISER card and its configuration method, device, and readable storage medium

Abstract

The present application discloses a RISER card and its configuration method, device, and readable storage medium, relating to the field of electronic technology. Since the RISER card provided by the present application introduces a DIP switch and is connected to a PCA9546 chip and multiple PCA9555 chips, it can receive the motherboard information sent by the motherboard connector, and according to the motherboard information, control the bandwidth in the bandwidth allocation circuit, control the PCA9555 chip to read the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface, confirm the PORT of the CPU of the motherboard, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard, so as to achieve corresponding adaptation and identification for motherboards with any bandwidth and silk screen at the same time, greatly improving the applicability.

Description

Technical Field

[0001] The present application relates to the field of electronic technologies, and particularly to a RISER card, a configuration method and device thereof, and a readable storage medium. Background Art

[0002] In recent years, with the development of electronic technologies, the applications of servers and motherboards have increased. In the field of servers, a board card used to connect to a Peripheral Component Interconnect Express (PCIE) device is generally called a RISER card. The RISER card is connected to the motherboard upstream and to the PCIE device downstream.

[0003] Currently, separate RISER cards are designed for each server. During project testing, there may be a situation where the RISER card has not been produced yet when the functions of the PCIE device need to be tested, and testing can only be carried out after the RISER card is produced, which greatly reduces the testing efficiency. Moreover, the bandwidth allocation scheme and the silkscreen identification scheme defined by the motherboard for the RISER card are inconsistent in each project, resulting in non-interoperability between RISER cards of different projects, and the development efficiency is reduced due to the low adaptability of the RISER card.

[0004] In view of the above technologies, it is an urgent problem for those skilled in the art to find a RISER card with higher adaptability. Summary of the Invention

[0005] The purpose of the present application is to provide a RISER card to facilitate solving the problem that due to the inconsistent bandwidth allocation scheme and silkscreen identification scheme defined by the motherboard for the RISER card in each project, the RISER cards between different projects cannot be interoperable, and the development efficiency is reduced due to the low adaptability of the RISER card.

[0006] To solve the above problems, the present application provides a RISER card, including: a motherboard connector, a PCIE interface, a bandwidth allocation circuit, and further including: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips;

[0007] The motherboard connector is connected to the motherboard and is used to implement communication between the RISER card and the motherboard;

[0008] The PCIE interface is used to connect to the PCIE device and is used to implement communication between the RISER card and the PCIE device;

[0009] The bandwidth allocation circuit is connected to the motherboard connector, and the DIP switch is connected to the motherboard connector and the bandwidth allocation circuit, and is configured to receive the motherboard information sent by the motherboard connector and control the bandwidth in the bandwidth allocation circuit according to the motherboard information.

[0010] The PCA9546 chip is connected to multiple PCA9555 chips. The PCA9546 chip is configured to control the PCA9555 chips to read the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface, confirm the PORT of the CPU of the motherboard, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard.

[0011] Preferably, the RISER card includes two X16 PCIE interfaces.

[0012] Preferably, the motherboard connector includes: bonding wires, an MCIO connector, and a gold finger connector;

[0013] The bonding wires, the MCIO connector, and the gold finger connector are all disposed on the edge of the RISER card and are used to connect to different motherboards.

[0014] Preferably, it further includes: a CPLD;

[0015] The CPLD is connected to the PCIE interface, and the 9555 chip is controlled by the 9546 chip to obtain the current position of the RISER card.

[0016] Preferably, the CPLD is configured to obtain the control right of the RISER card by switching the I2C MUX according to the SEL.

[0017] Preferably, it further includes: an alarm device:

[0018] The alarm device is connected to the PCIE interface and is configured to give an alarm when it receives that the PCIE device is not compatible with the RISER card.

[0019] To solve the above problems, this application also includes a method for configuring a RISER card, which is applied to a RISER card including a PCIE interface, a bandwidth allocation circuit, and further including: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The motherboard connector of the RISER card is connected to the motherboard. The PCIE interface is used to connect to a PCIE device. The bandwidth allocation circuit is connected to the motherboard connector, and the DIP switch is connected to the motherboard connector and the bandwidth allocation circuit. The PCA9546 chip is connected to multiple PCA9555 chips. The method includes;

[0020] Obtain the corresponding configured bandwidth of the motherboard, and control the DIP switch according to the configured bandwidth so that the bandwidth allocation circuit adapts to the configured bandwidth of the motherboard;

[0021] Control the PCA9555 chip to read the position information of the RISER card and the CPU+VPPADDR information corresponding to the PCIE interface;

[0022] Confirm the PORT of the CPU of the motherboard, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard.

[0023] To solve the above problems, this application also provides a RISER card configuration device, which is applied to a RISER card including a PCIE interface, a bandwidth allocation circuit, and further including: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The motherboard connector of the RISER card is connected to the motherboard. The PCIE interface is used to connect to a PCIE device. The bandwidth allocation circuit is connected to the motherboard connector, and the DIP switch is connected to the motherboard connector and the bandwidth allocation circuit. The PCA9546 chip is connected to multiple PCA9555 chips. The device includes:

[0024] An acquisition module, configured to obtain the corresponding configured bandwidth of the motherboard, and control the DIP switch according to the configured bandwidth so that the bandwidth allocation circuit adapts to the configured bandwidth of the motherboard;

[0025] A control module, configured to control the PCA9555 chip to read the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface;

[0026] A confirmation module, configured to confirm the PORT of the CPU of the motherboard, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard.

[0027] To solve the above problems, the present application also provides a RISER card configuration device, including a memory for storing a computer program;

[0028] a processor for implementing the steps of the RISER card configuration method as described above when executing the computer program.

[0029] To solve the above problems, the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the RISER card configuration method as described above.

[0030] The RISER card provided by the present application includes a PCIE interface, a bandwidth allocation circuit, and further includes: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The motherboard connector of the RISER card is connected to the motherboard. The PCIE interface is used to connect to a PCIE device. The bandwidth allocation circuit is connected to the motherboard connector, and the DIP switch is connected to the motherboard connector and the bandwidth allocation circuit. The PCA9546 chip and multiple PCA9555 chips are connected. Compared with the previous dedicated RISER cards, the RISER card provided by this solution can, by introducing a DIP switch and connecting a PCA9546 chip and multiple PCA9555 chips, receive the motherboard information sent by the motherboard connector, and according to the motherboard information, control the bandwidth in the bandwidth allocation circuit, control the PCA9555 chip to read the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface, confirm the PORT of the CPU of the motherboard, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard, so as to simultaneously achieve corresponding adaptation and identification for motherboards with arbitrary bandwidth and silk screen, greatly improving the applicability.

[0031] The RISER card configuration method, device, and readable storage medium provided by the present application correspond to the above-mentioned RISER card, so the beneficial effects are the same as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0033] Figure 1 It is a structural diagram of a RISER card provided for an embodiment of the present application;

[0034] Figure 2Flowchart of a method for configuring a RISER card provided by an embodiment of the present application;

[0035] Figure 3 Schematic diagram of a device for configuring a RISER card provided by an embodiment of the present application;

[0036] Figure 4 Structural diagram of a device for configuring a RISER card provided by another embodiment of the present application. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0038] The core of the present application is to provide a method, device and readable storage medium for configuring a RISER card, so as to solve the problem that the bandwidth allocation scheme and silkscreen identification scheme definition of the RISER card by the motherboard in each project are inconsistent, resulting in non-interoperability between RISER cards in different projects, and reducing the development efficiency due to the low adaptability of the RISER card.

[0039] In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0040] RISER Figure 1 Structural diagram of a RISER card provided by an embodiment of the present application. As Figure 1 shown, the RISER card includes: a motherboard connector 1, a PCIE interface 2, a bandwidth allocation circuit 3, and further includes: a dip switch 4, a PCA9546 chip 5, and multiple PCA9555 chips 6;

[0041] The motherboard connector 1 is connected to the motherboard and is used to implement communication between the RISER card and the motherboard;

[0042] The PCIE interface 2 is used to connect to a PCIE device and is used to implement communication between the RISER card and the PCIE device;

[0043] The bandwidth allocation circuit 3 is connected to the motherboard connector 1, and the dip switch 4 is connected to the motherboard connector 1 and the bandwidth allocation circuit 3, and is used to receive the motherboard information sent by the motherboard connector 1 and control the bandwidth in the bandwidth allocation circuit 3 according to the motherboard information;

[0044] The PCA9546 chip 5 is connected to multiple PCA9555 chips 6. The PCA9546 chip 5 is used to control the PCA9555 chips 6 to read the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface 2, confirm the PORT of the CPU on the motherboard, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface 2 to the motherboard.

[0045] It should be noted that a RISER is a PCI-E adapter card. PCI- means interface, which can be understood as an expansion card or an adapter card. A pcieRISERCard refers to a functional expansion card or adapter card inserted into a PCI-E interface, and it is a new generation of bus interface. The motherboard is the mainboard of a computer chassis, also known as the mainboard, system board, or motherboard. It is divided into two types: commercial motherboards and industrial motherboards. It is installed inside the chassis and is one of the most basic and important components of a microcomputer. The motherboard is generally a rectangular circuit board on which the main circuit systems of the computer are installed. Generally, there are components such as a BIOS chip, an I / O control chip, keyboard and panel control switch interfaces, indicator light connectors, expansion slots, and DC power supply connectors for the motherboard and expansion cards.

[0046] Bandwidth usually refers to the frequency band width occupied by a signal. When used to describe a channel, bandwidth refers to the maximum frequency band width of a signal that can effectively pass through the channel. For analog signals, bandwidth is also called frequency width and is measured in hertz (Hz). For example, the signal bandwidth of an analog voice telephone is 3400 Hz, and the bandwidth of a PAL-D TV channel is 8 MHz (including the guard band). For digital signals, bandwidth refers to the amount of data that a link can pass through per unit time. For example, the bandwidth of the B channel of ISDN is 64 Kbps. Since the transmission of digital signals is completed through the modulation of analog signals, to distinguish from analog bandwidth, the bandwidth of digital channels is generally directly described by the baud rate or symbol rate. Bandwidth is a core concept in fields such as information theory, radio, communication, signal processing, and spectroscopy.

[0047] A PORT is an interface through which data is transferred between a computer and other devices (such as printers, mice, keyboards, or monitors), between networks, or between directly connected computers. In this embodiment, no specific limitations are imposed on the components on the motherboard of the computer itself. It can be understood that for the Central Processing Unit (CPU), it is one of the main devices of an electronic computer and a core component in a computer. Its main function is to interpret computer instructions and process data in computer software. All operations in the computer are the responsibility of the CPU to read instructions, decode instructions, and execute instructions. The CPU is installed on the motherboard, so the corresponding operations are completed by the CPU. In this embodiment, no specific limitations are imposed on the types and quantities of electronic components and other specific parameters.

[0048] The PCA9546 chip 5 is used to convert multiple I2C (Inter-Integrated Circuit) signals into one I2C signal. The 9555 is used to read the CPU signal from a specific interface, so that the CPU signal can be sent to the Baseboard Management Controller (BMC) based on the position of the RISER card and the CPU signal in the motherboard, which is beneficial to the reception of the PCIE interface 2 signal. Therefore, there is a fixed binding relationship for the PCIE SLOT-MCIO-9555 (CPU+VPP ADDR) hardware on the RISER card; the Location ID is defined and transmitted from the MB to the RISER card through the I2C Cable and connected to the 9555 under the 9546CH0 of the RISER card; there is an I2C analog switch MUX on the motherboard. When the AC is powered on, the Complex Programmable Logic Device (CPLD) obtains control by switching the I2C MUX through the select device (SEL), obtains the position of the current RISER card (left, middle, right) by reading the 9555 under the 9546CH0 of the RISER card, obtains the CPU+VPP ADDR corresponding to the PCIE SLOT0 by reading the 9555 under the 9546CH1 of the RISER card, and then determines the PORT of the CPU corresponding to the PCIE SLOT0; and stores it in the CPLD. The BIOS obtains the corresponding information by reading the CPLD.

[0049] The RISER card provided in this embodiment includes a PCIE interface 2, a bandwidth allocation circuit 3, and also includes: a dip switch 4, a PCA9546 chip 5 and a plurality of PCA9555 chips. The mainboard connector 1 of the RISER card is connected to the mainboard, the PCIE interface 2 is used to connect the PCIE device, the bandwidth allocation circuit 3 is connected to the mainboard connector 1, and the dip switch 4 is connected to the mainboard connector 1 and the bandwidth allocation circuit 3, and the PCA9546 chip 5 is connected to the plurality of PCA9555 chips. Compared with the previous dedicated RISER card, the RISER card provided by the present solution can realize the motherboard information sent by the motherboard connector 1 by introducing the DIP switch 4 and the PCA9546 chip 5 and the connection of multiple PCA9555 chips, and can control the bandwidth in the bandwidth allocation circuit 3 according to the motherboard information, control the PCA9555 chip to read the location information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface 2, confirm the PORT of the CPU of the motherboard, and send the location information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface 2 to the motherboard, so as to achieve the corresponding adaptation and identification for the motherboard with any bandwidth and silk screen at the same time, and greatly improve the applicability.

[0050] The specific structure of the riser card is not limited in the above embodiment, and a preferred solution is provided here. The riser card includes two X16 PCIE interfaces 2.

[0051] The motherboard connector 1 is not limited in the above embodiment, and a preferred solution is provided here. The motherboard connector 1 includes: a welding wire, an MCIO connector, and a gold finger connector;

[0052] The welding wire is a low-voltage AC rubber-sheathed cable output by the welding machine. It carries a large current. Generally, the smallest cable must be more than 10 square meters to meet the needs of welding current. It is commonly known as welding wire. MCIO cable assembly connector is a component that electronic engineering technicians often come into contact with. It is used to build a bridge of communication between blocked or isolated circuits in the circuit, so that the current can flow and the circuit can achieve the predetermined function. Gold finger (connecting finger) is computer hardware such as (between the memory slots of the memory stick, the graphics card and the graphics card slot, etc.), all signals are transmitted through the gold finger. The gold finger is composed of many golden conductive contacts. Because its surface is gold-plated and the conductive contacts are arranged like fingers, it is called "gold finger". The above three are the three commonly used connection methods in the motherboard, so 3 different connectors are set based on the above three connection methods.

[0053] The bonding wires, MCIO connectors, and gold finger connectors are all arranged on the edge of the RISER card and are used to connect to different motherboards. Since the types of motherboards are different, for the motherboard connector 1, different connectors need to be set to ensure compatibility with different motherboards, thereby further improving the adaptability of the RISER card.

[0054] Considering the convenience of communication, a preferred solution is provided here. The RISER card further includes: CPLD;

[0055] The CPLD is connected to the PCIE interface 2, and controls the 9555 chip through the 9546 chip to obtain the current position of the RISER card.

[0056] Preferably, the CPLD is used to obtain the control right of the RISER card by switching the I2C MUX according to SEL.

[0057] Complex Programmable Logic Device (CPLD) is a device developed from PAL and GAL devices. Relatively speaking, it has a large scale and a complex structure, belonging to the scope of large-scale integrated circuits. It is a digital integrated circuit in which users can construct logic functions according to their respective needs. Its basic design method is to generate the corresponding target files by means of schematic diagrams, hardware description languages, etc. with the help of an integrated development software platform, and transfer the code to the target chip through a download cable ("in-system" programming) to implement the designed digital system.

[0058] It should be noted that the I2C bus supports any IC production process. The two-wire - serial data and serial clock lines transfer information between devices connected to the bus. Each device has a unique address identification (whether it is a microcontroller - single-chip microcomputer, LCD driver, memory, or keyboard interface), and can act as a transmitter or receiver (determined by the function of the device). Obviously, the LCD driver is just a receiver, while the memory can both receive and send data. In addition to transmitters and receivers, devices can also be regarded as masters or slaves when performing data transmission.

[0059] By introducing the control of the CPLD for system communication, the accuracy and speed of information transfer of the RISER card are guaranteed.

[0060] Considering the settings of the RISER card itself and the safety issues of compatibility, a preferred solution is provided here, which also includes; an alarm device:

[0061] The alarm device is connected to the PCIE interface 2 and is used to give an alarm when it receives that the PCIE device is incompatible with the RISER card.

[0062] It should be noted that in this embodiment, the specific structure of the alarm device in the RISER card is not limited. It can be understood that generally for the compatibility problem of the RISER card, the information can be directly sent to the monitoring terminal of the corresponding user, or external devices such as buzzers and warning lights can be used.

[0063] Figure 2 The flowchart of a RISER card configuration method provided by an embodiment of this application is applied to a RISER card including a PCIE interface, a bandwidth allocation circuit, and further including: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The main board connector of the RISER card is connected to the main board. The PCIE interface is used to connect to the PCIE device. The bandwidth allocation circuit is connected to the main board connector, and the DIP switch is connected to the main board connector and the bandwidth allocation circuit. The PCA9546 chip and multiple PCA9555 chips are connected, as Figure 2 shown, the method includes;

[0064] S10: Obtain the corresponding configured bandwidth of the main board, and control the DIP switch according to the configured bandwidth so that the bandwidth allocation circuit adapts to the configured bandwidth of the main board;

[0065] S11: Control the PCA9555 chip to read the position information of the RISER card and the CPU+VPPADDR information corresponding to the PCIE interface;

[0066] S12: Confirm the PORT of the CPU of the main board, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the main board.

[0067] Since the method provided in this embodiment corresponds to the above RISER card, the specific beneficial effects can be seen in the above RISER card device part.

[0068] The RISER card configuration method provided in this embodiment is applied to a RISER card including a PCIE interface, a bandwidth allocation circuit, and further including: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The motherboard connector of the RISER card is connected to the motherboard. The PCIE interface is used to connect to a PCIE device. The bandwidth allocation circuit is connected to the motherboard connector, and the DIP switch is connected to the motherboard connector and the bandwidth allocation circuit. The PCA9546 chip and multiple PCA9555 chips are connected to the RISER card. Compared with the previous dedicated RISER cards, the RISER card provided by this solution can, due to the introduction of the DIP switch, the PCA9546 chip, and the connection of multiple PCA9555 chips, receive the motherboard information sent by the motherboard connector, and according to the motherboard information, control the bandwidth in the bandwidth allocation circuit, control the PCA9555 chip to read the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface, confirm the PORT of the CPU of the motherboard, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard, so as to achieve corresponding adaptation and identification for motherboards with arbitrary bandwidth and silk screen at the same time, greatly improving the applicability.

[0069] Figure 3 The following is a schematic diagram of a RISER card configuration device provided by an embodiment of the present application. As Figure 3 shown, it is applied to a RISER card including a PCIE interface, a bandwidth allocation circuit, and further including: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The motherboard connector of the RISER card is connected to the motherboard. The PCIE interface is used to connect to a PCIE device. The bandwidth allocation circuit is connected to the motherboard connector, and the DIP switch is connected to the motherboard connector and the bandwidth allocation circuit. The PCA9546 chip and multiple PCA9555 chips are connected. The device includes:

[0070] An acquisition module 10, configured to acquire the corresponding configured bandwidth of the motherboard, and control the DIP switch according to the configured bandwidth so that the bandwidth allocation circuit adapts to the configured bandwidth of the motherboard;

[0071] A control module 11, configured to control the PCA9555 chip to read the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface;

[0072] A confirmation module 12, configured to confirm the PORT of the CPU of the motherboard, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard.

[0073] Since the embodiments in the method section correspond to those in the method section, for the embodiments of the device section and their corresponding beneficial effects, please refer to the description of the embodiments in the method section, which will not be elaborated here.

[0074] The RISER card configuration device provided in this application is applied to a RISER card including a PCIE interface, a bandwidth allocation circuit, and further includes: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The main board connector of the RISER card is connected to the main board. The PCIE interface is used to connect to a PCIE device. The bandwidth allocation circuit is connected to the main board connector, and the DIP switch is connected to the main board connector and the bandwidth allocation circuit. The PCA9546 chip and multiple PCA9555 chips are connected to the RISER card. Compared with the previous dedicated RISER cards, the RISER card provided in this solution can, by introducing a DIP switch, a PCA9546 chip, and multiple PCA9555 chips, receive the main board information sent by the main board connector, and according to the main board information, control the bandwidth in the bandwidth allocation circuit, control the PCA9555 chip to read the position information of the RISER card and the CPU+VPPADDR information corresponding to the PCIE interface, confirm the PORT of the CPU of the main board, and send the position information of the RISER card and the CPU+VPPADDR information corresponding to the PCIE interface to the main board, so as to achieve corresponding adaptation and identification for main boards with arbitrary bandwidth and silk screen at the same time, greatly improving the applicability.

[0075] In the above embodiments, the RISER card configuration method has been described in detail. This application also provides corresponding embodiments of the RISER card configuration device. It should be noted that this application describes the embodiments of the device section from two perspectives, one is from the perspective of functional modules, and the other is from the perspective of hardware.

[0076] Figure 4 The structure diagram of the RISER card configuration device provided in another embodiment of this application is as Figure 4 shown. The RISER card configuration device includes: a memory 20 for storing computer programs;

[0077] a processor 21 for implementing the steps of the RISER card configuration method as mentioned in the above embodiments when executing the computer programs.

[0078] The RISER card configuration device provided in this embodiment may include, but is not limited to, smart phones, tablet computers, laptop computers, or desktop computers, etc.

[0079] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one hardware form of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the Central Processing Unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a Graphics Processing Unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may further include an Artificial Intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0080] The memory 20 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 20 may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201. After the computer program is loaded and executed by the processor 21, it can implement the relevant steps of the RISER card configuration method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may further include an operating system 202 and data 203, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the RISER card configuration method.

[0081] In some embodiments, the RISER card configuration device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0082] Those skilled in the art can understand that Figure 4 the structure shown in

[0083] The RISER card configuration device provided by the embodiments of the present application includes a memory and a processor. When the processor executes the program stored in the memory, the following method can be implemented: the RISER card configuration method involved in the above embodiments.

[0084] Since the embodiments in the device part correspond to the embodiments in the method part, for the embodiments in the device part and their corresponding beneficial effects, please refer to the description of the embodiments in the method part, which will not be elaborated here for the time being.

[0085] The RISER card configuration device provided by the present application is applied to a RISER card including a PCIE interface, a bandwidth allocation circuit, and further includes: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The main board connector of the RISER card is connected to the main board. The PCIE interface is used to connect to a PCIE device. The bandwidth allocation circuit is connected to the main board connector, and the DIP switch is connected to the main board connector and the bandwidth allocation circuit. The RISER card is connected with the PCA9546 chip and multiple PCA9555 chips. Compared with the previous dedicated RISER cards, the RISER card provided by this solution can, by introducing a DIP switch and connecting the PCA9546 chip and multiple PCA9555 chips, receive the main board information sent by the main board connector, and according to the main board information, control the bandwidth in the bandwidth allocation circuit, control the PCA9555 chip to read the position information of the RISER card and the CPU+VPPADDR information corresponding to the PCIE interface, confirm the PORT of the CPU of the main board, and send the position information of the RISER card and the CPU+VPPADDR information corresponding to the PCIE interface to the main board, so as to achieve corresponding adaptation and identification for motherboards with any bandwidth and silk screen at the same time, greatly improving the applicability.

[0086] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps recorded in the above method embodiments are implemented.

[0087] It can be understood that if the methods in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this application, in essence, or the parts that contribute to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs.

[0088] Since the embodiments of the readable storage medium part correspond to the embodiments of the method part, for the descriptions of the embodiments of the device part and their corresponding beneficial effects, please refer to the descriptions of the embodiments of the method part, and will not be elaborated here for the time being.

[0089] The readable storage medium provided by this application is applied to a RISER card that includes a PCIE interface, a bandwidth allocation circuit, and further includes: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The main board connector of the RISER card is connected to the main board. The PCIE interface is used to connect to a PCIE device. The bandwidth allocation circuit is connected to the main board connector, and the DIP switch is connected to the main board connector and the bandwidth allocation circuit. The RISER card is connected with the PCA9546 chip and multiple PCA9555 chips. Compared with the previous dedicated RISER cards, the RISER card provided by this solution can, due to the introduction of the DIP switch and the connection of the PCA9546 chip and multiple PCA9555 chips, receive the main board information sent by the main board connector, and according to the main board information, control the bandwidth in the bandwidth allocation circuit, control the PCA9555 chip to read the position information of the RISER card and the CPU+VPPADDR information corresponding to the PCIE interface, confirm the PORT of the CPU of the main board, and send the position information of the RISER card and the CPU+VPPADDR information corresponding to the PCIE interface to the main board, so as to simultaneously achieve corresponding adaptation and identification for main boards with arbitrary bandwidths and silk screens, greatly improving the applicability.

[0090] The above has introduced in detail a method, device, and computer-readable storage medium for RISER card configuration provided in this application. Each embodiment in the specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0091] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device including the element.

Claims

1. A RISER card, comprising: Motherboard connector, PCIE interface, bandwidth allocation circuit, characterized by further comprising: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips; The motherboard connector is connected to the motherboard and is used to realize communication between the RISER card and the motherboard; The PCIE interface is connected to a PCIE device and is used to realize communication between the RISER card and the PCIE device; The bandwidth allocation circuit is connected to the motherboard connector, and the DIP switch is connected to the motherboard connector and the bandwidth allocation circuit, and is used to receive motherboard information sent by the motherboard connector and control the bandwidth in the bandwidth allocation circuit according to the motherboard information; The PCA9546 chip is connected to multiple PCA9555 chips. The PCA9546 chip is used to control the PCA9555 chips to read the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface, confirm the PORT of the CPU of the motherboard, and send the position information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard.

2. The RISER card according to claim 1, wherein The RISER card includes two X16 PCIE interfaces.

3. The RISER card according to claim 2, characterized in that, The motherboard connector includes: bonding wires, an MCIO connector, and a gold finger connector; The bonding wires, the MCIO connector, and the gold finger connector are all arranged on the edge of the RISER card and are used to connect to different motherboards.

4. The RISER card according to claim 2, characterized in that, It further comprises: CPLD; The CPLD is connected to the PCIE interface, and the 9546 chip is used to control the 9555 chip to obtain the current position of the RISER card.

5. The RISER card according to claim 4, characterized in that, The CPLD is used to obtain the control right of the RISER card by switching the I2C MUX according to SEL.

6. The RISER card according to any one of claims 1 to 5, characterized in that It further comprises; an alarm device: The alarm device is connected to the PCIE interface and is used to give an alarm when it receives that the PCIE device is not compatible with the RISER card.

7. A method for configuring a RISER card, characterized in that, Applied to a RISER card including a PCIE interface, a bandwidth allocation circuit, further comprising: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The motherboard connector of the RISER card is connected to the motherboard, the PCIE interface is used to connect to a PCIE device, the bandwidth allocation circuit is connected to the motherboard connector, the DIP switch is connected to the motherboard connector and the bandwidth allocation circuit, and the PCA9546 chip is connected to multiple PCA9555 chips. The method includes; Obtain the corresponding configured bandwidth of the motherboard, and control the DIP switch according to the configured bandwidth so that the bandwidth allocation circuit adapts to the configured bandwidth of the motherboard; Control the PCA9555 chips to read the position information of the RISER card and the CPU+VPPADDR information corresponding to the PCIE interface; Confirm the PORT of the CPU on the motherboard, and send the location information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard.

8. A RISER card configuration device, characterized in that, Applied to a RISER card including a PCIE interface, a bandwidth allocation circuit, further comprising: a DIP switch, a PCA9546 chip, and multiple PCA9555 chips. The motherboard connector of the RISER card is connected to the motherboard. The PCIE interface is used to connect to a PCIE device. The bandwidth allocation circuit is connected to the motherboard connector, and the DIP switch is connected to the motherboard connector and the bandwidth allocation circuit. The PCA9546 chip is connected to multiple PCA9555 chips. The device includes: An acquisition module, configured to acquire the corresponding configured bandwidth of the motherboard, and control the DIP switch according to the configured bandwidth so that the bandwidth allocation circuit adapts to the configured bandwidth of the motherboard; A control module, configured to control the PCA9555 chip to read the location information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface; A confirmation module, configured to confirm the PORT of the CPU on the motherboard, and send the location information of the RISER card and the CPU+VPP ADDR information corresponding to the PCIE interface to the motherboard.

9. A RISER card configuration device, characterized in that, Including a memory for storing a computer program; A processor, configured to implement the steps of the RISER card configuration method as claimed in claim 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the RISER card configuration method as claimed in claim 8 are implemented.

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