Display panel, preparation method thereof and display device

Abstract

This invention provides a display panel, a method for manufacturing the same, and a display device. The display panel includes a light-emitting device layer and an array substrate. The array substrate includes a substrate layer, an insulating module, a first conductive layer, and a second conductive layer. The insulating module is disposed on the substrate layer. The first conductive layer and the second conductive layer are staggered within the insulating module. The first conductive layer includes a padding layer, the padding layer of which does not coincide with the orthographic projection of the second conductive layer on the substrate layer; or the substrate layer has a first groove on a surface facing the conductive structure, the first groove of which coincides with the orthographic projection of the second conductive layer on the substrate layer.

Description

Technical Field

[0001] This invention relates to the field of display devices, and in particular to a display panel, its manufacturing method, and a display device. Background Technology

[0002] Currently, in the design of OLED (Organic Light-Emitting Diode) display panels, the metal trace layer below the light-emitting area is patterned, resulting in steps and unevenness on the pixel electrode layer. This makes it impossible for the organic light-emitting devices located on the pixel electrode layer to have a uniform device thickness, thus causing uneven light emission and greatly reducing the luminous efficiency of the light-emitting devices. Summary of the Invention

[0003] The purpose of this invention is to provide a display panel and its preparation method, as well as a display device, to solve the technical problems in the prior art, such as uneven light emission and low luminous efficiency caused by the inconsistent thickness of organic light-emitting devices.

[0004] To achieve the above objectives, the present invention provides a display panel comprising a light-emitting device layer and an array substrate. The light-emitting device layer is provided with a plurality of light-emitting devices, and the light-emitting device layer is disposed on the array substrate.

[0005] The array substrate includes a substrate layer, an insulating module, a first conductive layer, and a second conductive layer. The insulating module is disposed on the substrate layer. The first conductive layer and the second conductive layer are staggered within the insulating module, with the first conductive layer located on the side of the second conductive layer closer to the substrate layer.

[0006] The first conductive layer includes a padding layer, the padding layer and the orthographic projection of the second conductive layer on the substrate layer do not coincide; or the substrate layer has a first groove on a surface facing the conductive structure, the first groove and the orthographic projection of the second conductive layer on the substrate layer coincide.

[0007] Further, the substrate layer includes a base layer, a light-shielding layer, and a buffer layer. The light-shielding layer is disposed on the base layer. The buffer layer is disposed on the base layer and covers the light-shielding layer. The first groove is disposed on a surface of the buffer layer away from the light-shielding layer. The active layer in the array substrate is disposed in the first groove.

[0008] Furthermore, the depth of the first groove is less than or equal to the thickness of the active layer.

[0009] Further, the second conductive layer includes a first electrode layer, a second electrode layer, and a wiring layer. The second electrode layer is located on one side of the first electrode layer. The wiring layer is located on the side of the second electrode layer away from the first electrode layer. The first electrode layer, the second electrode layer, and the wiring layer are disposed on the same plane in the insulating module and are electrically insulated from each other. The orthographic projection of the padding layer on the substrate layer is located on both sides of the wiring layer.

[0010] Further, the insulating module includes a gate insulating layer, an interphase dielectric layer, a passivation layer, and a planarization layer. The gate insulating layer is disposed on the substrate layer, and the first conductive layer is disposed on a surface of the gate insulating layer away from the active layer. The interphase dielectric layer is disposed on the substrate layer and covers the gate insulating layer and the first conductive layer, and the second conductive layer is disposed on a surface of the interphase dielectric layer away from the second conductive layer. The passivation layer is disposed on the interphase dielectric layer and covers the second conductive layer. The planarization layer is disposed on the passivation layer.

[0011] The interphase dielectric layer has a second groove on one surface facing the second conductive layer, and the second conductive layer is located in the second groove.

[0012] Furthermore, the gate insulating layer includes a first insulating layer and a second insulating layer. The first insulating layer is disposed on a surface of the active layer of the array substrate away from the substrate layer. The second insulating layer is disposed on the substrate layer and corresponds to the wiring layer in the second conductive layer.

[0013] The padding layer is disposed on a surface of the second insulating layer away from the substrate layer, or the second insulating layer is disposed in a first groove. The first conductive layer further includes a gate layer, which is disposed on a surface of the first insulating layer away from the active layer.

[0014] The present invention also provides a method for preparing a display panel, the method comprising the following steps: preparing a substrate layer; preparing a first conductive layer, a second conductive layer and an insulating module on the substrate layer to form an array substrate; and preparing a plurality of light-emitting devices on the array substrate to form a light-emitting device layer.

[0015] After the substrate layer is prepared, the method further includes the following steps: forming a first groove on the substrate layer, wherein the first groove coincides with the orthographic projection of the second conductive layer on the substrate layer; or forming a pad layer during the preparation of the first conductive layer, wherein the pad layer does not coincide with the orthographic projection of the second conductive layer on the substrate layer.

[0016] Furthermore, the step of preparing the substrate layer includes the following steps: forming a light-shielding layer on a base layer;

[0017] A buffer layer covering the light-shielding layer is formed on the base layer; the first groove is formed on a surface of the buffer layer away from the light-shielding layer.

[0018] The step after preparing the substrate layer includes the following step: forming an active layer in the first groove.

[0019] Further, the step of fabricating the first conductive layer, the second conductive layer, and the insulating module on the substrate layer includes the following steps: forming a gate insulating layer on the substrate layer; forming the first conductive layer on the gate insulating layer; forming an interphase dielectric layer covering the gate insulating layer and the first conductive layer on the substrate layer; forming the second conductive layer on the interphase dielectric layer; forming a passivation layer covering the second conductive layer on the interphase dielectric layer; and forming a planarization layer on the passivation layer.

[0020] After forming the interphase dielectric layer on the substrate, the method further includes the following steps: forming a second groove on a surface of the interphase dielectric layer facing the second conductive layer, and forming the second conductive layer in the second groove.

[0021] The present invention also applies to a display device, the display device comprising the display panel as described above.

[0022] The advantages of the present invention are: the display panel and its manufacturing method of the present invention improve the surface flatness of the array substrate by increasing the film layer to raise the recessed parts in the array substrate or by reducing the film layer thickness of the raised parts, thereby improving the problem of inconsistent surface height of the light-emitting devices caused by the unevenness of the surface of the array substrate, thereby improving the luminous efficiency of the light-emitting devices and increasing the display brightness of the display panel. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the layered structure of the display panel in Embodiment 1 of the present invention;

[0025] Figure 2 This is a schematic flowchart of the display panel manufacturing method in Embodiment 1 of the present invention;

[0026] Figure 3 This is a schematic diagram of the layered structure after the light-shielding layer is formed in step S10 of Embodiment 1 of the present invention;

[0027] Figure 4 This is a schematic diagram of the layered structure after the buffer layer is formed in step S10 of Embodiment 1 of the present invention;

[0028] Figure 5 This is a schematic diagram of the layered structure after the active layer is formed in step S20 of Embodiment 1 of the present invention;

[0029] Figure 6 This is a schematic diagram of the layered structure formed after the formation of the gate insulating layer and the first conductive layer in step S30 of Embodiment 1 of the present invention;

[0030] Figure 7 This is a schematic diagram of the layered structure after the formation of the interphase dielectric layer in step S40 of Embodiment 1 of the present invention;

[0031] Figure 8 This is a schematic diagram of the layered structure after the formation of the second conductive layer in step S50 of Embodiment 1 of the present invention;

[0032] Figure 9 This is a schematic diagram of the layered structure after the pixel limiting layer is formed in step S60 of Embodiment 1 of the present invention;

[0033] Figure 10 This is a schematic diagram of the layered structure of the display panel in Embodiment 2 of the present invention;

[0034] Figure 11 This is a schematic flowchart of the display panel manufacturing method in Embodiment 2 of the present invention;

[0035] Figure 12 This is a schematic diagram of the layered structure after the light-shielding layer is formed in step S10 of Embodiment 2 of the present invention;

[0036] Figure 13 This is a schematic diagram of the layered structure after the buffer layer is formed in step S10 of Embodiment 2 of the present invention;

[0037] Figure 14 This is a schematic diagram of the layered structure after the active layer is formed in step S20 of Embodiment 2 of the present invention;

[0038] Figure 15 This is a schematic diagram of the layered structure formed after the gate insulating layer and the first conductive layer are formed in step S30 of Embodiment 2 of the present invention;

[0039] Figure 16 This is a schematic diagram of the layered structure after the formation of the interphase dielectric layer in step S40 of Embodiment 2 of the present invention;

[0040] Figure 17 This is a schematic diagram of the layered structure after the formation of the second conductive layer in step S50 of Embodiment 2 of the present invention;

[0041] Figure 18 This is a schematic diagram of the layered structure after the pixel limiting layer is formed in step S60 of embodiment 2 of the present invention.

[0042] The components in the diagram are shown below:

[0043] Display panel 10; Array substrate 100;

[0044] Substrate 110; Base layer 111;

[0045] Light-shielding layer 112; First light-shielding layer 1121;

[0046] Second light-shielding layer 1122; Buffer layer 113;

[0047] First groove 1131; Active layer 120;

[0048] Insulating module 130; Gate insulating layer 131;

[0049] First insulating layer 1311; Second insulating layer 1312;

[0050] Interphase dielectric layer 132; First connecting hole 1321;

[0051] Second groove 1322; passivation layer 133;

[0052] Planarization layer 134; Second connecting hole 135;

[0053] First conductive layer 140; Gate layer 141;

[0054] First layer 142; Second conductive layer 150;

[0055] First electrode layer 151; Second electrode layer 152;

[0056] Trace layer 153; Pixel electrode layer 200;

[0057] Pixel confinement layer 300; Light-emitting device layer 400;

[0058] Light-emitting device 410. Detailed Implementation

[0059] The following description, with reference to the accompanying drawings, illustrates preferred embodiments of the present invention, demonstrating its implementability. These embodiments provide a complete overview of the invention for those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0060] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of components is appropriately exaggerated in some places in the drawings.

[0061] Furthermore, the following descriptions of the embodiments of the invention are made with reference to the accompanying illustrations, illustrating specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," and "side," are merely directional references to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of the invention, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0062] When a component is described as being "on" another component, the component may be placed directly on the other component; alternatively, an intermediate component may exist on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "installed to" or "connected to" another component, both can be understood as being directly "installed" or "connected" to, or indirectly "installed to" or "connected to" another component via an intermediate component.

[0063] Example 1

[0064] This invention provides a display device, which can be an OLED display device, including a display panel 10 for providing a display image. The display device can be any display device with display functionality, such as a mobile phone, laptop, or tablet computer.

[0065] like Figure 1 As shown, the display panel 10 includes an array substrate 100 and a light-emitting device layer 400.

[0066] The array substrate 100 includes a substrate layer 110, an insulating module 130, an active layer 120, a first conductive layer 140, and a second conductive layer 150. The insulating module 130 includes a gate insulating layer 131, an interphase dielectric layer 132, a passivation layer 133, and a planarization layer 134.

[0067] The substrate layer 110 includes a base layer 111, a light-shielding layer 112, and a buffer layer 113.

[0068] The base layer 111 is an insulating base layer, which can be a rigid glass plate, a quartz plate, or a flexible polyimide film layer. When the base layer 111 is a flexible film layer, the display panel 10 can achieve flexible bending display.

[0069] The light-shielding layer 112 is disposed on one surface of the substrate 111, and has a first light-shielding layer 1121 and a second light-shielding layer 1122. The first light-shielding layer 1121 corresponds to the active layer 120, and the orthographic projection of the first light-shielding layer 1121 and the active layer 120 on the substrate 110 coincides. The second light-shielding layer corresponds to the wiring layer 153 of the second conductive layer 150, and the orthographic projection of the second light-shielding layer 1122 and the wiring layer 153 on the substrate 110 coincide. The light-shielding layer 112 is made of one or more metallic materials and is used to reflect external light incident from one side of the substrate 111 to prevent external light from affecting the operation of the active layer 120.

[0070] The buffer layer 113 is disposed on the base layer 111 and covers the exposed surface of the light-shielding layer 112. The buffer layer 113 is made of insulating inorganic material, which is used to insulate and protect the light-shielding layer 112 and the active layer 120, and can also buffer and protect the structure of the display panel 10, reduce the damage caused by impact during transportation, and at the same time isolate external water and oxygen intrusion.

[0071] The active layer 120 is disposed on a surface of the buffer layer 113 away from the light-shielding layer 112, and it can be made of semiconductor materials such as low-temperature polycrystalline silicon and metal oxide.

[0072] The gate insulating layer 131 is disposed on the substrate layer 110 and includes a first insulating layer 1311 and a second insulating layer 1312. The first insulating layer 1311 is disposed on a surface of the active layer 120 away from the buffer layer 113, and its width is smaller than the width of the active layer 120 to expose both ends of the active layer 120. The second insulating layer 1312 is disposed on the substrate layer 110 and corresponds to the second light-shielding layer 1122, that is, it also corresponds to the wiring layer 153 in the second conductive layer 150. At the same time, the width of the second insulating layer 1312 is greater than the width of the second light-shielding layer 1122 and the wiring layer 153, that is, the orthographic projection of the second insulating layer 1312, the second light-shielding layer 1122 and the wiring layer 153 on the substrate layer 110 coincides. Preferably, the thickness of the second insulating layer 1312 is equal to the sum of the thicknesses of the active layer 120 and the first insulating layer 1311, so that the top surface of the second insulating layer 1312 away from the substrate layer 110 and the top surface of the first insulating layer 1311 away from the substrate layer 110 are in the same plane, thereby reducing the step difference between the first insulating layer 1311 and the second insulating layer 1312.

[0073] The first conductive layer 140 includes a gate layer 141 and at least two pad layers 142. The gate layer 141 is disposed on a surface of the first insulating layer 1311 away from the active layer 120. The pad layers 142 are disposed on a surface of the second insulating layer 1312 away from the buffer layer 113, and the two pad layers 142 are respectively located at both ends of the second insulating layer 1312.

[0074] The interphase dielectric layer 132 is disposed on the buffer layer 113 and covers the exposed surfaces of the active layer 120, the gate insulating layer 131 and the first conductive layer 140.

[0075] The second conductive layer 150 is disposed on a surface of the interphase dielectric layer 132 away from the buffer layer 113, and includes a first electrode layer 151, a second electrode layer 152, and a wiring layer 153. The first electrode layer 151 and the second electrode layer 152 are respectively located at both ends of the active layer 120, and the bottom surfaces of the first electrode layer 151 and the second electrode layer 152 each have a connecting portion, which passes through the interphase dielectric layer 132 and is electrically connected to the active layer 120. The wiring layer 153 is located on the side of the second electrode layer 152 away from the first electrode layer 151, and corresponds to the second insulating layer 1312 and the second light-shielding layer 1122.

[0076] Specifically, the insulating module 130 is generally made of insulating inorganic materials, such as silicon oxide and silicon nitride. The first conductive layer 140 and the second conductive layer 150 are made of metallic materials with excellent conductivity.

[0077] When a current or voltage is applied to the gate layer 141, it generates an electric field. This electric field induces charges on the surface of the active layer 120, changing the width of the channel portion in the active layer 120. This achieves the purpose of controlling the current in the first electrode layer 151 and the second electrode layer 152, thereby driving each light-emitting device 410 in the display panel 10.

[0078] The light-emitting device layer 400 is disposed on the planarization layer 134 and has a plurality of light-emitting devices 410. For example... Figure 1 As shown, the light-emitting device 410 is electrically connected to the second electrode layer 152 in the array substrate 100 via the pixel electrode layer 200. Specifically, the pixel electrode layer 200 is disposed on a surface of the planarization layer 134 away from the passivation layer 133, and its bottom surface also has a connecting portion. The connecting portion of the pixel electrode layer 200 passes through the planarization layer 134 and the passivation layer 133 in sequence and contacts and is electrically connected to the upper surface of the second electrode layer 152.

[0079] The display panel 10 further includes a pixel defining layer 300, which is disposed on the planarization layer 134 and the pixel electrode layer 200. The pixel defining layer 300 has multiple openings that penetrate the pixel defining layer 300 and correspond to the pixel electrode layer 200, thus exposing the upper surface of the pixel defining layer 300. Each opening is provided with a light-emitting device 410, which is electrically connected to the pixel electrode layer 200 within the opening.

[0080] The orthographic projection of the pixel electrode layer 200 on the substrate layer 110 coincides with the orthographic projections of the first conductive layer 140 and the second conductive layer 150 on the substrate layer 110. Since the second conductive layer 150 has multiple conductive structures, the surface of the array substrate 100 is uneven, which also makes it impossible for the surface height of the pixel electrode layer 200 and the light-emitting device 410 on the array substrate 100 to be uniform.

[0081] Furthermore, the orthographic projections of the wiring layer 153 and the padding layer 142 on the substrate layer 110 do not coincide, and the orthographic projections of the two padding layers 142 are respectively located on the side where the orthographic projection of the wiring layer 153 is far from the orthographic projection of the second electrode layer 152, and between the orthographic projections of the wiring layer 153 and the second electrode layer 152. This allows the padding layer 142 to correspond to the gap between two adjacent conductive structures in the second conductive layer 150, increasing the total film thickness of the array substrate 100 at the gap in the second conductive layer 150. This reduces the step difference caused by the patterning of the conductive structures in the second conductive layer 150, reducing the step difference between the second conductive layer 150 and the interphase dielectric layer 132 to below 200 nanometers. This improves the problem of uneven light emission caused by the inability to unify the film surface height of the light-emitting device 410 due to the step difference, thereby improving the light emission efficiency of the light-emitting device 410.

[0082] This invention also provides a method for manufacturing a display panel 10, used to manufacture the display panel 10 as described above. The manufacturing process of the method is as follows: Figure 2 As shown, it includes steps S11-S17.

[0083] Step S11) Prepare substrate layer 110:

[0084] A layer of metallic material, either molybdenum or copper, is deposited on a glass substrate 111 using physical vapor deposition. The diffusion barrier layer can be made of a molybdenum-titanium alloy, molybdenum, tantalum, or other materials with a work function similar to copper.

[0085] The metal material layer is patterned using photolithography to form a shape such as... Figure 3 The first light-shielding layer 1121 and the second light-shielding layer 1122 are shown in the figure.

[0086] Furthermore, a diffusion barrier layer and an etch barrier layer can be deposited on the metal material layer using physical vapor deposition. The etch barrier layer can be made of metal oxides such as indium tin oxide or indium gallium zinc oxide. The light-shielding layer 112 and the diffusion barrier layer can use a hydrogen peroxide-based etchant as the patterning etchant, and the etch barrier layer can use an oxalic acid-based etchant as the patterning etchant.

[0087] An inorganic material is deposited on the base layer 111 by chemical vapor deposition to form a layer such as Figure 4 The buffer layer 113 shown.

[0088] The base layer 111, the first light-shielding layer 1121, the second light-shielding layer 1122, and the buffer layer 113 are combined to form the substrate layer 110.

[0089] Step S12) Forming the active layer 120:

[0090] A semiconductor material layer is deposited using physical vapor deposition (PVD). The semiconductor material can be a metal oxide such as indium tin oxide (ITI) or indium gallium zinc oxide (IGZ). The semiconductor material layer is then patterned using photolithography to form a shape such as… Figure 5 The active layer 120 shown is described above. The active layer 120 may use an oxalic acid-based etchant as the patterning agent.

[0091] Step S13) Forming a gate insulating layer 131 and a first conductive layer 140, and forming a pad layer 142 in the first conductive layer 140:

[0092] An inorganic material layer covering the active layer 120 is deposited on the substrate layer 110 using chemical vapor deposition, and a metal material layer is deposited on a surface of the inorganic material layer away from the active layer 120. The inorganic material layer and the metal material layer are patterned using photolithography, such as... Figure 6 As shown, a first insulating layer 1311 and a second insulating layer 1312 are formed in the gate insulating layer 131, and a gate layer 141 located on the first insulating layer 1311 and a pad layer 142 located on the second insulating layer 1312 are formed in the first conductive layer 140. During the patterning process of the gate layer 141, the active layer 120 is made conductive by plasma treatment after photoresist stripping of the gate layer 141.

[0093] Step S14) Forming an interphase dielectric layer 132:

[0094] An inorganic material is deposited on the substrate 110 using a chemical vapor deposition method to form the interphase dielectric layer 132. The interphase dielectric layer 132 is then patterned using a photolithography process to form a shape as shown below. Figure 7 The first connection hole 1321 shown penetrates the interphase dielectric layer 132 and is located at both ends of the active layer 120. The interphase dielectric layer 132 can be dry-etched using an oxidizing gas such as a fluorine-based solvent.

[0095] Step S15) Forming the second conductive layer 150:

[0096] A metal material layer filling the first connection hole 1321 is deposited on the interphase dielectric layer 132 using physical vapor deposition. The metal material layer is a stacked structure of a molybdenum-titanium alloy layer and a copper metal layer. The metal material layer is patterned using photolithography, such as... Figure 8 As shown, a first electrode layer 151, a second electrode layer 152, and a wiring layer 153 are formed in the second conductive layer 150. The second conductive layer 150 can be etched using a hydrogen peroxide-based etchant as a patterning etchant.

[0097] Furthermore, in step S14, the buffer layer 113 can be patterned again by photolithography to form a deep hole that passes through the interphase dielectric layer 132 and the buffer layer 113 in sequence. At the same time as step S15, the metal material is deposited in the deep hole so that the first electrode layer 151 or the second electrode layer 152 can be electrically connected to the light-shielding layer 112, thereby avoiding the floating gate effect of the light-shielding layer 112.

[0098] Furthermore, when the dry etching barrier layer on the light-shielding layer 112 is indium gallium zinc oxide, dry etching plasma is required to simultaneously conduct the etching barrier layer to ensure that the charge in the first electrode layer 151 in the subsequent second conductive layer 150 is transferred to the light-shielding layer 112, thereby compensating for the threshold voltage (Vth).

[0099] Step S16) Forming a passivation layer 133, a planarization layer 134, a pixel electrode layer 200, and a pixel defining layer 300:

[0100] The passivation layer 133 and the planarization layer 134 are formed on the interphase dielectric layer 132 by deposition. The passivation layer 133 and the planarization layer 134 are patterned to form a second connecting hole 135 penetrating the planarization layer 134 and the passivation layer 133.

[0101] A conductive material is deposited on the planar layer 134 to fill the second connection hole 135, and the conductive material is patterned to form the pixel electrode layer 200.

[0102] An insulating material is coated onto the planarization layer 134 and the pixel electrode layer 200, and then patterned to form a shape as shown. Figure 9 The pixel-defining layer 300 shown has multiple openings.

[0103] Step S17) Forming the light-emitting device layer 400:

[0104] Organic material layers such as a hole injection layer, a hole transport layer, and a light-emitting layer are printed in the opening using inkjet printing. An electron transport layer and an electron injection layer are formed on the light-emitting layer by vapor deposition. Finally, a cathode layer is formed by sputtering. The hole injection layer, the hole transport layer, the light-emitting layer, the electron transport layer, and the electron injection layer combine to form the light-emitting device 410 in the light-emitting device layer 400.

[0105] In this embodiment of the invention, by adding a pad layer, the film thickness between two adjacent conductive structures in the second conductive layer is also increased, which compensates for the step difference between the patterned conductive structures in the second conductive layer and the interphase dielectric layer, thereby improving the surface flatness of the array substrate, and further improving the flatness of the pixel electrode layer prepared on the surface of the array substrate. This ensures that the surface height of the light-emitting device on the pixel electrode layer is also kept uniform, making the light emitted by the light-emitting device more uniform, thereby improving the luminous efficiency of the light-emitting device.

[0106] Furthermore, the embodiments of the present invention are preferred embodiments, in which the padding layer can be fabricated simultaneously with the gate layer in the array substrate, and can share the same photomask with the gate layer, without increasing the process or the photomask, and without affecting the production sequence, and thus without affecting production efficiency.

[0107] Furthermore, experiments on luminous efficiency were conducted between the display panel provided in the embodiments of the present invention and the display panel with a high step difference in the comparative example, and the relevant data are shown in Table 1.

[0108]

[0109] Table 1

[0110] As shown in the table above, the luminous efficiency of the green light-emitting device in this embodiment on the flexible substrate is increased by 67.7% compared to Comparative Example 1 and by 20.9% compared to Comparative Example 2. The luminous efficiency of the green light-emitting device on the glass substrate in this embodiment is increased by 17.6% compared to Comparative Example 1 and by 11.1% compared to Comparative Example 2. Therefore, the display panel in this embodiment has a significantly improved luminous efficiency compared to the existing display panels in Comparative Examples 1 and 2.

[0111] Example 2

[0112] This invention provides a display panel 10, such as... Figure 10 As shown, the display panel 10 includes an array substrate 100 and a light-emitting device layer 400.

[0113] The array substrate 100 includes a substrate layer 110, an insulating module 130, an active layer 120, a first conductive layer 140, and a second conductive layer 150. The insulating module 130 includes a gate insulating layer 131, an interphase dielectric layer 132, a passivation layer 133, and a planarization layer 134.

[0114] The substrate layer 110 includes a base layer 111, a light-shielding layer 112, and a buffer layer 113.

[0115] The base layer 111 is an insulating base layer, which can be a rigid glass plate, a quartz plate, or a flexible polyimide film layer. When the base layer 111 is a flexible film layer, the display panel 10 can achieve flexible bending display.

[0116] The light-shielding layer 112 is disposed on one surface of the substrate 111, and has a first light-shielding layer 1121 and a second light-shielding layer 1122. The first light-shielding layer 1121 corresponds to the active layer 120, and the orthographic projection of the first light-shielding layer 1121 and the active layer 120 on the substrate 110 coincides. The second light-shielding layer corresponds to the wiring layer 153 of the second conductive layer 150, and the orthographic projection of the second light-shielding layer 1122 and the wiring layer 153 on the substrate 110 coincide. The light-shielding layer 112 is made of one or more metallic materials and is used to reflect external light incident from one side of the substrate 111 to prevent external light from affecting the operation of the active layer 120.

[0117] The buffer layer 113 is disposed on the base layer 111 and covers the exposed surface of the light-shielding layer 112. The buffer layer 113 is made of insulating inorganic material, which is used to insulate and protect the light-shielding layer 112 and the active layer 120, and can also buffer and protect the structure of the display panel 10, reduce the damage caused by impact during transportation, and at the same time isolate external water and oxygen intrusion.

[0118] The buffer layer 113 has at least two first grooves 1131 on one surface away from the light-shielding layer 112, and the two first grooves 1131 correspond to the first light-shielding layer 1121 and the second light-shielding layer 1122, respectively. The width of the first groove 1131 corresponding to the first light-shielding layer 1121 is smaller than the width of the first light-shielding layer 1121, and the width of the first groove 1131 corresponding to the second light-shielding layer 1122 is smaller than the width of the second light-shielding layer 1122.

[0119] The active layer 120 fills the first groove 1131 corresponding to the first light-shielding layer 1121, and can be fabricated from semiconductor materials such as low-temperature polycrystalline silicon and metal oxide. The depth of the first groove 1131 is less than or equal to the thickness of the active layer 120. Preferably, the depth of the first groove 1131 is equal to the thickness of the active layer 120, causing the surface of the active layer 120 away from the light-shielding layer 112 and the surface of the buffer layer 113 away from the light-shielding layer 112 to be in the same plane. This maximizes the reduction of the height of the second conductive layer 150 in the array substrate 100 without affecting the electrical connection structure of the active layer, thereby reducing the step difference between film layers.

[0120] The gate insulating layer 131 is disposed on the substrate layer 110 and includes a first insulating layer 1311 and a second insulating layer 1312. The first insulating layer 1311 is disposed on a surface of the active layer 120 away from the buffer layer 113, and its width is smaller than the width of the active layer 120 to expose both ends of the active layer 120. The second insulating layer 1312 is disposed in another of the first recesses 1131 and corresponds to the second light-shielding layer 1122, that is, it also corresponds to the wiring layer 153 in the second conductive layer 150. Preferably, the thickness of the second insulating layer 1312 is equal to the sum of the thicknesses of the active layer 120 and the first insulating layer 1311, so that the top surface of the second insulating layer 1312 away from the substrate layer 110 and the top surface of the first insulating layer 1311 away from the substrate layer 110 are in the same plane, reducing the step difference between the first insulating layer 1311 and the second insulating layer 1312.

[0121] The first conductive layer 140 is disposed on a surface of the first insulating layer 1311 away from the active layer 120. The first conductive layer 140 serves as the gate layer 141 in the array substrate 100, and changes the electrical conduction state of the active layer 120 through the electric field effect.

[0122] The interphase dielectric layer 132 is disposed on the buffer layer 113 and covers the exposed surfaces of the active layer 120, the gate insulating layer 131, and the first conductive layer 140. A plurality of second grooves 1322 are provided on a surface of the interphase dielectric layer 132 away from the buffer layer 113.

[0123] The second conductive layer 150 is disposed on a surface of the interphase dielectric layer 132 away from the buffer layer 113, and includes a first electrode layer 151, a second electrode layer 152, and a wiring layer 153. The first electrode layer 151 and the second electrode layer 152 are respectively located at both ends of the active layer 120 and are respectively located in a second groove 1322. The bottom surface of the first electrode layer 151 and the second electrode layer 152 each has a connecting portion, which passes through the interphase dielectric layer 132 and is electrically connected to the active layer 120. The wiring layer 153 is located on the side of the second electrode layer 152 away from the first electrode layer 151, and corresponds to the second insulating layer 1312 and the second light-shielding layer 1122, and is located in a second groove 1322.

[0124] The depth of the second groove 1322 is less than or equal to the thickness of the second conductive layer 150. Preferably, the depth of the second groove 1322 is equal to the thickness of the second conductive layer 150, causing a surface of the second conductive layer 150 away from the substrate layer 110 and a surface of the interphase dielectric layer 132 away from the substrate layer 110 to be located in the same plane, thereby further eliminating the step difference in the conductive structure between the interphase dielectric layer 132 and the second conductive layer 150.

[0125] The insulating module 130 is generally made of insulating inorganic materials, such as silicon oxide and silicon nitride. The first conductive layer 140 and the second conductive layer 150 are made of metallic materials with excellent conductivity.

[0126] When a current or voltage is applied to the gate layer 141, it generates an electric field. This electric field induces charges on the surface of the active layer 120, changing the width of the channel portion in the active layer 120. This achieves the purpose of controlling the current in the first electrode layer 151 and the second electrode layer 152, thereby driving each light-emitting device 410 in the display panel 10.

[0127] The light-emitting device layer 400 is disposed on the planarization layer 134 and has a plurality of light-emitting devices 410. For example... Figure 10 As shown, the light-emitting device 410 is electrically connected to the second electrode layer 152 in the array substrate 100 via the pixel electrode layer 200. Specifically, the pixel electrode layer 200 is disposed on a surface of the planarization layer 134 away from the passivation layer 133, and its bottom surface also has a connecting portion. The connecting portion of the pixel electrode layer 200 passes through the planarization layer 134 and the passivation layer 133 in sequence and contacts and is electrically connected to the upper surface of the second electrode layer 152.

[0128] The display panel 10 further includes a pixel defining layer 300, which is disposed on the planarization layer 134 and the pixel electrode layer 200. The pixel defining layer 300 has multiple openings that penetrate the pixel defining layer 300 and correspond to the pixel electrode layer 200, thus exposing the upper surface of the pixel defining layer 300. Each opening is provided with a light-emitting device 410, which is electrically connected to the pixel electrode layer 200 within the opening.

[0129] The orthographic projection of the pixel electrode layer 200 on the substrate layer 110 coincides with the orthographic projections of the first conductive layer 140 and the second conductive layer 150 on the substrate layer 110. Since the second conductive layer 150 has multiple conductive structures, the surface of the array substrate 100 is uneven, which also makes it impossible for the surface height of the pixel electrode layer 200 and the light-emitting device 410 on the array substrate 100 to be uniform.

[0130] Furthermore, the orthographic projection of the first groove 1131 on the substrate 110 coincides with the orthographic projection of the second conductive layer 150 on the substrate 110. This reduces the film thickness at the protrusions in the array substrate 100 caused by the second electrode layer 150, thereby improving the surface flatness of the array substrate 100. Simultaneously, the second groove 1131 embeds each conductive structure of the second conductive layer 150 into the interphase dielectric layer 132, reducing the step difference between the second conductive layer 150 and the interphase dielectric layer 132 to below 200 nanometers. This further flattens the surface of the array substrate 100, thereby improving the problem of uneven light emission caused by the inconsistent film surface height of the light-emitting device 410 due to the step difference, and increasing the luminous efficiency of the light-emitting device 410.

[0131] This invention also provides a method for manufacturing a display panel 10, used to manufacture the display panel 10 as described above. The manufacturing process of the method is as follows: Figure 11 As shown, it includes steps S21-S27.

[0132] Step S21) Prepare a substrate layer 110 and form a first groove 1131 on the substrate layer 110:

[0133] A layer of metallic material, either molybdenum or copper, is deposited on a glass substrate 111 using physical vapor deposition. The diffusion barrier layer can be made of a molybdenum-titanium alloy, molybdenum, tantalum, or other materials with a work function similar to copper.

[0134] The metal material layer is patterned using photolithography to form... Figure 12 The first light-shielding layer 1121 and the second light-shielding layer 1122 are shown in the figure.

[0135] Furthermore, a diffusion barrier layer and an etch barrier layer can be deposited on the metal material layer using physical vapor deposition. The etch barrier layer can be made of metal oxides such as indium tin oxide or indium gallium zinc oxide. The light-shielding layer 112 and the diffusion barrier layer can use a hydrogen peroxide-based etchant as the patterning etchant, and the etch barrier layer can use an oxalic acid-based etchant as the patterning etchant.

[0136] like Figure 13 As shown, an inorganic material layer is deposited on the base layer 111 by chemical vapor deposition to form a buffer layer 113. Two first grooves 1131, corresponding to the first light-shielding layer 1121 and the second light-shielding layer 1122, are formed on the buffer layer 113 by a wet etching process.

[0137] The base layer 111, the first light-shielding layer 1121, the second light-shielding layer 1122, and the buffer layer 113 are combined to form the substrate layer 110.

[0138] Step S22) Forming the active layer 120:

[0139] A semiconductor material is deposited using physical vapor deposition (PVD) to fill the first groove 1131 corresponding to the first light-shielding layer 1121. The semiconductor material can be a metal oxide such as indium tin oxide (ITI) or indium gallium zinc oxide (IGZ). The semiconductor material layer is then patterned using photolithography to form a shape such as... Figure 14 The active layer 120 shown is described above. The active layer 120 may use an oxalic acid-based etchant as the patterning agent.

[0140] Step S23) Forming the gate insulating layer 131 and the first conductive layer 140:

[0141] An inorganic material layer covering the active layer 120 is deposited on the substrate layer 110 using chemical vapor deposition. This inorganic material layer also fills a first groove 1131 corresponding to the second light-shielding layer 1122. A metal material layer is deposited on a surface of the inorganic material layer away from the active layer 120. The inorganic material layer and the metal material layer are patterned using photolithography, such as... Figure 15 As shown, a first insulating layer 1311 and a second insulating layer 1312 are formed in the gate insulating layer 131, and a first conductive layer 140 is disposed on the first insulating layer 1311. During the patterning process of the gate layer 141, the active layer 120 is made conductive by plasma treatment after photoresist stripping of the gate layer 141.

[0142] Step S24) Forming an interphase dielectric layer 132, and forming a second groove 1322 on the interphase dielectric layer 132:

[0143] An inorganic material is deposited on the substrate 110 using chemical vapor deposition to form the interphase dielectric layer 132. The interphase dielectric layer 132 is then patterned using grayscale or halftone mask photolithography. Figure 16 As shown, a plurality of second grooves 1322 are formed on a surface of the interphase dielectric layer 132 away from the substrate layer 110, and a first connection hole 1321 penetrating the interphase dielectric layer 132 is formed in the second groove 1322 corresponding to the active layer 120. The interphase dielectric layer 132 can be dry-etched using an oxidizing gas such as a fluorine-based gas.

[0144] Step S25) Forming the second conductive layer 150:

[0145] A metal material layer, filling the second groove 1322 and the first connecting hole 1321, is deposited on the interphase dielectric layer 132 using physical vapor deposition. The metal material layer is a stacked structure of a molybdenum-titanium alloy layer and a copper metal layer. The metal material layer is then patterned using photolithography. Figure 17 As shown, a first electrode layer 151, a second electrode layer 152, and a wiring layer 153 are formed in the second conductive layer 150. The second conductive layer 150 can be etched using a hydrogen peroxide-based etchant as a patterning etchant.

[0146] Furthermore, in step S24, the buffer layer 113 can be patterned again by photolithography to form a deep hole that passes through the interphase dielectric layer 132 and the buffer layer 113 in sequence. At the same time as step S25, the metal material is deposited in the deep hole so that the first electrode layer 151 or the second electrode layer 152 can be electrically connected to the light-shielding layer 112, thereby avoiding the floating gate effect of the light-shielding layer 112.

[0147] Furthermore, when the dry etching barrier layer on the light-shielding layer 112 is indium gallium zinc oxide, dry etching plasma is required to simultaneously conduct the etching barrier layer to ensure that the charge in the first electrode layer 151 in the subsequent second conductive layer 150 is transferred to the light-shielding layer 112, thereby compensating for the threshold voltage (Vth).

[0148] Step 26) Forming a passivation layer 133, a planarization layer 134, a pixel electrode layer 200, and a pixel confinement layer 300:

[0149] The passivation layer 133 and the planarization layer 134 are formed on the interphase dielectric layer 132 by deposition. The passivation layer 133 and the planarization layer 134 are patterned to form a second connecting hole 135 penetrating the planarization layer 134 and the passivation layer 133.

[0150] A conductive material is deposited on the planar layer 134 to fill the second connection hole 135, and the conductive material is patterned to form the pixel electrode layer 200.

[0151] An insulating material is coated onto the planarization layer 134 and the pixel electrode layer 200, and then patterned to form a shape as shown. Figure 18 The pixel-defining layer 300 with multiple openings described herein.

[0152] Step S27) Forming the light-emitting device layer 400:

[0153] Organic material layers such as a hole injection layer, a hole transport layer, and a light-emitting layer are printed in the opening using inkjet printing. An electron transport layer and an electron injection layer are formed on the light-emitting layer by vapor deposition. Finally, a cathode layer is formed by sputtering. The hole injection layer, the hole transport layer, the light-emitting layer, the electron transport layer, and the electron injection layer combine to form the light-emitting device 410 in the light-emitting device layer 400.

[0154] In this embodiment of the invention, by reducing the film thickness of the protruding portion in the array substrate through the first and second grooves, the step difference between the conductive structure in the second conductive layer and the interphase dielectric layer is reduced, thereby improving the surface flatness of the array substrate, and further improving the flatness of the pixel electrode layer prepared on the surface of the array substrate. This ensures that the surface height of the light-emitting device on the pixel electrode layer remains uniform, making the light emitted by the light-emitting device more uniform, thereby improving the luminous efficiency of the light-emitting device and increasing the display brightness of the display panel.

[0155] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A display panel, characterized by, include: The light-emitting device layer is provided with multiple light-emitting devices; An array substrate, wherein the light-emitting device layer is disposed on the array substrate; The array substrate includes: Substrate layer; insulating module disposed on the substrate layer, the insulating module including a gate insulating layer disposed on the substrate layer, the gate insulating layer including: a first insulating layer and a second insulating layer, the first insulating layer being disposed on a surface of the active layer of the array substrate away from the substrate layer, the second insulating layer being disposed on the substrate layer, the thickness of the second insulating layer being equal to the sum of the thickness of the first insulating layer and the thickness of the active layer of the array substrate, such that the top surface of the second insulating layer away from the substrate layer and the top surface of the first insulating layer away from the substrate layer are located in the same plane; A first conductive layer and a second conductive layer are disposed in the insulating module in a staggered manner, with the first conductive layer located on the side of the second conductive layer closer to the substrate layer. The first conductive layer is disposed on the surface of the gate insulating layer away from the active layer of the array substrate. The second insulating layer corresponds to the wiring layer in the second conductive layer. The second conductive layer has multiple conductive structures. The first conductive layer includes a padding layer, the padding layer not coinciding with the orthographic projection of the second conductive layer onto the substrate layer, the padding layer being disposed on the surface of the second insulating layer away from the substrate layer; or The substrate layer has a first groove on one surface facing the conductive structure. The first groove coincides with the orthographic projection of the second conductive layer on the substrate layer. The second insulating layer is disposed in the first groove.

2. The display panel of claim 1, wherein, The substrate layer includes: grassroots level; A light-shielding layer is provided on the base layer; A buffer layer is disposed on the base layer and covers the light-shielding layer; The first groove is disposed on a surface of the buffer layer away from the light-shielding layer; The active layer in the array substrate is disposed in the first groove.

3. The display panel of claim 2, wherein, The depth of the first groove is less than or equal to the thickness of the active layer.

4. The display panel of claim 1, wherein, The second conductive layer includes: First electrode layer; The second electrode layer is located on one side of the first electrode layer; The trace layer is located on the side of the second electrode layer that is away from the first electrode layer; The first electrode layer, the second electrode layer, and the wiring layer are disposed on the same plane in the insulating module and are electrically insulated from each other; The orthographic projection of the padding layer onto the substrate layer is located on both sides of the wiring layer.

5. The display panel of claim 1, wherein, The insulation module also includes: An interphase dielectric layer is disposed on the substrate layer and covers the gate insulating layer and the first conductive layer, and a second conductive layer is disposed on the surface of the interphase dielectric layer away from the second conductive layer; A passivation layer is disposed on the interphase dielectric layer and covers the second conductive layer; A planarization layer is disposed on the passivation layer; The interphase dielectric layer has a second groove on one surface facing the second conductive layer, and the second conductive layer is located in the second groove.

6. The display panel as described in claim 5, characterized in that, The first conductive layer further includes a gate layer disposed on a surface of the first insulating layer away from the active layer.

7. A method of manufacturing the display panel according to any one of claims 1 to 6, characterized by, Includes the following steps: Prepare a substrate layer; A first conductive layer, a second conductive layer, and an insulating module are fabricated on the substrate to form an array substrate; Multiple light-emitting devices are fabricated on the array substrate to form a light-emitting device layer; After preparing the substrate layer, the following steps are also included: A first groove is formed on the substrate layer, and the first groove coincides with the orthographic projection of the second conductive layer on the substrate layer. or A padding layer is formed during the fabrication of the first conductive layer, and the padding layer does not coincide with the orthographic projection of the second conductive layer onto the substrate.

8. The method of producing a display panel according to claim 7, wherein The step of preparing the substrate layer includes the following steps: A light-blocking layer is formed on a base layer; A buffer layer covering the light-shielding layer is formed on the base layer; The first groove is formed on a surface of the buffer layer away from the light-shielding layer; The step of preparing the substrate layer is further included in the following steps: An active layer is formed in the first groove.

9. The method for manufacturing a display panel as described in claim 7, characterized in that, The step of fabricating the first conductive layer, the second conductive layer, and the insulating module on the substrate layer further includes the following step: A gate insulating layer is formed on the substrate layer; The first conductive layer is formed on the gate insulating layer; An interphase dielectric layer covering the gate insulating layer and the first conductive layer is formed on the substrate layer; The second conductive layer is formed on the interphase dielectric layer; A passivation layer covering the second conductive layer is formed on the interphase dielectric layer; A planarization layer is formed on the passivation layer; Following the step of forming the interphase dielectric layer on the substrate layer, the method further includes the following steps: A second groove is formed on one surface of the interphase dielectric layer facing the second conductive layer, and the second conductive layer is formed in the second groove.

10. A display device, characterized by comprising: Includes the display panel as described in any one of claims 1-6.

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