A low-noise dual-output synchronous demodulation circuit and synchronous demodulation method

Abstract

The present invention discloses a low-noise dual-output synchronous demodulation circuit and method. The synchronous demodulation circuit includes a signal source to be measured, a reference signal source, a pulse generator, a voltage comparator, a logic operator, a reversible counter, a digital-to-analog converter, a digital filter, and an analog filter. A sinusoidal reference signal is generated by the pulse generator as a digital pulse signal. A sinusoidal voltage signal is generated by the voltage comparator and the logic operator as a synchronized pulse count signal. The reversible counter and the digital-to-analog converter are used to obtain a digital voltage signal and an analog voltage signal. Real-time looping is used to maintain the consistency of the voltage value of the sinusoidal voltage signal when the analog voltage signal is synchronized with the digital pulse signal. This synchronous demodulation method can effectively reduce high-frequency components and improve the signal-to-noise ratio of the demodulated signal. The synchronous demodulation circuit can directly provide dual outputs of a digital demodulation signal and an analog demodulation signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal demodulation, and in particular relates to a low-noise dual-output synchronous demodulation circuit and a synchronous demodulation method. Background Art

[0002] Signal modulation and demodulation have widespread and important applications in testing and communication systems. For example, in eddy current testing, a high-frequency sinusoidal signal generates a high-frequency magnetic field. The metal's eddy current effect modulates the detection signal, and precision demodulation technology can accurately detect internal metal damage and defects. Another example is wireless communications, where an audio signal is modulated onto a high-frequency carrier and transmitted. Advanced signal demodulation technology allows the receiving device to clearly restore the original audio information.

[0003] Among the many demodulation technologies, synchronous demodulation plays a very important role. A synchronous demodulator multiplies an amplitude modulated signal with a reference signal (the original carrier signal) and filters out high-frequency components using a low-pass filter, thereby restoring the original modulated signal. The most commonly used synchronous demodulator is a phase-sensitive detection circuit, which mainly includes analog phase-sensitive detection circuits and switching phase-sensitive detection circuits. Analog phase-sensitive detection circuits use analog multipliers to multiply the amplitude modulated signal with the reference signal; switching phase-sensitive detection circuits multiply the double-sideband amplitude modulated signal with the reference signal by controlling the switching state of transistors. The multiplication operations described above in synchronous demodulation all generate high-frequency noise, which needs to be filtered out by a low-pass filter to improve the signal-to-noise ratio of the final demodulated signal.

[0004] The current synchronous demodulation circuit has the following problems: (1) Analog multipliers have poor linearity and slow high-frequency response, and are easily affected by factors such as offset and temperature drift; (2) Switch multipliers are limited by the impedance characteristics and dynamic characteristics of the switch, and the demodulated signal has large errors and is expensive; (3) Multiplication operations will generate high-frequency components. The larger the amplitude of the amplitude modulated signal, the stronger the noise of the high-frequency component, and the worse the signal-to-noise ratio of the demodulated signal; (4) The demodulated signals are all analog voltage signals, and cannot directly provide digital demodulation signals. Summary of the Invention

[0005] In order to solve the above problems and overcome the shortcomings of existing synchronous demodulation technology, the purpose of the present invention is to provide a low-noise dual-output synchronous demodulation circuit and a synchronous demodulation method. The synchronous demodulation method can effectively reduce high-frequency noise and improve the signal-to-noise ratio of the demodulated signal. The synchronous demodulation circuit has a simple structure and is easy to implement. It can directly provide dual outputs of digital demodulation signals and analog demodulation signals.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] A low-noise dual-output synchronous demodulation circuit, characterized by comprising a signal source to be measured, a reference signal source, a pulse generator, a voltage comparator, a logic operator, a reversible counter, a digital-to-analog converter, a digital filter and an analog filter;

[0008] The signal source to be measured provides a sinusoidal voltage signal to be demodulated;

[0009] The reference signal source provides a sinusoidal reference signal having the same frequency as the sinusoidal voltage signal;

[0010] The pulse generator is connected to the reference signal source and is used to perform pulse triggering on the sinusoidal reference signal output by the reference signal source, and the output result is a digital pulse signal;

[0011] The voltage comparator is connected to the signal source to be measured and the digital-to-analog converter respectively, and is used to compare the sinusoidal voltage signal output by the signal source to be measured with the analog voltage signal output by the digital-to-analog converter, and the output result is a logic level signal;

[0012] The logic operator is connected to the pulse generator and the voltage comparator respectively, and is used to perform a logic operation on the digital pulse signal output by the pulse generator and the logic level signal output by the voltage comparator, and the output result is a pulse counting signal;

[0013] The reversible counter is connected to the logic operator and is used to reversibly accumulate the pulse counting signal output by the logic operator, and the output result is a digital voltage signal;

[0014] The digital-to-analog converter is connected to the reversible counter and is used to perform digital-to-analog conversion on the digital voltage signal output by the reversible counter, and the output result is an analog voltage signal;

[0015] The digital filter is connected to the reversible counter and is used to perform digital low-pass filtering on the digital voltage signal output by the reversible counter, and the output result is a digital demodulated signal;

[0016] The analog filter is connected to the digital-to-analog converter and is used to perform analog low-pass filtering on the analog voltage signal output by the digital-to-analog converter, and the output result is an analog demodulated signal.

[0017] Furthermore, the pulse generator is used to generate a high-level pulse at the zero point of each cycle of the sinusoidal reference signal where the signal changes from negative to positive, and output a digital pulse signal.

[0018] Furthermore, the voltage comparator is used to generate a logic high level when the sinusoidal voltage signal is greater than the analog voltage signal, and to generate a logic low level when the sinusoidal voltage signal is less than the analog voltage signal, and output a logic level signal.

[0019] Furthermore, the logic operator is used to synchronously generate a positive voltage pulse with a count plus 1 when the logic level signal is a logic high level in each cycle of the digital pulse signal, and to synchronously generate a negative voltage pulse with a count minus 1 when the logic level signal is a logic low level, and output a pulse counting signal.

[0020] Furthermore, the reversible counter is used to add 1 to the accumulated digital quantity when a positive voltage pulse with a count of plus 1 is input, and to subtract 1 from the accumulated digital quantity when a negative voltage pulse with a count of minus 1 is input, and output a digital voltage signal.

[0021] In order to achieve the above object, the present invention further provides a low-noise dual-output synchronous demodulation method using the above low-noise dual-output synchronous demodulation circuit, comprising the following steps:

[0022] Step 1: Provide a sinusoidal voltage signal to be demodulated and a sinusoidal reference signal of the same frequency;

[0023] Step 2: Pulse triggering the sinusoidal reference signal to output a digital pulse signal;

[0024] Step 3: Compare the sinusoidal voltage signal with the analog voltage signal and output a logic level signal;

[0025] Step 4: performing a logic operation on the digital pulse signal and the logic level signal to output a pulse counting signal;

[0026] Step 5: reversibly accumulate the pulse counting signal and output a digital voltage signal;

[0027] Step 6: Perform digital-to-analog conversion on the digital voltage signal to output an analog voltage signal;

[0028] Step 7: looping the above steps 3 to 6 in real time, wherein the voltage values ​​of the analog voltage signal and the sinusoidal voltage signal when the digital pulse signal is a high-level pulse are consistent;

[0029] Step 8: Perform digital low-pass filtering on the digital voltage signal and output a digital demodulated signal;

[0030] Step nine: perform analog low-pass filtering on the analog voltage signal and output an analog demodulated signal.

[0031] Compared with the prior art, the advantages of the present invention are:

[0032] (1) The present invention realizes synchronous demodulation multiplication operation through a voltage comparator, a logic operator, a reversible counter and a digital-to-analog converter, avoiding the problems existing in analog and switch-type multipliers, and has good dynamic characteristics, high detection accuracy, simple circuit structure and easy implementation;

[0033] (2) The high-frequency component generated by this synchronous demodulation method is the variation of the single-cycle digital voltage signal and the analog voltage signal, which is independent of the amplitude of the amplitude modulated signal. It can effectively reduce high-frequency noise and improve the signal-to-noise ratio of the demodulated signal.

[0034] (3) The synchronous demodulation circuit includes a digital voltage signal and an analog voltage signal, and can directly provide dual outputs of a digital demodulation signal and an analog demodulation signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the structure of the synchronous demodulation circuit of the present invention;

[0036] Figure 2 is a flow chart of the synchronous demodulation method of the present invention;

[0037] Figure 3 Schematic diagram of part of the signal in the synchronous demodulation process of the present invention. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0039] like Figure 1 、 3 As shown, a low-noise dual-output synchronous demodulation circuit includes a signal source to be measured, a reference signal source, a pulse generator, a voltage comparator, a logic operator, a reversible counter, a digital-to-analog converter, a digital filter and an analog filter;

[0040] The signal source to be measured provides a sinusoidal voltage signal U(t) to be demodulated;

[0041] The reference signal source provides a sinusoidal reference signal R(t) having the same frequency as the sinusoidal voltage signal U(t);

[0042] The pulse generator is connected to the reference signal source and is used to perform pulse triggering on the sinusoidal reference signal R(t) output by the reference signal source, triggering a high-level pulse at the zero point where the sinusoidal reference signal R(t) changes from negative to positive in each cycle, and outputting a digital pulse signal C1;

[0043] The voltage comparator is connected to the signal source to be measured and the digital-to-analog converter respectively, and is used to compare the sinusoidal voltage signal U(t) output by the signal source to be measured with the analog voltage signal V(t) output by the digital-to-analog converter, and generates a logic high level when the sinusoidal voltage signal U(t) is greater than the analog voltage signal V(t); and generates a logic low level when the sinusoidal voltage signal U(t) is less than the analog voltage signal V(t), and outputs a logic level signal C2;

[0044] The logic operator is connected to the pulse generator and the voltage comparator respectively, and is used to perform a logic operation on the digital pulse signal C1 output by the pulse generator and the logic level signal C2 output by the voltage comparator. When each cycle of the digital pulse signal C1 is a high-level pulse, the logic level signal C2 is a logic high level and a positive voltage pulse for counting plus 1 is synchronously generated. When the logic level signal C2 is a logic low level, a negative voltage pulse for counting minus 1 is synchronously generated and a pulse counting signal C3 is output;

[0045] The reversible counter is connected to the logic operator and is used to reversibly accumulate the pulse counting signal C3 output by the logic operator. When a positive voltage pulse with a count of plus 1 is input, the accumulated digital value is increased by 1, and when a negative voltage pulse with a count of minus 1 is input, the accumulated digital value is decreased by 1, and the digital voltage signal D(t) is output;

[0046] The digital-to-analog converter is connected to the reversible counter and is used to perform digital-to-analog conversion on the digital voltage signal D(t) output by the reversible counter and output an analog voltage signal V(t);

[0047] The digital filter is connected to the reversible counter and is used to perform digital low-pass filtering on the digital voltage signal D(t) output by the reversible counter and output a digital demodulated signal D O (t);

[0048] The analog filter is connected to the digital-to-analog converter and is used to perform analog low-pass filtering on the analog voltage signal V(t) output by the digital-to-analog converter to output an analog demodulated signal V O (t).

[0049] like Figure 2 、 3 As shown, based on the above-mentioned low-noise dual-output synchronous demodulation circuit, the corresponding synchronous demodulation method of the present invention includes the following steps:

[0050] In step S01, a sinusoidal voltage signal U(t) to be demodulated and a sinusoidal reference signal R(t) with the same frequency are provided;

[0051] In step S02, the sinusoidal reference signal R(t) is pulse-triggered to output a digital pulse signal C1;

[0052] In step S03, the sinusoidal voltage signal U(t) is compared with the analog voltage signal V(t), and a logic level signal C2 is output;

[0053] In step S04, a logic operation is performed on the digital pulse signal C1 and the logic level signal C2 to output a pulse counting signal C3;

[0054] In step S05, the pulse counting signal C3 is reversibly accumulated to output a digital voltage signal D(t);

[0055] In step S06, the digital voltage signal D(t) is converted into a digital-to-analog signal to output an analog voltage signal V(t);

[0056] In step S07, the above steps S03 to S06 are looped in real time, and the analog voltage signal V(t) is consistent with the voltage value of the sinusoidal voltage signal U(t) when the digital pulse signal C1 is a high-level pulse;

[0057] In step S08, the digital voltage signal D(t) is subjected to digital low-pass filtering to output a digital demodulated signal D O (t);

[0058] In step S09, the analog voltage signal V(t) is subjected to analog low-pass filtering to output an analog demodulated signal V O (t).

Claims

1. A low-noise dual-output synchronous demodulation circuit, characterized in that: It includes a signal source to be measured, a reference signal source, a pulse generator, a voltage comparator, a logic operator, a reversible counter, a digital-to-analog converter, a digital filter and an analog filter; The signal source to be measured provides a sinusoidal voltage signal to be demodulated; The reference signal source provides a sinusoidal reference signal having the same frequency as the sinusoidal voltage signal; The pulse generator is connected to the reference signal source and is used to perform pulse triggering on the sinusoidal reference signal output by the reference signal source, and the output result is a digital pulse signal; The voltage comparator is connected to the signal source to be measured and the digital-to-analog converter respectively, and is used to compare the sinusoidal voltage signal output by the signal source to be measured with the analog voltage signal output by the digital-to-analog converter, and the output result is a logic level signal; The logic operator is connected to the pulse generator and the voltage comparator respectively, and is used to perform a logic operation on the digital pulse signal output by the pulse generator and the logic level signal output by the voltage comparator, and the output result is a pulse counting signal; The reversible counter is connected to the logic operator and is used to reversibly accumulate the pulse counting signal output by the logic operator, and the output result is a digital voltage signal; The digital-to-analog converter is connected to the reversible counter and is used to perform digital-to-analog conversion on the digital voltage signal output by the reversible counter, and the output result is an analog voltage signal; The digital filter is connected to the reversible counter and is used to perform digital low-pass filtering on the digital voltage signal output by the reversible counter, and the output result is a digital demodulated signal; The analog filter is connected to the digital-to-analog converter and is used to perform analog low-pass filtering on the analog voltage signal output by the digital-to-analog converter, and the output result is an analog demodulated signal.

2. The low-noise dual-output synchronous demodulation circuit according to claim 1, characterized in that: The pulse generator is further used to trigger a high-level pulse at the zero point of each cycle of the sinusoidal reference signal changing from negative to positive, and output a digital pulse signal.

3. The low-noise dual-output synchronous demodulation circuit according to claim 1, characterized in that: The voltage comparator is further configured to generate a logic high level when the sinusoidal voltage signal is greater than the analog voltage signal, generate a logic low level when the sinusoidal voltage signal is less than the analog voltage signal, and output a logic level signal.

4. The low-noise dual-output synchronous demodulation circuit according to claim 1, characterized in that: The logic operator is further used to synchronously generate a positive voltage pulse with a count of plus 1 when the digital pulse signal is a high-level pulse in each cycle, and to synchronously generate a negative voltage pulse with a count of minus 1 when the logic level signal is a logic low level, and output a pulse counting signal.

5. The low-noise dual-output synchronous demodulation circuit according to claim 1, characterized in that: The reversible counter is further used to add 1 to the accumulated digital quantity when a positive voltage pulse with a count of plus 1 is input, and subtract 1 from the accumulated digital quantity when a negative voltage pulse with a count of minus 1 is input, and output a digital voltage signal.

6. A low-noise dual-output synchronous demodulation method, characterized by: Using the low-noise dual-output synchronous demodulation circuit according to any one of claims 1 to 5, the method comprises the following steps: Step 1: Provide a sinusoidal voltage signal to be demodulated and a sinusoidal reference signal of the same frequency; Step 2: Pulse triggering the sinusoidal reference signal to output a digital pulse signal; Step 3: Compare the sinusoidal voltage signal with the analog voltage signal and output a logic level signal; Step 4: performing a logic operation on the digital pulse signal and the logic level signal to output a pulse counting signal; Step 5: reversibly accumulate the pulse counting signal and output a digital voltage signal; Step 6: Perform digital-to-analog conversion on the digital voltage signal to output an analog voltage signal; Step 7: looping the above steps 3 to 6 in real time, wherein the voltage values ​​of the analog voltage signal and the sinusoidal voltage signal when the digital pulse signal is a high-level pulse are consistent; Step 8: Perform digital low-pass filtering on the digital voltage signal and output a digital demodulated signal; Step nine: perform analog low-pass filtering on the analog voltage signal and output an analog demodulated signal.

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