Compact integrated low noise amplifier

Abstract

A low noise amplifier includes a matching network for providing three-way coupling between an input node, a matching node, and a source node; a gate capacitor for providing AC coupling between the matching node and a gate node; a cascode amplifier for receiving a gate voltage at the gate node and outputting an output voltage at an output node in dependence on source degeneration at the source node; and a load network coupled to the output node. The matching network includes a shunt inductor, a series inductor, and a source degeneration inductor, the shunt inductor and the series inductor being stacked in a layout to have strong mutual coupling, the source degeneration inductor being disposed alongside the shunt inductor to have strong mutual coupling.

Description

Technical Field

[0001] This disclosure generally relates to low-noise amplifiers, and more particularly to compact, integrated low-noise amplifiers. Background Technology

[0002] like Figure 1 As shown, a conventional low-noise amplifier (hereinafter referred to as LNA) 100 receives an input voltage. V I and output voltage V O It includes: an impedance matching inductor 111; an AC coupling capacitor 121; a cascaded amplifier 130 including a first N-channel metal-oxide-semiconductor (NMOS) transistor 131, a second NMOS transistor 132, a DC coupling resistor 134, and a source attenuation inductor 133; and a load network 150 including a load inductor 151 and a load capacitor 152 connected in parallel. In this disclosure, " V DD "This indicates a power supply node. The first NMOS transistor 131 serves as a common-source stage, and the source attenuation inductor 133 is used to ensure that the input impedance of this common-source stage has a real part. The DC coupling resistor 134 is used to apply a first bias voltage." V A It is coupled to the gate of the first NMOS transistor 131 and establishes an appropriate bias condition for the first NMOS transistor 131. The AC coupling capacitor 121 is used to block the input voltage. V I The DC component. The second NMOS transistor 132 is biased by a second bias voltage. V B It is biased and used as a common-gate stage, which provides reverse isolation to the stacked amplifier 130. The LNA 100 is an existing circuit, the details of which will not be described here.

[0003] The performance of an LNA is typically assessed by its "return loss" and "noise figure," with high return loss and low noise figure being desirable. High return loss can be achieved through good impedance matching, and low noise figure through good noise matching; these are well-known to those skilled in the art, and therefore the details are not elaborated here. In a particular embodiment of interest, LNA 100 is an integrated circuit fabricated on a silicon substrate using a complementary metal-oxide-semiconductor (CMOS) process. In this example, inductors 111 and 133 may occupy a considerable layout area, making LNA 100 expensive. Furthermore, to protect the first NMOS transistor 131 in an electrostatic discharge (ESD) event, an ESD protection circuit 170 is typically used, comprising a forward diode 171 and a reverse diode 172 connected in parallel. Additionally, a bonding pad is required when packaging this integrated circuit, which actually results in a parasitic capacitance 160. Both parasitic capacitance 160 and ESD protection circuit 170 may cause reflection loss and / or serious degradation of noise figure.

[0004] What is needed in this technical field is an integrated LNA with the following characteristics: compact layout area, good ESD protection, and good performance. Summary of the Invention

[0005] One embodiment of the low-noise amplifier disclosed herein includes: a matching network for providing three-way coupling between an input node, a matching node, and a source node; a gate capacitor for providing AC coupling between the matching node and a gate node; a stacked amplifier for receiving a gate voltage at the gate node and outputting an output voltage at an output node based on the source attenuation of the source node; and a load network coupled to the output node, wherein the matching network includes a bypass inductor, a series inductor, and a source attenuation inductor, the bypass inductor and the series inductor being stacked in a layout to have strong mutual coupling, and the source attenuation inductor being disposed next to the bypass inductor to have strong mutual coupling.

[0006] Another embodiment of the low-noise amplifier disclosed herein includes: a bypass inductor for connecting an input node to ground; a series inductor for coupling the input node to a matching node; a source attenuation inductor for coupling a source node to ground; a gate capacitor for coupling the matching node to a gate node; a stacked amplifier for receiving a gate voltage at the gate node and outputting an output voltage at an output node based on the source attenuation of the source node; and a load network coupled to the output node, wherein the bypass inductor and the series inductor are stacked in a layout to have strong mutual coupling, and the source attenuation inductor is disposed next to the bypass inductor to have strong mutual coupling.

[0007] The features, implementation, and technical effects of the present invention are described in detail below with reference to the accompanying drawings, and preferred embodiments are described in detail. Attached Figure Description

[0008] Figure 1 This shows a schematic diagram of a conventional low-noise amplifier;

[0009] Figure 2 A schematic diagram of a low-noise amplifier is shown according to an embodiment of the present disclosure; and

[0010] Figure 3 An embodiment of the present disclosure shows a method for... Figure 2 Top view of the layout of a matching network for a low-noise amplifier.

[0011] Symbol Explanation

[0012] 100: Low-noise amplifier

[0013] 111: Impedance matching inductor

[0014] 121: AC coupling capacitor

[0015] 130: Stacked Amplifier

[0016] 131: First NMOS transistor

[0017] 132: Second NMOS transistor

[0018] 133: Source attenuation inductor

[0019] 134: DC coupling resistor

[0020] 150: Load Network

[0021] 151: Load Inductance

[0022] 152: Load capacitor

[0023] 160: Parasitic capacitance

[0024] 170: ESD protection circuit

[0025] 171: Diode

[0026] 172: Diode

[0027] V I Input voltage

[0028] V O Output voltage

[0029] V DD Power supply node

[0030] V A First bias voltage

[0031] V B Second bias voltage

[0032] 200: Low-noise amplifier

[0033] 230: Stacked Amplifier

[0034] 250: Load network

[0035] 251: Load Inductance

[0036] 252: Load capacitor

[0037] 260: Matching Network

[0038] 270: Parasitic capacitance

[0039] NI: Input Node

[0040] NM: Matching Node

[0041] NS: Source node

[0042] NG: Gate node

[0043] NO: Output Node

[0044] ND: Drain node

[0045] CG: Gate capacitance

[0046] V g Gate voltage

[0047] V i Input voltage

[0048] V o Output voltage

[0049] V m Matching voltage

[0050] V d Drain voltage

[0051] V b1 First bias voltage

[0052] V b2 Second bias voltage

[0053] V s Source node voltage

[0054] L1: Bypass inductor

[0055] L2: Series inductor

[0056] L3: Source attenuation inductor

[0057] Mutual coupling between L1 and L2

[0058] Mutual coupling between L1 and L2

[0059] M1: First NMOS transistor

[0060] M2: Second NMOS transistor

[0061] RB: DC coupling resistor

[0062] RDL: Relay Layer

[0063] UTM: Ultra-thick metal layer

[0064] 310: Display Figure 3 The diagram of the square

[0065] 321, 323, 332, 334, 341: Metallic traces

[0066] 322, 331, 333: Contact Detailed Implementation

[0067] This disclosure focuses on low-noise amplifiers. While this specification discloses several embodiments that may be considered preferred examples for carrying out the invention, it should be noted that the invention can be carried out in various ways and is not limited to the specific examples described below, nor to the specific manner in which the technical features of those specific examples are implemented. In other instances, well-known details have not been shown or described to avoid obscuring the viewpoint of this disclosure.

[0068] Those skilled in the art will understand the microelectronics-related terms and basic concepts used in this disclosure, such as "voltage," "bias," "noise," "reflection loss," "inductance," "capacitance," "resistance," "mutual coupling," "common-source," "common-gate," "cascode," "load," "source degeneration," "resonant cavity," "parallel connection," "series," "shunt," "via," "circuit node," "ground," "power supply," "frequency," "alternate current (AC)," "direct current (DC)," "MOS (Metal-Oxide-Semiconductor) transistor," "CMOS (Complementary Metal-Oxide-Semiconductor) process technology," "NMOS (n-channel Metal-Oxide-Semiconductor) transistor," and "PMOS (p-channel Metal-Oxide-Semiconductor) transistor." When such terms and basic concepts are used in microelectronics texts, they are readily apparent to those skilled in the art, and therefore their details are not elaborated herein.

[0069] Those skilled in the art will understand without further explanation that units such as nH (nano-Henry), pH (pico-Henry), pF (pico-Farad), and nm (nanometer) are used in this specification. (micron)

[0070] Those skilled in the art can understand the electronic components included in the circuit diagram, such as inductors, capacitors, resistors, NMOS transistors, PMOS transistors, etc., without needing redundant explanations of how one component is connected to another. Those skilled in the art can also identify a ground symbol, a capacitor symbol, an inductor symbol, a resistor symbol, and the symbols for PMOS and NMOS transistors, and can identify the "source terminal," "gate terminal," and "drain terminal" of these transistors. Regarding MOS transistors, for the sake of brevity, in the following description, "source terminal" is simply referred to as "source," "gate terminal" as "gate," and "drain terminal" as "drain."

[0071] A MOS transistor, PMOS transistor, or NMOS transistor has a threshold voltage. A MOS transistor turns on when its gate-to-source voltage is greater than its threshold voltage (in absolute terms). The absolute value of the difference between the gate-to-source voltage and the threshold voltage when a MOS transistor is turned on is called the "over-drive voltage." When a MOS transistor is turned on and its over-drive voltage is less than its drain-to-source voltage (in absolute terms), the MOS transistor is in a "saturation region." A MOS transistor is only an effective gain element when it is in this "saturation region."

[0072] As is known to those skilled in the art, a circuit is an assembly of transistors, capacitors, resistors, and / or other electronic components interconnected in a particular manner to perform a particular function.

[0073] A network is a collection of one or more circuits.

[0074] In this disclosure, when the meaning of a "circuit node" is clearly understood from the context, the "circuit node" is often simply referred to as a "node".

[0075] Figure 2 A schematic diagram of a low noise amplifier (LNA) 200 is shown according to an embodiment of the present disclosure. The LNA 200 includes: a matching network 260 for providing three-way coupling between an input node NI, a matching node NM, and a source node NS to achieve a combined function of impedance matching (between the input node NI and the matching node NM) and source attenuation (at the source node NS); a gate capacitor CG for providing AC coupling between the matching node NM and a gate node NG; and a cascaded amplifier 230 for receiving a gate voltage at the gate node NG based on the source attenuation at the source node NS.V g And output a voltage at an output node NO. V o A load network 250 is coupled to the output node NO. Additionally, a parasitic capacitance 270 is located at the input node NI, caused by a bond pad, for example, used to package the LNA 200 in a quad-flat-no-leads (QFN) package. The LNA 200 can be considered a variant of the LNA 100, incorporating the following technical changes: the ESD protection circuitry 170 is removed; the inductor 111 is replaced by a matching network 260; and the source attenuation inductor 133 is incorporated into the matching network 260 as part of it.

[0076] Matching network 260 includes three inductors: a bypass inductor L1, a series inductor L2, and a source attenuation inductor L3. The bypass inductor L1 shunts the input node NI to ground. The series inductor L2 couples the input node NI to the matching node NM. The source attenuation inductor L3 couples the source node NS to ground. The bypass inductor L1 and the series inductor L2 are stacked in a layout to provide strong mutual coupling. The source attenuation inductor L3 is positioned very close to the shunt inductor L1 to create strong mutual coupling. The purpose of the bypass inductor L1 is twofold: first, it helps compensate for the parasitic capacitance 270 located at the input node NI, allowing for better impedance and noise matching; second, it provides an effective discharge path in the event of an electrostatic discharge (ESD) event, eliminating the need for an ESD protection circuit (e.g., ESD protection circuit 170). In one embodiment, the bypass inductor L1 and the series inductor L2 are arranged in a concentric topology, with a portion of the source attenuation inductor L3 adjacent to and parallel to a portion of the bypass inductor L1.

[0077] The above arrangement offers several advantages. First, it provides strong coupling from the bypass inductor L1 to the series inductor L2, thus increasing the effective inductance value of the series inductor L2 and allowing the designer to use an inductor with a smaller inductance value as the series inductor L2. Second, the bypass inductor L1 is stacked with the series inductor L2 in this layout, resulting in highly area efficient use of space. Third, it provides strong coupling from the bypass inductor L1 to the source attenuation inductor L3, thus enhancing the effectiveness of source attenuation for the common-source stacked amplifier 230.

[0078] The gate capacitance CG provides effective AC coupling, therefore, a matching voltage at the matching node NM V m The AC component is approximately equal to the gate voltage. V g AC component.

[0079] The stacked amplifier 230 includes a common-source stage and a common-gate stage. The common-source stage includes a first NMOS transistor M1, and the common-gate stage includes a second NMOS transistor M2. The first NMOS transistor M1 is used to receive the gate voltage at the gate node NG according to the following conditions. V g And output a drain voltage at a drain node ND. V d A bias condition is given by a first bias voltage via a DC coupling resistor RB. V b1 Establishment; and source decay at the source node NS. The second NMOS transistor M2 is used based on a second bias voltage. V b2 The established bias condition receives the drain voltage at the drain node ND. V d and the output voltage is output at the output node NO. V o Here, " V DD "Indicates a power supply node, while" V s This represents the voltage located at the source node NS. This first bias voltage. V b1 With the second bias voltage V b2 It is appropriately determined so that both the first NMOS transistor M1 and the second NMOS transistor M2 are biased in the saturation region.

[0080] In an alternative embodiment (not shown) Figure 2 (However, it is clear to those skilled in the art that) the first bias voltage V b1 The DC coupling to the gate node NG is cut off, and instead, the DC coupling resistor RB is set across the gate node NG and the drain node ND. In this example, the first NMOS transistor M1 is referred to as "self-biased," a concept well known to those skilled in the art, and therefore will not be described in detail here.

[0081] Load network 250 is a resonant tank comprising a load inductor 251 and a load capacitor 252 connected in parallel, wherein a resonant frequency of the resonant tank is approximately equal to an input voltage. V i The frequency of interest, the input voltage V i This refers to the voltage at the input node NI. In one embodiment, the load capacitor 252 is adjustable and can be adjusted according to the frequency in question. The concept and embodiments of adjustable capacitors are well known to those skilled in the art, and therefore their details are not described herein.

[0082] In one embodiment, the LNA 200 is fabricated on a silicon substrate using a 55-nanometer CMOS process, but this is not a limitation of the present invention. In the above embodiment, the LNA 200 includes multiple metal layers and a via layer. The multiple metal layers include a redistribution layer (RDL) and an ultra-thick metal (UTM) layer, and the via layer is used to create a connection between the metal on the RDL and the metal on the UTM layer. Figure 3 A top view of a layout of a matching network 260 is shown according to an embodiment of the present disclosure. Block 310 shows... Figure 3The diagram illustrates the following. The bypass inductor L1 is implemented using metal traces 321 (on the RDL) and 323 (on the UTM layer). Metal trace 321 extends from the input node NI to a contact 322. Metal trace 323 spirals outward in a clockwise direction (from contact 322 to ground). At contact 322, metal traces 321 and 323 are connected together via a via. Metal trace 321 further extends to contact 331. The series inductor L2 is implemented using metal traces 332 (on the UTM layer) and 334 (on the RDL). Metal trace 332 spirals outward in a clockwise direction (from contact 331 to contact 333). Metal trace 334 extends from contact 333 to the mating node NM. Metal trace 332 is connected to metal trace 321 via a via located at contact 331, and metal trace 334 is connected to metal trace 332 via a via located at contact 333. The source attenuation inductor L3 is implemented using metal trace 341 (located on the UTM layer). Metal trace 341 extends from the source node NS to ground. As shown, the bypass inductor L1 and the series inductor L2 are stacked and arranged in a concentric structure. The source attenuation inductor L3 is arranged in close proximity to the bypass inductor L1 and parallel to the last section of the bypass inductor L1.

[0083] In a non-restrictive paradigm: V DD The voltage is 1.3V; the frequency range that is of concern is between 5.1GHz and 7.2GHz; the inductance value of the bypass inductor L1 is 3.7nH; the inductance value of the series inductor L2 is 1.1nH; the inductance value of the source attenuation inductor L3 is 75pH; It is 0.5; The value is 0.2; the gate capacitance CG is 1pF; the W / L ratio of the NMOS transistor M1 (which represents...) is... )for ;RB is 36 k Ohm; V b1 The voltage is 0.5V; the W / L of the NMOS transistor M2 is... ; V b2 The voltage is 1.1V; the inductance of the load inductor 251 is 1nH; and the adjustment range of the load capacitor 252 is between 50fF and 400fF.

[0084] The integration of the source attenuation inductor L3 gives the input impedance of the stacked amplifier 230 a real part, which is important for impedance and noise matching. However, while this feature is desirable, it is not absolutely necessary. In other words, the designer can choose to remove the source attenuation inductor L3, and the performance of the LNA 200 may degrade. In practice, even if the designer chooses to remove the source attenuation inductor L3, the designer still needs to connect the source node NS to ground via a metal trace. This inevitably exhibits an inductive nature and is equivalent to a parasitic inductance located next to the adjacent inductor L1, which is also connected to ground. In other words, in practice, even if the designer chooses to remove the source attenuation inductor L3, it will still exist there, albeit as a parasitic inductance. Therefore, Figure 2 The illustration and the relationship with Figure 2 The related appended claims are still valid in the above context.

[0085] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on its explicit or implicit content. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of this specification.

Claims

1. A low-noise amplifier, comprising: A matching network is used to provide three-way coupling between an input node, a matching node, and a source node; A gate capacitor is used to provide AC coupling between the matched node and a gate node; A cascaded amplifier is used to receive a gate voltage at the gate node and output an output voltage at an output node based on the source attenuation of the source node. as well as A load network is coupled to the output node, wherein the matching network includes a bypass inductor, a series inductor, and a source attenuation inductor. The bypass inductor and the series inductor are stacked in a layout to have strong mutual coupling, and the source attenuation inductor is positioned next to the bypass inductor to have strong mutual coupling. The bypass inductor and the series inductor are arranged in a concentric structure, and both the bypass inductor and the series inductor are spiraled outward in the same direction.

2. The low-noise amplifier of claim 1, wherein a portion of the source attenuation inductor is adjacent to and parallel to a portion of the tail end of the bypass inductor.

3. The low-noise amplifier of claim 1, wherein the stacked amplifier comprises a common-source stage and a common-gate stage; the common-source stage comprises a first N-channel metal-oxide-semiconductor transistor, the first N-channel metal-oxide-semiconductor transistor being configured to receive the gate voltage at the gate node and output a drain voltage at a drain node according to the source attenuation of the source node; the common-gate stage comprises a second N-channel metal-oxide-semiconductor transistor, the second N-channel metal-oxide-semiconductor transistor being configured to receive the drain voltage at the drain node and output the output voltage at the output node.

4. The low-noise amplifier of claim 3, wherein the stacked amplifier further includes a DC coupling resistor for coupling a first bias voltage to the gate node.

5. The low-noise amplifier of claim 3, wherein the stacked amplifier further includes a DC coupling resistor configured to bridge the gate node and the drain node.

6. The low-noise amplifier of claim 1, wherein the load network includes a load inductor and a load capacitor connected in a bypass manner.

7. The low-noise amplifier of claim 6, wherein the load capacitance is adjusted according to a frequency relevant to an input voltage at the input node.

8. A low-noise amplifier, comprising: An inductor is connected on one side to transfer an input node to ground; A series of inductors is used to couple the input node to a matching node; A source attenuation inductor is used to couple a source node to ground; A gate capacitor is used to couple the matched node to a gate node; A cascaded amplifier is used to receive a gate voltage at the gate node and output an output voltage at an output node based on the source attenuation of the source node. as well as A load network is coupled to the output node, wherein the bypass inductor and the series inductor are stacked in a layout to have strong mutual coupling, and the source attenuation inductor is placed next to the bypass inductor to have strong mutual coupling. The bypass inductor and the series inductor are arranged in a concentric structure, and both the bypass inductor and the series inductor are spiraled outward in the same direction.

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