Base chip, memory system, and semiconductor structure

Abstract

Embodiments of the present application provide a base chip, a storage system and a semiconductor structure. The base chip is configured to receive first data and first encoded data and perform first error detection and correction processing in a write phase, the first encoded data is obtained by performing first error correction code encoding processing on the first data, and second error correction code encoding processing is performed on the first data after the first error detection and correction processing. In the write phase, based on a selection signal, the base chip selects to transmit to-be-written data to a storage chip, the to-be-written data is one of initial data or second data, the second data includes second encoded data and the first data after the first error detection and correction processing, and the initial data includes the first data and the first encoded data. In a read phase, based on the selection signal, the base chip selects to transmit the initial data or third data, the third data includes third encoded data and the first data after the second error detection and correction processing. Embodiments of the present application can improve the read-write performance of the storage system.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular, to a base chip, a storage system, and a semiconductor structure. BACKGROUND

[0002] Semiconductor storage can be divided into non-volatile storage and volatile storage. Dynamic random access memory (DRAM) as volatile storage has advantages of high storage density and fast read-write speed, and is widely used in various electronic systems.

[0003] With the increasingly advanced process technology and higher storage density of DRAM, errors may occur in the stored data in the DRAM, which seriously affects the performance of the DRAM. Therefore, the error checking and correction (ECC) technology is usually used in the DRAM to detect or correct errors in the stored data. SUMMARY

[0004] Embodiments of the present application provide a base chip, a storage system, and a semiconductor structure, which at least benefit the problem of controller or storage chip area shortage.

[0005] According to some embodiments of the present application, the embodiments of the present application provide a base chip applied to a storage system, comprising: the base chip is configured to, in a write phase, receive first data and first encoded data and perform first error detection and correction processing, the first encoded data is obtained by performing first error correction code encoding processing on the first data, and second error correction code encoding processing is performed on the first data after the first error detection and correction processing to generate second encoded data, in the write phase, based on a selection signal, selecting to transmit to-be-written data to a storage chip, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data and the first data after the first error detection and correction processing, and the initial data comprising the first data and the first encoded data; the base chip is further configured to, if the to-be-written data is the second data, in a read phase, receiving the second data from the storage chip and performing second error detection and correction processing, performing third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoded data, and in the read phase, based on the selection signal, selecting to transmit read data, the read data being one of third data or the initial data from the storage chip, the third data comprising the third encoded data and the first data after the second error detection and correction processing.

[0006] In addition, the base chip comprises: a first error detection and correction module configured to receive the first data and the first encoded data in the write stage and perform the first error detection and correction processing; a second encoding module configured to receive the first data after the first error detection and correction processing and perform the second error correction code encoding processing to generate the second encoded data; a second error detection and correction module configured to receive the second data in the read stage and perform the second error detection and correction processing; a third encoding module configured to receive the first data after the second error detection and correction processing in the read stage and perform the third error correction code encoding processing to generate the third encoded data; a first selection module configured to select one of the initial data or the second data to be transmitted to the storage chip based on the selection signal; and a second selection module configured to output read data based on the selection signal, the read data being one of the third data or the initial data from the storage chip.

[0007] In addition, the base chip further comprises: a first serial-parallel conversion module configured to receive the first data and the first encoded data in the write stage, perform first serial-parallel conversion processing on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-parallel conversion processing to the first error detection and correction module and the first selection module; and a first parallel-serial conversion module configured to receive the read data from the second selection module in the read stage, perform first parallel-serial conversion processing on the read data, and transmit the read data after the first parallel-serial conversion processing to the controller.

[0008] In addition, the base chip further comprises: a second parallel-serial conversion module configured to receive the to-be-written data from the first selection module in the write stage and perform second parallel-serial conversion processing, and transmit the to-be-written data after the second parallel-serial conversion processing to the storage chip; and a second serial-parallel conversion module configured to receive the second data or the initial data from the storage chip in the read stage and perform second serial-parallel conversion processing.

[0009] In addition, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction processing, and record error conditions of the first data and the first encoded data in the transmission process based on the first error detection flag signal.

[0010] In addition, the base chip further comprises a first storage buffer module configured to store error conditions of the first data and the first encoded data in the transmission process; a first command module configured to receive a first polling instruction and generate a first command signal and a first clock signal; and the first storage buffer module is further configured to output a first representation signal based on the first command signal and the first clock signal, the first representation signal representing error conditions of the first data or the first encoded data in the transmission process.

[0011] In addition, the base chip is further configured to generate a second error detection flag signal during the second error detection and correction processing, and record error conditions of the second encoded data and the first data after the first error detection and correction processing in the transmission process based on the second error detection flag signal.

[0012] In addition, the base chip further comprises a second storage buffer module configured to store error conditions of the second encoded data and the first data after the first error detection and correction processing in the transmission process; a second command module configured to receive a second polling instruction and generate a second command signal and a second clock signal; and the second storage buffer module is further configured to output a second representation signal based on the second command signal and the second clock signal, the second representation signal representing error conditions of the second encoded data or the first data after the first error detection and correction processing in the transmission process.

[0013] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a storage system, comprising a controller, a base chip and a storage chip; the controller is configured to perform first error correction code encoding processing on first data in a write phase to generate first encoded data, and transmit the first data and the first encoded data to the base chip; the base chip is configured to receive the first data and the first encoded data in the write phase and perform first error detection and correction processing, and perform second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoded data, and select to transmit to-be-written data to the storage chip based on a selection signal in the write phase, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data and the first data after the first error detection and correction processing, and the initial data comprising the first data and the first encoded data; the base chip is further configured to, if the to-be-written data is the second data, receive the second data from the storage chip and perform second error detection and correction processing in a read phase, perform third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoded data, and select to transmit read data to the controller based on the selection signal in the read phase, the read data being one of third data or the initial data from the storage chip, the third data comprising the third encoded data and the first data after the second error detection and correction processing; the storage chip is configured to receive the to-be-written data and store the to-be-written data in the write phase, and transmit the read data to the base chip in the read phase; the controller is further configured to receive the read data in the read phase, perform third error detection and correction processing on the read data, and obtain the first data after the third error detection and correction processing.

[0014] In addition, the controller comprises: a first encoding module configured to perform the first error correction code encoding processing on the first data in the write phase to generate the first encoded data; and a third error detection and correction module configured to receive the read data and perform the third error detection and correction processing in the read phase.

[0015] In addition, the base chip comprises: a first error detection and correction module configured to receive the first data and the first encoded data in the write stage and perform the first error detection and correction processing; a second encoding module configured to receive the first data after the first error detection and correction processing in the write stage and perform the second error correction code encoding processing to generate the second encoded data; a second error detection and correction module configured to receive the second data in the read stage and perform the second error detection and correction processing; a third encoding module configured to receive the first data after the second error detection and correction processing in the read stage and perform the third error correction code encoding processing to generate the third encoded data; a first selection module configured to select one of the initial data or the second data to be transmitted to the storage chip based on the selection signal; and a second selection module configured to output read data based on the selection signal, the read data being one of the third data or the initial data from the storage chip.

[0016] In addition, the base chip further comprises: a first serial-parallel conversion module configured to receive the first data and the first encoded data in the write stage, perform first serial-parallel conversion processing on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-parallel conversion processing to the first error detection and correction module and the first selection module; and a first parallel-serial conversion module configured to receive the read data from the second selection module in the read stage, perform first parallel-serial conversion processing on the read data, and transmit the read data after the first parallel-serial conversion processing to the controller.

[0017] In addition, the base chip further comprises: a second parallel-serial conversion module configured to receive the to-be-written data from the first selection module in the write stage, perform second parallel-serial conversion processing, and transmit the to-be-written data after the second parallel-serial conversion processing to the storage chip; and a second serial-parallel conversion module configured to receive the second data or the initial data from the storage chip in the read stage and perform second serial-parallel conversion processing.

[0018] In addition, the first error correction code encoding process, the first error detection and correction process, the third error correction code encoding process and the third error detection and correction process are performed by using a first encoding algorithm, and the second error correction code encoding process and the second error detection and correction process are performed by using a second encoding algorithm, and the first encoding algorithm is different from the second encoding algorithm.

[0019] In addition, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record error conditions of the first data and the first encoded data in the transmission process based on the first error detection flag signal; and the storage system further comprises a first register configured to store the error conditions of the first data and the first encoded data in the transmission process.

[0020] In addition, the base chip is further configured to generate a second error detection flag signal during the second error detection and correction process, and record error conditions of the second encoded data and the first data after the first error detection and correction process in the transmission process based on the second error detection flag signal; and the storage system further comprises a second register configured to store the error conditions of the second encoded data and the first data after the first error detection and correction process in the transmission process.

[0021] In addition, the controller is further configured to generate a third error detection flag signal during the third error detection and correction process, and record error conditions of the first data after the second error detection and correction process in the transmission process based on the third error detection flag signal; and the storage system further comprises a third register configured to store the error conditions of the first data after the second error detection and correction process in the transmission process.

[0022] According to some embodiments of the present application, a further aspect of the embodiments of the present application further provides a semiconductor structure, comprising: a carrier substrate; the storage system, and the controller and the base chip are located on the surface of the carrier substrate, and the storage chip is located on the surface of the base chip away from the carrier substrate.

[0023] The technical scheme provided by the embodiments of the present application has the following advantages:

[0024] In the technical solution of the base chip provided in the embodiment of the present application, the base chip selects whether to participate in error correction code encoding processing and error detection and correction processing based on a selection signal in a data transmission process. On the one hand, the base chip can share the error detection and correction function required by the controller, which is conducive to saving the chip area required by the controller and reducing the chip design difficulty of the controller. On the other hand, the base chip can select whether to perform data error detection and correction based on the selection signal, which can meet different requirements of data error detection and correction capability and meet different requirements of data transmission rate. Specifically, if the base chip does not participate in data error detection and correction processing, the data transmission rate is fast. If the base chip participates in data error detection and correction processing, the data error detection and correction capability is high, and the data error detection and correction accuracy can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0025] One or more embodiments are illustrated by way of example in the figures that form a part of this patent document. These example are not intended to limit the application, but to clarify and explain the principles of the at least one embodiment. The accompanying drawings include identical or similar components that have been given the same reference numerals, and will be limited to the extent that the drawings are not necessarily to scale.

[0026] Figure 1 is a structural schematic diagram of a semiconductor structure;

[0027] Figure 2 is Figure 1 is a data transmission schematic diagram in the semiconductor structure provided;

[0028] Figures 3 to 6 is a structural schematic diagram of a base chip provided in the embodiment of the present application;

[0029] Figures 7-10 is a structural schematic diagram of a storage system provided in the embodiment of the present application

[0030] Figure 11 is a sectional structural schematic diagram of a semiconductor structure provided in the embodiment of the present application. DETAILED DESCRIPTION

[0031] Figure 1 is a structural schematic diagram of a semiconductor structure, Figure 2 is Figure 1 a data transmission schematic diagram in the semiconductor structure provided.

[0032] With reference to Figure 1 , the semiconductor structure can include: a substrate 11; a base chip (base die) 12 and a controller (processor) 13 respectively located on the surface of the substrate 11; a plurality of core chips (core die) 14 are stacked on the base chip 12, and the core chip 14 can be a DRAM chip. With reference to Figure 2, the data transmission process in the semiconductor structure includes: in the writing stage, the controller 13 transmits data to the base chip 12, the base chip 12 transmits data to the core chip 14, and the controller 13 can perform error correction code encoding processing on the data before transmitting the data; in the reading stage, the core chip 14 transmits data to the base chip 12, then the base chip 12 transmits data to the controller 13, the controller 13 receives data and performs error correction code decoding processing to detect and correct errors of the data.

[0033] It can be found that in the above semiconductor structure, the base chip 12 does not participate in the error detection and correction processing, that is, the base chip 12 does not have error correction code encoding function and corresponding error detection and correction function, and the controller 13 or the core chip 14 needs to complete the error detection and correction, which causes the chip area of the controller 13 and the core chip 14 to be more nervous, and thus affects the performance of the controller 13 and the core chip 14, and further causes the storage performance of the whole semiconductor structure to be improved.

[0034] The present application provides a base chip, a storage system and a semiconductor structure. Figure 3 The first structure schematic diagram of the base chip provided by some embodiments of the present application is shown in the following figure, Figure 4 The second structure schematic diagram of the base chip provided by some embodiments of the present application is shown in the following figure, Figure 5 The third structure schematic diagram of the base chip provided by some embodiments of the present application is shown in the following figure, Figure 6 The structure schematic diagram based on the above. Figure 4

[0035] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present application, many technical details are proposed in order to make the reader better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed by the present application can be realized.

[0036] Reference is made to Figure 3 ​, the base chip 100 is configured to receive the first data data1 and the first encoded data ecc1 and perform first error detection and correction processing in a write phase, the first encoded data ecc1 is obtained by performing first error correction code encoding processing on the first data data1, and second error correction code encoding processing is performed on the first data data1 after the first error detection and correction processing to generate second encoded data ecc2, and the base chip 100 is configured to select to transmit the data to be written to the storage chip based on the selection signal SEL in the write phase, the data to be written is one of the initial data data0 or the second data, the second data includes the second encoded data ecc2 and the first data data1 after the first error detection and correction processing, and the initial data data0 includes the first data data1 and the first encoded data ecc1; the base chip 100 is further configured to, if the data to be written is the second data, receive the second data from the storage chip and perform second error detection and correction processing in a read phase, and perform third error correction code encoding processing on the first data data1 after the second error detection and correction processing to generate third encoded data ecc3, and select to transmit the read data based on the selection signal SEL in the read phase, the read data is one of the third data or the initial data data0 from the storage chip, and the third data includes the third encoded data ecc3 and the first data data1 after the second error detection and correction processing.

[0037] In the embodiment of the application, the base chip 100 selects whether to participate in error correction code encoding processing and error detection and correction processing based on the selection signal SEL in the data transmission process. On the one hand, the base chip 100 can share the error detection and correction function required by the controller, which is beneficial to save the chip area required by the controller and reduce the chip design difficulty of the controller. On the other hand, the base chip 100 can select whether to perform data error detection and correction based on the selection signal SEL, which can meet different requirements of data error detection and correction capability and meet different requirements of data transmission rate. Specifically, if the base chip 100 does not participate in data error detection and correction processing, the data transmission rate is fast; if the base chip 100 participates in data error detection and correction processing, the data error detection and correction capability is high, and the data error detection and correction accuracy can be improved.

[0038] In some embodiments, the base chip 100 can be connected between a first port A and a second port B, wherein the first port A is connected with a data transmission port of a controller of the storage system, and the second port B is connected with a data transmission port of a storage chip of the storage system. It can be understood that the first port A and the second port B are collectively referred to, the first port A includes a plurality of data transmission ports, and the second port B includes a plurality of data transmission ports, wherein the number of data transmission ports is related to the number of data to be transmitted by the base chip 100, for example, the number of data transmission ports can be the same as the number of data to be transmitted by the base chip 100, and one data can be transmitted through one data transmission port.

[0039] The error correction code encoding process and the error detection and correction process are both used to implement ECC error detection and correction, to find and locate errors occurring in the first data transmission process, and to correct the errors. In some embodiments, the ECC error detection and correction can use the error correction mechanism of Reed Solomon Code (RS), and accordingly, the error correction code encoding process can use the RS encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process can use the RS decoding algorithm. In other embodiments, the ECC error detection and correction can use the error correction mechanism of Hamming Code, and accordingly, the error correction code encoding process can use the Hamming Code encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process can use the Hamming Code decoding algorithm.

[0040] In some embodiments, the first data data1 can be 256-bit data, and accordingly, the first encoded data ecc1 can be 16-bit data. It can be understood that in other embodiments, the number of bits of the first encoded data can also be different accordingly, due to the difference in the specific algorithm used by the first error correction code encoding process. In addition, the number of bits of the first data data1 can also be other quantities, such as 128, 512, etc.

[0041] Figure 4 A second structure diagram of the base chip provided by the embodiments of the present application is provided. Referring to FIG. 2, the base chip 100 can be connected between a first port A and a second port B, wherein the first port A is connected with a data transmission port of a controller of the storage system, and the second port B is connected with a data transmission port of a storage chip of the storage system. It can be understood that the first port A and the second port B are collectively referred to, the first port A includes a plurality of data transmission ports, and the second port B includes a plurality of data transmission ports, wherein the number of data transmission ports is related to the number of data to be transmitted by the base chip 100, for example, the number of data transmission ports can be the same as the number of data to be transmitted by the base chip 100, and one data can be transmitted through one data transmission port. Figure 4In some embodiments, the base chip 100 can include: a first error detection and correction module 110 configured to receive and perform first error detection and correction processing on the first data data1 and the first encoded data ecc1 in the write phase; a second encoding module 111 configured to receive the first data data1 after the first error detection and correction processing and perform second error correction code encoding processing to generate second encoded data ecc2 in the write phase; a second error detection and correction module 121 configured to receive and perform second error detection and correction processing on the second data in the read phase; a third encoding module 120 configured to receive the first data data1 after the second error detection and correction processing and perform third error correction code encoding processing to generate third encoded data ecc3 in the read phase; a first selection module S1 configured to select one of the initial data data0 or the second data to be transmitted to the memory chip based on a selection signal SEL; and a second selection module S2 configured to output read data based on the SEL selection signal, the read data being one of the third data or the initial data data0 from the memory chip.

[0042] It can be understood that if the data to be written is the initial data data0, i.e., the data to be written is the first data data1 and the first encoded data ecc1 from the controller, the read data is the initial data data0 from the memory chip, i.e., the read data is the first data data1 and the first encoded data ecc1 from the memory chip, the first data data1 not being subjected to error detection and correction processing; if the data to be written is the second data, i.e., the data to be written is the second encoded data ecc2 and the first data data1 after the first error detection and correction processing, the read data is the third data, the third data including the third encoded data ecc3 and the first data data1 after the second error detection and correction processing.

[0043] The first error detection and correction processing can detect errors in the transmission of the first data data1 and the first encoded data ecc1 from the controller to the base chip 100, and correct the errors if any. The second error detection and correction processing can detect errors in the transmission of the second data between the base chip 100 and the storage chip, and correct the errors if any. It can be understood that the transmission of the second data between the base chip 100 and the storage chip includes the transmission of the second data from the base chip 100 to the storage chip in the writing stage, and the transmission of the second data from the storage chip to the base chip 100 in the reading stage. In this way, the data transmission of at least two transmission paths can be detected and corrected, which is beneficial to locating the specific path of the data transmission error, and the at least twice error detection and correction processing is beneficial to improving the accuracy of data correction.

[0044] The first selection module S1 and the second selection module S2 are configured to provide a selection of whether the base chip 100 participates in the ECC error detection and correction in the entire storage system. The first selection module S1 and the second selection module S2 are configured to determine whether the base chip 100 participates in the ECC error detection and correction under different conditions of the required storage rate and the required data accuracy of the storage system.

[0045] In addition, the third encoding module 120 performs a third error correction code encoding process on the first data data1 after the second error detection and correction processing, so as to transmit the third encoded data ecc3 and the first data data1 after the second error detection and correction processing to the controller, so that the controller can perform the error detection and correction processing on the first data again in the reading stage, which is beneficial to further improving the accuracy of data correction.

[0046] In addition, it can be understood that the first error correction code encoding process and the second error correction code encoding process can be performed by different encoding algorithms. For example, the first encoded data ecc1 can be 16-bit data, and the second encoded data ecc2 can be 32-bit data. Correspondingly, the first error detection and correction processing and the second error detection and correction processing can be performed by different decoding algorithms, i.e., the first error correction code encoding process and the first error detection and correction processing are performed by a first decoding algorithm, and the second error correction code encoding process and the second error detection and correction processing are performed by a second decoding algorithm. The first decoding algorithm and the second decoding algorithm can be different. The ECC error detection and correction is performed by different decoding algorithms, which is beneficial to further improving the accuracy of data correction and reducing the difficulty of the base chip 100 in identifying different encoded data. In some other embodiments, the first decoding algorithm and the second decoding algorithm can be the same.

[0047] The second encoding module 111 is connected between the first error detection and correction module 110 and the memory chip, and the second error detection and correction module 121 is connected between the memory chip and the third encoding module 120. The second error detection and correction module 121 receives the second encoding data ecc2 and the first data data1 after the first error detection and correction processing, and performs second error detection and correction processing on the second encoding data ecc2 and the first data data1 after the first error detection and correction processing.

[0048] It should be noted that "first", "second" and "third" in the embodiments of the present application are only for distinguishing the description, and the order of appearance of each feature is not particularly limited.

[0049] The working principle of the base chip 100 will be described in detail below. Figure 4 The working principle of the base chip 100 will be described in detail below.

[0050] In the first case, the first selection module S1 and the second selection module S2 determine that the base chip 100 does not participate in ECC error detection and correction under the control of the selection signal SEL:

[0051] In the write-in stage, the initial data from the controller is stored in the memory chip through the first selection module S1, and the initial data includes the first data data1 from the controller and the first encoding data ecc1; in the read stage, the read data from the memory chip is transmitted to the controller through the second selection module S2, and the read data is the first data data1 from the memory chip and the first encoding data ecc1, and the first data data1 is the first data data1 without error detection and correction processing.

[0052] In the above storage process, the base chip 100 does not participate in ECC error detection and correction, and the controller performs error detection and correction, which is beneficial to improve the data transmission rate.

[0053] In the second case, the first selection module S1 and the second selection module S2 determine that the base chip 100 participates in ECC error detection and correction under the control of the selection signal SEL:

[0054] In the write-in stage, the first data data1 and the first encoding data ecc1 from the controller are transmitted to the first error detection and correction module, and the first error detection and correction module 110 performs first error detection and correction processing, and then transmits the first data data1 after the first error detection and correction processing to the second encoding module 111 for second error correction code encoding processing to generate second encoding data ecc2. Then, the second encoding data ecc2 and the first data data1 after the first error detection and correction processing are stored in the memory chip through the first selection module S1.

[0055] In the reading stage, the second encoded data ecc2 from the memory chip and the first data data1 after the first error detection and correction processing are transmitted to the second error detection and correction module 121 to perform the second error detection and correction processing, and the first data data1 after the second error detection and correction processing is transmitted to the third encoding module 120 to perform the third error correction code encoding processing to generate the third encoded data ecc3, and the third encoded data ecc3 and the first data data1 after the second error detection and correction processing are transmitted to the controller via the second selection module S2, and the third encoded data ecc3 and the first data data1 after the second error detection and correction processing are the read data.

[0056] In the above storage process, the controller and the base chip 100 participate in the ECC error detection and correction, which is beneficial to improve the data error detection and correction accuracy.

[0057] Figure 5 A third structure diagram of the base chip provided in the embodiments of the present application is shown. Referring to Figure 5 In some embodiments, the base chip 100 can further include: a first DES module 130 configured to receive the first data data1 and the first encoded data ecc1 in the writing stage, perform first DES processing on the first data data1 and the first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 after the first DES processing to the first error detection and correction module 110 and the first selection module S1; and a first SER module 140 configured to receive the read data from the second selection module S2 in the reading stage, perform first SER processing on the read data, and transmit the read data after the first SER processing to the controller.

[0058] The first DES module 130 and the first SER module 140 can reduce the number of transmission channels between the base chip 100 and the controller, increase the number of bit positions transmitted by each transmission channel, and save the number of data transmission ports required to be arranged on the base chip 100 and the controller, thereby saving the chip area of the base chip 100 and the chip area of the controller. The first data data1 is transmitted to the first DES module 130 in a serial manner, and the first DES module 130 can also be referred to as a deserializer, that is, the first data data1 and the first encoded data ecc1 in a serial manner are deserialized. The first SER module 140 serially processes the read data and transmits the read data after the serial processing, and the first SER module 140 can also be referred to as a serializer.

[0059] For example, the first data data1 is 256 bits, and the first data data1 is transmitted to the first serial-parallel conversion module 130 through 32 transmission channels. The first encoded data ecc1 is 16 bits, and the first encoded data ecc1 is transmitted to the first serial-parallel conversion module 130 through 2 transmission channels. After the first data data1 and the first encoded data ecc1 are deserialized by the first serial-parallel conversion module 130, the first data data1 is transmitted to the first error detection and correction module 110 in parallel through 256 transmission channels, and the first encoded data ecc1 is transmitted to the first error detection and correction module 110 through 16 transmission channels.

[0060] If the base chip 100 does not participate in ECC error detection and correction, the read data is 256 bits + 16 bits, where the 256 bits are the first data data1 that has not been subjected to error detection and correction processing, and the 16 bits are the first encoded data ecc1. After the read data is serialized by the first parallel-serial conversion module 140, the read data can become 32 + 2 serial data, and the 32 + 2 serial data can be transmitted through 32 + 2 transmission channels. The 32 serial data is the first data data1, and the 2 serial data is the first encoded data ecc1.

[0061] If the base chip 100 participates in ECC error detection and correction, the read data is 256 bits + 16 bits, where the 256 bits are the first data data1 that has been subjected to second error detection and correction processing, and the 16 bits are the third encoded data ecc3. After the read data is serialized by the first parallel-serial conversion module 140, the read data can become 32 + 2 serial data, and the 32 + 2 serial data can be transmitted through 32 + 2 transmission channels. The 32 serial data is the first data data1 that has been subjected to second error detection and correction processing, and the 2 serial data is the third encoded data ecc3.

[0062] Reference Figure 5 In some embodiments, in addition to the first serial-parallel conversion module 130 and the first parallel-serial conversion module 140, the base chip 100 can further include a second parallel-serial conversion module 150 configured to receive data to be written from the first selection module S1 in a writing stage and perform second parallel-serial conversion processing, and transmit the data to be written after the second parallel-serial conversion processing to a storage chip. The base chip 100 can further include a second serial-parallel conversion module 160 configured to receive second data or initial data from the storage chip in a reading stage and perform second serial-parallel conversion processing.

[0063] The second parallel-serial conversion module 150 serially processes the data to be written, which is conducive to reducing the transmission channel between the base chip 100 and the storage chip, thereby saving the number of data transmission ports required to be set on the base chip 100 and the storage chip, and further saving the chip area of the base chip 100 and the chip area of the storage chip. For example, if the base chip 100 participates in ECC error detection and correction, the data to be written includes the first data data1 of 256 bits after the first error detection and correction processing and the second encoded data ecc2 of 32 bits. After the parallel-serial conversion processing by the second parallel-serial conversion module 150, 128+16 transmission channels can be used to transmit the data to be written to the storage chip, wherein the 128 transmission channels transmit the first data data1 after the first error detection and correction processing, and the 16 transmission channels transmit the second encoded data ecc2.

[0064] If the base chip 100 participates in ECC error detection and correction, the second serial-parallel conversion module 160 parallelly processes the second data transmitted from the storage chip, that is, serial-parallel conversion processing is performed on the second data, and the second data after the serial-parallel conversion processing is transmitted to the second error detection and correction module 121. If the base chip 100 does not participate in ECC error detection and correction, the second serial-parallel conversion module 160 parallelly processes the initial data transmitted from the storage chip to be transmitted to the controller.

[0065] In addition, in some embodiments, the base chip 100 can also be configured to generate a first error detection flag signal during the error detection and correction processing, and record the error condition of the first data data1 and the first encoded data ecc1 in the transmission process based on the first error detection flag signal. Specifically, if the first data data1 or the first encoded data ecc1 has an error in the transmission process, the first error detection flag signal is generated; if the first data data1 and the first encoded data ecc1 have no error in the transmission process, the first error detection flag signal is not generated. In addition, in some embodiments, the first error detection flag signal can be defined as: if the first data data1 or the first encoded data ecc1 has an error in the transmission process, the first error detection flag signal is 1; if the first data data1 and the first encoded data ecc1 have no error in the transmission process, the first error detection flag signal is 0. In other embodiments, the first error detection flag signal can also be defined as: if the first data data1 or the first encoded data ecc1 has an error in the transmission process, the first error detection flag signal is 0; if the first data data1 and the first encoded data ecc1 have no error in the transmission process, the first error detection flag signal is 1.

[0066] The first error detection flag signal can be used to determine whether the first data data1 or the first encoded data ecc1 is in error in the data transmission path from the controller to the base chip 100 during the write stage.

[0067] As shown in Figure 6 , Figure 6 the first data data1 and the first encoded data ecc1 are stored in the first storage buffer module 101. Figure 4 In some embodiments, the base chip 100 can further include a first storage buffer module 101 configured to store error conditions of the first data data1 and the first encoded data ecc1 during transmission; a first command module 102 configured to receive the first polling instruction PS1 and generate a first command signal CMD1 and a first clock signal CLK1; and the first storage buffer module is further configured to output a first representation signal flag1 based on the first command signal CMD1 and the first clock signal CLK1, the first representation signal flag1 representing the error conditions of the first data data1 or the first encoded data ecc1 during transmission.

[0068] It can be understood that the error conditions of the first data data1 and the first encoded data ecc1 during transmission refer to the error conditions of the first data data1 and the first encoded data ecc1 during transmission from the controller to the base chip 100.

[0069] In addition, in the case where the first polling instruction PS1 is not received, the first storage buffer module 101 only stores the error conditions of the first data data1 and the first encoded data ecc1 during transmission; the first command module 102 controls the first storage buffer module 101 to output the first representation signal flag1 representing the error conditions of the first data data1 or the first encoded data ecc1 during transmission after receiving the first polling instruction PS1. Based on the first representation signal flag1, the error conditions of the first data data1 and the first encoded data ecc1 can be determined.

[0070] In some embodiments, the first characteristic signal flag1 can be a binary number string, for example, if the first data data1 or the first encoded data ecc1 is detected to be in error during transmission, a 1 is recorded, and if the first data data1 and the first encoded data ecc1 are not detected to be in error during transmission, a 0 is recorded, so that after a period of time, the first characteristic signal flag1 is a binary number string composed of 0 and 1. In other embodiments, the first characteristic signal flag1 can also be a decimal value, for example, the first storage buffer module 101 can be a counter, and if the first data data1 is detected to be in error during transmission, the counter is incremented by 1, so that after a period of time, the first characteristic signal flag1 is a decimal value related to the number of errors.

[0071] In some embodiments, the first storage buffer module 101 can be a first-in first-out (FIFO) register. Using a first-in first-out register as the first storage buffer module 101 can buffer continuous data streams and prevent data loss during storage operations. In addition, the errors of the first data data1 during transmission are collected and stored, which can avoid frequent bus operations and improve data transmission speed.

[0072] In addition, in some embodiments, the first clock signal CLK1 can be independently generated by the first command module 102; in other embodiments, the first clock signal CLK1 can also be externally provided, for example, generated by a controller generating the first polling instruction PS1.

[0073] In some embodiments, referring to Figure 6 The base chip 100 can also be configured to generate a second error detection flag signal during the second error detection and correction processing, and based on the second error detection flag signal, record the error of the second encoded data ecc2 and the first data data1 after the first error detection and correction processing during transmission. Through the second error detection flag signal, it can be determined whether the second encoded data ecc2 and the first data data1 are in error in the data transmission path from the storage chip to the base chip 100 during the reading stage.

[0074] For detailed description of the second error detection flag signal, reference can be made to the corresponding description of the first error detection flag signal described above, which will not be repeated here.

[0075] Referring to Figure 6In some embodiments, the base chip 100 can also include a second storage buffer module 131 configured to store the second encoded data ecc2 and the error condition of the first data data1 in the transmission process after the first error detection and correction processing; a second command module 132 receiving the second polling instruction PS2 and generating a second command signal CMD2 and a second clock signal CLK2; the second storage buffer module 131 is further configured to output a second characteristic signal flag2 based on the second command signal CMD2 and the second clock signal CLK2, the second characteristic signal flag2 representing the error condition of the second encoded data ecc2 and the first data data1 in the transmission process after the first error detection and correction processing.

[0076] The detailed description of the second storage buffer module 131 can refer to the foregoing description of the first storage buffer module 101, and the detailed description of the second command module 132 can refer to the foregoing description of the first command module 102, which will not be repeated here.

[0077] The base chip 100 provided by the above embodiments not only has the function of data transmission, but also has the functions of error correction code encoding processing and error detection and correction processing. Therefore, the chip area of the base chip 100 can be effectively utilized, the chip area pressure of the controller and the storage chip can be reduced, and the chip area of the controller and the storage chip can be saved.

[0078] In addition, the base chip 100 can also have the functions of data serial processing and deserial processing, which is beneficial to reduce the transmission channel between the controller and the base chip 100, reduce the transmission channel between the storage chip and the base chip 100, thereby saving the number of data transmission ports required on the controller, the base chip 100 and the storage chip, and further saving the chip area of the controller, the base chip 100 and the storage chip.

[0079] In addition, the first error detection and correction module 110 and the second error detection and correction module 121 can perform error detection and correction on the data, which is beneficial to improve the data error detection and correction capability, and can locate the transmission path of the data error.

[0080] Another embodiment of the present application also provides a storage system, which includes a controller, a storage chip and a base chip as described in the foregoing embodiments. The storage system provided by another embodiment of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as the foregoing embodiments can refer to the detailed description of the foregoing embodiments, which will not be repeated here.

[0081] Figure 7 The first structure diagram of the storage system provided by the embodiments of the present application.

[0082] Reference Figure 7 The storage system comprises a base chip 200, a controller 300 and a storage chip 400; the controller is configured to perform first error correction code encoding processing on first data data1 in a write phase to generate first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 to the base chip; the base chip 200 is configured to receive the first data data1 and the first encoded data ecc1 in the write phase and perform first error detection and correction processing, and perform second error correction code encoding processing on the first data data1 after the first error detection and correction processing to generate second encoded data ecc2, and select to transmit to-be-written data to the storage chip 400 based on a selection signal in the write phase, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data ecc2 and the first data data1 after the first error detection and correction processing, and the initial data comprising the first data data1 and the first encoded data ecc1; the base chip 200 is further configured to, if the to-be-written data is the second data, receive the second data from the storage chip 400 and perform second error detection and correction processing in a read phase, perform third error correction code encoding processing on the first data data1 after the second error detection and correction processing to generate third encoded data ecc3, and select to transmit read data to the controller 300 based on the selection signal SEL in the read phase, the read data being one of third data or the initial data from the storage chip 400, the third data comprising the third encoded data ecc3 and the first data data1 after the second error detection and correction processing; the storage chip 400 is configured to receive the to-be-written data and store the to-be-written data in the write phase, and transmit the read data to the base chip 200 in the read phase; the controller 300 is further configured to receive the read data in the read phase, perform third error detection and correction processing on the read data, and obtain the first data data1 after the third error detection and correction processing.

[0083] In the above storage system, the error correction code encoding processing and the error detection and correction processing performed on the data can be implemented by the base chip 200, so that the storage chip 400 does not need to perform the encoding processing and the error detection and correction processing, and the base chip 200 can share the encoding processing and the error detection and correction processing required by the controller 300, so that the functions required by the controller 300 and the storage chip 400 are relatively reduced, thereby relieving the pressure of the chip area of the controller 300 and the storage chip 400, so as to better improve the performance of the controller 300 and the storage chip 400, for example, the reliability of the storage chip 400 can be improved, thereby improving the storage performance of the storage system. In addition, through the selection signal SEL, the base chip 200 can be selected to participate in the encoding processing and the error detection and correction processing, so that the selectivity of the read and write operation of the storage system is improved.

[0084] In some embodiments, the storage system can be a DRAM storage system, for example, a DDR (double data rate) 4 DRAM storage system, a DDR5 DRAM storage system. In other embodiments, the storage system can also be a SRAM (Static Random-Access Memory) storage system, a NAND storage system, a NOR storage system, a FeRAM storage system, or a PcRAM storage system.

[0085] The controller 300 can include a first encoding module 301 configured to perform a first error correction code encoding process on the first data data1 in the write phase to generate first encoded data ecc1, and a third error detection and correction module 302 configured to receive read data and perform a third error detection and correction process in the read phase.

[0086] The base chip 200 can provide a high-speed interface for transmitting data in the storage system, and in addition, the base chip 200 is also used to manage and control the storage chip 400. In some embodiments, the base chip 200 can be used to monitor and manage the temperature of the storage chip 400, and can also be used to perform Memory Build-In-Self Test (MBIST) and self-repair on the storage chip 400. In addition, the base chip 200 is also used for error detection and correction of the transmitted data.

[0087] Figure 8 A second structural diagram of a storage system provided by an embodiment of the present application is provided. Referring to FIG. 2B, the storage system includes a base chip 200, a plurality of storage chips 400, and a controller 300. Figure 8In some embodiments, the base chip 200 can include: a first error detection and correction module 210 configured to receive the first data data1 and the first encoded data ecc1 in the write stage and perform first error detection and correction processing; a second encoding module 211 configured to receive the first data data1 after the first error detection and correction processing in the write stage and perform second error correction code encoding processing to generate second encoded data ecc2; a second error detection and correction module 221 configured to receive the second data in the read stage and perform second error detection and correction processing; a third encoding module 220 configured to receive the first data data1 after the second error detection and correction processing in the read stage and perform third error correction code encoding processing to generate third encoded data ecc3; a first selection module S11 configured to transmit one of the initial data or the second data to the memory chip 400 based on a selection signal selection SEL; and a second selection module S21 configured to output read data based on the selection signal SEL, the read data being one of the third data or the initial data from the memory chip.

[0088] The working principle of the storage system can refer to the corresponding description of the foregoing embodiments, which will not be repeated here. It can be understood that the controller 300 can perform third error detection and correction processing on the first data data1 after the second error detection and correction processing, and the controller 300 can also perform third error detection and correction processing on the first data data1 after the first error detection and correction processing.

[0089] In some embodiments, the first error correction code encoding processing, the third error correction code encoding processing, the first error detection and correction processing, and the third error detection and correction processing are performed by using a first encoding algorithm, the second error correction code encoding processing and the second error detection and correction processing are performed by using a second encoding algorithm, and the first encoding algorithm is different from the second encoding algorithm. Using different encoding algorithms for error detection and correction of data is beneficial to further improve the accuracy of error detection and correction of data. Specifically, the encoding algorithms used by the second encoding module 211 and the first encoding module 301 can be different, the encoding algorithms used by the second encoding module 211 and the third encoding module 220 can be different, and the decoding algorithms used by the first error detection and correction module 210 and the second error detection and correction module 221 can be different.

[0090] Reference Figure 8The storage chip 400 comprises a first storage module 410, the first storage module 410 being configured to store one of first data data1 or first error detection and correction processed data data1; and a second storage module 420, the second storage module 420 being configured to store one of first encoded data ecc1 or second encoded data ecc2.

[0091] Figure 9 A third structure diagram of a storage system provided by an embodiment of the present application is shown in FIG. 3. Referring to FIG. 3, Figure 9 In some embodiments, the base chip 200 further comprises a first serial-parallel conversion module 230, the first serial-parallel conversion module 230 being configured to receive and perform first serial-parallel conversion processing on the first data data1 and the first encoded data ecc1 in the write stage, and transmit the first serial-parallel conversion processed first data data1 and first encoded data ecc1 to the first error detection and correction module 210 and the first selection module S11; and a first parallel-serial conversion module 240, the first parallel-serial conversion module 240 being configured to receive and perform first parallel-serial conversion processing on read data from the second selection module S21 in the read stage, and transmit the first parallel-serial conversion processed read data to the controller 300.

[0092] Specifically, the first serial-parallel conversion module 230 is connected between a data transmission port of the controller 300 and a data transmission port of the first selection module S11, and the first parallel-serial conversion module 240 is connected between the data transmission port of the controller 300 and a data transmission port of the second selection module S21. In this way, the number of transmission channels between the controller 300 and the base chip 200 can be less than the number of bits of the first data data1, thereby saving the number of transmission channels between the controller 300 and the base chip 200, saving the number of data transmission ports required to be provided on the base chip 200 and the controller 300, and facilitating reduction of the complexity of the electrical connection structure between the controller 300 and the base chip 200, and saving the chip area of the controller 300 and the base chip 200.

[0093] Referring to FIG. 3, Figure 9 The base chip 200 further comprises a second parallel-serial conversion module 250, the second parallel-serial conversion module 250 being configured to receive and perform second parallel-serial conversion processing on to-be-written data from the first selection module S11 in the write stage, and transmit the second parallel-serial conversion processed to-be-written data to the storage chip 400; and a second serial-parallel conversion module 260, the second serial-parallel conversion module 260 being configured to receive and perform second serial-parallel conversion processing on second data or initial data from the storage chip 400 in the read stage.

[0094] In this way, the number of transmission channels between the memory chip 400 and the base chip 200 can be less than the number of bits of the first data data1, thereby saving the number of transmission channels between the memory chip 400 and the base chip 200. This helps to reduce the number of data transmission ports required on the base chip 200 and the memory chip 400, and also helps to reduce the complexity of the electrical connection structure between the memory chip 400 and the base chip 200, thus saving the chip area of ​​the memory chip 400 and the base chip 200.

[0095] refer to Figure 10 , Figure 10 In order to be in Figure 8 In some embodiments, the basic chip 200 may be configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data data1 and the first encoded data ecc1 during transmission based on the first error detection flag signal; the storage system may also include a first register 501, which is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during transmission.

[0096] Specifically, refer to Figure 10 The base chip 200 may include: a first storage cache module 201, configured to store the first data data1 and the first encoded data ecc1 during transmission error conditions; a first command module 202, which receives a first polling instruction PS1 and generates a first command signal CMD1 and a first clock signal CLK1; the first storage cache module 201 is also configured to output a first characterization signal flag1 to the first register 500 based on the first command signal CMD1 and the first clock signal CLK1, the first characterization signal flag1 characterizing the error conditions of the first data data1 or the first encoded data ecc1 during transmission.

[0097] In some embodiments, the controller 300 may also be configured to issue a first polling instruction PS1 to the first command module 202, that is, the controller 300 periodically issues queries to control the first storage cache module 201 to output a first representation signal flag1 to the first register 501. It is understood that in other embodiments, the first polling instruction may also be provided by external circuitry.

[0098] refer to Figure 10In some embodiments, the base chip 200 can be further configured to generate a second error detection flag signal during a second error detection and correction process, and record error conditions of the second encoded data ecc2 and the first data data1 after the first error detection and correction process during transmission based on the second error detection flag signal flag2; the storage system can further include a second register 502 configured to store the error conditions of the second encoded data ecc2 and the first data data1 after the first error detection and correction process during transmission.

[0099] With reference to Figure 10 In some embodiments, the base chip 200 can further include a second storage cache module 251 configured to store the error conditions of the second encoded data ecc2 and the first data data1 after the first error detection and correction process during transmission; a second command module 261 configured to receive a second polling instruction PS2 and generate a second command signal CMD2 and a second clock signal CLK2; the second storage cache module 251 is further configured to output a second representation signal flag2 to the second register 502 based on the second command signal CMD2 and the second clock signal CLK2, the second representation signal flag2 representing the error conditions of the second encoded data ecc2 or the first data data1 after the first error detection and correction process during transmission.

[0100] With reference to Figure 10 In some embodiments, the controller 300 can be further configured to generate a third error detection flag signal during a third error detection and correction process, and record error conditions of the first data data1 after the second error detection and correction process during transmission based on the third error detection flag signal; the storage system can further include a third register 503 configured to store the error conditions of the first data data1 after the second error detection and correction process during transmission.

[0101] With reference to Figure 10 In some embodiments, the controller 300 can further include a third storage cache module 271 configured to store the error conditions of the first data after the second error detection and correction process during transmission; a third command module 281 configured to receive a third polling instruction PS3 and generate a third command signal CMD3 and a third clock signal CLK3; the third storage cache module 271 is further configured to output a third representation signal flag3 to the third register 503 based on the third command signal CMD3 and the third clock signal CLK3, the third representation signal flag3 representing the error conditions of the first data data1 after the second error detection and correction process during transmission.

[0102] It can be understood that the first register 501, the second register 502 and the third register 503 can be the same register.

[0103] The storage system provided by the above embodiment has the following advantages. The base chip 200 can implement the error detection and correction function, and accordingly, the storage chip 400 does not need to have the error detection and correction function. The base chip 200 can share the error detection and correction function originally borne by the controller 300, thereby being beneficial to saving the space area of the controller 300 and the storage chip 400, improving the storage performance of the storage chip 400, and thus improving the storage performance of the storage system. Meanwhile, the base chip 200 can select whether to participate in the ECC error detection and correction based on the selection signal SEL, so that the read and write performance of the storage system meets different requirements. Specifically, if the base chip 200 does not participate in the ECC error detection and correction, the data transmission rate of the storage system is fast, and if the base chip 200 participates in the ECC error detection and correction, the data error detection and correction accuracy of the storage system is high.

[0104] In addition, the first error detection and correction module 210, the second error detection and correction module 221 and the third error detection and correction module 302 are arranged, so that error detection and correction can be performed on different data transmission paths, the error detection and correction capability of the storage system is improved, and it is beneficial to locating the specific data transmission path where the error occurs.

[0105] Correspondingly, the embodiment of the application further provides a semiconductor structure. The semiconductor structure can include the storage system provided by the above embodiment. The semiconductor structure provided by the embodiment of the application will be described in detail below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as the above embodiment can refer to the detailed description of the above embodiment, which will not be described hereinafter.

[0106] Figure 11 The semiconductor structure provided by the embodiment of the application is a cross-sectional structure schematic diagram.

[0107] Reference Figure 11 The semiconductor structure includes: a bearing substrate 600; the storage system provided by the above embodiment, and the controller 300 and the base chip 200 are located on the surface of the bearing substrate 600, and the storage chip 400 is located on the surface of the base chip 200 away from the bearing substrate 600.

[0108] The semiconductor structure can include a plurality of storage chips 400 arranged in sequence. The semiconductor structure can be a DRAM device, an SRAM device or the like.

[0109] In some embodiments, the carrier substrate 600 can be a PCB (Printed Circuit Board) circuit board. For detailed description of the storage system, reference can be made to the foregoing embodiments, which will not be repeated here.

[0110] The semiconductor structure can be a 2.5D (dimensions) device, i.e., the semiconductor structure is a stacked structure, which is conducive to saving the size in the horizontal direction, and the ECC error detection and correction function is realized by using the base chip 200 in the semiconductor structure, which is conducive to improving the performance of the semiconductor structure.

[0111] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A base chip applied to a storage system, characterized in that, The base chip is configured to receive first data and first encoded data and perform first error detection and correction processing in a write phase, the first encoded data being obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoded data, select to transmit to-be-written data to a storage chip based on a selection signal in the write phase, the to-be-written data being one of initial data or second data, the second data including the second encoded data and the first data after the first error detection and correction processing, and the initial data including the first data and the first encoded data. The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the storage chip and perform second error detection and correction processing in a read phase, perform third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoded data, and select to transmit read data based on the selection signal in the read phase, the read data being one of third data or the initial data from the storage chip, and the third data including the third encoded data and the first data after the second error detection and correction processing. The base chip includes: a first error detection and correction module configured to receive the first data and the first encoded data and perform the first error detection and correction processing in the write phase; a second encoding module configured to receive the first data after the first error detection and correction processing and perform the second error correction code encoding processing to generate the second encoded data in the write phase; a second error detection and correction module configured to receive the second data and perform the second error detection and correction processing in the read phase; a third encoding module configured to receive the first data after the second error detection and correction processing and perform the third error correction code encoding processing to generate the third encoded data in the read phase; a first selection module configured to select to transmit one of the initial data or the second data to the storage chip based on the selection signal; a second selection module configured to output read data based on the selection signal, the read data being one of the third data or the initial data from the storage chip; The base chip further includes: a first serial-to-parallel conversion module configured to receive the first data and the first encoded data in the write phase, perform first serial-to-parallel conversion processing on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion processing to the first error detection and correction module and the first selection module. ​ The first parallel-to-serial conversion module is configured to receive the read data from the second selection module in a read stage, perform first parallel-to-serial conversion processing on the read data, and transmit the read data after the first parallel-to-serial conversion processing to a controller.

2. The base chip of claim 1, wherein, The base chip further comprises: The second parallel-to-serial conversion module is configured to receive the to-be-written data from the first selection module in a write stage and perform second parallel-to-serial conversion processing, and transmit the to-be-written data after the second parallel-to-serial conversion processing to the memory chip. The second parallel-to-serial conversion module is configured to receive the second data or the initial data from the memory chip in a read stage and perform second serial-to-parallel conversion processing.

3. A base chip applied to a storage system, characterized in that, The base chip is configured to receive first data and first encoded data in a write stage and perform first error detection and correction processing, the first encoded data being obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoded data, select to-be-written data based on a selection signal in the write stage, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data and the first data after the first error detection and correction processing, and the initial data comprising the first data and the first encoded data; The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the memory chip in a read stage and perform second error detection and correction processing, perform third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoded data, and select to transmit read data based on the selection signal in the read stage, the read data being one of third data or the initial data from the memory chip, the third data comprising the third encoded data and the first data after the second error detection and correction processing. The base chip is further configured to generate a first error detection flag signal during the first error detection and correction processing, and record error conditions of the first data and the first encoded data in a transmission process based on the first error detection flag signal. The base chip further comprises:

4. The base chip of claim 3, wherein, The first storage buffer module is configured to store error conditions of the first data and the first encoded data in a transmission process; The first command module receives a first polling instruction and generates a first command signal and a first clock signal; The first storage buffer module is further configured to output a first representation signal based on the first command signal and the first clock signal, the first representation signal representing error conditions of the first data or the first encoded data in a transmission process. The base chip is configured to receive first data and first encoded data in a write stage and perform first error detection and correction processing, the first encoded data being obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoded data, select to-be-written data based on a selection signal in the write stage, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data and the first data after the first error detection and correction processing, and the initial data comprising the first data and the first encoded data; 5. A base chip applied to a storage system, characterized in that, The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the memory chip in a read stage and perform second error detection and correction processing, perform third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoded data, and select to transmit read data based on the selection signal in the read stage, the read data being one of third data or the initial data from the memory chip, the third data comprising the third encoded data and the first data after the second error detection and correction processing. The base chip is further configured to generate a first error detection flag signal during the first error detection and correction processing, and record error conditions of the first data and the first encoded data in a transmission process based on the first error detection flag signal. The base chip further comprises: The first storage buffer module is configured to store error conditions of the first data and the first encoded data in a transmission process; The first command module receives a first polling instruction and generates a first command signal and a first clock signal; The first storage buffer module is further configured to output a first representation signal based on the first command signal and the first clock signal, the first representation signal representing error conditions of the first data or the first encoded data in a transmission process. The base chip is configured to receive first data and first encoded data in a write stage and perform first error detection and correction processing, the first encoded data being obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoded data, select to-be-written data based on a selection signal in the write stage, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data and the first data after the first error detection and correction processing, and the initial data comprising the first data and the first encoded data; The base chip is configured to receive first data and first encoded data and perform first error detection and correction processing in a write phase, the first encoded data being obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoded data, and select to transmit to-be-written data to the memory chip based on a selection signal in the write phase, the to-be-written data being one of initial data or second data, the second data including the second encoded data and the first data after the first error detection and correction processing, and the initial data including the first data and the first encoded data; The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the memory chip and perform second error detection and correction processing in a read phase, perform third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoded data, and select to transmit read data based on the selection signal in the read phase, the read data being one of third data or the initial data from the memory chip, the third data including the third encoded data and the first data after the second error detection and correction processing. The base chip is further configured to generate a second error detection flag signal during the second error detection and correction processing, and record error conditions of the second encoded data and the first data after the first error detection and correction processing in a transmission process based on the second error detection flag signal.

6. The base chip of claim 5, wherein, The base chip further includes: a second storage buffer module configured to store error conditions of the second encoded data and the first data after the first error detection and correction processing in a transmission process; a second command module configured to receive a second polling instruction and generate a second command signal and a second clock signal; The second storage buffer module is further configured to output a second representation signal based on the second command signal and the second clock signal, the second representation signal representing error conditions of the second encoded data or the first data after the first error detection and correction processing in a transmission process.

7. A storage system, characterized by The system includes a controller, a base chip, and a memory chip, and further includes: The controller is configured to perform first error correction code encoding processing on first data to generate first encoded data in a write phase, and transmit the first data and the first encoded data to the base chip; The base chip is configured to receive the first data and the first encoded data and perform first error detection and correction processing in a write phase, and perform second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoded data, and select to transmit to-be-written data to the storage chip based on a selection signal in the write phase, the to-be-written data being one of initial data or second data, the second data including the second encoded data and the first data after the first error detection and correction processing, and the initial data including the first data and the first encoded data; The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the storage chip and perform second error detection and correction processing in a read phase, and perform third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoded data, and select to transmit read data to the controller based on the selection signal in the read phase, the read data being one of third data or the initial data from the storage chip, and the third data including the third encoded data and the first data after the second error detection and correction processing; The storage chip is configured to receive the to-be-written data and store the to-be-written data in the write phase, and transmit the read data to the base chip in the read phase; The controller is further configured to receive the read data, perform third error detection and correction processing on the read data, and obtain the first data after the third error detection and correction processing in the read phase; The base chip includes: a first error detection and correction module configured to receive the first data and the first encoded data and perform the first error detection and correction processing in the write phase; a second encoding module configured to receive the first data after the first error detection and correction processing and perform the second error correction code encoding processing to generate the second encoded data in the write phase; a second error detection and correction module configured to receive the second data and perform the second error detection and correction processing in the read phase; a third encoding module configured to receive the first data after the second error detection and correction processing and perform the third error correction code encoding processing to generate the third encoded data in the read phase; a first selection module configured to select to transmit one of the initial data or the second data to the storage chip based on the selection signal; a second selection module configured to output read data based on the selection signal, the read data being one of the third data or the initial data from the storage chip.

8. The storage system of claim 7, wherein, The controller includes: a first encoding module configured to perform the first error correction code encoding process on the first data to generate the first encoded data in the write phase; a third error detection and correction module configured to receive the read data and perform the third error detection and correction process in the read phase.

9. The storage system of claim 7, wherein, The base chip further comprises: a first serial-to-parallel conversion module configured to receive the first data and the first encoded data in the write phase, perform first serial-to-parallel conversion process on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion process to the first error detection and correction module and the first selection module; a first parallel-to-serial conversion module configured to receive the read data from the second selection module in the read phase, perform first parallel-to-serial conversion process on the read data, and transmit the read data after the first parallel-to-serial conversion process to the controller.

10. The storage system of claim 9, wherein, The base chip further comprises: a second parallel-to-serial conversion module configured to receive the to-be-written data from the first selection module in the write phase, perform second parallel-to-serial conversion process on the to-be-written data, and transmit the to-be-written data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module configured to receive the second data or the initial data from the storage chip in the read phase, and perform second serial-to-parallel conversion process.

11. A storage system, characterized by The system comprises a controller, a base chip, and a storage chip, and further comprises: the controller is configured to perform first error correction code encoding process on first data to generate first encoded data in the write phase, and transmit the first data and the first encoded data to the base chip; the base chip is configured to receive the first data and the first encoded data and perform first error detection and correction process in the write phase, perform second error correction code encoding process on the first data after the first error detection and correction process to generate second encoded data, select to-be-written data to the storage chip based on a selection signal in the write phase, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data and the first data after the first error detection and correction process, and the initial data comprising the first data and the first encoded data; The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the storage chip in a reading stage and perform a second error detection and correction processing, perform a third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoding data, and select to transmit reading data to the controller based on the selection signal in the reading stage, the reading data being one of third data or the initial data from the storage chip, the third data including the third encoding data and the first data after the second error detection and correction processing. The storage chip is configured to, in the writing stage, receive the to-be-written data and store the to-be-written data, and in the reading stage, transmit the reading data to the base chip. The controller is further configured to, in the reading stage, receive the reading data, perform a third error detection and correction processing on the reading data, and obtain the first data after the third error detection and correction processing. The first error correction code encoding processing, the first error detection and correction processing, the third error correction code encoding processing, and the third error detection and correction processing are performed by using a first encoding algorithm, the second error correction code encoding processing and the second error detection and correction processing are performed by using a second encoding algorithm, and the first encoding algorithm is different from the second encoding algorithm.

12. A storage system, characterized by The controller, the base chip, and the storage chip are further configured to: The controller is configured to, in a writing stage, perform a first error correction code encoding processing on first data to generate first encoding data, and transmit the first data and the first encoding data to the base chip. The base chip is configured to, in the writing stage, receive the first data and the first encoding data and perform a first error detection and correction processing, perform a second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoding data, and select to transmit to-be-written data to the storage chip based on a selection signal in the writing stage, the to-be-written data being one of initial data or second data, the second data including the second encoding data and the first data after the first error detection and correction processing, and the initial data including the first data and the first encoding data. The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the storage chip in a reading stage and perform a second error detection and correction processing, perform a third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoding data, and select to transmit reading data to the controller based on the selection signal in the reading stage, the reading data being one of third data or the initial data from the storage chip, the third data including the third encoding data and the first data after the second error detection and correction processing. The storage chip is configured to receive and store the to-be-written data in the write phase, and transmit the read data to the base chip in the read phase; The controller is further configured to receive the read data in the read phase, perform third error detection and correction processing on the read data, and obtain the first data after the third error detection and correction processing; The base chip is further configured to generate a first error detection flag signal during the first error detection and correction processing, and record error conditions of the first data and the first encoded data in the transmission process based on the first error detection flag signal; the storage system further comprises: A first register configured to store error conditions of the first data and the first encoded data in the transmission process.

13. A storage system, characterized by The storage system comprises a controller, a base chip, and a storage chip, and further comprises: The controller is configured to perform first error correction code encoding processing on the first data in the write phase to generate first encoded data, and transmit the first data and the first encoded data to the base chip; The base chip is configured to receive and perform first error detection and correction processing on the first data and the first encoded data in the write phase, perform second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoded data, select to transmit to-be-written data to the storage chip based on a selection signal in the write phase, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data and the first data after the first error detection and correction processing, and the initial data comprising the first data and the first encoded data; The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the storage chip and perform second error detection and correction processing in the read phase, perform third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoded data, and select to transmit read data to the controller based on the selection signal in the read phase, the read data being one of third data or the initial data from the storage chip, the third data comprising the third encoded data and the first data after the second error detection and correction processing; The storage chip is configured to receive and store the to-be-written data in the write phase, and transmit the read data to the base chip in the read phase; The controller is further configured to receive the read data in the read phase, perform third error detection and correction processing on the read data, and obtain the first data after the third error detection and correction processing; The base chip is further configured to generate a second error detection flag signal during the second error detection and correction processing, and record error conditions of the second encoded data and the first data after the first error detection and correction processing in a transmission process based on the second error detection flag signal; and the storage system further comprises: a second register configured to store error conditions of the second encoded data and the first data after the first error detection and correction processing in a transmission process.

14. A storage system, characterized by The storage system comprises a controller, a base chip and a storage chip, and further comprises: The controller is configured to perform first error correction code encoding processing on first data to generate first encoded data in a write phase, and transmit the first data and the first encoded data to the base chip; The base chip is configured to receive the first data and the first encoded data and perform first error detection and correction processing in the write phase, perform second error correction code encoding processing on the first data after the first error detection and correction processing to generate second encoded data, and select to transmit to-be-written data to the storage chip based on a selection signal in the write phase, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data and the first data after the first error detection and correction processing, and the initial data comprising the first data and the first encoded data; The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the storage chip and perform second error detection and correction processing in a read phase, perform third error correction code encoding processing on the first data after the second error detection and correction processing to generate third encoded data, and select to transmit read data to the controller based on the selection signal in the read phase, the read data being one of third data or the initial data from the storage chip, the third data comprising the third encoded data and the first data after the second error detection and correction processing; The storage chip is configured to receive the to-be-written data and store the to-be-written data in the write phase, and transmit the read data to the base chip in the read phase; The controller is further configured to receive the read data in the read phase, perform third error detection and correction processing on the read data, and obtain the first data after the third error detection and correction processing; The controller is further configured to generate a third error detection flag signal during the third error detection and correction processing, and record error conditions of the first data after the second error detection and correction processing in a transmission process based on the third error detection flag signal; and the storage system further comprises: a third register configured to store error conditions of the first data after the second error detection and correction processing in a transmission process.

15. A storage system, characterized by The storage system comprises a controller, a base chip and a storage chip, and further comprises: The controller is configured to perform a first error correction code encoding process on the first data to generate first encoded data in a write phase, and transmit the first data and the first encoded data to the base chip; The base chip is configured to receive the first data and the first encoded data and perform a first error detection and correction process in the write phase, and perform a second error correction code encoding process on the first data after the first error detection and correction process to generate second encoded data, and select to transmit to-be-written data to the memory chip based on a selection signal in the write phase, the to-be-written data being one of initial data or second data, the second data comprising the second encoded data and the first data after the first error detection and correction process, and the initial data comprising the first data and the first encoded data; The base chip is further configured to, if the to-be-written data is the second data, receive the second data from the memory chip and perform a second error detection and correction process in a read phase, and perform a third error correction code encoding process on the first data after the second error detection and correction process to generate third encoded data, and select to transmit read data to the controller based on the selection signal in the read phase, the read data being one of third data or the initial data from the memory chip, the third data comprising the third encoded data and the first data after the second error detection and correction process; The memory chip is configured to receive the to-be-written data and store the to-be-written data in the write phase, and transmit the read data to the base chip in the read phase; The controller is further configured to receive the read data in the read phase, perform a third error detection and correction process on the read data, and obtain the first data after the third error detection and correction process; The memory chip comprises: a first storage module, the first storage module being configured to store one of the first data or the first data after the first error detection and correction process; a second storage module, the second storage module being configured to store one of the first encoded data or the second encoded data.

16. A semiconductor structure, characterized by comprises: a carrier substrate; The storage system of any one of claims 7-15, and the controller and the base chip are located on a surface of the carrier substrate, and the memory chip is located on a surface of the base chip away from the carrier substrate.

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