Performing flush recovery using parallel traversal of slice reordering buffers (SROBS)

Abstract

Parallel traversal of slice reorder buffers (SROBs) is disclosed herein for performing flush recovery. In an exemplary embodiment, a register mapping circuit provides a rename mapping table (RMT) comprising RMT entries representing logical register number (LRN) to physical register number (PRN) mappings. The register mapping circuit also provides an SROB comprising a plurality of SROB slices, each SROB slice corresponding to a respective LRN. Each SROB slice tracks non-committed instructions that write to the LRN corresponding to that SROB slice and maintains the instructions in program order with respect to each other. Upon detecting a non-committed instruction that writes to an LRN, the register mapping circuit allocates an SROB slice entry in the SROB slice corresponding to the LRN. Upon occurrence of a pipeline flush from a target instruction, the register mapping circuit restores RMT entries of the RMT to their previous mapping state based on parallel traversal of the SROB slices of the SROB.

Description

TECHNICAL FIELD

[0001] The technology of this disclosure relates to speculative instruction execution in processor-based devices, and, more specifically, to recovery from pipeline flushes that can occur during speculative instruction execution. BACKGROUND

[0002] A common feature of conventional modern processor devices is branch prediction, which employs mechanisms to predict the direction of branches resulting from control flow instructions (e.g., conditional branch instructions), and to enable speculative execution of instructions on the predicted execution path. Since some branch predictions are incorrect, such branch prediction mechanisms also include hardware for recovery from the effects of speculative instruction execution resulting from a mispredicted branch. To enable this recovery, the branch prediction mechanism must "flush" from the execution pipeline the instructions of the speculative execution younger than the mispredicted branch instruction, undo all updates performed by the instructions of the speculative execution in different microarchitectures, and restore these structures to their original state existing prior to the mispredicted branch instruction. In addition to branch mispredictions, pipeline flushes can also occur in response to other control hazards. For example, after an attempt to execute a load or store against a memory location whose computed address is invalid or cannot be accessed, a pipeline flush can have to be performed.

[0003] One microarchitecture affected by flush recovery is the rename map table (RMT). Provided by processor devices that support register renaming, the RMT stores the most recent logical register-to-physical register mapping used by the processor device to establish true data dependencies. Since the mapping stored by the RMT can be modified by instructions of the speculative execution, recovery from a flush requires restoring each RMT mapping to the previous mapping state existing when the instruction that triggered the flush ("target instruction") performed register renaming. Restoring the RMT is a time-sensitive operation because instructions on the "correct" execution path taken after the flush cannot proceed through the processor device's execution pipeline until the RMT is restored to its previous mapping state. If the previous mapping state of the RMT is not recovered fast enough, the processor device can be forced to stall the execution pipeline.

[0004] Existing RMT recovery techniques can generally be categorized according to the point at which the recovery process begins. In one approach, referred to as "delayed recovery," the recovery process does not begin until the target instruction becomes the oldest uncommitted instruction in the reorder buffer (ROB), a queue that tracks the state of instructions being run in program order after register renaming. Once the target instruction is the oldest uncommitted instruction in the ROB, the RMT can be recovered simply by copying the contents of the commit map table (CMT) into the RMT. However, while delayed recovery is easy to implement, it can result in a significant drop in processor performance in cases where there are many older uncommitted instructions when the flush is initiated.

[0005] Another approach, referred to as "immediate recovery," involves beginning the recovery process immediately when the flush is initiated. Some immediate recovery mechanisms can use RMT snapshots that are created for each branch instruction and used to restore the RMT when the corresponding branch instruction is determined to have been mispredicted. The RMT snapshots can be used alone or in combination with "walking" the ROB (i.e., sequentially accessing entries in the ROB between the entry for the target instruction and the point at which the snapshot of the RMT was taken, and undoing the changes made to the RMT by each corresponding instruction). Other immediate recovery techniques can involve using the contents of the CMT as a starting point and walking the ROB from the oldest uncommitted instruction to the target instruction while undoing the changes made by each corresponding instruction. Another immediate recovery approach involves using the contents of the RMT as a starting point and walking the ROB from the youngest uncommitted instruction to the target instruction while undoing the changes. Generally speaking, the performance of immediate recovery mechanisms can depend on the number of snapshots required and / or the number of instructions that need to be walked to restore the previous mapping state of the RMT under each approach.

[0006] Accordingly, there is a need for mechanisms that more efficiently recover the RMT after a pipeline flush. SUMMARY

[0007] The exemplary embodiments disclosed herein include performing flush recovery using parallel traversal of slice reorder buffers (SROBs). In this regard, in an exemplary embodiment, a processor device includes a register mapping circuit that provides a rename mapping table (RMT). The RMT includes a plurality of RMT entries, each RMT entry representing a mapping of a logical register number (LRN) to a physical register number (PRN). The register mapping circuit also provides an SROB that includes a plurality of SROB slices. Each SROB slice corresponds to a respective LRN, and each SROB slice includes a plurality of SROB slice entries. Each SROB slice is functionally similar to a conventional reorder buffer (ROB), except that the SROB slice only tracks non-committed instructions that write to the LRN corresponding to the SROB slice, and only maintains the instructions relative to each other in program order. In an exemplary operation, the register mapping circuit allocates an SROB slice entry for a non-committed instruction in the SROB slice corresponding to the LRN upon detecting a write to the LRN in an execution pipeline of the processor device. If the register mapping circuit subsequently receives an indication of a pipeline flush from a target instruction within the execution pipeline, the register mapping circuit restores a plurality of RMT entries of the RMT to their previous mapping state based on parallel traversal of the SROB slices of the SROB. Since the traversal of the SROB slices is performed in parallel, and each SROB slice can contain fewer instructions than a conventional ROB, flush recovery can be accomplished more efficiently than conventional methods.

[0008] In some embodiments, the count of SROB slice entries within each SROB slice can be the same size as the count of ROB entries in a ROB provided by the register mapping circuit, or can be smaller than the count of ROB entries in a ROB. In the latter case, if the register mapping circuit needs to allocate an SROB slice entry to a non-committed instruction, but there are no SROB slice entries available within the appropriate SROB slice, in some embodiments the register mapping circuit can stall the execution pipeline until an SROB slice entry within the SROB slice becomes available. Some embodiments can provide that the register mapping circuit can allocate the oldest SROB slice entry to the non-committed instruction, rather than stall the execution pipeline. Subsequently, if the register mapping circuit determines that the overwritten contents of the oldest SROB slice entry are necessary for flush recovery, the register mapping circuit can perform a traversal of the ROB. Similarly, some embodiments can provide a partially serial ROB (PSROB), and the oldest SROB slice entry can be evicted before being allocated to a non-committed instruction. In such embodiments, if the register mapping circuit determines that the overwritten contents of the evicted oldest SROB slice entry are necessary for flush recovery, the register mapping circuit can perform a traversal of the PSROB.

[0009] In another example embodiment, a register mapping circuit in a processor device is provided. The register mapping circuit includes an RMT including a plurality of RMT entries, each RMT entry representing a mapping of an LRN of a plurality of LRNs to a PRN of a plurality of PRNs. The register mapping circuit also includes an SROB subdivided into a plurality of SROB slices, each SROB slice corresponding to a respective LRN of the plurality of LRNs and each SROB slice including a plurality of SROB slice entries. The register mapping circuit is configured to detect, within an execution pipeline of the processor device, an uncommitted instruction including a write instruction to a destination LRN of the plurality of LRNs. The register mapping circuit is also configured to allocate, to the uncommitted instruction, an SROB slice entry of a SROB slice of the plurality of SROB slices of the SROB corresponding to the destination LRN. The register mapping circuit is also configured to receive, from a target instruction within the execution pipeline, an indication of a pipeline flush. The register mapping circuit is also configured to, in response to receiving the indication of the pipeline flush, restore, based on a parallel traversal of the plurality of SROB slices corresponding to the LRNs of the plurality of RMT entries, the plurality of RMT entries to a corresponding plurality of previous mapping states.

[0010] In another example embodiment, a method of performing flush recovery using parallel traversal of SROBs is provided. The method includes detecting, by a register mapping circuit of a processor device, within an execution pipeline of the processor device, an uncommitted instruction including a write instruction to a destination LRN of a plurality of LRNs. The method also includes allocating, to the uncommitted instruction, an SROB slice entry of a SROB slice of a plurality of SROB slices of an SROB of the processor device corresponding to the destination LRN, wherein each SROB slice of the plurality of SROB slices corresponds to a respective LRN of the plurality of LRNs. The method also includes receiving, from a target instruction within the execution pipeline, an indication of a pipeline flush. The method also includes, in response to receiving the indication of the pipeline flush, restoring, based on a parallel traversal of the plurality of SROB slices corresponding to the LRNs of the plurality of RMT entries, a plurality of RMT entries of the RMT to a corresponding plurality of previous mapping states.

[0011] In another exemplary embodiment, a non-transitory computer-readable medium is provided. This non-transitory computer-readable medium stores computer-executable instructions that, when executed by a processor device, cause the processor device to detect an uncommitted instruction within its execution pipeline. The uncommitted instruction includes a write instruction to a destination LRN among a plurality of LRNs. The computer-executable instructions further cause the processor device to allocate an SROB slice entry from a plurality of SROB slices of the processor device's SROBs corresponding to the destination LRN to the uncommitted instruction, wherein each SROB slice corresponds to a corresponding LRN among the plurality of LRNs. The computer-executable instructions further cause the processor device to receive a pipeline flushing instruction from a target instruction within the execution pipeline. The computer-executable instructions further cause the processor device, in response to receiving the pipeline flushing instruction, to restore a plurality of RMT entries to their corresponding previously mapped states based on a parallel traversal of the plurality of SROB slices corresponding to the LRNs of the plurality of RMT entries.

[0012] Those skilled in the art will understand the scope of this disclosure and will implement additional embodiments of this disclosure after reading the following detailed description of preferred embodiments associated with the accompanying drawings. Attached Figure Description

[0013] The accompanying drawings, which are included in and form a part of this specification, illustrate several embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0014] Figure 1 This is a block diagram of an exemplary processor-based device configured to perform flush recovery using parallel traversal of a slice reorder buffer (SROB);

[0015] Figure 2 According to some embodiments Figure 1 A schematic diagram of the reordering buffer and exemplary content of the SROB;

[0016] Figure 3 Provided according to some embodiments Figure 1 The register mapping circuit is used to use Figure 1 A flowchart illustrating an exemplary operation of parallel traversal of the SROB to perform flush recovery;

[0017] Figure 4 Provided according to some embodiments Figure 1 A flowchart illustrating an exemplary operation of the register mapping circuitry for allocating new SROB slice entries;

[0018] Figure 5 Provided according to some embodiments Figure 1a flowchart of exemplary operations of a register mapping circuit for allocating new SROB slice entries in embodiments that overwrite old SROB slice entries;

[0019] Figure 6 There is provided, in accordance with some embodiments Figure 1 a flowchart of exemplary operations of a register mapping circuit for allocating new SROB slice entries in embodiments that overwrite old SROB slice entries; Figure 1 a flowchart of exemplary operations of a portion-serial reorder buffer (PSROB) in an embodiment that allocates new SROB slice entries; and

[0020] Figure 7 is a block diagram of an exemplary processor-based device (e.g., a processor-based device of Figure 1 configured to perform flush recovery using parallel traversal of SROBs. DETAILED DESCRIPTION

[0021] Exemplary embodiments disclosed herein include performing flush recovery using parallel traversal of slice reorder buffers (SROBs). In this regard, in an exemplary embodiment, a processor device includes a register mapping circuit that provides a rename mapping table (RMT). The RMT includes a plurality of RMT entries, each RMT entry representing a mapping of a logical register number (LRN) to a physical register number (PRN). The register mapping circuit also provides an SROB, the SROB including a plurality of SROB slices. Each SROB slice corresponds to a respective LRN, and each SROB slice includes a plurality of SROB slice entries. Each SROB slice is functionally similar to a conventional reorder buffer (ROB), except that the SROB slice only tracks non-committed instructions that write to the LRN corresponding to that SROB slice, and only maintains those instructions in program order relative to each other. In exemplary operations, the register mapping circuit allocates an SROB slice entry for a non-committed instruction in the SROB slice corresponding to the LRN upon detecting a write to the LRN in an execution pipeline of the processor device with a non-committed instruction. If the register mapping circuit subsequently receives an indication of a pipeline flush from a target instruction within the execution pipeline, the register mapping circuit restores a plurality of RMT entries of the RMT to their previous mapping state based on parallel traversal of the SROB slices of the SROB. Because the traversal of the SROB slices is performed in parallel, and each SROB slice can contain fewer instructions than a conventional ROB, flush recovery can be accomplished more efficiently than conventional methods.

[0022] In some embodiments, the count of SROB slice entries within each SROB slice may be the same as, or less than, the count of ROB entries in the ROB provided by the register mapping circuitry. In the latter case, if the register mapping circuitry needs to assign an SROB slice entry to an uncommitted instruction, but no SROB slice entry is available in the appropriate SROB slice, in some embodiments, the register mapping circuitry may initiate a delay in the execution pipeline, delaying it until the SROB slice entry within the SROB slice becomes available. Some embodiments may specify that the register mapping circuitry can assign the oldest SROB slice entry to the uncommitted instruction instead of initiating a delay in the execution pipeline. Subsequently, if the register mapping circuitry determines that a flush recovery requires the rewrite of the oldest SROB slice entry for flush recovery, the register mapping circuitry may perform a traversal of the ROB. Similarly, some embodiments may provide a partially serial ROB (PSROB) where the oldest SROB slice entry can be evicted before being assigned to an uncommitted instruction. In such an embodiment, if the register mapping circuitry determines that the rewrite of the oldest SROB slice entry being evicted is necessary for flush recovery, the register mapping circuitry can perform a traversal of the PSROB.

[0023] In this regard, Figure 1 An exemplary processor-based device 100 is illustrated, which provides a processor device 102 for processing executable instructions. In some embodiments, the processor device 102 may be one of a plurality of processor devices of the processor-based device 100. Figure 1 The processor device 102 includes an execution pipeline 104, which includes circuitry configured to execute an instruction stream 106 comprising computer-executable instructions. Figure 1 In the example, execution pipeline 104 includes fetch circuitry 108, which is configured to fetch instruction stream 106 from instruction memory 110 for executable instructions. As a non-limiting example, instruction memory 110 may be provided in or as part of system memory (not shown) of processor-based device 100. Instruction cache 112 may also be provided in processor device 102 to cache instructions fetched from instruction memory 110, thereby reducing latency in fetch circuitry 108. Figure 1 The fetch circuit 108 in the example is configured to provide instructions to one or more instruction pipelines I0-I before the instructions arrive at the execution circuit (“EXEC circuit”) 114 to be executed. N Preprocessing is performed in the middle. Instruction pipeline I0-I NDifferent processing circuits (or "stages") across execution pipeline 104 are provided to concurrently process fetched instructions prior to execution in execution circuit 114 to increase throughput.

[0024] Apart from Figure 1 In addition to the execution pipeline 104, a decoding circuit 116 is included. The decoding circuit 116 is configured to decode the instruction retrieved by the fetch circuit 108 into a decoded instruction to determine the required instruction type and action, and further determine which instruction pipeline I0-I the decoded instruction should be placed in. N The decoded instructions are then placed into the instruction pipeline I0-I. N One or more of the register names in the decoded instructions are then provided to the renaming circuit 118. The renaming circuit 118 determines whether any register names in the decoded instructions should be renamed to avoid register dependencies that could prevent parallel or out-of-order processing of instructions.

[0025] The renaming circuit 118 is configured to invoke the rename mapping table (RMT) 120 provided by the register mapping circuit 122 to rename the logical source register operands and / or logical destination register operands of the decoded instructions to multiple physical registers 124(0)-124(P) in the physical register file (PRF) 126 (each corresponding to multiple physical register numbers (PRN) (PRN0, PRN1, ... PRN)). P Each physical register 124(0)-124(P) in the PRF 126 is configured to store data for the source register operand and / or destination register operand of the decoded instruction. The RMT 120 contains multiple RMT entries 128(0)-128(L), each RMT entry corresponding to multiple logical register numbers (LRN) LRN0-LRN0. L A corresponding logical register number corresponds to each entry. RMT entries 128(0)-128(L) are configured to store information in the form of address pointers to physical registers in a plurality of physical registers 124(0)-124(P) in PRF 126. In some embodiments, RMT entries 128(0)-128(L) are also associated with corresponding program sequence identifiers 130(0)-130(L), each program sequence identifier providing an indication of the program sequence location of an instruction that causes the creation of a mapping from logical registers to physical registers represented by RMT entries 128(0)-128(L). In the event of a flush, program sequence identifiers 130(0)-130(L) can be used to determine which entries in RMT entries 128(0)-128(L) are updated by speculatively executed instructions earlier than the target instruction, and therefore should be restored to the previous mapping state.

[0026] Figure 1 The execution pipeline 104 also includes a register access circuit ("RACC circuit") 132 configured to access one of the physical registers 124(0)-124(P) in the PRF 126 named by the mapping entry of the RMT entry 128(0)-128(L) corresponding to the logical register number LRN0-LRN L N The execution pipeline 104 also provides a scheduler circuit ("SCHED circuit") 134 configured to store decoded instructions in a reservation entry (not shown) until all source register operands of the decoded instruction are available. In addition, a writeback circuit 136 is provided in the execution pipeline 104 to write back (i.e., commit) values produced from executed instructions to memory, such as the PRF 126, a data cache memory system (not shown), or a main memory (not shown). It should be understood that the elements of the execution pipeline 104 can be provided in a different configuration or order than shown in some embodiments. For example, as shown in FIG. 1C, according to some embodiments, the register access circuit 132 can follow the scheduler circuit 134 within the execution pipeline 104 rather than preceding the scheduler circuit 134. Figure 1 Figure 1

[0027] Figure 1 The execution pipeline 104 also provides a branch prediction circuit 138. The branch prediction circuit 138 is configured to speculatively predict the outcome of a condition of a fetched conditional flow control instruction (not shown), such as a conditional branch instruction, that controls which path in the instruction control flow path of the instruction stream 106 is fetched into the instruction pipeline 106 for execution. With an accurate speculative prediction method, the condition of the fetched conditional flow control instruction does not have to be resolved when executed by the execution circuit 114 before the execution pipeline 104 can continue processing the speculatively fetched instruction. N L ​​​However, if the condition of the conditional flow control instruction has been determined to be a misprediction when the conditional flow control instruction is executed in the execution circuit 114, the speculative fetched instructions in the execution pipeline 104 that follow the mispredicted conditional flow instruction (i.e., the target instruction) will be flushed because the direction of program flow is not as predicted and will not include processing of those speculative fetched instructions. When a flush occurs (e.g., as a result of a branch misprediction), the register mapping circuit 122 is configured to restore the previous mapping state (i.e., the logical register to physical register mapping of each of the RMT entries 128(0)-128(L) of the RMT 120) that can have been altered by the instruction stream of instructions that entered the execution pipeline 104 after the target instruction. N

[0029] To facilitate restoring the previous mapping state of the RMT 120, the register mapping circuit 122 provides a re-order buffer (ROB) 140 containing a plurality of ROB entries 142(0)-142(R) that are assigned to the “in-flight” instructions (i.e., “uncommitted instructions”) being processed by the execution pipeline 104 but have not yet been committed. The ROB entries 142(0)-142(R) are sequentially assigned to the uncommitted instructions in program order. Information regarding changes to the mapping of logical register numbers LRN0-LRN L Figure 1 The register mapping circuit 122 also includes a commit mapping table (CMT) 144 that provides a plurality of mapping entries 146(0)-146(L) in which the logical register to physical register mapping produced by committed instructions is stored. The CMT 144 is only updated at committed instructions and thus is not altered in response to a flush.

[0030] ​​As described above, conventional techniques for restoring RMT 120 to its previously mapped state after flushing, including delayed recovery and immediate recovery techniques, can be inefficient when flushing involves a large number of older uncommitted instructions. Therefore, the exemplary embodiments disclosed herein provide a slice ROB (SROB) 148. SROB 148 is further divided into multiple SROB slices (“SLICE”) 150(0)-150(L), each slice including multiple SROB slice entries, such as SROB slice entries 152(0)-152(X), 154(0)-154(X). Each SROB slice in SROB slices 150(0)-150(L) operates in a similar manner to ROB 140, except that each SROB slice 150(0)-150(L) is associated with multiple LRNs LRN0-LRN. L It corresponds to a corresponding LRN and only tracks uncommitted instructions written to the destination LRN corresponding to that SROB slice 150(0)-150(L). For example, Figure 1 In the example, SROB slice 150(0) corresponds to LRN0, so uncommitted instructions are tracked, which include write instructions to the destination LRN LRN0. SROB slice entries 152(0)-152(X) and 154(0)-154(X) store the same data as ROB entries 142(0)-142(R) for their respective uncommitted instructions, and are allocated sequentially according to the procedural order relative to other SROB slice entries within the same SROB slice 150(0)-150(L).

[0031] In an example operation, register mapping circuit 122, upon detecting an uncommitted instruction written to a destination LRN in execution pipeline 104, allocates one of SROB slice entries 152(0)-152(X), 154(0)-154(X) in the SROB slice 150(0)-150(L) corresponding to the destination LRN for the uncommitted instruction. If register mapping circuit 122 subsequently receives an indication of a pipeline flush from a target instruction within execution pipeline 104, register mapping circuit 122 restores a plurality of RMT entries 128(0)-128(L) of RMT 120 to their previous mapping state based on a parallel traversal of SROB slices 150(0)-150(L) of SROB 148. For example, register mapping circuit 122 can perform a traversal of each of SROB slice entries 150(0)-150(L) in parallel by accessing SROB slice entries 152(0)-152(X), 154(0)-150(X) corresponding to uncommitted instructions younger than the target instruction that caused the flush, and using data stored in each of SROB slice entries 152(0)-152(X), 154(0)-154(X) to undo changes made by the uncommitted instructions to RMT entries 128(0)-128(L) corresponding to the LRN for each SROB slice 150(0)-150(L). Because the traversal of SROB slices 150(0)-150(L) is performed in parallel, and because each of SROB slices 150(0)-150(L) can contain fewer instructions than ROB 140, flush recovery can be accomplished more efficiently than conventional methods.

[0032] In some embodiments, the count of each of SROB slice entries 152(0)-152(X), 154(0)-154(X) can be the same as the count of ROB entries 142(0)-142(R) (i.e., X = R). Such embodiments can provide improved performance because the size of SROB slices 150(0)-150(L) is large enough to handle the case where each uncommitted write instruction in ROB 140 targets the same destination LRN LRN0-LRN L However, the cost of improved performance is an increase in processor resources required to implement SROB 148.

[0033] Other embodiments can provide that the count of each of the SROB slice entries 152(0)-152(X), 154(0)-154(X) can be less than the count of the ROB entries 142(0)-142(R) (i.e., X < R). In such embodiments, the register mapping circuit 122 provides special handling for the case where none of the SROB slice entries 152(0)-152(X), 154(0)-154(X) are available for assignment to a new non-committed instruction. According to some embodiments, if none of the SROB slice entries 152(0)-152(X), 154(0)-154(X) are available for assignment, the register mapping circuit 122 can initiate a stall of the execution pipeline 104 until one of the SROB slice entries 152(0)-152(X), 154(0)-154(X) within the appropriate SROB slice 150(0)-150(L) becomes available for assignment. Once the stall is resolved (i.e., when one of the SROB slice entries 152(0)-152(X), 154(0)-154(X) becomes available), the register mapping circuit 122 assigns one of the SROB slice entries 152(0)-152(X), 154(0)-154(X) within the appropriate SROB slice 150(0)-150(L).

[0034] In some embodiments, in response to determining that none of the SROB slice entries 152(0)-152(X) and 154(0)-154(X) are available for allocation, register mapping circuit 122 may rewrite the oldest SROB slice entries 152(0)-152(X) and 154(0)-154(X) for a new uncommitted instruction. If register mapping circuit 122 subsequently determines that the rewritten contents of the oldest SROB slice entries 152(0)-152(X) and 154(0)-154(X) are necessary for flush recovery, register mapping circuit 120 may perform a traversal of ROB 140 in a normal manner to restore the RMT entries 128(0)-128(L) of RMT 120 to their previous mapping state. Because performing a traversal of ROB140 can result in the same performance penalty as conventional mechanisms used for flush recovery, in some embodiments, register mapping circuitry 122 may provide a partially serial ROB (PSROB) 156 comprising multiple PSROB entries 158(0)-158(P). In such an embodiment, if no free SROB slice entries 152(0)-152(X), 154(0)-154(X) are allocated for new uncommitted instructions, PSROB 156 operates in a similar manner to ROB140, but only allocates PSROB entries 158(0)-158(P) to store SROB slice entries 152(0)-150(X), 154(0)-154(X) evicted from SROB slices 150(0)-150(L). If the register mapping circuit 122 subsequently determines that the rewrite of the oldest SROB slice entries 152(0)-152(X) and 154(0)-154(X) is necessary for flush recovery, then the register mapping circuit 122 may perform a traversal of PSROB 156 to restore the RMT entries 128(0)-128(L) of RMT 120 to their previous mapping state.

[0035] To illustrate according to some embodiments Figure 2 The exemplary content of ROB 140 and SROB 148 provides Figure 2 .exist Figure 1 In, it is shown Figure 2 The register mapping circuits are 122, ROB 140, and SROB 148. ROB 140 includes ROB entries 142(0)-142(6), each ROB entry corresponding to uncommitted instructions I0-I6. Instructions I0-I6 include instructions for writing to destinations LRN LRN0 and LRN1. Figure 1 In the example, LRN0 and LRN1 are respectively with Figure 1corresponding to SROB slices 150(0) and 150(1). In example operations, register mapping circuit 122 detects uncommitted instructions I0-I6 (e.g., in execution pipeline 104) and allocates ROB entries 142(0)-142(6) for uncommitted instructions I0-I6, respectively. For instructions I0, I2, I4, and I6, register mapping circuit 122 also allocates SROB slice entries 152(0), 154(0), 152(1), and 154(1), respectively. Figure 1

[0036] During execution of instructions I0-I6, target instruction I3 fails to execute as expected (e.g., because target instruction I3 is determined to be a mispredicted branch instruction, or because target instruction I3 is a load or store instruction whose computed address of a memory location is invalid or cannot be accessed). A pipeline flush is triggered such that register mapping circuit 122 receives an indication 200 of the pipeline flush from target instruction I3. The pipeline flush causes all instructions younger than target instruction I3 (i.e., instructions I4-I6) to be flushed from execution pipeline 104 and requires that RMT 120 be restored to a previous mapping state corresponding to the state of RMT 120 when execution of target instruction I3 was attempted. Figure 2 RMT 120 is also restored to a previous mapping state corresponding to the state of RMT 120 when execution of target instruction I3 was attempted.

[0037] Rather than traversing ROB 140 in a conventional manner to restore RMT 120, register mapping circuit 122 performs a parallel traversal of SROB slices 150(0) and 150(1) to identify SROB slice entries corresponding to any flushed instructions I4-I6 and to undo any mapped changes made by flushed instructions I4-I6 to RMT 120. In examples where SROB slices 150(0) and 150(1) are implemented as separate data structures, the parallel traversal of SROB slices 150(0) and 150(1) can be performed in parallel. Figure 1 In the example of FIG. 1, the parallel traversal of SROB slices 150(0) and 150(1) causes register mapping circuit 122 to identify SROB slice entries 152(1) and 154(1) as corresponding to instructions I4 and I6, uncommitted instructions younger than target instruction I3, and modified mappings in RMT 120. Register mapping circuit 122 then uses data in SROB slice entries 152(1) and 154(1) to restore RMT entries corresponding to LRN0 and LRN1 in RMT 120 (e.g., RMT entries 128(0) and 128(1) in RMT 120) to a previous mapping state. Figure 3

[0038] In some examples, register mapping circuit 122 can use program order identifiers 130(0)-130(L) of RMT entries 128(0)-128(L) to determine LRNs LRN0-LRN L ​​Which of the RMT entries needs to be restored to its previous mapping state? For example, register mapping circuit 122 can determine, based on program sequence identifiers 130(0)-130(L), that the mapping state of one of the RMT entries 128(0)-128(L) was modified by an uncommitted instruction older than the target instruction I3. Register mapping circuit 122 can then optimize the restoration of RMT 120 by not performing a traversal of the SROB slices 150(0)-150(L) corresponding to the LRN of that particular RMT entry.

[0039] Figure 1 A flowchart 300 according to some embodiments is provided, which illustrates Figure 1 Exemplary operation of register mapping circuit 122 for using Figure 3 Parallel traversal of SROB 148 is used to perform flush recovery. For clarity, in the description Figure 1 Referenced at the time Figure 2 and Figure 3 The elements. In Figure 2 In this process, the operation begins with the register mapping circuit 122 of processor device 102 detecting uncommitted instructions (e.g., within the execution pipeline 104 of processor device 102). Figure 2 The uncommitted instruction I0 includes instructions to multiple LRNs LRN0-LRN. L The write instruction to the destination LRN LRN0 in the register mapping circuit 122 allocates to the uncommitted instruction I0 the SROB slice entries 152(0)-152(X) of the multiple SROB slices 150(0)-150(L) of the processor device 102 corresponding to the destination LRN LRN0 in the multiple SROB slices 150(0)-150(L), wherein each SROB slice in the multiple SROB slices 150(0)-150(L) is associated with the multiple LRN LRN0-LRN L The corresponding LRN in the diagram corresponds to (box 304). In some embodiments, the register mapping circuit 122 also assigns multiple ROB entries 142(0)-142(R) of ROB 140 to multiple corresponding uncommitted instructions (e.g., ...) in the execution pipeline 104 of the processor device 102. Figure 1 The instructions I0-I6), including multiple uncommitted instructions I0-I6, include uncommitted instruction I0 (box 306).

[0040] The register mapping circuit 122 then receives an indication 200 of a pipeline flush from a target instruction I3 within the execution pipeline 104 (block 308). In response, the register mapping circuit 122 restores the plurality of RMT entries 128(0)-128(L) of the RMT 120 to a corresponding plurality of previous mapping states based on a parallel traversal of the plurality of SROB slices 150(0)-150(L) corresponding to the LRNs in the plurality of RMT entries 128(0)-128(L) (block 310). In some embodiments, the register mapping circuit 122 can further restore the plurality of RMT entries 128(0)-128(L) to the corresponding plurality of previous mapping states based on the plurality of program order identifiers 130(0)-130(L) in the plurality of RMT entries 128(0)-128(L) (block 312).

[0041] To illustrate exemplary operations of the register mapping circuit 122 for allocating new SROB slice entries 152(0)-152(X), 154(0)-154(X) in accordance with some embodiments, Figure 4 Figure 4 A flowchart 400 is provided. For purposes of clarity, the elements of the Figure 1 are referenced while describing the flowchart 400. In the Figure 4 , it is assumed that the count of SROB slice entries 152(0)-152(X), 154(0)-154(X) of the SROB 148 in the Figure 1 is less than the count of ROB entries 142(0)-142(R) of the ROB 140 in the Figure 1 . In the Figure 4 , operations begin with the register mapping circuit 122 determining whether an SROB slice entry (e.g., SROB slice 150(0)) of the plurality of SROB slice entries 152(0)-152(X) of the SROB slice is available for allocation (block 402). If so, the register mapping circuit 122 allocates the SROB slice entry, such as SROB slice entry 152(0) (block 404). Figure 5

[0042] However, if the register mapping circuit 122 determines that no SROB slice entry is available for allocation at decision block 402, the register mapping circuit 112 initiates a stall of the execution pipeline 104 of the processor device 102 (block 406). Once the stall is resolved (i.e., by one of the SROB slice entries 152(0)-152(X) becoming available for allocation), the register mapping circuit 122 allocates the SROB slice entry, such as SROB slice entry 152(0) (block 408).

[0043] Figure 1 A flowchart 500 is provided, which illustrates​​Figure 1 example operation of the register mapping circuit 122 for allocating a new SROB slice entry 152(0)-152(X), 154(0)-154(X) in an embodiment of the ROB 140 of Figure 5 for clarity, references are made to elements of Figure 1 Figure 5 Figure 1 Figure 1 Figure 5 Figure 1 The operation in the embodiment of the register mapping circuit 122 for allocating a new SROB slice entry 152(0)-152(X), 154(0)-154(X) in an embodiment of the PSROB 156 of

[0044] However, if the register mapping circuit 122 determines at decision block 502 that no SROB slice entry is available for allocation, the register mapping circuit 112 allocates the oldest SROB slice entry, e.g., SROB slice entry 152(0) (block 506). Subsequently, in the course of performing a flush recovery, the register mapping circuit 122 determines whether the overwritten contents of the oldest SROB slice entry 152(0) are necessary for the flush recovery (block 508). For example, the register mapping circuit 122 can determine that the oldest SROB slice entry among the remaining SROB slice entries 152(0)-152(X) of the SROB slice 150(0) corresponds to an instruction that follows the target instruction in program order. If the overwritten contents of the oldest SROB slice entry 152(0) are determined to be necessary for the flush recovery, the register mapping circuit further restores the plurality of RMT entries 128(0)-128(L) to the corresponding plurality of previous mapping states based on the traversal of the ROB 140 (block 510). Otherwise, processing continues as described in the embodiments disclosed herein (block 512).

[0045] To illustrate the example operation of the register mapping circuit 122 for allocating a new SROB slice entry 152(0)-152(X), 154(0)-154(X) in an embodiment of the PSROB 156 of Figure 1 Figure 6 To illustrate the example operation of the register mapping circuit 122 for allocating a new SROB slice entry 152(0)-152(X), 154(0)-154(X) in an embodiment of the PSROB 156 of Figure 6 A flowchart 600 is provided. For clarity, references are made to elements of Figure 1 ​​​​​​The elements of Figure 6 Figure 1 The ROB 140 of Figure 1 The count of SROB slice entries 152(0)-152(X), 154(0)-154(X) of the SROB 148 is less than the count of ROB entries 142(0)-142(R) of the ROB 140 of Figure 6 In the event that the count of SROB slice entries 152(0)-152(X), 154(0)-154(X) of the SROB 148 is less than the count of ROB entries 142(0)-142(R) of the ROB 140 of Figure 7 In the event that the count of SROB slice entries 152(0)-152(X), 154(0)-154(X) of the SROB 148 is less than the count of ROB entries 142(0)-142(R) of the ROB 140 of

[0046] However, if the register mapping circuit 122 determines at decision block 402 that no SROB slice entry is available for allocation, the register mapping circuit 112 evicts the oldest SROB slice entry (e.g., SROB slice entry 152(0)) of the plurality of SROB slice entries 152(0)-152(X) of the SROB slice 150(0) to the PSROB 156 (block 606). The register mapping circuit 122 then allocates the oldest SROB slice entry 152(0) (block 608). The register mapping circuit 122 subsequently determines whether the overwritten contents of the evicted oldest SROB slice entry 152(0) are necessary for flush recovery in performing a flush recovery process (block 610). If so, the register mapping circuit further restores the plurality of RMT entries 128(0)-128(L) to the corresponding plurality of previous mapping states based on the traversal of the PSROB 156 (block 612). Otherwise, processing continues as described in the embodiments disclosed herein (block 614).

[0047] Figure 1 is a block diagram of an exemplary processor-based device 700 (e.g., the processor-based device 100 of Figure 1 The processor-based device 700 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based device 700 includes a processor 702. The processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc., and can correspond to the processor 102 of Figure 7 ​the processor device 102. The processor 702 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, the processor 702 includes an instruction cache 704 for temporary, fast access memory storage of instructions and an instruction processing circuit 710. Instructions retrieved or prefetched from memory (e.g., from system memory 708 over system bus 706) are stored in instruction cache 704. Instruction processing circuit 710 is configured to process instructions retrieved into instruction cache 704 and process the instructions for execution.

[0048] The processor 702 and system memory 708 are coupled to a system bus 706 and can interconnect peripheral devices included in the processor-based device 700. As is known, the processor 702 communicates with these other devices by exchanging address, control, and data information over the system bus 706. For example, as an example of a peripheral device, the processor 702 can transmit bus transaction requests to a memory controller 712 in system memory 708. Although Figure 7 not shown in FIG. 7, multiple system buses 706 can be provided, wherein each system bus constitutes a different fabric. In this example, the memory controller 712 is configured to provide memory access requests to a memory array 714 in system memory 708. The memory array 714 includes an array of memory bitcells for storing data. As non-limiting examples, system memory 708 can be read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0049] Other devices can be connected to the system bus 706. As Figure 7 shown in FIG. 7, these devices can include, as examples, system memory 708, one or more input devices 716, one or more output devices 718, a modem 724, and one or more display controllers 720. The input device(s) 716 can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) 718 can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem 724 can be any device configured to allow exchange of data to and from a network 726. The network 726 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), Bluetooth TMNetwork and the Internet. Modem 724 can be configured to support any type of communication protocol required. Processor 702 can also be configured to access display controller 720 over system bus 706 to control information sent to one or more displays 722. Displays 722 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0050] ​ Processor-based device 700 in FIG. 7 can include a set of instructions 728 that can be encoded with an explicit consumer naming model based on arrival, executed by processor 702 for any application required according to the specification. Instructions 728 can be stored in system memory 708, processor 702, and / or instruction cache 704 as an example of a non-transitory computer-readable medium 730. Instructions 728 can also reside, completely or at least partially, within system memory 708 and / or processor 702 during their execution. Instructions 728 can further be transmitted or received over network 726 via modem 724, such that network 726 includes computer- readable medium 730.

[0051] While computer-readable medium 730 is shown in an example embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions 728. The term "computer- readable medium" shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by a processing device and that cause the processing device to perform any one or more of the methodologies of embodiments disclosed herein. Therefore, the

[0052] Embodiments disclosed herein include various steps. The steps of embodiments disclosed herein can be formed by hardware components, or can be embodied in machine- executable instructions, which can be used to program a general-purpose or a special-purpose processor to perform the steps. Alternatively, the steps can be performed by a combination of hardware and software processes.

[0053] The embodiments disclosed herein can be provided as a computer program product or software process running on a computer system or other electronic device, which can include a computer readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the various embodiments disclosed herein. The machine-readable medium can include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, DVDs, ROMs, RAMs, erasable programmable

[0054] Unless specifically stated otherwise and as can be apparent to one skilled in the art and as specifically discussed elsewhere herein, the words "comprise," "comprises," "comprising," "including," "includes," "contain," "contains," "including," "includes," "carry" and "carries" and any variations thereof herein are used inclusively and not with a limiting meaning each time they appear.

[0055] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the description above. In addition, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the embodiments as described herein.

[0056] Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna system described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such

[0057] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field- Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In addition, the controller can be a processor. The processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0058] Embodiments disclosed herein can be embodied in hardware and in instructions stored in hardware, and can reside, for example, in RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. In the alternative, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0059] It is also noted that the operational steps described in any of the example embodiments herein are described to provide examples and discussion. The operations described can be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step can actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the example embodiments can be combined. One of ordinary skill in the art will also understand that information and signals can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0060] Unless specifically stated otherwise, any methods specified in this agreement are not to be construed as requiring their steps to be performed in a particular order. Accordingly, if a method claim does not actually recite a specific order thereof, or that the steps are to be performed in a specific order, then it is not intended that any particular order be inferred, unless specifically stated.

[0061] Various modifications and changes can be made as would be obvious to a person skilled in the art having the benefit of this disclosure without departing from the spirit or ambit of the application. The present application should be interpreted in the broadest way allowable by law and the principles and applications disclosed herein should not be limited to the embodiments described hereinabove by way of example.

Claims

1. A register mapping circuit in a processor device, the register mapping circuit comprising: A rename mapping table (RMT) is provided, which includes multiple RMT entries, each RMT entry representing a mapping from multiple logical register numbers (LRNs) to multiple physical register numbers (PRNs). as well as A reordering buffer (ROB), which includes multiple ROB entries; A slice reordering buffer (SROB) is further divided into multiple SROB slices, each SROB slice including multiple SROB slice entries, wherein each SROB slice is configured to track only uncommitted instructions written to the corresponding LRN in the multiple LRNs; The register mapping circuit is configured as follows: Uncommitted instructions are detected within the execution pipeline of the processor device, the uncommitted instructions including write instructions to a destination LRN among the plurality of LRNs; The SROB slice entry in the plurality of SROB slices that are assigned to the destination LRN among the plurality of SROB slices of the SROB that are assigned to the unsubmitted instruction; Receive instructions for pipeline flushing from the target instructions within the execution pipeline; as well as In response to receiving the instruction for pipeline flushing, the plurality of RMT entries are restored to their corresponding previous mapping states based on the sequential access of the plurality of SROB slices corresponding to the LRNs of the plurality of RMT entries, which are executed in parallel.

2. The register mapping circuit according to claim 1, wherein: The plurality of RMT entries include corresponding plurality of program sequence identifiers; and The register mapping circuit is configured to further restore the plurality of RMT entries to their corresponding previous mapping states based on the plurality of program sequence identifiers of the plurality of RMT entries.

3. The register mapping circuit according to claim 1, wherein: The register mapping circuit is further configured to assign the plurality of ROB entries to the corresponding plurality of uncommitted instructions in the execution pipeline of the processor device, wherein the plurality of uncommitted instructions includes the uncommitted instruction.

4. The register mapping circuit of claim 3, wherein the count of the plurality of SROB slice entries of each of the plurality of SROB slices of the SROB is equal to the count of the plurality of ROB entries.

5. The register mapping circuit according to claim 3, wherein: The count of the multiple SROB slice entries in each of the multiple SROB slices of the SROB is less than the count of the multiple ROB entries; and The register mapping circuit is also configured to allocate the SROB slice entries by being configured to perform the following: It was determined that none of the plurality of SROB slice entries for the SROB slice were available for allocation; as well as In response to the determination that no SROB slice entry is available for allocation among the plurality of SROB slice entries of the SROB slice: Initiate a delay in the execution pipeline of the processor device; And in response to the resolution of the delay, the SROB slice entry is allocated.

6. The register mapping circuit according to claim 3, wherein: The count of the multiple SROB slice entries in each of the multiple SROB slices of the SROB is less than the count of the multiple ROB entries; and The register mapping circuit is also configured to allocate the SROB slice entries by being configured to perform the following: It was determined that none of the plurality of SROB slice entries for the SROB slice were available for allocation; as well as In response to determining that no SROB slice entry is available for allocation among the plurality of SROB slice entries of the SROB slice, the oldest SROB slice entry is allocated.

7. The register mapping circuit of claim 6, wherein the register mapping circuit is configured to restore the plurality of RMT entries to the corresponding plurality of previous mapping states by performing the following: While traversing the SROB slices, determining the rewritten content of the oldest SROB slice entry is necessary for flush recovery; and In response to the determination that the rewritten content of the oldest SROB slice entry is necessary for flush recovery, the plurality of RMT entries are further restored to the corresponding plurality of previous mapping states based on the traversal of the ROB.

8. The register mapping circuit according to claim 3, wherein: The register mapping circuit also includes a portion of the serial ROB (PSROB); The count of the multiple SROB slice entries in each of the multiple SROB slices of the SROB is less than the count of the multiple ROB entries; and The register mapping circuit is also configured to allocate the SROB slice entries by being configured to perform the following: It was determined that none of the plurality of SROB slice entries for the SROB slice were available for allocation; as well as In response to the determination that no SROB slice entry is available for allocation among the plurality of SROB slice entries of the SROB slice: The oldest SROB slice entry among the plurality of SROB slice entries of the SROB slice is expelled to the PSROB; and Assign the oldest SROB slice entry.

9. The register mapping circuit of claim 8, wherein the register mapping circuit is configured to restore the plurality of RMT entries to the corresponding plurality of previous mapping states by performing the following: While performing the traversal of the SROB slices, it is determined whether the rewrite content of the oldest SROB slice entry being evicted is necessary for flush recovery; and In response to the determination that the rewritten content of the oldest SROB slice entry being evicted is necessary for flush recovery, the plurality of RMT entries are further restored to their corresponding plurality of previous mapping states based on the traversal of the PSROB.

10. A method for performing flush recovery using parallel traversal of a slice reorder buffer (SROB), the method comprising: Uncommitted instructions within the execution pipeline of the processor device are detected by the register mapping circuitry of the processor device. The uncommitted instructions include write instructions to a destination LRN in a plurality of logical register numbers (LRNs), wherein the register mapping circuitry includes a reorder buffer (ROB). The SROB slice entry in the SROB slice of the processor device corresponding to the destination LRN is assigned to the uncommitted instruction, wherein each of the multiple SROB slices is configured to track only the uncommitted instruction written to the corresponding LRN in the multiple LRNs; Receive instructions for pipeline flushing from the target instructions within the execution pipeline; as well as In response to receiving the instruction for pipeline flushing, based on the sequential access of the plurality of SROB slices corresponding to the LRNs of the plurality of RMT entries executed in parallel, the plurality of RMT entries are restored to their corresponding plurality of previous mapping states.

11. The method of claim 10, wherein: The plurality of RMT entries include corresponding plurality of program sequence identifiers; and Further, based on the multiple program sequence identifiers of the multiple RMT entries, the multiple RMT entries are restored to the corresponding multiple previous mapping states.

12. The method of claim 10, further comprising: The reordering buffer (ROB) is assigned to a plurality of corresponding uncommitted instructions in the execution pipeline of the processor device, wherein the plurality of uncommitted instructions include the uncommitted instructions.

13. The method of claim 12, wherein the count of the plurality of SROB slice entries for each of the plurality of SROB slices of the SROB is equal to the count of the plurality of ROB entries.

14. The method according to claim 12, wherein: The count of the multiple SROB slice entries in each of the multiple SROB slices of the SROB is less than the count of the multiple ROB entries; and Assigning the SROB slice entries includes: It was determined that none of the plurality of SROB slice entries for the SROB slice were available for allocation; and In response to the determination that no SROB slice entry is available for allocation among the plurality of SROB slice entries of the SROB slice: Initiating a delay in the execution pipeline of the processor device; and allocating the SROB slice entry in response to the resolution of the delay.

15. The method according to claim 12, wherein: The count of the multiple SROB slice entries in each of the multiple SROB slices of the SROB is less than the count of the multiple ROB entries; and Assigning the SROB slice entries includes: It was determined that none of the plurality of SROB slice entries for the SROB slice were available for allocation; as well as In response to determining that no SROB slice entry is available for allocation among the plurality of SROB slice entries of the SROB slice, the oldest SROB slice entry is allocated.

16. The method of claim 15, wherein restoring the plurality of RMT entries to the corresponding plurality of previous mapping states comprises: While performing the traversal of the SROB slice, determining the rewrite content of the oldest SROB slice entry is necessary for flush recovery; as well as In response to the determination that the rewritten content of the oldest SROB slice entry is necessary for flush recovery, the plurality of RMT entries are further restored to the corresponding plurality of previous mapping states based on the traversal of the ROB.

17. The method according to claim 12, wherein: The count of the multiple SROB slice entries in each of the multiple SROB slices of the SROB is less than the count of the multiple ROB entries; and Assigning the SROB slice entries includes: It was determined that none of the plurality of SROB slice entries for the SROB slice were available for allocation; and In response to the determination that no SROB slice entry is available for allocation among the plurality of SROB slice entries of the SROB slice: The oldest SROB slice entry among the plurality of SROB slice entries of the SROB slice is expelled to a partial serial ROB (PSROB); and the oldest SROB slice entry is assigned.

18. The method of claim 17, wherein restoring the plurality of RMT entries to the corresponding plurality of previous mapping states comprises: While performing the traversal of the SROB slice, it is necessary to determine the rewrite content of the oldest SROB slice entry that was evicted for flush recovery; as well as In response to the determination that the rewritten content of the oldest SROB slice entry being evicted is necessary for flush recovery, the plurality of RMT entries are further restored to their corresponding plurality of previous mapping states based on the traversal of the PSROB.

19. A non-transitory computer-readable medium having stored thereon computer-executable instructions, which, when executed by a processor device, cause the processor device to: Detecting uncommitted instructions within the execution pipeline of the processor device, the uncommitted instructions including write instructions to a destination LRN in a plurality of logical register numbers (LRNs), wherein the processor device includes a reorder buffer (ROB); The SROB slice entry in the SROB slice of the Slice Reorder Buffer (SROB) of the processor device that is assigned to the uncommitted instruction is the SROB slice entry of the SROB slice corresponding to the destination LRN, wherein each of the plurality of SROB slices is configured to track only the uncommitted instruction written to the corresponding LRN in the plurality of LRNs; Receive instructions for pipeline flushing from the target instructions within the execution pipeline; as well as In response to receiving the instruction for pipeline flushing, based on the sequential access of the plurality of SROB slices corresponding to the LRNs of the plurality of RMT entries executed in parallel, the plurality of RMT entries are restored to their corresponding plurality of previous mapping states.

20. The non-transitory computer-readable medium according to claim 19, wherein: The plurality of RMT entries include corresponding plurality of program sequence identifiers; and The computer-executable instructions cause the processor device to further restore the plurality of RMT entries to the corresponding plurality of previously mapped states based on the plurality of program sequence identifiers of the plurality of RMT entries.

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