A memory access method and device based on MCAL and a multi-core chip
By adopting the MCAL specification in multi-core chips to set a general timer variable for each core and using internal bus addresses for mapping and offsetting, the problems of slow external bus access speed and unreasonable memory allocation are solved, achieving fast memory access and efficient memory utilization.
CN116126776BActive Publication Date: 2026-07-03BEIJING TONGFANG MICROELECTRONICS
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING TONGFANG MICROELECTRONICS
- Filing Date
- 2022-12-19
- Publication Date
- 2026-07-03
AI Technical Summary
Technical Problem
In existing multi-core chips, slow external bus access speed and unreasonable memory allocation lead to memory waste and illegal segment copying problems.
Method used
A unified address processing mechanism is adopted, and a general timer variable is set for each core through the MCAL specification. The internal bus address is used for mapping and offsetting, so that each core can quickly access the internal memory of the core through the internal bus.
Benefits of technology
This allows different cores to quickly access their respective internal memory via an internal bus, avoiding memory waste and illegal segment copying, and improving access speed and memory utilization efficiency.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN116126776B_ABST
Abstract
This application discloses a memory access method, apparatus, and multi-core chip based on MCAL. The memory access method, using the General Purpose Timer (GPT) in MCAL as an example, includes: setting i+1 general-purpose timer variables numbered from 0 to i for i+1 cores; setting the starting address of the internal memory of the i-th core allocated to the i-th general-purpose timer variable as the actual physical address accessed via the external bus; offsetting the starting address of the internal memory of the i-th core mapped by the i-th general-purpose timer variable, so that the i-th general-purpose timer variable is remapped to the internal bus address accessed via the internal bus; constructing a pointer array of structure variables based on the i+1 general-purpose timer variables; and accessing the internal memory of the i-th core via the internal bus through the i-th general-purpose timer variable.
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Citation Information
Patent Citations
CN101196859A
CN101673254A