Eight-channel dram

Abstract

A DRAM device may have eight channels. In a first mode, these channels may all be operated independently of each other and each access different internal memory cores. In a second mode, four of the eight channels may be inactivated. In a third mode, six of the eight channels are inactivated leaving two channels active. In a fourth mode, seven channels are inactivated leaving a single channel active. In each of the second mode, third mode, and fourth mode, the remaining active channel(s) respectively access the internal memory cores that otherwise would have been accessed by the inactivated channels. To help reduce the pin count of an eight-channel device (and associated controller), various signals may be shared between the eight channels and / or subgroups (e.g., four channels per subgroup, two channels per subgroup, etc.).

Description

Docket: 765-0253P - 11441US01EIGHT-CHANNEL DRAMBRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure 1 A is a block diagram illustrating a first mode of an eight-channel DRAM.

[0002] Figure IB is a block diagram illustrating a second mode of an eight-channel DRAM.

[0003] Figure 1C is a block diagram illustrating example active circuitry when the eightchannel DRAM is in the second mode.

[0004] Figure ID is a block diagram illustrating a third mode of an eight-channel DRAM.

[0005] Figure IE is a block diagram illustrating example active circuitry when the eightchannel DRAM is in the third mode.

[0006] Figure IF is a block diagram illustrating example active circuitry for a fourth mode of an eight-channel DRAM.

[0007] Figure 2A illustrates example mounting and channel interconnections to utilize a controller eight-channel mode.

[0008] Figure 2B illustrates example mounting and channel interconnections to utilize a controller eight-channel mode with DRAMs in a clamshell configuration.

[0009] Figure 2C illustrates example mounting and channel interconnections to utilize a controller four-channel mode.

[0010] Figure 2D illustrates example mounting and channel interconnections to utilize a controller four-channel mode with DRAMs in a clamshell configuration.

[0011] Figure 2E illustrates example mounting and channel interconnections to utilize a controller two-channel mode.

[0012] Figure 2F illustrates example mounting and channel interconnections to utilize a controller two-channel mode with DRAMs in a clamshell configuration.

[0013] Figure 3 is a block diagram illustrating an eight-channel DRAM system with shared clock signals, command / address signal training, and data signal training.

[0014] Figure 4 is a block diagram illustrating an eight-channel DRAM system with perchannel clock signals.

[0015] Figure 5 is a block diagram illustrating an eight-channel DRAM system with bidirectional per-channel clock signals.

[0016] Figure 6 is a block diagram illustrating an eight-channel DRAM system with channel groups sharing clock signals.Docket: 765-0253P - 11441US01

[0017] Figure 7 is a block diagram illustrating an eight-channel DRAM system with channel groups sharing command / address and clock signals.

[0018] Figure 8 is a flowchart illustrating a method of operating an eight-channel mode system.

[0019] Figure 9 is a flowchart illustrating a method of operating a four-channel mode system.

[0020] Figure 10 is a flowchart illustrating a method of operating a two-channel mode system.

[0021] Figure 11 is a block diagram illustrating a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] In an embodiment, a dynamic random access memory (DRAM) device may have eight channels (i.e., an eight-channel device). In a first mode (i.e., eight-channel mode), these channels may all be operated independently of each other and each access (e.g., read and write) operates on different internal memory cores. In a second mode, four of the eight channels may be inactivated (i.e., four-channel mode). In an embodiment, in a third mode, six of the eight channels are inactivated leaving two channels active (i.e., two-channel mode). In an embodiment, in a fourth mode, seven channels are inactivated leaving a single channel active (i.e., one-channel mode). In each of the second mode, third mode, and fourth mode, the remaining active channel(s) respectively access the internal memory cores that otherwise would have been accessed by the inactivated channels. In an embodiment, the data width of the active channels is the same as the data width used in the eight-channel mode.

[0023] To help reduce the pin count of an eight-channel device (and associated controller), various signals may be shared between the eight channels and / or subgroups (e.g., four channels per subgroup, two channels per subgroup, etc.). For example, a single write clock signal may be shared among the channels of a two- or four-channel subgroup. Similarly, for example, a single read clock signal may be shared among the channels of a two- or four-channel subgroup. In another example, the command / address (CA) signals may be shared among the channels of a multiple channel subgroup (e.g., a two-channel subgroup, or four-channel subgroup).

[0024] The descriptions and embodiments disclosed herein are made primarily with references to DRAM devices and DRAM memory arrays. This, however, should be understood to be a first example due at least to the widespread adoption of DRAM technology. It should beDocket: 765-0253P - 11441US01 understood that other memory technologies may also benefit from the methods and / or apparatus described herein. These memory technologies include, but are not limited to static random access memory (SRAM), non-volatile memory (such as flash), conductive bridging random access memory (CBRAM — a.k.a., programmable metallization cell — PMC), resistive random access memory (a.k.a., RRAM or ReRAM), magnetoresistive random-access memory (MRAM), Spin-Torque Transfer (STT-MRAM), phase change memory (PCM), and the like, and / or combinations thereof. Accordingly, it should be understood that in the disclosures and / or descriptions given herein, these aforementioned technologies may be substituted for, included with, and / or encompassed within, the references to DRAM, DRAM devices, and / or DRAM arrays made herein.

[0025] Figure 1 A is a block diagram illustrating a first mode of an eight-channel DRAM. In Figure 1 A, DRAM device 101 is configured with eight active channels: channel A 110a, channel B 110b, channel C 110c, channel D 1 lOd, channel E 1 lOe, channel F 11 Of, channel G 110g, and channel H 1 lOh. The active circuitry / logic for channel A 110a when DRAM device 101 is configured in the eight active channel (a.k.a., eight-channel) mode comprises a set of memory cores 114a that are accessed via channel A, channel A control circuitry 113a, and channel A interface (I / F) circuitry 112a. The active circuitry / logic for channel B 110b when DRAM device 101 is configured in eight-channel mode comprises a set of memory cores 114b that are accessed via channel B, channel B control circuitry 113b, and channel B interface circuitry 112b. The active circuitry / logic for channel C 110c when DRAM device 101 is configured in eight-channel mode comprises a set of memory cores 114c that are accessed via channel C, channel C control circuitry 113c, and channel C interface circuitry 112c. The active circuitry / logic for channel D 1 lOd when DRAM device 101 is configured in eight-channel mode comprises a set of memory cores 114d that are accessed via channel D, channel D control circuitry 113d, and channel D interface circuitry 112d. The active circuitry / logic for channel E 1 lOe when DRAM device 101 is configured in eight-channel mode comprises a set of memory cores 114e that are accessed via channel E, channel E control circuitry 113e, and channel E interface circuitry 112e. The active circuitry / logic for channel F 1 lOf when DRAM device 101 is configured in eight-channel mode comprises a set of memory cores 114f that are accessed via channel F, channel F control circuitry 113f, and channel F interface circuitry 112f. The active circuitry / logic for channel G 110g when DRAM device 101 is configured in eight-channel modeDocket: 765-0253P - 11441US01 comprises a set of memory cores 1 14g that are accessed via channel G, channel G control circuitry 113g, and channel G interface circuitry 112g. The active circuitry / logic for channel H 1 lOh when DRAM device 101 is configured in eight-channel mode comprises a set of memory cores 114h that are accessed via channel H, channel H control circuitry 113h, and channel H interface circuitry 112h.

[0026] Channel A interface circuitry 112a is operatively coupled to control circuitry 113a and memory cores 114a. Channel A control circuitry 113a is operatively coupled to memory cores 114a. Channel A control circuitry 113a receives commands and addresses from channel A interface circuitry 112a. These commands include commands to access (i.e., read, write, activate, precharge, etc.) one or more of memory cores 114a. In the case of a write command, data received at Channel A interface circuitry 112a (e.g., from a controller) is coupled to one or more of memory cores 114a to be stored. In the case of a read command, the addressed one or more of memory cores 114a couples retrieved data to channel A interface circuitry 112a to be transmitted externally (e.g., to a controller).

[0027] Channel B interface circuitry 112b is operatively coupled to control circuitry 113b and memory cores 114a. Channel B control circuitry 113b is operatively coupled to memory cores 114b. Channel B control circuitry 113b receives commands and addresses from channel B interface circuitry 112b. These commands include commands to access (i.e., read, write, activate, precharge, etc.) one or more of memory cores 114b. In the case of a write command, data received at channel B interface circuitry 112b (e.g., from a controller) is coupled to one or more of memory cores 114b to be stored. In the case of a read command, the addressed one or more of memory cores 114b couples retrieved data to channel B interface circuitry 112b to be transmitted externally (e.g., to a controller).

[0028] Channel C interface circuitry 112c is operatively coupled to control circuitry 113c and memory cores 114c. Channel C control circuitry 113c is operatively coupled to memory cores 114c. Channel C control circuitry 113c receives commands and addresses from channel C interface circuitry 112c. These commands include commands to access (i.e., read, write, activate, precharge, etc.) one or more of memory cores 114c. In the case of a write command, data received at channel C interface circuitry 112c (e.g., from a controller) is coupled to one or more of memory cores 114c to be stored. In the case of a read command, the addressed one orDocket: 765-0253P - 11441US01 more of memory cores 114c couples retrieved data to channel C interface circuitry 1 12c to be transmitted externally (e.g., to a controller).

[0029] Channel D interface circuitry 112d is operatively coupled to control circuitry 113d and memory cores 114d. Channel D control circuitry 113d is operatively coupled to memory cores 114d. Channel D control circuitry 113d receives commands and addresses from channel D interface circuitry 112d. These commands include commands to access (i.e., read, write, activate, precharge, etc.) one or more of memory cores 114d. In the case of a write command, data received at channel D interface circuitry 112d (e.g., from a controller) is coupled to one or more of memory cores 114d to be stored. In the case of a read command, the addressed one or more of memory cores 114d couples retrieved data to channel D interface circuitry 112d to be transmitted externally (e.g., to a controller).

[0030] Channel E interface circuitry 112e is operatively coupled to control circuitry 113e and memory cores 114e. Channel E control circuitry 113e is operatively coupled to memory cores 114e. Channel E control circuitry 113e receives commands and addresses from channel E interface circuitry 112e. These commands include commands to access (i.e., read, write, activate, precharge, etc.) one or more of memory cores 114e. In the case of a write command, data received at channel E interface circuitry 112e (e.g., from a controller) is coupled to one or more of memory cores 114e to be stored. In the case of a read command, the addressed one or more of memory cores 114e couples retrieved data to channel E interface circuitry 112e to be transmitted externally (e.g., to a controller).

[0031] Channel F interface circuitry 112f is operatively coupled to control circuitry 113f and memory cores 114f. Channel F control circuitry 113f is operatively coupled to memory cores 114f. Channel F control circuitry 113f receives commands and addresses from channel F interface circuitry 112f. These commands include commands to access (i.e., read, write, activate, precharge, etc.) one or more of memory cores 114f. In the case of a write command, data received at channel F interface circuitry 112f (e.g., from a controller) is coupled to one or more of memory cores 114f to be stored. In the case of a read command, the addressed one or more of memory cores 114f couples retrieved data to channel F interface circuitry 112f to be transmitted externally (e.g., to a controller).

[0032] Channel G interface circuitry 112g is operatively coupled to control circuitry 113g and memory cores 114g. Channel G control circuitry 113g is operatively coupled to memoryDocket: 765-0253P - 11441US01 cores 114g. Channel G control circuitry 1 13g receives commands and addresses from channel G interface circuitry 112g. These commands include commands to access (i.e., read, write, activate, precharge, etc.) one or more of memory cores 114g. In the case of a write command, data received at channel G interface circuitry 112g (e.g., from a controller) is coupled to one or more of memory cores 114g to be stored. In the case of a read command, the addressed one or more of memory cores 114g couples retrieved data to channel G interface circuitry 112g to be transmitted externally (e.g., to a controller).

[0033] Channel H interface circuitry 112h is operatively coupled to control circuitry 113h and memory cores 114h. Channel H control circuitry 113h is operatively coupled to memory cores 114h. Channel H control circuitry 113h receives commands and addresses from channel H interface circuitry 112h. These commands include commands to access (i.e., read, write, activate, precharge, etc.) one or more of memory cores 114h. In the case of a write command, data received at channel H interface circuitry 112h (e.g., from a controller) is coupled to one or more of memory cores 114h to be stored. In the case of a read command, the addressed one or more of memory cores 114h couples retrieved data to channel H interface circuitry 112h to be transmitted externally (e.g., to a controller).

[0034] Channel A-H interfaces 112a-l 12h may include circuitry (e.g., drivers, receivers, etc.) as well as pads, package pins, solder balls, or other means of electrically connecting a DRAM integrated circuit to a substrate, such as a printed circuit board. Memory cores 114a-l 14h may comprise dynamic random access memory (DRAM) arrays or other types of memory arrays, for example, static random access memory (SRAM) arrays, or non-volatile memory arrays such as flash.

[0035] It should be understood from the foregoing that, in eight-channel mode, each of channels A-H 110a-l lOh comprise enough active circuitry and electrical connection points to each operate independently of each other channel A-H 110a- 11 Oh. Each of channels A-H 110a- 11 Oh in eight-channel mode operate the command, address, and data transfer functions of their respective channel A-H 110a-l lOh independently of the other channels A-H 110a-l lOh.

[0036] In an embodiment, each of channels A-H 110a-l lOd respective interface circuitry 112a-l 12h may include bidirectional data (DQ) lines (e.g., eight data lines and one for errordetection, correction, and / or parity.) In another embodiment, each of channels A-H 110a-l lOh respective interface circuitry 112a-l 12h includes eight (8) bidirectional data (DQ) lines. Each ofDocket: 765-0253P - 11441US01 channels A-H 110a-l lOh respective interface circuitry 112a-l 12h includes a C / A bus. Each of the channel A-H 110a- 11 Oh C / A buses may include separate and independent, from the other C / A buses, data bus inversion (DBI), error detection (EDC), and timing signals (e.g., write strobes).

[0037] In an embodiment, each channel A-H 110a-l lOd may each receive one or more independent clocking signal(s) (not shown in Figures 1 A-1B) that drive the operations of that respective channel A-H 110a- 11 Oh. In another embodiment, channels A-H 110a- 11 Oh may all share the one or more clock signal(s). In another embodiment, subgroups (e.g., two channels, four channels) of channels A-H 110a-l lOh may share respective clock signal(s). Thus, multiple channels A-H 110a-l lOh and / or subgroups of channels A-H 110a-l lOh may share common clocking signal(s). For example, channel A 110a, channel B 110b, channel C 110c, and channel D 1 lOd may share a clocking signal while channel E 1 lOe, channel F 1 lOf, channel G 110g, and channel H 1 lOh share another clocking signal. Even though channels A-H 110a-l lOh (or subgroups thereof) function independently, their operations are driven by, and aligned to, the common / shared clocking signal(s).

[0038] Figure IB is a block diagram illustrating a second mode of an eight-channel DRAM. In Figure IB, DRAM device 101 is configured with four active channels: channel A 110a, channel C 110c, channel E 1 lOe, and channel G 110g. Thus, in this four-channel mode, channel B interface circuitry 112b and channel B control circuitry 113b are inactivated, unused, and / or powered off. Likewise, in this four-channel mode, channel D interface circuitry 112d, channel F interface circuitry 112f, channel H interface circuitry 112h, channel D control circuitry 113d, channel F control circuitry 113f, and channel H control circuitry 113h are inactivated, unused, and / or powered off.

[0039] However, in the four-channel mode, memory cores 114b, memory cores 114d, memory cores 114f, and memory cores 114h are configured to be accessed via the remaining four active channels. For example, memory cores 114b may be accessed via channel A 110a, memory cores 114d may be accessed via channel C 110c, memory cores 114f may be accessed via channel E 1 lOe, and memory cores 114h may be accessed via channel G 110g. Memory cores 114b being able to be accessed via channel A 110a in the four-channel mode is illustrated in Figure IB by the arrows from channel A interface circuitry 112a and channel A control circuitry 113a to and from memory cores 114b (which, in eight-channel mode, are accessed viaDocket: 765-0253P - 11441US01 channel B 110b.) Memory cores 1 14d being able to be accessed via channel C 1 10c in the four- channel mode is illustrated in Figure IB by the arrows from channel C interface circuitry 112c and channel C control circuitry 113c to and from memory cores 114d (which, in eight-channel mode, would be accessed via channel D 1 lOd.) Memory cores 114f being able to be accessed via channel E 1 lOe in the four-channel mode is illustrated in Figure IB by the arrows from channel E interface circuitry 112e and channel E control circuitry 113e to and from memory cores 114f (which, in eight-channel mode, would be accessed via channel F 1 lOf.) Memory cores 114h being able to be accessed via channel G 110g in the four-channel mode is illustrated in Figure IB by the arrows from channel G interface circuitry 112g and channel G control circuitry 113g to and from memory cores 114h (which, in eight-channel mode, would be accessed via channel H 1 lOh.) Thus, in an embodiment, the amount of memory accessible via channel A 110a is increased in the four-channel mode (e.g., doubled if memory cores 114a and 114b each have the same capacity.) Likewise, the amount of memory respectively accessible via channel C 110c, channel E 1 lOe, and channel G 110g is increased in the four-channel mode (e.g., doubled if memory cores 114a-l 14h each have the same capacity.)

[0040] Figure 1C is a block diagram illustrating example active circuitry when the eightchannel DRAM is in the second mode. In Figure 1C, the inactive, unused, and / or powered down circuitry in the four-channel mode is not shown. The circuitry that is active in the four-channel mode is shown. Thus, in Figure 1C, channel A interface circuitry 112a, control circuitry 113a, memory cores 114a, and memory cores 114b are shown. Figure 1C also illustrates the active couplings in four-channel mode between: interface circuitry 112a and control circuitry 113a; control circuitry 113a and memory cores 114a; control circuitry 113a and memory cores 114b; memory cores 114a and interface circuitry 112a; and memory cores 114b and interface circuitry 112a. Likewise, in Figure 1C, channel C interface circuitry 112c, channel C control circuitry 113c, memory cores 114c, memory cores 114d are shown. Figure 1C also illustrates the active couplings in four-channel mode between: channel C interface circuitry 112c and channel C control circuitry 113c; channel C control circuitry 113c and memory cores 114c; channel C control circuitry 113c and memory cores 114d; memory cores 114c and channel C interface circuitry 112c; and memory cores 114d and channel C interface circuitry 112c. In Figure 1C, channel E interface circuitry 112e, channel E control circuitry 113e, memory cores 114e, memory cores 114f are shown. Figure 1C also illustrates the active couplings in four-channelDocket: 765-0253P - 11441US01 mode between: channel E interface circuitry 1 12e and channel E control circuitry 113e; channel E control circuitry 113e and memory cores 114e; channel E control circuitry 113e and memory cores 114f; memory cores 114e and channel E interface circuitry 112e; and memory cores 114f and channel E interface circuitry 112e. Finally, in Figure 1C, channel G interface circuitry 112g, channel G control circuitry 113g, memory cores 114g, memory cores 114h are shown. Figure 1C also illustrates the active couplings in four-channel mode between: channel G interface circuitry 112g and channel G control circuitry 113g; channel G control circuitry 113g and memory cores 114g; channel G control circuitry 113g and memory cores 114h; memory cores 114g and channel G interface circuitry 112g; and memory cores 114h and channel G interface circuitry 112g.

[0041] Figure ID is a block diagram illustrating a third mode of an eight-channel DRAM. In Figure ID, DRAM device 101 is configured with two active channels: channel A 110a and channel E 1 lOe. Thus, in this two-channel mode, channel B interface circuitry 112b, channel C interface circuitry 112c, channel D interface circuitry 112d, channel F interface circuitry 112f, channel G interface circuitry 112g, channel H interface circuitry 112h, channel B control circuitry 113b, channel C control circuitry 113c, channel D control circuitry 113d, channel F control circuitry 113f„ channel G control circuitry 113g, and channel H control circuitry 113h are inactivated, unused, and / or powered off.

[0042] However, in the two-channel mode, memory cores 114b, memory cores 114c, memory cores 114d, memory cores 114f, memory cores 114g, and memory cores 114h are configured to be accessed via the remaining two active channels. For example, memory cores 114b- 114d may be accessed via channel A 110a and memory cores 114f-l 14h may be accessed via channel E 1 lOe. Memory cores 114b- 114d being able to be accessed via channel A 110a in the two-channel mode is illustrated in Figure ID by the respective arrows from channel A interface circuitry 112a and channel A control circuitry 113a to and from memory cores 114b- 114d. Memory cores 114f-l 14h being able to be accessed via channel E 1 lOe in the two-channel mode is illustrated in Figure ID by the respective arrows from channel E interface circuitry 112e and channel E control circuitry 113e to and from memory cores 114f- 114h. Thus, in an embodiment, the amount of memory accessible via channel A 110a and channel E 1 lOe is each increased in the two-channel mode (e.g., quadrupled if memory cores 114a-l 14h each have the same capacity) when compared to the eight-channel mode.Docket: 765-0253P - 11441US01

[0043] Figure IE is a block diagram illustrating example active circuitry when the eightchannel DRAM is in the third mode. In Figure IE, the inactive, unused, and / or powered down circuitry in the two-channel mode is not shown. The circuitry that is active in the two-channel mode is shown. Thus, in Figure IE, channel A interface circuitry 112a, control circuitry 113a, and memory cores 114a-l 14d are shown. Figure IE also illustrates the active couplings in two- channel mode between: interface circuitry 112a and control circuitry 113a; control circuitry 113a and memory cores 114a-l 14d; and memory cores 114a-l 14d and interface circuitry 112a. Likewise, in Figure IE, channel E interface circuitry 112e, channel E control circuitry 113e, and memory cores 114e- 114h are shown. Figure IE also illustrates the active couplings in two- channel mode between: channel E interface circuitry 112e and channel E control circuitry 113e; channel E control circuitry 113e and memory cores 114e-l 14h; and memory cores 114e-l 14h and channel E interface circuitry 112e.

[0044] Figure IF is a block diagram illustrating example active circuitry for a fourth mode of an eight-channel DRAM. In Figure IF, DRAM device 101 is configured with one active channel: channel A 110a. Thus, in this one-channel mode, channel B interface circuitry 112b, channel C interface circuitry 112c, channel D interface circuitry 112d, channel E interface circuitry 112e, channel F interface circuitry 112f, channel G interface circuitry 112g, channel H interface circuitry 112h, channel B control circuitry 113b, channel C control circuitry 113c, channel D control circuitry 113d, channel E control circuitry 113e, channel F control circuitry 113f, channel G control circuitry 113g, and channel H control circuitry 113h are inactivated, unused, and / or powered off.

[0045] In the one-channel mode, memory cores 114b- 114h are configured to be accessed via the remaining active channel A 110a. Memory cores 114b- 114h being able to be accessed via channel A 110a in the one-channel mode is illustrated in Figure IF by the respective arrows from channel A interface circuitry 112a and channel A control circuitry 113a to and from memory cores 114b- 114h. Thus, in an embodiment, the amount of memory accessible via channel A 110a is increased in the one-channel mode (e.g., multiplied by eight if memory cores 114a-l 14h each have the same capacity) when compared to the eight-channel mode.

[0046] In Figure IF, the inactive, unused, and / or powered down circuitry in the one-channel mode is not shown. The circuitry that is active in the one-channel mode is shown. Thus, in Figure IF, channel A interface circuitry 112a, control circuitry 113a, and memory cores 114a-Docket: 765-0253P - 11441US01114h are shown. Figure IE also illustrates the active couplings in one-channel mode between: interface circuitry 112a and control circuitry 113a; control circuitry 113a and memory cores 114a-l 14h; and memory cores 114a-l 14h and interface circuitry 112a.

[0047] In an embodiment, the DRAM device 101 includes one or more registers (e.g., in one or more of control circuitry 113a-133g) to store a register value that determines modes (e.g., eight-, four-, or two-channel modes) such that interface circuitry 112a- 112g are operated and / or coupled to the internal circuits in the manner as described and / or illustrated in the Figures. For example, this register value (i.e., mode) may be set by a memory controller via one or more of the channels. The memory controller includes an interface that issues a mode register set (MRS) command, along with the register value to DRAM device 101. DRAM device 101 receives the MRS command and stores the register value(s) in the register(s) to set the mode. In another example, the register value(s) may also be set using serial presence detect circuitry where parameter information pertaining to DRAM 101, stored in a memory device (such as a serial presence detect (SPD) device) or DRAM 101 itself is read by the memory controller or other interface. The memory controller then, based on the parameter information, sets the mode using one of the methods described herein. In another example, the register value (or mode) may be set by a signal (i.e., voltage) asserted on a pin during power-up, reset, and / or normal operating state. The memory controller may assert the voltage on the pin which is included on DRAM 101. In another embodiment, one or more different package or module designs can be used for the different modes. These different package or module designs may also be configured set the signal (i.e., voltage) on a pin of DRAM 101 that determines the mode.

[0048] Figure 2A illustrates example mounting and channel interconnections to utilize a controller eight-channel mode. In Figure 2A, memory system 201 comprises eight-channel memory device 210, controller 220, and substrate 291. Memory device 210 includes eight (8) memory access channel interfaces 210a-210h. Controller 220 includes eight (8) memory access channel interfaces 220a-220h. In Figure 2A, memory device 210 is configured in eight-channel mode. Similarly, controller 220 is configured in eight-channel mode.

[0049] Controller 220 and memory device 210 may be one or more integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 220, manages the flow of data going to and from memory devices and / or memory modules. Memory device 210 may be a standalone device, or may be a component of a memory moduleDocket: 765-0253P - 11441US01 such as a DIMM module used in servers. In an embodiment, memory device 210 may be a device that adheres to, or is compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory device 210 may be, or comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 220 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect. In addition, memory controller functionality may be disposed on a separate Input / Output (I / O) die along with the transmitter / receiver circuits that interface to the memory device. Such an I / O die may include other types of I / O interfaces, as well as one or more chiplet interfaces that communicate with one or more respective CPU chiplet dies. The I / O die and CPU chiplet dies may be co-packaged together and coupled to one-another via a silicon interposer.

[0050] In Figure 2A, controller 220 and memory device 210 are mounted on the same side of substrate 291. Substrate 291 operatively couples channel H interface 220h with channel H interface 21 Oh, channel G interface 220g with channel G interface 210g, channel F interface 220f with channel F interface 21 Of, channel E interface 220e with channel E interface 210e, channel D interface 220d with channel D interface 21 Od, channel C interface 220c with channel C interface 210c, channel B interface 220b with channel B interface 210b, and channel A interface 220a with channel A interface 210a.

[0051] Figure 2B illustrates example mounting and channel interconnections to utilize a controller eight-channel mode with the DRAMs in a clamshell configuration. In Figure 2B, memory system 202 comprises eight-channel memory device 210, eight-channel memory device 211, controller 220, and substrate 292. Memory device 210 includes eight (8) memory access channel interfaces 210a-210h. Memory device 211 includes eight (8) memory access channel interfaces 21 la-21 Ih. Controller 220 includes eight (8) memory access channel interfaces 220a- 220h. In Figure 2B, memory device 210 and memory device 211 are configured in four-channel mode. Controller 220 is configured in eight-channel mode.

[0052] In Figure 2B, controller 220 and memory device 210 are mounted on the same side of substrate 292. Memory device 211 is mounted on the opposite side of substrate 292 as memoryDocket: 765-0253P - 11441US01 device 210 and controller 220. Substrate 292 operatively couples channel H interface 220h with channel G interface 211g, channel G interface 220g with channel G interface 210g, channel F interface 220f with channel E interface 21 le, channel E interface 220e with channel E interface 21 Oe, channel D interface 220d with channel C interface 211c, channel C interface 220c with channel C interface 210c, channel B interface 220b with channel A interface 211a, and channel A interface 220a with channel A interface 210a.

[0053] Figure 2C illustrates example mounting and channel interconnections to utilize a controller four-channel mode. In Figure 2C, memory system 203 comprises eight-channel memory device 210, controller 220, and substrate 293. Memory device 210 includes eight (8) memory access channel interfaces 210a-210h. Controller 220 includes eight (8) memory access channel interfaces 220a-220h. In Figure 2C, memory device 210 is configured in four-channel mode. Similarly, controller 220 is configured in four-channel mode.

[0054] In Figure 2C, controller 220 and memory device 210 are mounted on the same side of substrate 293. Substrate 291 operatively couples channel G interface 220g with channel G interface 210g, channel E interface 220e with channel E interface 21 Oe, channel C interface 220c with channel C interface 210c, and channel A interface 220a with channel A interface 210a.

[0055] Figure 2D illustrates example mounting and channel interconnections to utilize a controller four-channel mode with DRAMs in a clamshell configuration. In Figure 2D, memory system 204 comprises eight-channel memory device 210, eight-channel memory device 211, controller 220, and substrate 294. Memory device 210 includes eight (8) memory access channel interfaces 210a-210h. Memory device 211 includes eight (8) memory access channel interfaces 21 la-21 Ih. Controller 220 includes eight (8) memory access channel interfaces 220a-220h. In Figure 2D, memory device 210 and memory device 211 are configured in two-channel mode. Controller 220 is configured in four-channel mode.

[0056] In Figure 2D, controller 220 and memory device 210 are mounted on the same side of substrate 294. Memory device 211 is mounted on the opposite side of substrate 294 as memory device 210 and controller 220. Substrate 291 operatively couples channel F interface 220f with channel E interface 21 le, channel E interface 220e with channel E interface 210e, channel B interface 220b with channel A interface 211a, and channel A interface 220a with channel A interface 210a.Docket: 765-0253P - 11441US01

[0057] Figure 2E illustrates example mounting and channel interconnections to utilize a controller two-channel mode. In Figure 2E, memory system 203 comprises eight-channel memory device 210, controller 220, and substrate 295. Memory device 210 includes eight (8) memory access channel interfaces 210a-210h. Controller 220 includes eight (8) memory access channel interfaces 220a-220h. In Figure 2E, memory device 210 is configured in two-channel mode. Similarly, controller 220 is configured in two-channel mode.

[0058] In Figure 2E, controller 220 and memory device 210 are mounted on the same side of substrate 295. Substrate 295 operatively couples channel E interface 220e with channel E interface 210e, and channel A interface 220a with channel A interface 210a.

[0059] Figure 2F illustrates example mounting and channel interconnections to utilize a controller two-channel mode with DRAMs in a clamshell configuration. In Figure 2F, memory system 206 comprises eight-channel memory device 210, eight-channel memory device 211, controller 220, and substrate 296. Memory device 210 includes eight (8) memory access channel interfaces 210a-210h. Memory device 211 includes eight (8) memory access channel interfaces 21 la-21 Ih. Controller 220 includes eight (8) memory access channel interfaces 220a-220h. In Figure 2F, memory device 210 and memory device 211 are configured in one-channel mode. Controller 220 is configured in two-channel mode.

[0060] In Figure 2F, controller 220 and memory device 210 are mounted on the same side of substrate 291. Memory device 211 is mounted on the opposite side of substrate 296 as memory device 210 and controller 220. Substrate 296 operatively couples channel A interface 220a with channel A interface 210a, and channel E interface 220e with channel A interface 211a.

[0061] In an embodiment, controller 220, memory device 210 and / or memory device 211 includes one or more registers to store a register value that determines the mode (e.g., eight-, four-, or two-channel modes) as described and / or illustrated in the Figures. For example, this register value (i.e., mode) in memory device 210 and / or memory device 211 may be set by memory controller 220 via one or more of the channels. Memory controller includes an interface (e g., one or more of channel A-H interfaces 220a-220h) that may issue a mode register set (MRS) command, along with the register value to memory device 210 and / or memory device 211. Memory device 210 and / or memory device 211 receives a respective MRS command and stores the register value(s) in the register(s) to set the mode. In another example, the register value(s) may also be set using serial presence detect circuitry where parameter informationDocket: 765-0253P - 11441US01 pertaining to memory device 210 and / or memory device 211, stored in a memory device (such as a serial presence detect (SPD) device) or memory device 210 and / or memory device 211 itself is read by the memory controller (which may set the mode of controller 220) or other interface. Memory controller 220 may then, based on the parameter information, set the mode(s) using one of the methods described herein. In another example, the register value (or mode) may be set by a signal (i.e., voltage) asserted on a pin of memory device 210 and / or memory device 211 during power-up, reset, and / or normal operating state. Memory controller 220 may assert the voltage on the pin which is included on memory device 210 and / or memory device 211. In another embodiment, one or more different package or module designs can be used for the different modes. These different package or module designs may also be configured set the signal (i.e., voltage) on a pin of memory device 210 and / or memory device 211 that determines the mode

[0062] Figure 3 is a block diagram illustrating an eight-channel DRAM system with shared clock signals, command / address signal training, and data signal training. In Figure 3, system 300 comprises memory device 310, controller 320, and interconnect 390. Controller 320 comprises channel physical interfaces 320a-320b, memory clock transmitter 325, read clock receiver 326, memory clock oscillator 327, and memory clock generator 328. Memory device 310 comprises channel physical interfaces 310a-310b, memory clock receiver 315, read clock transmitter 316, command / address (CA) interface clock divider 317, data (DQ) interface clock divider 318, and read clock generator 319.

[0063] Memory clock oscillator 327 is operatively coupled with memory clock generator 328 (e g., a phase-locked loop or delay-locked loop). A first output of memory clock generator 328 is provided to memory clock receiver 315 via interconnect 390. A second output of memory clock generator 328 is provided to each of channel physical interfaces 320a-320b. Similarly, read clock generator 319 is operatively coupled with read clock transmitter 316. The output of read clock transmitter 316 is provided read clock receiver 326 via interconnect 390. The output of read clock receiver 326 is provided to each of channel physical interfaces 320a-320b.

[0064] The output of memory clock receiver 315 is provided to CA interface divider 317 and DQ interface divider 318. The output of CA interface divider 317 is provided to each of channel physical interfaces 310a-310b. The output of DQ interface divider 318 is provided to each of channel physical interfaces 310a-310b.Docket: 765-0253P - 11441US01

[0065] In Figure 3, channel A physical interface 320a includes error signal receiver 321a, error handling circuitry 322a, command / address signal training block 360a, and data signal training block 340a. CA signal training (alignment) block 360a includes phase calibrator 365a, clock phase controller 363a, controller command / address circuitry 367a, and command / address transmitters 361a. Clock phase controller 363a adjusts the phase / timing alignment of the memory clock signal received from memory clock generator 328 under the control of phase calibrator 365a. The output of clock phase controller 363a is provided to the clock inputs of command / address transmitters 361a to govern the timing that each command / address signal (e.g., generated by controller command / address circuitry 367a) is transmitted to memory 310 via interconnect 390.

[0066] Channel A physical interface 310a includes error signal circuitry 312a, error signal transmitter circuitry 311, command / address signal training block 350a, and data signal training block 330a. The output of DQ interface divider 318 is provided to the clock input of read clock transmitter 316 to govern the timing that a read clock for channel A is transmitted to controller 320 via interconnect 390. CA training (alignment) block 350a includes command / address receivers 352a and memory command / address signal circuitry 357a. An output of CA interface divider 317 is provided to the clock inputs of command / address receivers 352a to govern the timing that each command / address signal of channel A physical interface 310a is sampled. Similarly, the output of CA interface divider 317 is provided to the clock input of error signal transmitter 31 la to govern the timing that an error signal for channel A is transmitted to controller 320 via interconnect 390.

[0067] Channel A data (DQ) signal training block 340a includes DQ transmitters 341a, DQ receivers 342a, clock phase controller 343a, clock phase controller 344a, phase calibrator 345a, DQ input circuitry 346a, and DQ output circuitry 347a. Clock phase controller 343a adjusts the phase / timing alignment of the memory clock signal received from memory clock generator 328 under the control of phase calibrator 345a. The output of clock phase controller 343a is provided to the clock inputs of data transmitters 341a to govern the timing that each DQ signal (e g., generated by DQ output circuitry 347a) is transmitted to memory device 310 via interconnect 390. Clock phase controller 344a adjusts the phase / timing alignment of the read clock signal received from read clock receiver 326 under the control of phase calibrator 345a. The output ofDocket: 765-0253P - 11441US01 clock phase controller 344a is provided to the clock inputs of data receivers 342a to govern the timing that each DQ signal is sampled.

[0068] Channel A data (DQ) signal training block 330a includes DQ transmitters 331a, DQ receivers 332a, and memory cores 335a. The output of DQ interface divider 318 is provided to the clock input of DQ transmitters 33 la to govern the timing that the data signals (e.g., read data from cores 335a) for channel A are transmitted to controller 320 via interconnect 390. The output of DQ interface divider 318 is provided to the clock input of DQ receivers 332a (e.g., write data destined for cores 335a) to govern the timing that the data signals for channel A are sampled.

[0069] Figure 4 is a block diagram illustrating an eight-channel DRAM system with perchannel clock signals. In Figure 4, memory system 400 comprises memory device 410 and controller 420. Memory device 410 comprises a plurality of memory access channels 410a-410c (e.g., eight). Controller 420 comprises a corresponding plurality of memory access channel interfaces 420a-420c (e.g., eight).

[0070] Memory access channel A interface 420a of controller 420 is operatively coupled with memory access channel A interface 410a of memory device 410. Memory access channel A interface 420a of controller 420 is operatively coupled with memory access channel A interface 410a of memory device 410 via channel A command / address signals CAa[], channel A DQ signals DQa[], channel A read clock signal RCKa, and channel A write clock signal WCKa. Memory access channel B interface 420b of controller 420 is operatively coupled with memory access channel B interface 410b of memory device 410. Memory access channel B interface 420b of controller 420 is operatively coupled with memory access channel B interface 410b of memory device 410 via channel B command / address signals CAb[], channel B DQ signals DQb[], channel B read clock signal RCKb, and channel B write clock signal WCKb. Memory access channel C interface 420c of controller 420 is operatively coupled with memory access channel C interface 410c of memory device 410. Memory access channel C interface 420c of controller 420 is operatively coupled with memory access channel C interface 410c of memory device 410 via channel C command / address signals CAc[], channel C DQ signals DQc[], channel C read clock signal RCKc, and channel C write clock signal WCKc. Accordingly, it should be understood from Figure 4 that each memory channel access interface 410a-410c andDocket: 765-0253P - 11441US01 each memory channel access interface 420a-420c have separate and independent read clock and write clock signals (i.e., transmitters, receivers, control, etc.)

[0071] Figure 5 is a block diagram illustrating an eight-channel DRAM system with bidirectional per-channel clock signals. In Figure 5, memory system 500 comprises memory device 510 and controller 520. Memory device 510 comprises a plurality of memory access channels 510a-510c (e.g., eight). Controller 520 comprises a corresponding plurality of memory access channel interfaces 520a-520c (e.g., eight).

[0072] Memory access channel A interface 520a of controller 520 is operatively coupled with memory access channel A interface 510a of memory device 510. Memory access channel A interface 520a of controller 520 is operatively coupled with memory access channel A interface 510a of memory device 510 via channel A command / address signals CAa[], channel A DQ signals DQa[], and channel A bidirectional read / write clock signal RWCKa. Memory access channel B interface 520b of controller 520 is operatively coupled with memory access channel B interface 510b of memory device 510. Memory access channel B interface 520b of controller 520 is operatively coupled with memory access channel B interface 510b of memory device 510 via channel B command / address signals CAb[], channel B DQ signals DQb[], channel B bidirectional read / write clock signal RWCKb. Memory access channel C interface 520c of controller 520 is operatively coupled with memory access channel C interface 510c of memory device 510. Memory access channel C interface 520c of controller 520 is operatively coupled with memory access channel C interface 510c of memory device 510 via channel C command / address signals CAc[], channel C DQ signals DQc[], channel C bidirectional read / write clock signal RWCKc. Accordingly, it should be understood from Figure 5 that each memory channel access interface 510a-510c and each memory channel access interface 520a- 520c have separate and independent bidirectional read / write clock signals (i.e., transmitters, receivers, control, etc.)

[0073] Figure 6 is a block diagram illustrating an eight-channel DRAM system with channel groups sharing clock signals. In Figure 6, memory system 600 comprises memory device 610 and controller 620. Memory device 610 comprises a plurality of memory access channels 610a- 610c (e.g., eight) and a plurality of shared signal interfaces 610ab-610cd (e.g., four). Controller 620 comprises a corresponding plurality of memory access channel interfaces 620a-620c (e.g., eight), and a corresponding plurality of shared signal interfaces 620ab-620cd (e g., four).Docket: 765-0253P - 11441US01

[0074] Memory access channel A interface 620a of controller 620 is operatively coupled with memory access channel A interface 610a of memory device 610. Memory access channel A interface 620a of controller 620 is operatively coupled with memory access channel A interface 610a of memory device 610 via channel A command / address signals CAa[] and channel A DQ signals DQa[]. Memory access channel B interface 620b of controller 620 is operatively coupled with memory access channel B interface 610b of memory device 610. Memory access channel B interface 620b of controller 620 is operatively coupled with memory access channel B interface 610b of memory device 610 via channel B command / address signals CAb[] and channel B DQ signals DQb[], Memory access channel A interface 610a, memory access channel A interface 620a, memory access channel B interface 610b, memory access channel B interface 620b, share a read clock signal RCKab and a write clock signal WCKab. Accordingly, channels AB shared signal interface 620ab of controller 620 is operatively coupled with channels AB shared signal interface 610ab of memory device 610. Channels AB shared signal interface 620ab of controller 620 is operatively coupled with channels AB shared signal interface 610ab via shared read clock signal RCKab and shared write clock signal WCKab.

[0075] Figure 7 is a block diagram illustrating an eight-channel DRAM system with channel groups sharing command / address and clock signals. In Figure 7, memory system 700 comprises memory device 710 and controller 720. Memory device 710 comprises a plurality of memory access channels 710a-710d (e.g., eight) and a plurality of shared signal interfaces 710ab-710cd (e.g., four). Controller 720 comprises a corresponding plurality of memory access channel interfaces 720a-720d (e.g., eight), and a corresponding plurality of shared signal interfaces 720ab-720cd (e.g., four).

[0076] Memory access channel A interface 720a of controller 720 is operatively coupled with memory access channel A interface 710a of memory device 710. Memory access channel A interface 720a of controller 720 is operatively coupled with memory access channel A interface 710a of memory device 710 via channel A DQ signals DQa[], Memory access channel B interface 720b of controller 720 is operatively coupled with memory access channel B interface 710b of memory device 710. Memory access channel B interface 720b of controller 720 is operatively coupled with memory access channel B interface 710b of memory device 710 via channel B DQ signals DQb[], Memory access channel A interface 710a, memory access channel A interface 720a, memory access channel B interface 710b, memory access channel BDocket: 765-0253P - 11441US01 interface 720b, share command / address signals CAab[], a read clock signal RCKab, and a write clock signal WCKab. Accordingly, channels AB shared signal interface 720ab of controller 720 is operatively coupled with channels AB shared signal interface 710ab of memory device 710. Channels AB shared signal interface 720ab of controller 720 is operatively coupled with channels AB shared signal interface 710ab via shared command / address signals CAab[], shared read clock signal RCKab, and shared write clock signal WCKab.

[0077] Memory access channel C interface 720c of controller 720 is operatively coupled with memory access channel C interface 710c of memory device 710. Memory access channel C interface 720c of controller 720 is operatively coupled with memory access channel C interface 710c of memory device 710 via channel C DQ signals DQc[], Memory access channel D interface 720d of controller 720 is operatively coupled with memory access channel D interface 710d of memory device 710. Memory access channel D interface 720d of controller 720 is operatively coupled with memory access channel D interface 710d of memory device 710 via channel D DQ signals DQd[], Memory access channel C interface 710c, memory access channel C interface 720c, Memory access channel D interface 710d, memory access channel D interface 720d, share command / address signals CAcd[], a read clock signal RCKcd, and a write clock signal WCKcd. Accordingly, channels CD shared signal interface 720cd of controller 720 is operatively coupled with channels CD shared signal interface 710cd of memory device 710. Channels CD shared signal interface 720cd of controller 720 is operatively coupled with channels CD shared signal interface 710cd via shared command / address signals CAcd[], shared read clock signal RCKcd, and shared write clock signal WCKcd.

[0078] It should be understood from Figures 4-7 that other combinations of independent (i.e., not shared) per-channel signals and shared signals are contemplated. For example, rather than having both RCK and WCK signals shared between channels as illustrated in, for example, Figures 6-7, some embodiments may have just one of RCK and WCK shared and the other be independent per-channel signals.

[0079] Figure 8 is a flowchart illustrating a method of operating an eight-channel mode system. The steps illustrated in Figure 8 may be performed by one or more elements of DRAM device 101, system 201, system 300, system 400, system 500, system 600, and / or system 700, and / or their components. A memory device having eight memory access channel interfaces isDocket: 765-0253P - 11441US01 configured in an eight memory access channel mode (802). For example, memory 210 may be configured to be accessed via all eight memory access channel interfaces 210a-210h.

[0080] While in the mode, respective memory access commands, respective memory access addresses, and respective memory access data is communicated via the eight memory access channel interfaces (804). For example, as illustrated in Figure 2A, while in the eight memory access channel mode, memory device 210 may communicate, via channels A-H 210a-210h, commands, addresses, and data with respective channels A-H 220a-220h of controller 220.

[0081] Figure 9 is a flowchart illustrating a method of operating a four-channel mode system. The steps illustrated in Figure 9 may be performed by one or more elements of DRAM device 101, system 202, system 300, system 400, system 500, system 600, and / or system 700, and / or their components. A memory device having eight memory access channel interfaces is configured in a four memory access channel mode (902). For example, memory 210 and may be configured to be accessed via memory access channel A interface 210a, memory access channel C interface 210c, memory access channel E interface 210e, and memory access channel G interface 210g. Similarly, for example, memory device 211 and may be configured to be accessed via memory access channel A interface 211a, memory access channel C interface 211c, memory access channel E interface 21 le, and memory access channel G interface 211g.

[0082] While in the mode, respective memory access commands, respective memory access addresses, and respective memory access data is communicated via four of the eight memory access channel interfaces (904). For example, as illustrated in Figure 2B, while in the four memory access channel mode, memory device 210 may communicate, via channel A interface A 210a, channel C interface 210c, channel E interface 210e, and channel G interface 210g, commands, addresses, and data with respective channel A interface 220a, channel C interface 220c, channel E interface 220e, and channel G interface 220g of controller 220. Similarly, for example, memory device 211 may communicate, via channel A interface 21 la, channel C interface 211c, channel E interface 21 le, and channel G interface 211g, commands, addresses, and data with respective channel B interface 220b, channel D interface 220d, channel F interface 220f, and channel H interface 220h of controller 220.

[0083] Figure 10 is a flowchart illustrating a method of operating a two-channel mode system. The steps illustrated in Figure 10 may be performed by one or more elements of DRAM device 101, system 204, system 300, system 400, system 500, system 600, and / or system 700,Docket: 765-0253P - 11441US01 and / or their components. A memory device having eight memory access channel interfaces is configured in a two memory access channel mode (1002). For example, memory 210 and may be configured to be accessed via memory access channel A interface 210a and memory access channel E interface 210e. Similarly, for example, memory device 211 and may be configured to be accessed via memory access channel A interface 211a and memory access channel E interface 21 le.

[0084] While in the mode, respective memory access commands, respective memory access addresses, and respective memory access data is communicated via two of the eight memory access channel interfaces (1004). For example, as illustrated in Figure 2D, while in the two memory access channel mode, memory device 210 may communicate, via channel A interface A 210a and channel E interface 210e, commands, addresses, and data with respective channel A interface 220a and channel E interface 220e of controller 220. Similarly, for example, memory device 211 may communicate, via channel A interface 211a and channel E interface 21 le, commands, addresses, and data with respective channel B interface 220b and channel F interface 220f of controller 220.

[0085] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of DRAM device 101, system 201, system 202, system 203, system 204, system 205, system 300, system 400, system 500, system 600, and / or system 700, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry -level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0086] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, GIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note thatDocket: 765-0253P - 11441US01 physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0087] Figure 11 is a block diagram illustrating one embodiment of a processing system 1100 for including, processing, or generating, a representation of a circuit component 1120. Processing system 1100 includes one or more processors 1102, a memory 1104, and one or more communications devices 1106. Processors 1102, memory 1104, and communications devices 1106 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1108.

[0088] Processors 1102 execute instructions of one or more processes 1112 stored in a memory 1104 to process and / or generate circuit component 1120 responsive to user inputs 1114 and parameters 1116. Processes 1112 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1120 includes data that describes all or portions of DRAM device 101, system 201, system 202, system 203, system 204, system 205, system 300, system 400, system 500, system 600, and / or system 700, and their components, as shown in the Figures.

[0089] Representation 1120 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry -level descriptions. Moreover, representation 1120 may be stored on storage media or communicated by carrier waves.

[0090] Data formats in which representation 1120 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

[0091] User inputs 1114 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1116 may include specifications and / or characteristics that are input to help define representation 1120. For example, parameters 1116 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics,Docket: 765-0253P - 11441US01 etc ), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0092] Memory 1104 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1112, user inputs 1114, parameters 1116, and circuit component 1120.

[0093] Communications devices 1106 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1100 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1106 may transmit circuit component 1120 to another system. Communications devices 1106 may receive processes 1112, user inputs 1114, parameters 1116, and / or circuit component 1120 and cause processes 1112, user inputs 1114, parameters 1116, and / or circuit component 1120 to be stored in memory 1104.

[0094] Implementations discussed herein include, but are not limited to, the following examples:

[0095] Example 1: A dynamic random access memory (DRAM), comprising: at least eight groups of memory cores; at least eight memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, to receive memory access addresses, to receive data to be stored in a corresponding one of the groups of memory cores, and to transmit data retrieved from the corresponding one of the groups of memory cores; a first one- half of the at least eight memory access channel interfaces to, in a second mode, each respectively receive memory access commands, receive memory access addresses, receive data to be stored in a corresponding two of the groups of memory cores, and transmit data retrieved from the corresponding two of the groups of memory cores, a second one-half of the at least eight memory access channel interfaces to, in the second mode, be disabled; and one-quarter of the at least eight memory access channel interfaces to, in a third mode, each respectively receive memory access commands, receive memory access addresses, receive data to be stored in a corresponding four of the groups of memory cores, and transmit data retrieved from the corresponding four of the groups of memory cores, a remaining three-quarters of the at least eight memory access channel interfaces that are not in the one-quarter to, in the third mode, be disabled.Docket: 765-0253P - 11441US01

[0096] Example 2: The DRAM of example 1, wherein one-eighth of the at least eight memory access channel interfaces to, in a fourth mode, each respectively receive memory access commands, receive memory access addresses, receive data to be stored in a corresponding eight of the groups of memory cores, and transmit data retrieved from the corresponding eight of the groups of memory cores, a remaining seven-eighths of the at least eight memory access channel interfaces that are not in the one-eighth to, in the fourth mode, be disabled.

[0097] Example 3: The DRAM of example 1, wherein a plurality of subgroups of the at least eight memory access channel interfaces are to each be synchronized by respective read clock signals shared among channel interfaces of each respective subgroup.

[0098] Example 4: The DRAM of example 1, wherein a plurality of subgroups of the at least eight memory access channel interfaces are to each be synchronized by respective write clock signals shared among channel interfaces of each respective subgroup.

[0099] Example 5: The DRAM of example 1, wherein a plurality of subgroups of the at least eight memory access channel interfaces are to each receive commands and addresses via command / address signals shared among channel interfaces of each respective subgroup.

[0100] Example 6: The DRAM of example 1, wherein at least one of the at least eight memory access channel interfaces are synchronized by a bidirectional timing reference signal.

[0101] Example 7: The DRAM of example 1, wherein the at least eight memory access channel interfaces comprise signals that are to use a pulse amplitude modulation scheme that has more than two levels.

[0102] Example 8: A DRAM device, comprising: eight groups of electrical connection points corresponding to, in a first mode, eight memory channel interfaces, the eight memory channel interfaces to, in the first mode, operate independently of each other to each access one of eight respective sets of memory cores, where the eight respective sets of memory cores are nonoverlapping sets; a first four of the eight groups of electrical connection points corresponding to, in a second mode, four memory channel interfaces, the four of the eight memory channel interfaces to, in the second mode, operate independently of each other to each access one of four respective sets of memory cores, where the four respective sets of memory cores are nonoverlapping sets, a union of the four respective sets of memory cores and a union of the eight respective sets of memory cores to result in an equivalent set of memory cores; and a first two of the eight groups of electrical connection points corresponding to, in a third mode, two memoryDocket: 765-0253P - 11441US01 channel interfaces, the two of the eight memory channel interfaces to, in the third mode, operate independently of each other to each access one of two respective sets of memory cores, where the two respective sets of memory cores are non-overlapping sets, a union of the two respective sets of memory cores and a union of the eight respective sets of memory cores to result in an equivalent set of memory cores.

[0103] Example 9: The DRAM device of example 8, wherein a first one of the eight groups of groups of electrical connection points corresponding to, in a fourth mode, one memory channel interface, the one of the eight memory channel interfaces to, in the fourth mode, operate to access the eight respective sets of memory cores.

[0104] Example 10: The DRAM device of example 8, wherein a plurality of subgroups of the eight memory channel interfaces are to each be synchronized by respective read clock signals shared among channel interfaces of each respective subgroup.

[0105] Example 11 : The DRAM device of example 8, wherein a plurality of subgroups of the eight memory channel interfaces are to each be synchronized by respective write clock signals shared among channel interfaces of each respective subgroup.

[0106] Example 12: The DRAM device of example 8, wherein a plurality of subgroups of the eight memory channel interfaces are to each receive commands and addresses via command / address electrical connection points shared among channel interfaces of each respective subgroup.

[0107] Example 13: The DRAM device of example 8, wherein the eight memory channel interfaces are synchronized by a bidirectional timing reference signal.

[0108] Example 15: The DRAM device of example 8, wherein the eight memory channel interfaces comprise signals that are to use a pulse amplitude modulation scheme that has more than two levels.

[0109] Example 15: A DRAM device, comprising: a package having signal connection points grouped into a first group, a second group, a third group, a fourth group, a fifth group, a sixth group, a seventh group, and an eighth group, each of the first group, the second group, the third group, the fourth group, the fifth group, the sixth group, the seventh group, and the eighth group to serve as connection points for a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth memory channel, respectively; and at least one DRAM integrated circuit disposed attached to the package, the at least one DRAM integrated circuit to, in a first mode,Docket: 765-0253P - 11441US01 operate each of the first, second, third, fourth, fifth, sixth, seventh, and eighth memory channels independent of the other of the first, second, third, fourth, fifth, sixth, seventh, and eighth memory channels, the at least one DRAM integrated circuit to, in a second mode, operate the first, second, third, and fourth memory channels and disable the fifth, sixth, seventh, and eighth memory channels, the at least one DRAM integrated circuit to, in a third mode, operate the first and second memory channels, and disable the third, fourth, fifth, sixth, seventh, and eighth memory channels.

[0110] Example 16: The DRAM device of example 15, wherein the at least one DRAM integrated circuit is to, in a fourth mode, operate the first memory channel, and disable the second, third, fourth, fifth, sixth, seventh, and eighth memory channels.

[0111] Example 17: The DRAM device of example 15, wherein the first memory channel is to be synchronized by a read clock signal and a write clock signal that are shared with at least one of the second, third, fourth, fifth, sixth, seventh, and eighth memory channels.

[0112] Example 18: The DRAM device of example 15, wherein the first memory channel is to receive commands and addresses via command / address signals that are shared with at least one of the second, third, fourth, fifth, sixth, seventh, and eighth memory channels.

[0113] Example 19: The DRAM device of example 15, wherein the first memory channel is to be synchronized by a bidirectional timing reference signal.

[0114] Example 20: The DRAM device of example 15, wherein the first, second, third, fourth, fifth, sixth, seventh, and eighth memory channels comprise signals that are to use a pulse amplitude modulation scheme that has more than two levels.

[0115] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

Docket: 765-0253P - 11441US01CLAIMSWhat is claimed is:

1. A dynamic random access memory (DRAM), comprising: at least eight groups of memory cores; at least eight memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, to receive memory access addresses, to receive data to be stored in a corresponding one of the groups of memory cores, and to transmit data retrieved from the corresponding one of the groups of memory cores; a first one-half of the at least eight memory access channel interfaces to, in a second mode, each respectively receive memory access commands, receive memory access addresses, receive data to be stored in a corresponding two of the groups of memory cores, and transmit data retrieved from the corresponding two of the groups of memory cores, a second one-half of the at least eight memory access channel interfaces to, in the second mode, be disabled; and one-quarter of the at least eight memory access channel interfaces to, in a third mode, each respectively receive memory access commands, receive memory access addresses, receive data to be stored in a corresponding four of the groups of memory cores, and transmit data retrieved from the corresponding four of the groups of memory cores, a remaining three-quarters of the at least eight memory access channel interfaces that are not in the one-quarter to, in the third mode, be disabled.

2. The DRAM of claim 1, wherein one-eighth of the at least eight memory access channel interfaces to, in a fourth mode, each respectively receive memory access commands, receive memory access addresses, receive data to be stored in a corresponding eight of the groups of memory cores, and transmit data retrieved from the corresponding eight of the groups of memory cores, a remaining seven-eighths of the at least eight memory access channel interfaces that are not in the one-eighth to, in the fourth mode, be disabled.Docket: 765-0253P - 11441US013. The DRAM of claim 1, wherein a plurality of subgroups of the at least eight memory access channel interfaces are to each be synchronized by respective read clock signals shared among channel interfaces of each respective subgroup.

4. The DRAM of claim 1, wherein a plurality of subgroups of the at least eight memory access channel interfaces are to each be synchronized by respective write clock signals shared among channel interfaces of each respective subgroup.

5. The DRAM of claim 1, wherein a plurality of subgroups of the at least eight memory access channel interfaces are to each receive commands and addresses via command / address signals shared among channel interfaces of each respective subgroup.

6. The DRAM of claim 1, wherein at least one of the at least eight memory access channel interfaces are synchronized by a bidirectional timing reference signal.

7. The DRAM of claim 1, wherein the at least eight memory access channel interfaces comprise signals that are to use a pulse amplitude modulation scheme that has more than two levels.

8. A DRAM device, comprising: eight groups of electrical connection points corresponding to, in a first mode, eight memory channel interfaces, the eight memory channel interfaces to, in the first mode, operate independently of each other to each access one of eight respective sets of memory cores, where the eight respective sets of memory cores are nonoverlapping sets; a first four of the eight groups of electrical connection points corresponding to, in a second mode, four memory channel interfaces, the four of the eight memory channel interfaces to, in the second mode, operate independently of each other to each access one of four respective sets of memory cores, where the four respective sets of memory cores are non-overlapping sets, a union of the four respective sets of memory cores and a union of the eight respective sets of memory cores to result in an equivalent set of memory cores; andDocket: 765-0253P - 11441US01 a first two of the eight groups of electrical connection points corresponding to, in a third mode, two memory channel interfaces, the two of the eight memory channel interfaces to, in the third mode, operate independently of each other to each access one of two respective sets of memory cores, where the two respective sets of memory cores are non-overlapping sets, a union of the two respective sets of memory cores and a union of the eight respective sets of memory cores to result in an equivalent set of memory cores.

9. The DRAM device of claim 8, wherein a first one of the eight groups of groups of electrical connection points corresponding to, in a fourth mode, one memory channel interface, the one of the eight memory channel interfaces to, in the fourth mode, operate to access the eight respective sets of memory cores.

10. The DRAM device of claim 8, wherein a plurality of subgroups of the eight memory channel interfaces are to each be synchronized by respective read clock signals shared among channel interfaces of each respective subgroup.

11. The DRAM device of claim 8, wherein a plurality of subgroups of the eight memory channel interfaces are to each be synchronized by respective write clock signals shared among channel interfaces of each respective subgroup.

12. The DRAM device of claim 8, wherein a plurality of subgroups of the eight memory channel interfaces are to each receive commands and addresses via command / address electrical connection points shared among channel interfaces of each respective subgroup.

13. The DRAM device of claim 8, wherein the eight memory channel interfaces are synchronized by a bidirectional timing reference signal.

14. The DRAM device of claim 8, wherein the eight memory channel interfaces comprise signals that are to use a pulse amplitude modulation scheme that has more than two levels.Docket: 765-0253P - 11441US0115. A DRAM device, comprising: a package having signal connection points grouped into a first group, a second group, a third group, a fourth group, a fifth group, a sixth group, a seventh group, and an eighth group, each of the first group, the second group, the third group, the fourth group, the fifth group, the sixth group, the seventh group, and the eighth group to serve as connection points for a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth memory channel, respectively; and at least one DRAM integrated circuit disposed attached to the package, the at least one DRAM integrated circuit to, in a first mode, operate each of the first, second, third, fourth, fifth, sixth, seventh, and eighth memory channels independent of the other of the first, second, third, fourth, fifth, sixth, seventh, and eighth memory channels, the at least one DRAM integrated circuit to, in a second mode, operate the first, second, third, and fourth memory channels and disable the fifth, sixth, seventh, and eighth memory channels, the at least one DRAM integrated circuit to, in a third mode, operate the first and second memory channels, and disable the third, fourth, fifth, sixth, seventh, and eighth memory channels.

16. The DRAM device of claim 15, wherein the at least one DRAM integrated circuit is to, in a fourth mode, operate the first memory channel, and disable the second, third, fourth, fifth, sixth, seventh, and eighth memory channels.

17. The DRAM device of claim 15, wherein the first memory channel is to be synchronized by a read clock signal and a write clock signal that are shared with at least one of the second, third, fourth, fifth, sixth, seventh, and eighth memory channels.

18. The DRAM device of claim 15, wherein the first memory channel is to receive commands and addresses via command / address signals that are shared with at least one of the second, third, fourth, fifth, sixth, seventh, and eighth memory channels.

19. The DRAM device of claim 15, wherein the first memory channel is to be synchronized by a bidirectional timing reference signal.Docket: 765-0253P - 11441US0120. The DRAM device of claim 15, wherein the first, second, third, fourth, fifth, sixth, seventh, and eighth memory channels comprise signals that are to use a pulse amplitude modulation scheme that has more than two levels.

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