Memory flow control register

Abstract

The described apparatus and methods relate to memory flow control registers for memory systems that can support non-deterministic protocols. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store a value indicating a total number of memory requests that can be serviced by the memory device simultaneously. The logic can be configured by a device manufacturer during assembly. The manufacturer can determine limits or capabilities of the system based on components and structure, and disclose the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the value and limit the number of memory requests sent to the device based on the value. Thus, the memory flow control register can improve latency and bandwidth when accessing a memory device via an interconnect.

Description

Technical Field

[0001] This application relates to electronic devices, and more specifically, to memory flow control registers. Background Technology

[0002] Computers, smartphones, and other electronic devices rely on processors and memory. The processor executes code based on data to run applications and provide features to the user. The processor obtains code and data from memory. Memory in electronic devices can include volatile memory (e.g., random access memory (RAM)) and non-volatile memory (e.g., flash memory). Similar to the number of cores or processor speed, the rate at which data can be accessed and the access latency can also affect the performance of an electronic device.

[0003] Furthermore, the demand for memory in electronic devices continues to evolve and grow. For example, as manufacturers design and manufacture processors to execute code faster, processors benefit from faster access to data in memory. Applications on electronic devices may also operate on even larger datasets that require even more memory. Summary of the Invention

[0004] One aspect of this disclosure provides a method comprising: issuing a request via a controller to read one or more values ​​stored in at least one register of a memory device, the one or more values ​​indicating a number of memory requests that can be served by the memory device; and receiving a response via the controller from the memory device, the response comprising the one or more values.

[0005] Another aspect of this disclosure provides a method comprising: receiving at a memory device a request to read one or more values ​​from at least one register of the memory device, the one or more values ​​indicating a number of memory requests that can be served by the memory device; and transmitting through the memory device a response containing the one or more values.

[0006] Another aspect of this disclosure provides an apparatus comprising: an interface configured to be coupled to a memory device via an interconnect; and a controller coupled to the interface, the controller being configured to: issue a request via the interconnect for reading one or more values ​​stored in at least one register of the memory device, the one or more values ​​indicating a number of memory requests that can be served by the memory device; and receive a response via the interconnect from the memory device, the response including the one or more values.

[0007] Another aspect of this disclosure provides an apparatus comprising: an interface configured to be coupled to a host device via an interconnect; and at least one register configured to be readable by the host device via the interconnect; and storing one or more values ​​indicating a number of memory requests that can be served by a memory device associated with the apparatus. Attached Figure Description

[0008] This document describes, with reference to the following diagrams, devices and techniques for operating or interoperating with memory flow control registers. The same labels are used in all diagrams to refer to the same features and components:

[0009] Figure 1 Illustrate an example device that can implement aspects of memory flow control registers;

[0010] Figure 2 Illustrate an example computing system that can implement memory flow control registers through memory devices;

[0011] Figure 3 Examples of systems that can implement aspects of memory flow control registers are illustrated, the systems may include host devices and memory devices coupled together via interconnects;

[0012] Figure 4 Examples of controllers for initiators and targets that can implement aspects of memory flow control registers are illustrated, and the controllers can communicate across interconnects employing an integral-based protocol;

[0013] Figure 5 This section illustrates an example of another computing system in which aspects of memory flow control registers can be implemented via memory devices;

[0014] Figure 6 A flowchart illustrating an example procedure for implementing aspects of memory flow control registers; and

[0015] Figure 7 A flowchart illustrating another example of the process of implementing an aspect of the memory flow control register. Detailed Implementation

[0016] Overview

[0017] Processors and memory work together to deliver features in computers and other electronic devices, including smartphones. As processors and memory work together more quickly, electronic devices often offer enhanced features such as high-resolution graphics and artificial intelligence. The amount of memory required by some applications, such as those for artificial intelligence and virtual-real graphics, is constantly increasing. Advances in processors often outpace advancements in the connectivity between processors and memory. Furthermore, as the development of data- and bandwidth-intensive applications continues, manufacturers are seeking improved links and mechanisms to reduce the bandwidth and latency associated with accessing memory located on connected devices.

[0018] The processor and memory can be mounted on a printed circuit board (PCB), such as a motherboard. A PCB may contain sockets for accepting at least one processor and one or more memory modules, as well as various wiring infrastructures to enable communication between the two or more components. However, the area provided by the PCB for sockets and wiring infrastructure is limited. Some PCBs contain sockets shaped into linear slots and designed to accept multiple dual in-line memory modules (DIMMs). These sockets can be fully occupied by the DIMMs, while the processor can still utilize more memory. In such cases, if more memory is available, the system can have improved performance.

[0019] The printed circuit board may also include at least one peripheral component interconnect (PCI) high-speed (PCI) (PCIe) slots. PCIe is designed to provide a common interface for various types of components that can be coupled to a PCB. Compared to some earlier standards, PCIe offers higher data transfer rates or a smaller footprint on a PCB, combining both speed and size. PCIe links enable the interconnection of processors and peripheral memory devices at significantly increased speeds compared to earlier standards. Therefore, some PCBs allow the processor to access memory devices connected to the PCB via PCIe slots.

[0020] However, PCIe links have limitations in environments with large shared memory pools and devices requiring high bandwidth and low latency. For example, PCIe links do not specify mechanisms to support consistency and are often ineffective at managing isolated memory pools. Additionally, the latency of PCIe links can be too high to effectively manage shared memory access across multiple devices within a system. Therefore, using only the PCIe protocol to access memory may not provide as much functionality, flexibility, or reliability as needed.

[0021] In such cases, another protocol can be layered on top of the PCIe protocol. Another example of a higher-level protocol is the Compute High-Speed ​​Link (CXL) protocol. The CXL protocol can be implemented on top of the physical layer governed by the PCIe protocol. The CXL protocol targets processor- and memory-intensive workloads (e.g., accelerators, memory expanders) where consistent, efficient memory access or interaction between the processor and memory is required. The CXL protocol addresses some of the limitations of the PCIe link by providing an interface that leverages the PCIe 5.0 physical layer and electrical components, while providing a low-latency path for memory access and consistent caching between the processor and memory devices. This provides high-bandwidth, low-latency connectivity between host devices (e.g., processors, CPUs, SoCs) and memory devices (e.g., accelerators, memory expanders, memory buffers, intelligent input / output (I / O) devices). The CXL protocol also addresses the growing high-performance computing workloads by supporting heterogeneous processing and memory systems with potential applications in artificial intelligence, machine learning, communication systems, and other high-performance computing.

[0022] Various electronic devices (e.g., mobile phones with a System-on-a-Chip (SoC) or cloud computing servers with dozens of processing units) may employ memory coupled to a processor via CXL-based interconnects (referred to herein as “CXL links”). For clarity, consider a device having a host device coupled to another device (e.g., a memory extender, or another device comprising Type 1, Type 2, and Type 3 CXL devices) via CXL links. The host device may include a processor and a controller (e.g., a host-side controller) coupled to the interconnects. The other device (sometimes referred to herein as a memory device) may include another controller (e.g., a memory-side controller) coupled to the interconnects and one or more memory arrays to store information in SRAM, DRAM, flash memory, etc.

[0023] During operation, the host-side controller sends a memory request to the memory-side controller via the interconnect. The memory request may be or may include a read request or a write request. The memory-side controller receives the request and satisfies the memory request directly or indirectly using the memory array via a memory response. Therefore, the memory-side controller sends a memory response to the host-side controller via the interconnect. To satisfy a read request, the memory-side controller may return the requested data as a memory response, such as a slave-master data response message (e.g., a data response message, such as S2MDRSMemData). If the requested data is unavailable, the memory-side controller may return a No Data Response (NDR) message (e.g., S2M NDR Cmp). To satisfy a write request, the memory-side controller may acknowledge the write operation as a memory response (e.g., an S2M NDR Cmp message).

[0024] To increase bandwidth and reduce latency, the memory-side controller may include at least one request queue capable of accumulating multiple memory requests received from the host-side controller. In other words, the host-side controller can send a "next" memory request before receiving a memory response corresponding to a "previous" memory request. This ensures that the memory device is not idle while waiting for another memory request that the host-side controller has already prepared. This technique also allows for better utilization of the interconnect by transmitting the next memory request before a memory response for the previous memory request is ready. However, the request queue at the memory-side controller may have space for a limited number of entries. If the host-side controller overflows the request queue at the memory-side controller, memory access can slow down, and the overflow can even cause data corruption. In other words, without a mechanism to control the flow of memory access requests, bandwidth or latency can degrade, and errors may occur.

[0025] One method for modulating (e.g., regulating) a memory request flow involves using points. A specific number of points can be granted to the host-side controller, with the maximum number of points based on the size of the memory-side controller's request queue. If the host-side controller currently has at least one point, it can send a memory request to the host-side controller via an interconnect. If the host-side controller has exhausted its allocated points, it waits until at least one point has been replenished before issuing another memory request.

[0026] The memory-side controller can be responsible for replenishing integrations. The memory-side controller can use communication across the interconnect to indicate to the host-side controller that one or more integrations have been replenished or returned. For example, a memory response containing read data or write acknowledgements may also include an integration return indication. In some cases, the memory-side controller returns integrations in response to removing a memory request from its request queue. This integration system approach prevents request queue overflow at the memory-side controller and prevents error conditions from occurring.

[0027] However, due to the oversupply of total memory requests present in or at the memory device, this method may not prevent bandwidth reduction or latency increase. In addition to the memory-side controller and memory array, the memory device may also include other components that facilitate memory request processing. For example, the memory device may include at least one "internal" interconnect and one or more memory controllers coupled to the memory array to control access to the memory array (e.g., via interface coupling). Any of these components may include at least one corresponding memory request queue. For example, each of two memory controllers may include a corresponding request queue in two request queues.

[0028] In response to a memory-side controller removing a memory request from its request queue, the memory-side controller forwards the memory request to a "downstream" or "back-end" component, such as one of the memory controllers. The receiving memory controller may accumulate memory requests in its corresponding request queue. This accumulation may occur, for example, due to a slower memory array being unable to process requests at the rate it receives requests from the memory-side controller. Therefore, even if unserved memory requests are "piling up" at the memory device, the memory-side controller can still return the accumulated requests to the host-side controller.

[0029] Allowing the request queue of the memory controller or other back-end components to become saturated can reduce the data bandwidth throughput of the memory system. This saturation can also increase the latency between when the memory device accepts a memory request from the host device and when the memory device provides a corresponding memory response. Therefore, returning an integral to the host controller whenever a memory request is removed from the request queue at the memory-side controller can adversely affect memory system performance.

[0030] Furthermore, the memory device may include one or more memory response queues. Memory response queues may exist at either the memory-side controller or a back-end component of the memory device (such as the memory controller). Oversaturating the response queues can also reduce bandwidth and increase latency. The response queues can become "backup" if, for example, internal or external interconnects are too busy or oversubscribed. For instance, the interconnect between the host device and the memory device may be oversubscribed by the memory device or other devices coupled to the interconnect (e.g., another PCIe device). In such cases, this type of integration return system can cause at least one response queue of the memory device to become full, which can further slow down the memory device to the point of adversely affecting bandwidth and latency.

[0031] Reduced processing bandwidth and increased latency of memory devices can be classified as poor performance. Slow memory performance can cause system-level problems and lead to user dissatisfaction. In particular, if poor performance conflicts with advertised performance capabilities or published technical specifications (such as Quality of Service (QoS) indications), users can blame the memory device manufacturer. Even if attributed to a communication scheme based on insufficient integration, the host device may still cause bandwidth and latency problems by sending too many memory requests to the memory device, leading to the aforementioned accusations.

[0032] To address, and at least partially mitigate, this document describes an example method for managing memory request flows in devices and systems, which uses an integral-based scheme to control the memory request flows. One method may involve adding a simple circuitry to the device, such as one or more hardware registers that can store one or more values, which a host can read to limit the maximum number of pending requests in the system at any given time. For example, the number of pending memory requests may include the number of memory requests present on or currently being processed by the memory device and / or pending within the memory device. In some cases, the registers may be configured by the manufacturer during device assembly or testing. The manufacturer determines appropriate limits or security capabilities of the system based on the components and circuitry, and may expose overall capabilities (e.g., QoS) based on the determined limits. When the memory device is connected to a host, the host can read at least one value from at least one register and limit the number of memory requests sent to the device based on said at least one value.

[0033] Consider an instance system containing one or more registers, where the total number of memory requests that can be serviced by the memory device (e.g., the number of memory requests that may not be completed in or at the device, or the number of memory requests authorized to be serviced by the memory device) can be transmitted to the host side via the instance system. The total number of memory requests that can be serviced by the memory device may be the number of memory requests that the memory device can service within a certain time frame to provide a specific Quality of Service (QoS) or to meet another specified technology or performance parameter. For example, hardware registers located in or mapped to the PCI configuration space of the memory device (e.g., a CXL device) may be configured by the device manufacturer during manufacturing, testing, assembly, or initialization. The registers may store one or more values ​​indicating the total number of combined memory requests (e.g., write requests and read requests) that may not be completed in the memory device. This number may be determined based on various factors, such as the round-trip time (e.g., device pin latency) from unpacking the request and forwarding it from the memory-side controller until a memory response to the request is received at the memory-side controller. Other factors may include the time it takes for memory requests to flow through the various interconnects, controllers, and queues within the memory device as described above (e.g., this can affect the device's propagation latency) and / or may include (e.g., the back-end memory configuration of one or more DRAM components of a memory expander).

[0034] The host device can read registers during initialization or startup when a new device is connected to the system (e.g., hot-plugged installation) or when it boots up via a connected device (e.g., upon power-on or immediately after exiting sleep or hibernation mode). In some embodiments, the hardware registers may include three or more different registers that transmit three different values. One register may be a total request register (e.g., CXL_Device_Max_Total_Request_Outstanding_Limit_REG) indicating the total number of possible incomplete read and write requests in the memory device. Two other registers may individually indicate the number of possible incomplete read and write requests in the memory device (e.g., CXL_Device_Max_Read_Request_Outstanding_Limit_REG and CXL_Device_Max_Write_Request_Outstanding_Limit_REG). The host device can then control the number of incomplete memory requests at any given time based on the values ​​read from the registers. Depending on the register configuration, the host can limit the total number of requests (e.g., both read and write requests), the total number of requests and one or both of the read / write requests, the number of read requests only, or the number of write requests only, to maintain the system's performance at advertised or otherwise specified performance.

[0035] By employing one or more of these implementations, the memory device gains greater control over the flow of memory requests received from the host device. Controlling the memory request flow in this way allows the device to operate more efficiently within the advertised performance specifications (e.g., a given QoS). Furthermore, these implementations allow device manufacturers to combine components and subsystems from different vendors and configure the device to operate within defined specifications and at defined QoS. This provides manufacturers with more options when building devices, allowing them to offer a wider range of products with different performance levels and price points. Customers, in turn, can select devices and systems that meet their technical needs and budget constraints and are confident that the chosen hardware will deliver the advertised capabilities.

[0036] While some embodiments have been described above with respect to memory-side controllers implementing certain techniques in memory devices, host-side controllers in host devices may alternatively implement the same or similar techniques. Examples of host-side embodiments are further described herein.

[0037] Instance operating environment

[0038] Figure 1 Example device 102 is generally described at 100 locations as an aspect in which a memory flow control register can be implemented. Device 102 can be implemented as, for example, at least one electronic device. Example electronic device implementations include Internet of Things (IoT) device 102-1, tablet device 102-2, smartphone 102-3, laptop computer 102-4 (or desktop computer), passenger vehicle 102-5 (or other vehicle), server computer 102-6, server cluster 102-7 which may be part of cloud computing infrastructure or data center, and a portion thereof (e.g., printed circuit board (PCB) or module assembly).

[0039] Other examples of device 102 include wearable devices such as smartwatches or smart glasses; entertainment devices such as set-top boxes or streaming dongles, smart TVs, gaming devices, or virtual reality (VR) goggles; server motherboards or sockets; home appliances; vehicles or drones, including their electronic components; industrial equipment; security or other sensor devices; and so on. Each type of electronic device or other device may include one or more components to provide some computing functionality or features enabled or enhanced by the hardware or technologies described herein.

[0040] In an example implementation, device 102 may include at least one host device 104, at least one interconnect 106, and at least one memory device 108. Host device 104 may include at least one processor 114, at least one cache memory 116, and at least one controller 118. Memory device 108 may include at least one controller 110 and at least one memory 112. Memory 112 may be implemented using one or more memory types.

[0041] Memory 112 may be implemented, for example, as a dynamic random access memory (DRAM) die or module, including DRAM devices implemented in a three-dimensional (3D) stacked manner (e.g., high-bandwidth memory (HBM) device or hybrid memory cube (HMC) device). DRAM may include, for example, synchronous DRAM (SDRAM) or double data rate (DDR) DRAM (DDR DRAM). Memory 112 may also be implemented using static random access memory (SRAM). Therefore, memory device 108 can be used as main memory or cache memory, including both cases. Alternatively, memory device 108 can be used as storage memory. In such cases, memory 112 may be implemented, for example, as a storage-class memory type (e.g., employing 3DXPoint). TM Alternatively, it could be phase-change memory (PCM), flash memory, magnetic hard disk, or solid-state drive (e.g., non-volatile memory). ( The storage-level memory type of the device is implemented.

[0042] Regarding host device 104, processor 114 may be coupled to cache memory 116, and cache memory 116 may be coupled to controller 118. Processor 114 may also be coupled directly or indirectly (e.g., via the depicted cache memory 116) to controller 118. Host device 104 may include other components to form, for example, a system-on-a-chip (SoC). Processor 114 may include or comprise a general-purpose processor, central processing unit (CPU), graphics processing unit (GPU), neural network engine or accelerator, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) integrated circuit (IC), communication processor (e.g., modem or baseband processor), SoC, etc.

[0043] In operation, controller 118 may provide a high-level interface or logical interface between processor 114 and at least one memory device (e.g., memory external to host device 104). Controller 118 may, for example, receive memory requests from processor 114 and provide the memory requests to external memory through appropriate formatting, packaging, timing, reordering, etc. Controller 118 may forward responses to memory requests received from external memory to processor 114.

[0044] Controller 118 may communicate with multiple memory devices (or other types of devices, some of which may include one or more memory components) via one or more interconnects (e.g., interconnect 106). Regarding connections external to host device 104, host device 104 may be coupled to memory device 108 via interconnect 106 (e.g., using an interface). Memory device 108 may be coupled to, or may contain, main memory or storage memory, and in some cases, both. Another device (e.g., cache memory or a switch) may be coupled between host device 104 and memory device 108 and may be part of or separate from interconnect 106.

[0045] The depicted interconnect 106, along with other interconnects (not shown) that communicatively couple various components together, enables data to be transferred between two or more components. Examples of interconnects include buses, switching structures, crossover switches, one or more wires carrying voltage or current signals, etc. Interconnect 106 may be implemented as a parallel propagation path. For example, interconnect 106 may include at least one command and address bus and at least one data bus, each of which synchronously carries multiple bits per clock cycle. Each bus may be implemented as a unidirectional or bidirectional bus. Alternatively, interconnect 106 may be implemented as a serial propagation path. For example, interconnect 106 may conform to PCIe standards (e.g., version 4, 5, 6, or future versions). Interconnect 106 may include multiple serial propagation paths, such as multiple lanes in a PCIe implementation.

[0046] Figure 1 The components of device 102 depicted represent an instance computing architecture that may include a hierarchical memory system. A hierarchical memory system may include different tiers of memory, each tier having different speeds, capacities, or volatile / non-volatile characteristics. Therefore, memory device 108 may be described with respect to at least a portion of the main memory of device 102. However, memory device 108 may form at least a portion of cache memory, storage memory, SoC, etc., of device 102.

[0047] Although Figure 1Various embodiments of device 102 are depicted and described herein, but device 102 may be implemented in alternative ways. For example, host device 104 may include multiple cache memories, include multi-level cache memories, or may omit cache memories. Memory (e.g., memory device 108) may have corresponding "internal" or "local" cache memories (not shown). In some cases, host device 104 may omit processor 114 and / or include other logic. Generally, the components described and illustrated may be implemented in alternative ways, including implementations in distributed memory systems or shared memory systems. Figure 1 Compared to the components depicted in and described herein, the given device 102 may also contain more, fewer, or different components.

[0048] The host device 104 and any of the individual memories can be implemented in various ways. In some cases, the host device 104 and the memory device 108 may reside on separate chipsets or racks within a server computing environment. In other cases, both the host device 104 and the memory device 108 may be mounted on the same printed circuit board (PCB) (e.g., a rigid or flexible motherboard or PCB assembly) or physically supported by said same PCB. The host device 104 and the memory device 108 may also be integrated onto the same IC or manufactured on separate ICs but packaged together.

[0049] The memory device 108 may also be coupled to a plurality of host devices 104 via one or more interconnects 106 and may be able to respond to memory requests from two or more of the plurality of host devices 104. Each host device 104 may include a respective controller 118, or the plurality of host devices 104 may share a common controller 118. References below Figure 2 An instance computing system architecture is described, having at least one host device 104 coupled to a memory device 108.

[0050] However, continue to refer to Figure 1 Interconnect 106 can propagate one or more communications. Host device 104 and memory device 108 can exchange at least one memory request / memory response 120. For example, controller 118 can transmit a memory request to controller 110 via interconnect 106. Therefore, controller 110 can transmit a corresponding memory response to controller 118 via interconnect 106. In some cases, interconnect 106 operates according to an integration-based protocol. Therefore, integration-related information 122 can be exchanged between host device 104 and memory device 108. For example, controller 110 can transmit an integration return to controller 118 so that controller 118 can transmit another memory request.

[0051] Therefore, host device 104 and memory device 108 can communicate using an integration-based protocol. The controller 110 of memory device 108 may include integration logic 124, and the controller 118 of host device 104 may include integration logic 126. In an example embodiment, integration logic 124 and / or integration logic 126 may facilitate communication via interconnect 106 using at least one protocol based on integration operation.

[0052] Points-based protocols may use tokens or another number-based authorization scheme to authorize the initiator and / or target to communicate separately with the target and / or initiator. For example, controller 118 may transmit a communication (e.g., a memory request) via interconnect 106 to controller 110 in response to having at least one point. This transmission "consumes" at least one point. The integration logic 124 of controller 110 can modulate the communication flow from controller 118 by modulating the frequency or rate at which the integration logic 124 returns points to the integration logic 126 of controller 118. Example techniques for modulating such point returns are described herein to increase memory request processing bandwidth or reduce memory response latency. References below... Figure 4 Describe an example of an integral-based protocol.

[0053] In some implementations, device 102 operates one or more protocols via interconnect 106. Device 102 can operate across interconnect 106, for example, to compute high-speed links. TM (CXL) protocol. In at least some of these cases, device 102 may overlay the CXL protocol on top of the PCIe protocol used for the physical layer. Therefore, controller 118 may conform to the CXL standard or the PCIe standard (including both). Similarly, controller 110 may conform to the CXL standard or the PCIe standard (including both). Reference below Figure 4 Describe instances of integral-based aspects of one or more versions of the CXL standard.

[0054] Memory device 108 may also include at least one register 128. Register 128 may be a hardware register, such as a read-only register or a read-write register. In some embodiments in which device 102 operates across interconnect 106 according to the CXL protocol and / or PCIe protocol, at least one register 128 may be mapped to a PCIe configuration space or a CXL device configuration space (e.g., as described with reference to, for example, CXL standard versions 1.0, 1.1, 2.0, or later). Register 128 may be separate from or integrated with controller 110 (as depicted). Host device 104 may read one or more values ​​stored in register 128 via interconnect 106 (e.g., controller 118, processor 114, or another component may read values ​​from register 128 via interconnect 106). Thus, host device 104 and memory device 108 may exchange register-related information 130. For example, host device 104 (e.g., controller 118) may issue a request to read a value stored in register 128 and receive a response from memory device containing (e.g., from interconnect 106 in register 128) the value.

[0055] At least one register 128 can be used to address some of the inefficiencies associated with the integration-based memory streaming protocol in CXL devices, as described above. For example, register 128 may store a value indicating the number of memory requests (e.g., read requests, write requests, or both) that can be serviced by memory device 108 (e.g., the number of memory requests that may not be completed in or at memory device 108 or the number of memory requests authorized to be serviced by memory device 108). The total number of memory requests that can be serviced by the memory device may be the number of memory requests that the memory device can service within a certain time period to provide a specific quality of service (QoS) or to meet another specified technology or performance parameter. For example, “incomplete” memory requests may include pending or existing memory requests (read and / or write) on memory device 108, memory requests that have been received at memory device 108 but not processed, memory requests that memory device 108 has received but has not yet responded to, ongoing memory requests in downstream or back-end components of memory device 108, combinations thereof, etc.

[0056] One or more values ​​may be based on factors other than the integral that is only available for the request. These factors may include, for example, the so-called “pin latency” of memory device 108 (e.g., the round-trip time for a memory request to be forwarded from controller 110 to memory 112 and for a returned response to be received at controller 110). Other factors include the capacity and available space in the memory queue or buffer within memory device 108, the propagation latency within memory device 108, and / or the configuration of memory 112. When host device 104 receives a response from register 128 (e.g., as part of an exchange of register-related information 130), the response containing a value stored in register 128, host device 104 (e.g., controller 118) may control the number of incomplete memory requests in the memory device based on that value. Reference Figure 5 Additional details regarding the operation of device 102 relative to register 128 are described below. Other circuit systems, techniques, and mechanisms are also described below. However, an example computing architecture with one or more processors and memory devices is described next.

[0057] Figure 2 An example computing system 200 is described, which can implement aspects of memory flow control registers in a memory device. In some embodiments, the computing system 200 includes at least one memory device 108, at least one interconnect 106, and at least one processor 202. The memory device 108 may include at least one memory array 206, at least one interface 204, and at least one controller 110, or be associated with these components. The at least one controller 110 may be communicatively coupled to the memory array 206 via at least one interconnect 208 (e.g., an "internal" interconnect). The memory array 206 and the controller 110 may be components integrated on a single semiconductor die or located on a separate semiconductor die (e.g., but still coupled to or disposed on the same PCB). Each of the memory array 206 or the controller 110 may also be distributed across multiple dies.

[0058] Memory device 108 may correspond to Figure 1 The device 102 may contain one or more of a cache memory, main memory, or storage memory. Therefore, the memory array 206 may comprise an array of memory cells. These memory cells may include, but are not limited to, memory cells of static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), three-dimensional (3D) stacked DRAM, double data rate (DDR) memory, low-power dynamic random access memory (DRAM), low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM), phase-change memory (PCM), or flash memory.

[0059] The controller 110 may include any one or more of a number of components that the memory device 108 may use to perform various operations. These operations may include communicating with other devices, managing performance, modulating memory access rates, and performing memory read or write operations. For example, the controller 110 may include at least one register 212, at least one example of request logic 214, at least one example of response logic 216, and at least one example of integration logic 124.

[0060] Register 212 may be implemented, for example, to store data for use by controller 110, for use by another portion of memory device 108, or for use by a portion of host device 104 (e.g., Figure 1 The controller 118 depicted herein uses one or more registers containing information. Register 212 may store, for example, the maximum integration level, parameters used to control the flow modulation process using integration, etc. In some embodiments, memory device 108 also includes register 128 as a separate component (e.g., Figure 1 and Figure 2 As shown in the diagram). In other embodiments (e.g., in... Figure 4 As shown in the diagram, register 128 may be part of another component (e.g., controller 110). In other cases ( Figure 2 (Not shown in the image) Register 212 may contain register 128, or perform the function of register 128, as shown in the reference. Figure 1 , Figure 3 and / or Figure 5 As described. (See reference) Figure 1 As described, the value stored in register 128 (or register 212) can be read by another device (e.g., host device 104 or processor 202). The value stored in register 128 may indicate, for example, the number of memory requests (e.g., read requests, write requests, and / or combinations of read and write requests) that may be serviced by memory device 108 (e.g., requests that may not be completed in or at memory device 108). Figure 2 As shown in the example computing system 200 depicted, the value stored in register 128 can be read via interface 204 and interconnect 106.

[0061] Request logic 214 may process one or more memory requests, for example, by formulating a request, directing the request to a next or final destination, or performing a memory access operation (e.g., a read or write operation). Response logic 216 may prepare at least one memory response, for example, by obtaining the requested data or generating a write response. Integration logic 124 may use integration modulation across the memory request stream of interconnect 106, as described below (including references). Figure 4 Further description.

[0062] Interface 204 can directly or indirectly couple controller 110 or memory array 206 to interconnect 106. For example... Figure 2 As shown, register 212, request logic 214, response logic 216, and integration logic 124 may be part of a single component (e.g., controller 110). In other embodiments, one or more of 212, request logic 214, response logic 216, or integration logic 124 may be implemented as separate components, which may be provided on a single semiconductor die or disposed across multiple semiconductor dies. These components of controller 110 may be individually or collectively coupled to interconnect 106 via interface 204.

[0063] Interconnect 106 can implement any one or more of a variety of interconnects that communicatively couple various components together and enable the transfer of commands, addresses, messages, packets and / or other information and data between two or more of the various components (e.g., between memory device 108 and any one or more processors 202). The information and data can be propagated directly via interconnect 106 or using some form of encapsulation (e.g., packets, frames, or microchips). Although interconnect 106 in Figure 2 The information is represented by a single line or arrow, but the interconnect 106 may include at least one bus, at least one switching structure, at least one cross switch, one or more wires or traces carrying voltage or current signals, at least one switch, one or more buffers, at least one branch, etc.

[0064] In some respects, memory device 108 may be relative to ( Figure 1 Either the host device 104 or the processor 202 may be implemented as a "separate" physical component. Examples of separate physical components include, but are not limited to, printed circuit boards (PCBs), which may be rigid or flexible; memory cards; memory modules; and memory modules, including single in-line memory modules (SIMMs), dual in-line memory modules (DIMMs), and non-volatile memory high-speed (NVMe) modules. Thus, separate physical components may be located together within the same housing of the electronic device or memory product or may be distributed above server racks, data centers, etc. Alternatively, the memory device 108 may be packaged or integrated with other physical components (including the host device 104 or the processor 202), for example, by being mounted on a common PCB or combined together in a single device package or by being integrated into the device's SoC.

[0065] like Figure 2As shown, one or more processors 202 may include one or more of a computer processor 202-1, a baseband processor 202-2, or an application processor 202-3, which are coupled to a memory device 108 via interconnect 106. Each processor 202 may be a CPU, GPU, SoC, ASIC, FPGA, etc., or may be a part of a CPU, GPU, SoC, ASIC, FPGA, etc. In some cases, a single processor may include multiple processing cores or resources, each dedicated to a different function, such as modem management, application, graphics, central processing, neural network acceleration, etc. In some embodiments, the baseband processor 202-2 may include or be coupled to a modem (…). Figure 2 (Not shown in the image) and may be referred to as a modem processor. The modem and / or baseband processor 202-2 can be connected via, for example, a cell, Wi-Fi... Ultra-wideband (UWB), near-field, or another technology or protocol used for wireless communication are wirelessly coupled to the network.

[0066] In various embodiments, processor 202 can be connected to different memories in different ways. For example, processor 202 can be directly connected to memory device 108 (e.g., via interconnect 106 as shown). Alternatively, one or more of processors 202 can be indirectly connected to memory device 108, for example, via a network connection, through one or more other devices or components, and / or using at least one other interconnect. Each processor 202 can be similar to Figure 1 This is implemented using processor 114. Therefore, the corresponding processor 202 may include or be associated with a corresponding controller, such as... Figure 1 The controller 118 is depicted in the diagram. Alternatively, two or more processors 202 may access the memory device 108 using a shared or system controller 118. In either of these cases, the controller 118 may include (e.g., Figure 1 The integral logic 126. Each processor 202 may also be individually connected to a corresponding memory. As shown, the computer processor 202-1 may be coupled to at least one DIMM 210 inserted into a DIMM slot on the motherboard. The DIMM 210 may be coupled to the memory controller (not shown) of the computer processor 202-1.

[0067] The devices and methods described herein are suitable for use with memory devices designed to work with a PCIe bus. Therefore, the described principles can be incorporated into memory devices with a PCIe interface. Additionally, the memory device can communicate via interconnect 106 by overlaying the CXL protocol onto the physical PCIe interface. Examples of memory standards involving CXL are issued by the Computing High Speed ​​Link Association and may include versions 1.0, 1.1, 2.0, and future versions. Therefore, host device 104 or memory device 108 (in some cases, both) may conform to at least one CXL standard. Therefore, for clarity, some terms in this document may be derived from one or more of these standards or their versions. However, the described principles are also applicable to memory devices conforming to other standards (including earlier or future versions of such standards) and to memory devices that do not follow common standards. References Figure 3 , Figure 4 and Figure 5 Describe an example of a system that may include PCIe interfaces and CXL protocol overlays.

[0068] Figure 3 An example of a system 300 that can implement aspects of a memory flow control register is illustrated. The system may include a host device 104 and a memory device 108 coupled together via interconnect 106. System 300 may be configured as follows: Figure 1 At least a portion of the device 102 shown. As illustrated, the host device 104 includes a processor 114 and a controller 118, which can be implemented by at least one initiator 302. Thus, the initiator 302 may be coupled to the processor 114 or to the interconnect 106 (including coupling to both), and the initiator 302 may be coupled between the processor 114 and the interconnect 106. Instances of the initiator 302 may include a leader, master, master controller, requester or requesting component, main component, etc.

[0069] In the illustrated example system 300, memory device 108 includes a controller 110, which can be implemented via at least one target 304. Target 304 can be coupled to interconnect 106. Therefore, target 304 and initiator 302 can be coupled to each other via interconnect 106. Instances of target 304 can include followers, secondary, slave devices, responders, or response components, etc. Memory device 108 also includes memory 112, which can be implemented via at least one memory module or chip or via another component (e.g., DRAM 310), as described below. In some embodiments, memory device 108 also includes memory as a separate component (e.g., Figure 1 and Figure 2 Register 128 (as shown in the diagram). In other embodiments (e.g.) Figure 4As shown in the diagram, register 128 may be part of another component (e.g., controller 110). In other cases ( Figure 2 or Figure 3 (Not shown), another register or component (e.g., register 212) may contain register 128 or register 520, or perform the function of register 128 or register 520. Host device 104 may read the value stored in register 128 (or register 212 or 520) via interconnect 106, as referenced. Figure 1-5 As described. In Figure 3 For clarity, the connection between register 128 and host device 104 is omitted.

[0070] In an example implementation, initiator 302 includes at least one link controller 312, and target 304 includes at least one link controller 314. Link controller 312 or link controller 314 may initiate, coordinate, cause, or otherwise participate in or control signaling across the physical or logical link implemented across interconnect 106 according to one or more protocols, including, for example, any one or two of the CXL protocol or PCIe protocol. Link controller 312 may be coupled to interconnect 106. Link controller 314 may also be coupled to interconnect 106. Therefore, link controller 312 may be coupled to link controller 314 via interconnect 106. Each link controller 312 or 314 may, for example, control communication via interconnect 106 at the link layer or at one or more other layers of a given protocol. Communication signaling may include, for example, requests 316, responses 318, etc.

[0071] The memory device 108 may additionally include at least one interconnect 306 and at least one memory controller 308 (MC308). Within the memory device 108, and relative to target 304, the interconnect 306, memory controller 308, and / or DRAM 310 (or other memory components) may be referred to as “back-end” components of the memory device 108. In some cases, the interconnect 306 is internal to the memory device 108 and may operate in the same or different manner as the interconnect 306.

[0072] As shown, the memory device may include multiple memory controllers 308-1 and 308-2 and / or multiple DRAMs 310-1 and 310-2. Although two of the components are shown, the memory device 108 may include one or more memory controllers and / or one or more DRAMs. For example, the memory device 108 may include four memory controllers and 16 DRAMs, such as four DRAMs per memory controller. The memory components of the memory device 108 are depicted as DRAMs only as examples; one or more of the memory components may be implemented as another type of memory. For example, the memory components may include non-volatile memory, such as flash or PCM. Alternatively, the memory components may include other types of volatile memory, such as SRAM. The memory device 108 may also include any combination of memory types.

[0073] In some cases, the memory device 108 may contain the target 304, interconnect 306, at least one memory controller 308, and at least one DRAM 310 within a single housing or other enclosure. However, the enclosure may be omitted or may be used with ( Figure 1 The housing of the host device 104, system 300, or device 102 is integrated. Interconnect 306 may be mounted on a PCB. Each of target 304, memory controller 308, and DRAM 310 may be manufactured on at least one IC and packaged together or individually. The packaged IC may be fixed to or otherwise supported by a PCB (or PCB assembly) and may be directly or indirectly coupled to interconnect 306. However, components of memory device 108 may be manufactured, packaged, assembled, and / or housed in other ways.

[0074] like Figure 3 As illustrated, target 304 (including its link controller 314) is coupled to interconnect 306. Each memory controller 308 of the plurality of memory controllers 308-1 and 308-2 is also coupled to interconnect 306. Therefore, target 304 and each memory controller 308 of the plurality of memory controllers 308-1 and 308-2 can communicate with each other via interconnect 306. Each memory controller 308 is coupled to at least one DRAM 310. As shown, each respective memory controller 308 of the plurality of memory controllers 308-1 and 308-2 is coupled to at least one respective DRAM 310 of the plurality of DRAMs 310-1 and 310-2. However, each memory controller 308 of the plurality of memory controllers 308-1 and 308-2 is coupled to a respective set of the plurality of DRAMs or other memory components.

[0075] Each memory controller 308 may access at least one DRAM 310 by implementing one or more memory access protocols to facilitate reading or writing data based on at least one memory address. For memory access based on memory type or memory component (e.g., organization of multiple DRAMs), the memory controller 308 may increase bandwidth or reduce latency. Multiple memory controllers 308-1 and 308-2 and multiple DRAMs 310-1 and 310-2 can be organized in a variety of different ways. For example, each memory controller 308 may implement one or more memory channels for accessing the DRAM. Additionally, the DRAM may be manufactured to contain one or more ranks, such as single-rank or double-rank memory modules. Each DRAM 310 (e.g., at least one DRAM IC chip) may also contain multiple libraries, such as 8 or 16 libraries.

[0076] This document now describes an example of a host device 104 accessing memory device 108. The example is described in terms of a general memory access (e.g., a memory request) that may include memory read access (e.g., a memory read request for a retrieval operation) or memory write access (e.g., a memory write request for a storage operation). Processor 114 may provide memory access request 352 to initiator 302. Memory access request 352 may be propagated via a bus or other interconnects within host device 104. This memory access request 352 may be or may include a read request or a write request. Initiator 302 (e.g., its link controller 312) may reformulate the memory access request into a format suitable for interconnect 106. This reformulation may be performed based on a physical protocol or logical protocol (including both) suitable for interconnect 106. Examples of such protocols are described below.

[0077] Initiator 302 can therefore prepare request 316 and transmit request 316 to target 304 via interconnect 106. Target 304 receives request 316 from initiator 302 via interconnect 106. Target 304 (including its link controller 314) can process request 316 to determine (e.g., extract, decode, or interpret) a memory access request. Based on the determined memory access request, target 304 can forward memory request 354 to memory controller 308 via interconnect 306, in this example, memory controller 308 is first memory controller 308-1. For other memory accesses, target data for second DRAM 310-2 can be accessed via second memory controller 308-2. Therefore, first memory controller 308-1 receives memory request 354 via internal interconnect 306.

[0078] The first memory controller 308-1 can prepare a memory command 356 based on a memory request 354. The first memory controller 308-1 can provide the memory command 356 to the first DRAM 310-1 via an interface or interconnect suitable for the DRAM type or other memory components. The first DRAM 310-1 receives the memory command 356 from the first memory controller 308-1 and can perform the corresponding memory operation. Based on the result of the memory operation, the first DRAM 310-1 can generate a memory response 362. If the memory request 316 is for a read operation, then the memory response 362 can contain the requested data (e.g., a data response message, such as S2M DRS MemData). If the requested data is unavailable, then the memory-side controller can return a no-data response message, such as S2M NDR Cmp. If the memory request 316 is for a write operation, then the memory response 362 can contain (e.g., a write complete message, such as S2M NDR Cmp) an acknowledgment that the write operation was successfully performed. The first DRAM 310-1 can provide the memory response 362 to the first memory controller 308-1.

[0079] To fulfill a read request, the memory-side controller returns the requested data as a memory response, such as a slave-master data response message (e.g., a data response message, such as S2M DRS MemData). If the requested data is unavailable, the memory-side controller may return a No Data Response (NDR) message (e.g., S2M NDR Cmp). To fulfill a write request, the memory-side controller may acknowledge the write operation as a memory response (e.g., an S2M NDR Cmp message).

[0080] The first memory controller 308-1 receives a memory response 362 from the first DRAM 310-1. Based on the memory response 362, the first memory controller 308-1 can prepare a memory response 364 and transmit the memory response 364 to the target 304 via interconnect 306. The target 304 receives the memory response 364 from the first memory controller 308-1 via interconnect 306. Based on this memory response 364, and in response to the corresponding request 316, the target 304 can formulate a response 318 for the requested memory operation. The response 318 may include a read data or write response and is formulated according to one or more protocols of interconnect 106.

[0081] In response to a memory request 316 from host device 104, target 304 may transmit a response 318 to initiator 302 via interconnect 106. Initiator 302 then receives response 318 from target 304 via interconnect 106. Initiator 302 can then respond to a “start” memory access request 352, in this example, originating from processor 114. To achieve this, initiator 302 prepares a memory access response 366 using information from response 318 and provides the memory access response 366 to processor 114. In these ways, host device 104 can obtain memory access services from memory device 108 using interconnect 106. Example aspects of interconnect 106 will now be described.

[0082] Interconnect 106 can be implemented in numerous ways to enable the exchange of memory-related communications between initiator 302 and target 304. Typically, interconnect 106 can carry memory-related information, such as data or memory addresses, between initiator 302 and target 304. In some cases, either initiator 302 or target 304 (including both) may prepare such information for transmission across interconnect 106 by encapsulating the memory-related information. The memory-related information may be encapsulated into, for example, at least one data packet (e.g., a microchip). One or more packets may contain at least one header with information indicating or describing the contents of each packet.

[0083] In example implementations, interconnect 106 can support, enforce, or implement memory coherence for shared memory systems, cache memories, combinations thereof, etc. Alternatively, interconnect 106 can operate based on an integral allocation system. Thus, initiator 302 and target 304 can communicate using, for example, an integral-based flow control mechanism 320. Having integrals allows an entity (e.g., initiator 302) to issue another memory request 316 to target 304. Target 304 can return integrals to "refill" the integral balance at initiator 302. Integrating logic 124 of target 304 or integrating logic 126 of initiator 302 (two examples of integral logic working together) can implement an integral-based communication scheme across interconnect 106. References below... Figure 4 Describe examples of integration-based communication protocols.

[0084] System 300, initiator 302, or target 304 may operate according to one or more physical or logical protocols or interface with interconnect 106. For example, they may be interconnected according to peripheral components. Interconnector 106 is built using the PCIe or PCI-E standard. Applicable versions of the PCIe standard may include 1.x, 2.x, 3.x, 4.0, 5.0, 6.0, and future or replacement versions. In some cases, at least one other standard layer overlays the physical-oriented PCIe standard. For example, initiator 302 or target 304 may calculate high-speed links... TM The (CXL) standard communicates via interconnect 106. Applicable versions of the CXL standard may include 1.x, 2.0, and future or alternative versions. Therefore, initiator 302 and / or target 304 can operate in a manner compliant with the PCIe standard and / or the CXL standard. The CXL standard can operate based on integrals (e.g., read integrals and write integrals). See below for further details. Figure 4 Describe instances of integral types, integral allocation, integral usage, and flow control via integrals.

[0085] Instance technology and hardware

[0086] Figure 4 An example of a controller for an initiator 302 and a target 304 that can communicate across an interconnect 106 employing an integration-based protocol is generally described at point 400. Initiator 302 may include link controller 312, and target 304 may include link controller 314. Also, Figure 1 and 3 As shown, link controller 312 may include integration logic 126, and link controller 314 may include integration logic 124. Integration logic 124 and integration logic 126 may support an implementation of an integration-based flow control mechanism 320 that allows one or more communications based on at least one integration owned.

[0087] In an example implementation, link controller 312 or link controller 314 (comprising both link controllers) may communicate across interconnect 106 using an integral-based protocol. The integral-based protocol may be implemented using, for example, an integral-based flow control mechanism 320. To achieve this, integral logic 126 may monitor the number of one or more integrals 412, and integral logic 124 may monitor one or more integrals 414. Typically, integral logic 126 permits link controller 312 to transmit communication (e.g., request 316) to link controller 314 based on one or more integrals 412. Transmitting request 316 may use or “consume” one of the one or more integrals 412. Based on one or more integrals 414, integral logic 124 at link controller 314 may modulate the rate of transmission from link controller 312 by controlling the transmission of integral return 420. Integral return 420 may replenish the indicated number of one or more integrals 412 at integral logic 126. This use of integrals is further described below.

[0088] like Figure 4 As described, link controller 312 may include at least one example of at least request queue 402, at least one arbitrator 404, at least one response queue 406, and integration logic 126. Link controller 314 may include at least one example of at least request queue 452, at least one arbitrator 454, at least one response queue 456, and integration logic 124. In some cases, request queue 402 or 452 may be split into read paths and write paths. Therefore, request queue 402 may include at least one read queue 408 and at least one write queue 410. Similarly, request queue 452 may include at least one read queue 458 and at least one write queue 460.

[0089] In an instance operation for initiator 302, link controller 312 may receive memory access request 352 at request queue 402. Request queue 402 routes the request to read queue 408 or write queue 410, respectively, based on whether the memory access request is for a read operation or a write operation. Arbitrator 404 controls access to interconnect 106 based on instructions or commands from integration logic 126. Integration logic 126 authorizes arbitrator 404 to issue request 316 via interconnect 106 based on having one or more integrals 412. For example, integration logic 126 may permit arbitrator 404 to issue one request 316 for each available integral 412. If integration logic 126 currently does not have any integrals 412, then arbitrator 404 may be prevented from issuing request 316 (e.g., by blocking or not authorizing such issuance via integration logic 126).

[0090] Response queue 406 may buffer a plurality of responses 318 received from link controller 314 via interconnect 106. Each response 318 may contain at least one memory response (e.g., with read data or write response) or at least one integration return 420. Thus, response 318 may contain both a memory response and an integration return 420. For memory responses, response queue 406 buffers the responses until response queue 406 can provide a memory access response 366 to ( Figure 1 and 3 Up to processor 114. For integral return 420, response queue 406 (containing associated logic) can forward the returned number of integrals 420 to integral logic 126. Integrating logic 126 can thus replenish at least a portion of integrals 412.

[0091] Continuing with the example operation, but for target 304, link controller 314 can receive request 316 at request queue 452. Request queue 452 can then route request 316 to read queue 458 or write queue 460, depending on whether the request is a read request or a write request. Arbitrator 454 can select a read request from read queue 458 or a write request from write queue 460 for transmission as memory request 354 to downstream components, such as memory controllers. In response to the transmission of memory request 354 corresponding to request 316 stored in request queue 452, arbitrator 454 notifies integration logic 124 that request 316 has been transmitted to (e.g., ...). Figure 1-3 The memory device 108 is a downstream component. Therefore, the integration logic 124 can add the integration 414 to a set of one or more integrations 414 that are specified to be returned to the link controller 312.

[0092] Therefore, since link controller 314 has forwarded the corresponding request 316 from request queue 452 to downstream components of memory device 108, integration logic 124 can track how many points 414 can be returned to integration logic 126 (e.g., maintain its record). Integration logic 124 notifies response queue 456 of the existence of points 414 to be returned to integration logic 126. When a memory response 364 is received at response queue 456, response queue 456 stores memory response 364. In conjunction with sending memory response 364 as response 318 to link controller 312, response queue 456 may contain at least one integration return 420. Integration return 420 may indicate the number of points 414 being returned to integration logic 126 to increase the number of points 412.

[0093] In these ways, link controller 314 can use an integral-based protocol to control (e.g., blocking, gating, modulation, or harmonizing) the request flow 316 from link controller 312. This allows link controller 314 to prevent request queue 452 from overflowing from receiving too many requests 316 (e.g., from receiving requests 316 at a rate faster than they can be forwarded downstream). Alternatively, an integral-based protocol can also be used to control the flow of responses 318 from link controller 314 to link controller 312. Response queue 456 of link controller 314 can be blocked from transmitting responses 318, but integral logic 124 has a “response” integral that authorizes the transmission of such responses. Figure 4(Except as otherwise shown in the text). These response integrals may differ from one or more “request” integrals 414 associated with request 316. In such cases, the integral logic 126 of the link controller 312 may return the response integral to the integral logic 124 in response to a memory access response 366 issued from the response queue 406. Thus, the initiator 302 and the target 304 may implement the integral-based flow control mechanism 320 bidirectionally.

[0094] Various methods can be employed for integration-based communication protocols. For example, an integration may correspond to a transmission across an interconnect, a packet, a chip, or a request or response. In some cases, a transmission may include multiple requests and / or responses, for example, by encapsulating multiple requests and / or responses into a packet or chip. In some cases, an integration may correspond substantially to any type of request or response so that, given an integration, the initiator can transmit any category of request or response. Alternatively or additionally, an integration may be specific to one or more types of requests or responses. Examples of communication types include read-related requests and write-related requests. An integration may also be specific regarding whether data is permitted to be included in a corresponding transmission. These and other communication characteristics can be further combined to create other or additional specific types of integration.

[0095] This paper describes some implementation schemes of integral systems used in certain CXL systems, using examples rather than limitations. Typically, if one or more buffers on a memory device are full and therefore unable to receive any more requests (or any more responses on the return path), then the integral-based flow control mechanism used in CXL can exert "backpressure" on the host device. In some example systems, three types of integrals can exist on the initiating or target device to control the flow of traffic between them: ReqCrd, DataCrd, and RspCrd. These integral types are request integral (ReqCrd), data integral (DataCrd), and response integral (RspCrd).

[0096] The services can be categorized as follows. For communication from the initiator to the target (e.g., from a host device to a memory device):

[0097] REQ: Requests that do not involve reading large amounts of data. These requests can be controlled using ReqCrd.

[0098] RwD: Requests that involve writing large amounts of data. These requests can be controlled using DataCrd.

[0099] For communication from the target to the initiator (e.g., from a memory device to a host device):

[0100] DRS: A response that provides a general data read response. These responses can be controlled using DataCrd.

[0101] NDR: A response that does not have a substantial data write response. These responses can be controlled using RspCrd.

[0102] These examples of CXL terms can be applied to Figure 4 The overall system. At the host device, which may be represented by initiator 302, integration logic 126 decrements the ReqCrd value (e.g., the number of one or more integrals 412) in response to forwarding the microchip across interconnect 106 to target 304. If the ReqCrd value reaches zero, integration logic 126 causes arbitrator 404 to stop sending the microchip. At the memory device, which may be represented by target 304, link controller 314 processes the received microchip. Arbitrator 454 forwards the request 316 contained in the microchip as a read or write memory request 354 to the back-end memory. Integration logic 124 increments the ReqCrd value (e.g., the number of a series of integrals 414) in response to the forwarding of memory request 354. Link controller 314 returns the accumulated request integral (ReqCrd) at integration logic 124 to integration logic 126 via at least one response 318. This integral return of 420 can be associated with the decrement of ReqCrd at integral logic 124 and the increment of ReqCrd at integral logic 126. Although “integration” is described herein with reference to the CXL standard, the implementation of the memory flow control register as described herein is applicable to and beneficial to other integral-based systems operating in a similar manner.

[0103] While integral-based flow control can be effective in controlling traffic between initiator 302 and target 304 (e.g., between a host and a memory device), it also has several characteristics that can adversely affect device and system performance. For example, as described above, when a host (e.g., link controller 312) sends a request, an integral is deducted. However, when a memory device (e.g., link controller 314) unpacks or depacks a request, or when a memory device forwards a request from request queue 452, integral logic 124 returns an integral to link controller 312. This return means that link controller 312 can send another request to link controller 314. However, due to latency in “downstream” components of request queue 452 (e.g., back-end interconnects, memory controllers, buffers, queues, and / or memory arrays), the memory device or system may be oversubscribed at different downstream locations. This oversubscription can still occur even if the integral-based flow control system instructs the host to send additional requests to the memory device.

[0104] This problem can be difficult to solve because it may be difficult to account for all the latency of all the various components of the memory device, which may be from different vendors. Consequently, if the host maintains transmit requests, it may adversely affect the pin latency and other performance characteristics of the CXL device. For example, even if the integration system is "appropriately" modulating traffic relative to the size of request queue 452 and the speed at which link controller 314 can clear request queue 452, the device may still not operate at the level published by the manufacturer (e.g., QoS). The details of the memory flow control register are described below.

[0105] In some implementations, target 304 (link controller 314) may also include register 128. In other cases (not shown), another register or component (e.g., integration logic 124) may include register 128 or perform its function. Host device 104 (e.g., link controller 312) may read values ​​stored in register 128 (or another register or component) via interconnect 106, as referenced. Figure 1-5 As described. In Figure 4 For clarity, the connection between register 128 and host device 104 is omitted.

[0106] Figure 5 This describes another example of a computing system 500 that implements aspects of a memory flow control register via a memory device. In some embodiments, the computing system 500 includes at least one host device 104, at least one memory device 108, and at least one interconnect 106. The computing system 500 can be configured as follows: Figure 1 The device 102 shown, such as Figure 2 The computing system 200 shown or such Figure 3 At least a portion of the system 300 shown.

[0107] The host device 104 may include a processor 114 and a controller 118. The controller 118 may be implemented by at least one initiator 502. For example, the initiator 502 may be implemented or operated in a manner similar to that of the initiator 302. Thus, the initiator 502 may be coupled to the processor 114 or to the interconnect 106 (including coupling to both), and the initiator 502 may be coupled between the processor 114 and the interconnect 106.

[0108] Memory device 108 may include or be associated with back-end memory 504. Back-end memory 504 may include one or more memory components (e.g., as referenced). Figure 1 The memory 112 described, or as referenced Figure 3The described DRAM 310 and one or more memory controllers, such as MC 308, are included. The memory device 108 may also include at least one interface 506 and at least one controller 110. Controller 110 may be implemented via at least one target 510. For example, target 510 may be implemented or operated in a manner similar to target 304. Target 510 may be coupled to interconnect 106 via interface 506. Thus, memory device 108 (e.g., target 510) and host device 104 (e.g., initiator 502) may be coupled to each other via interconnect 106. At least one controller 110 may also be coupled via at least one interconnect 508 (e.g., interconnect 508 may be similar to...). Figure 3 The described interconnect 306 (implemented or operated in a manner) is communicatively coupled to the back-end memory 504. The back-end memory 504 and the controller 110 may be components integrated on a single semiconductor die or located on separate semiconductor dies (e.g., but still packaged together or coupled to or placed on the same PCB). Each of the memory array 206 or the controller 110 may also be distributed across multiple dies.

[0109] Initiator 502 includes at least one link controller 512, and target 510 includes at least one link controller 514. Either or both of link controllers 512 and 514 may initiate, coordinate, cause, or otherwise participate in or control signaling across the physical or logical link implemented across interconnect 106 according to one or more protocols, including, for example, any one or both of the PCIe or CXL protocols described herein. Link controller 512 may be coupled to interconnect 106. Link controller 514 may also be coupled to interconnect 106. Thus, link controller 512 may be coupled to link controller 514 via interconnect 106. Each link controller 512 or 514 may, for example, control communication via interconnect 106 at the link layer or at one or more other layers of a given protocol. Communication signaling may include, for example, requests 516, responses 518, etc.

[0110] The devices and methods described herein are suitable for use with memory devices designed to work with a PCIe bus. Therefore, the described principles can be incorporated into memory devices with a PCIe interface. Additionally, memory device 108 can communicate via interconnect 106 by overlaying the CXL protocol onto the physical PCIe interface. Examples of memory standards involving CXL are issued by the Computing High Speed ​​Link Association and may include versions 1.0, 1.1, 2.0, and future versions. Therefore, interconnect 106 coupling host device 104 and memory device 108 may conform to at least one CXL standard. In other words, memory device 108 may be a CXL device (e.g., a Type 1 CXL device, a Type 2 CXL device, or a Type 3 CXL device) or conform to the CXL standard. Therefore, for clarity, some terms in this document may be derived from one or more of these standards or their versions. However, the described principles are also applicable to memory devices conforming to other standards (including earlier or future versions of such standards) and to memory devices that do not follow common standards.

[0111] The memory device 108 may also include at least one register 520. Register 520 may be a hardware register, such as a read-only register or a read-write register. For example, register 520 may be as described in the reference... Figure 1 The described register 128. In some embodiments in which the computing system 500 operates the CXL protocol and / or PCIe protocol across interconnect 106, at least one register 520 may reside in or be mapped to the CXL device configuration space (e.g., as described in reference standards such as CXL standard version 1.0, 1.1, 2.0, or later). Figure 5 As shown, register 520 may be separate from controller 110. In some embodiments (not shown), register 520 may be integrated with controller 110.

[0112] Register 520 may be coupled to interconnect 106 via interface 506. Therefore, other devices (e.g., host device 104) may read register 520 via interconnect 106. In some embodiments, register 520 may store instructions for memory devices (e.g., reference memory). Figure 1The number of memory requests (e.g., write and read requests) that can be serviced (e.g., may not be completed) as described. In some embodiments, the device manufacturer may store the value in register 520 during the assembly and configuration of memory device 108. The device manufacturer may determine the value based on various factors. These factors may include the round-trip time or pin latency of the memory device (e.g., the round-trip time of a request-response pair from interface 506) from when a request is unpacked or depacked and forwarded from the memory-side controller until a memory response for the request is received at the memory-side controller. Other factors may include the time taken for memory requests to flow through queues within the various interconnects, controllers, and memory devices (e.g., device propagation latency), as described above, and the configuration of back-end memory 504. For example, the back-end memory 504 may be configured as one or more DRAMs and / or other memory components (e.g., Type 3 CXL device memory, such as memory expanders) that operate as back-end memory 504.

[0113] The value indicating the number of potentially incomplete memory requests in the memory device 108 can be configured in several different ways. For example, the value may include at least one value indicating the total number of possible combinations of incomplete write and read requests. In other embodiments, the stored value may include at least two values. Consider three examples. First, a value indicating the number of potentially incomplete write requests and another value indicating the total number of possible combinations of incomplete write and read requests. Second, a value indicating the number of potentially incomplete read requests and another value indicating the total number of possible combinations of incomplete write and read requests. Third, a value indicating the number of potentially incomplete write requests and another value indicating the number of possible incomplete read requests.

[0114] While the described examples can be used to indicate the total number of possible incomplete write and read requests in memory device 108, examples including the number of possible incomplete write requests can enable other functionalities. For example, some memory devices (e.g., 3DXP devices or other memory types) may use read-modify-write operations, perform error correction for metadata transformation, etc. Enabling write request number control and limit values ​​can be advantageous in these scenarios. In some embodiments, examples including the number of possible incomplete read requests can also enable other functionalities. For example, in applications or devices that may have large read workloads, enabling read request number control and limit values ​​can similarly benefit from reduced latency.

[0115] Additionally, one or more registers 520 mapped to the CXL device configuration space can be configured in several ways. For example, register 520 may be a register containing at least one value indicating the total number of possible combinations of write and read requests that may not be completed. In another example, register 520 may be a register containing at least one value indicating the number of possible write requests that may not be completed. In yet another example, register 520 may be a register containing at least one value indicating the number of possible read requests that may not be completed. In some embodiments, register 520 may contain a combination of the foregoing examples.

[0116] In other words, register 520 may contain a total request register (e.g., CXL_Device_Max_Total_Request_Outstanding_Limit_REG) indicating the total number of possible combinations of read and write requests that may not be completed in the memory device, a read register (e.g., CXL_Device_Max_Read_Request_Outstanding_Limit_REG) indicating the total number of possible combinations of read and write requests that may not be completed in the memory device, and a combination of those registers indicating the total number of possible combinations of read and write requests that may not be completed in the memory device. The host device may then limit the amount of a corresponding memory request based on the value read from the register. Depending on the configuration of the register, the host may limit only the total number of combinations of requests (e.g., both read and write) or the total number of combinations of read and write requests (e.g., the host may limit 1) the total number of requests and the number of read requests and / or 2) the total number of requests and the number of write requests) to maintain the system performance at advertised levels.

[0117] like Figure 5 As depicted, host device 104 may include interface 522. Initiator 502 may be coupled to interconnect 106 via interface 522. Thus, host device 104 (e.g., initiator 502) and memory device 108 (e.g., target 510) may be coupled to each other via interconnect 106 and interface 522. Controller 118 (e.g., initiator 502) may issue a request to memory device 108 via interconnect 106 to read one or more values ​​(e.g., request 516) stored in register 520. The one or more values ​​may indicate the number of memory requests that may be incomplete in memory device 108. Host device 104 may also receive a response from memory device 108 via interconnect 106, the response may include one or more values ​​(e.g., response 518). As described above, the values ​​indicating the number of memory requests that may be incomplete in memory device can be configured in several different ways.

[0118] When host device 104 receives a response from register 520 (e.g., as...) Figure 1 When the response includes a value stored in register 520 (part of the exchange of register-related information 130), the host device 104 (e.g., controller 118) can control the number of incomplete memory requests in memory device 108 based on the value. As mentioned, the memory flow control register can be used to address some of the inefficiencies associated with integral-based memory flow protocols in CXL devices, as described above. For example, controller 118 can control the number of incomplete memory requests in memory device 108 to prevent the number of incomplete memory requests in memory device 108 from exceeding the number of memory requests indicated by one or more values. In some embodiments, controller 118 can control the number of incomplete memory requests in memory device 108 during periods in which controller 118 operates under an integral-based flow control system, the integral-based flow control system indicating that integrals can be used to allow controller 118 to issue memory requests to memory device 108, as described above.

[0119] In some embodiments, controller 118 may, during or as part of an initialization operation, issue a request to the memory device via interconnect 106 to read one or more values ​​stored in register 520. In some embodiments, the initialization operation may be an initialization in response to the memory device 108 being powered on (e.g., changing from an "off" state to an "on" state or waking from a low-power or "sleep" mode) or to a device connected to or associated with controller 118, such as host device 104 (e.g., hot-plugging or hot-swapping operation). In other words, controller 118 may read values ​​from register 520 when either host device 104 and / or memory device 108 (or components thereof) or both are initialized. In some cases, this may be a process similar to reading other configuration registers immediately after initialization.

[0120] Controller 118 may use any of a variety of techniques to control the number of incomplete memory requests in memory device 108. For example, controller 118 may compare the number of incomplete memory requests in memory device 108 with the number of potentially incomplete memory requests in memory device 108 based on one or more values. In some cases, host device 104 (e.g., controller 118) maintains a counter indicating the number of incomplete requests. The counter is incremented (e.g., incremented) in response to the transmission of request 516. The counter is decremented (e.g., decremented) in response to the reception of response 518. The value of this counter may be compared with the value of register 520, as received from memory device 108. Multiple counters may be present at host device 104. For example, the counter may be a counter for each type of communication described above with respect to transmittable values ​​(e.g., the total number of combined read and write requests, the number and total number of read requests, the number and total number of write requests, or the number of read and write requests).

[0121] In response to the number of incomplete memory requests in memory device 108 being less than the number of potentially incomplete memory requests (e.g., based on the comparison), controller 118 may issue another memory request to memory device 108. Conversely, in response to the number of incomplete memory requests in memory device 108 being greater than or equal to the number of potentially incomplete memory requests (e.g., based on the comparison), controller 118 may abstain from issuing memory requests to memory device 108 at least until this condition changes.

[0122] In a manner similar to that described herein with respect to memory device 108, host device 104 can communicate via interconnect 106 by overlaying the CXL protocol onto a physical PCIe interface. Therefore, interconnect 106 coupling host device 104 and memory device 108 may conform to at least one CXL standard (e.g., CXL version 1.0, 1.1, 2.0, or another version). In other words, the initiator 502 of host device 104 may be a CXL controller (e.g., a CXL link controller) or conform to the CXL standard.

[0123] The host device 104 can use at least one register 520 to address problems related to the integral-based flow control system, as described above. For example, by using the described techniques and register 520 to account for the mismatch between the integral-based request queue availability and the overall CXL pin latency, the memory device 108 and the instance computing system can be configured to operate closer to the manufacturer-published technical parameters and at the manufacturer-published level (e.g., QoS).

[0124] While the description generally pertains to devices and techniques for implementing memory flow control registers for Type 3 CXL devices (e.g., memory extenders), it can be extended to other types of CXL devices (e.g., Type 1 and Type 2 CXL devices) as well as non-CXL devices (e.g., PCIe devices).

[0125] Instance methods

[0126] This section is for reference. Figure 6 and 7 The flowcharts and diagrams describing example methods for implementing memory flow control registers are provided. These descriptions may also reference... Figure 1-5 The components, entities, and other aspects described herein are for reference only by way of examples.

[0127] Figure 6 A flowchart illustrating an example process 600 for implementing aspects of a memory flow control register is provided. At block 602, the controller issues a request to read one or more values ​​stored in at least one register of the memory device. These one or more values ​​may indicate, for example, references to... Figure 1 The number of memory requests that can be serviced by the memory device (e.g., the number of memory requests that may not be completed in or at the memory device, or the number of memory requests authorized to be serviced by the memory device) is described. The total number of memory requests that can be serviced by the memory device may be the number of memory requests that the memory device can service within a certain time period to provide a specific quality of service (QoS) or to meet another specified technical or performance parameter. For example, the controller 118 of the host device 104 (e.g., initiator 502) may send a request (e.g., request 516) to the memory device 108 via interconnect 106 to read one or more values ​​stored in register 520. The one or more values ​​may indicate the number of memory requests that can be serviced by the memory device 108 or may not be completed in or at the memory device 108.

[0128] In some implementations, host device 104 and memory device 108 operate on the CXL protocol and / or PCIe protocol across interconnect 106. In other words, memory device 108 may be a CXL device (e.g., a Type 1, Type 2, or Type 3 CXL device), initiator 502 (of controller 118) may be a CXL link controller, and register 520 may be located in or mapped to a CXL device configuration space (e.g., as described in reference standards such as CXL standard versions 1.0, 1.1, 2.0, or later).

[0129] For reference Figure 5As described, the value indicating the number of potentially incomplete memory requests in the memory device 108 can be configured in several different ways. For example, the value may include at least one value indicating the total number of potentially incomplete write and read requests. In other embodiments, the stored value may include at least two values. Consider three examples. First, a value indicating the number of potentially incomplete write requests, and another value indicating the total number of potentially incomplete write and read requests. Second, a value indicating the number of potentially incomplete read requests, and another value indicating the total number of potentially incomplete write and read requests. Third, a value indicating the number of potentially incomplete write requests, and another value indicating the number of potentially incomplete read requests.

[0130] Similarly, register 520 can be configured in several ways. For example, register 520 may be a register containing at least one value indicating the total number of possible combinations of write and read requests that may not be completed. In another instance, register 520 may be a register containing at least one value indicating the number of possible write requests that may not be completed. In yet another instance, register 520 may be a register containing at least one value indicating the number of possible read requests that may not be completed. In some embodiments, register 520 may contain a combination of the foregoing examples.

[0131] At block 604, the controller receives a response from the memory device. The response may contain one or more values ​​stored in a register. For example, host device 104 may receive a response (e.g., response 518) from memory device 108 via interconnect 106, which may contain one or more values ​​stored in register 520.

[0132] Optionally, at block 606, the controller may control the number of unfulfilled memory requests in the memory device based on one or more values. For example, host device 104 (e.g., controller 118) may control the number of unfulfilled memory requests in memory device 108 based on a value received from register 520 of memory device 108. For example, controller 118 may control the number of unfulfilled memory requests in memory device 108 to prevent the number of unfulfilled memory requests in memory device 108 from exceeding the number of memory requests indicated by one or more values. In some embodiments, controller 118 may operate under an integral-based flow control system during periods when the integral-based flow control system indicates that the integral is available to allow the controller to issue memory requests to the memory device. During such periods, controller 118 may control the number of unfulfilled memory requests in memory device 108 to prevent the number of unfulfilled memory requests in memory device 108 from exceeding the number of memory requests indicated by one or more values, even if the integral-based flow control system indicates that the integral is available to allow the controller to issue memory requests to the memory device, the blocking behavior will still occur. For example, controller 118 may prevent the transmission of memory requests to prevent the number of incomplete memory requests at memory device 108 from exceeding the number of permitted memory requests at memory device as indicated by one or more values, even if controller 118 has an integral authorized to transmit another memory request.

[0133] The controller 118 can use any of a variety of techniques to control the number of unfulfilled memory requests in the memory device 108. For example, see reference... Figure 5 As described, controller 118 may use one or more values ​​(e.g., in combination with one or more counters, as described above) to compare the number of incomplete memory requests in memory device 108 with the number of potentially incomplete memory requests in memory device 108. In response to the number of incomplete memory requests in memory device 108 being less than the number of potentially incomplete memory requests in memory device 108 (e.g., based on the comparison), controller 118 may continue to issue memory requests to memory device 108. Conversely, in response to the number of incomplete memory requests in memory device 108 being greater than or equal to the number of potentially incomplete memory requests, controller 118 may block or abort issuing memory requests to memory device 108.

[0134] In some implementation schemes, such as reference Figure 5As described, controller 118 may, during or as part of an initialization operation, issue a request to read one or more values ​​stored in register 520 to the memory device via interconnect 106. For example, the initialization operation may be an initialization in response to powering on memory device 108 (e.g., changing from an "off" state to an "on" state or waking from a low-power or "sleep" mode) or to a device connected to or associated with controller 118, such as host device 104 (e.g., hot-plugging or hot-swapping operation).

[0135] Figure 7 A flowchart illustrating another example of a process 700 implementing an aspect of a memory flow control register. At block 702, the memory device receives a request to read one or more values ​​from at least one register of the memory device, said values ​​indicating the number of memory requests that can be serviced by the memory device (e.g., the number of memory requests that may not be completed in or at the memory device, or the number of memory requests authorized to be serviced by the memory device), as referenced. Figure 1 As described. For example, memory device 108 (e.g., target 510) may receive a request (e.g., request 516) from host device 104 (e.g., initiator 502) via interconnect 106 to read one or more values ​​stored in register 520. The one or more values ​​may indicate the number of memory requests that can be serviced by memory device 108 or that may not have been completed in memory device 108.

[0136] At block 704, the memory device transmits a response containing one or more values ​​stored in a register. For example, memory device 108 (e.g., target 510) may transmit a response (e.g., response 518) to host device 104 (e.g., initiator 502) via interconnect 106. The response may contain one or more values ​​stored in register 520.

[0137] For reference Figure 5 and Figure 6 As described, the value indicating the number of potentially incomplete memory requests in the memory device 108 can be configured in several different ways. For example, the value may include at least one value indicating the total number of potentially incomplete write and read requests. In other embodiments, the stored value may include at least two values. Consider three examples. First, a value indicating the number of potentially incomplete write requests, and another value indicating the total number of potentially incomplete write and read requests. Second, a value indicating the number of potentially incomplete read requests, and another value indicating the total number of potentially incomplete write and read requests. Third, a value indicating the number of potentially incomplete write requests, and another value indicating the number of potentially incomplete read requests.

[0138] Similarly, register 520 can be configured in several ways. For example, register 520 may be a register containing at least one value indicating the total number of possible combinations of write and read requests that may not be completed. In another instance, register 520 may be a register containing at least one value indicating the number of possible write requests that may not be completed. In yet another instance, register 520 may be a register containing at least one value indicating the number of possible read requests that may not be completed. In some embodiments, register 520 may contain a combination of the foregoing examples.

[0139] In some implementations, host device 104 and memory device 1018 operate on the CXL protocol and / or PCIe protocol across interconnect 106. In other words, memory device 108 may be a CXL device (e.g., a Type 1, Type 2, or Type 3 CXL device), target 510 (controller 110) may be a CXL link controller, and register 520 may be located in or mapped to a CXL device configuration space (e.g., as described in reference standards, such as CXL standard versions 1.0, 1.1, 2.0, or later).

[0140] The order in which the operations are shown and / or described in the flowcharts and diagrams described above is not intended to be limiting. Any number or combination of the described process operations can be combined or rearranged in any order to implement a given method or an alternative method. Operations can also be omitted from the described method or added to the described method. Furthermore, the described operations can be implemented in a completely or partially overlapping manner.

[0141] These methods can be implemented, for example, in hardware (e.g., a fixed logic circuit system or a processor incorporating memory), firmware, software, or a combination thereof. The methods can be implemented using… Figures 1 to 5 The diagrams illustrate one or more of the devices or components shown, which may be further divided, combined, rearranged, etc. The devices and components in these diagrams typically represent: hardware, such as electronic devices, packaged modules, IC chips, or circuits; firmware or its operation; software; or combinations thereof. Therefore, these diagrams illustrate some of the many possible systems or devices capable of implementing the described methods.

[0142] Unless the context otherwise requires, the use of the word “or” herein may be interpreted as the use of “inclusive or”, or as allowing the inclusion or application of a term containing or applying one or more items linked by the word “or” (e.g., the phrase “A or B” may be interpreted as allowing only “A”, only “B”, or both “A” and “B”). As used herein, the phrase referring to “at least one of…” in a list of items means any combination of those items containing a single member. For example, “at least one of a, b, or c” may cover a, b, c, ab, ac, bc, and abc, as well as any combination having multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). Furthermore, the items represented in the figures and the terms discussed herein may indicate one or more items or terms, and are therefore interchangeable with single or multiple forms of items and terms in this written description.

[0143] in conclusion

[0144] Although embodiments for memory flow control registers have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. In fact, the specific features and methods are disclosed as example embodiments for memory flow control registers.

Claims

1. A method for memory flow control, the method comprising: The controller issues a request to read one or more values, which indicate the number of memory requests served by the computation high-speed link CXL memory device, and the one or more values ​​are stored in at least one register mapped to the CXL device configuration space of the CXL memory device, the at least one register containing one or more of the following: A first register contains at least one first value, the at least one first value indicating the total number of combinations of write and read requests that may not be completed in or at the CXL memory device; A second register contains at least one second value indicating the number of write requests that may not have been completed in or at the CXL memory device; or A third register contains at least one third value indicating the number of read requests that may not have been completed in or at the CXL memory device; and The controller receives a response from the CXL memory device, the response containing at least a portion of the one or more values.

2. The method of claim 1, further comprising: The number of unfulfilled memory requests in or at the CXL memory device is controlled based on one or more of the values.

3. The method of claim 1, further comprising: The number of unfulfilled memory requests in or at the CXL memory device is controlled to prevent the number of unfulfilled memory requests in or at the CXL memory device from exceeding the number of memory requests indicated by the one or more values.

4. The method of claim 1, further comprising: During the period in which the controller operates under the integral-based flow control system, the number of unfulfilled memory requests in or at the CXL memory device is controlled to prevent the number of unfulfilled memory requests in or at the CXL memory device from exceeding the number of memory requests indicated by the one or more values, wherein the integral-based flow control system indicates one or more integrals that can be used to allow the controller to issue memory requests to the CXL memory device.

5. The method of claim 1, further comprising: The controller uses one or more values ​​to compare the number of memory requests that are not completed in or at the CXL memory device with the number of memory requests that can be served by the CXL memory device. and A memory request is sent to the CXL memory device in response to the fact that the number of memory requests that are not completed in or at the CXL memory device is less than the number of memory requests that can be served by the CXL memory device.

6. The method of claim 1, further comprising: The controller uses one or more values ​​to compare the number of memory requests that are not completed in or at the CXL memory device with the number of memory requests that can be served by the CXL memory device. and The transmission of memory requests to the CXL memory device is stopped in response to the fact that the number of unfulfilled memory requests in or at the CXL memory device is greater than or equal to the number of memory requests that can be served by the CXL memory device.

7. The method of claim 1, further comprising: The controller reads one or more values ​​stored in at least one register of the CXL memory device during the initialization operation.

8. The method of claim 7, wherein the initialization operation responds to at least one of the following: The CXL memory device is powered on; or The CXL memory device is connected to the controller or a device associated with the controller.

9. The method of claim 1, wherein the one or more values ​​indicating the number of memory requests that can be served by the CXL memory device include at least one of the following: The first value; The first value and the second value; The first value and the third value; or The second value and the third value.

10. The method of claim 1, wherein the CXL memory device comprises a type 1 CXL device, a type 2 CXL device, or a type 3 CXL device.

11. The method of claim 1, wherein the controller comprises a CXL controller.

12. The method of claim 1, wherein write memory requests and read memory requests that may not be completed in or at the CXL memory device include one or more of the following: write memory requests or read memory requests pending or existing in or at the CXL memory device; write memory requests or read memory requests that have been received in or at the CXL memory device but have not yet been processed by the CXL memory device; write memory requests or read memory requests that have been received by the CXL memory device but have not yet been responded to by the CXL memory device; or write memory requests or read memory requests that are in progress in a downstream or back-end component of the CXL memory device.

13. The method of claim 1, wherein the at least one register mapped to the CXL device configuration space of the CXL memory device is either separate from or integrated with the controller.

14. A method for a memory device, the method comprising: In or at a high-speed CXL memory device, a request to read one or more values ​​is received, the one or more values ​​indicating the number of memory requests served by the CXL memory device, the one or more values ​​being read from at least one register mapped to the CXL device configuration space of the CXL memory device, the at least one register containing one or more of the following: A first register contains at least one first value, the at least one first value indicating the total number of combinations of write and read requests that may not be completed in or at the CXL memory device; A second register contains at least one second value indicating the number of write requests that may not have been completed in or at the CXL memory device; or A third register contains at least one third value indicating the number of read requests that may not have been completed in or at the CXL memory device; and The CXL memory device emits a response containing at least a portion of the one or more values.

15. The method of claim 14, wherein the one or more values ​​indicating the number of memory requests that can be served by the CXL memory device include at least one of the following: The first value; The first value and the second value; The first value and the third value; or The second value and the third value.

16. The method of claim 14, wherein the CXL memory device comprises a type 1 CXL device, a type 2 CXL device, or a type 3 CXL device.

17. The method of claim 14, wherein write memory requests and read memory requests that may not be completed in or at the CXL memory device include one or more of the following: write memory requests or read memory requests pending or existing in or at the CXL memory device; write memory requests or read memory requests that have been received in or at the CXL memory device but have not yet been processed by the CXL memory device; write memory requests or read memory requests that have been received by the CXL memory device but have not yet been responded to by the CXL memory device; or write memory requests or read memory requests that are in progress in a downstream or back-end component of the CXL memory device.

18. A device for memory flow control, the device comprising: An interface configured to be coupled to a compute high-speed link CXL memory device via interconnects; and A controller, coupled to the interface, is configured to: A request to read one or more values ​​is transmitted to the CXL memory device via the interconnect, the one or more values ​​indicating the number of memory requests served by the CXL memory device, the one or more values ​​being stored in at least one register mapped to the CXL device configuration space of the CXL memory device, the at least one register containing one or more of the following: A first register contains at least one first value, the at least one first value indicating the total number of combinations of write and read requests that may not be completed in or at the CXL memory device; A second register contains at least one second value indicating the number of write requests that may not have been completed in or at the CXL memory device; or A third register contains at least one third value indicating the number of read requests that may not have been completed in or at the CXL memory device; and A response is received from the CXL memory device via the interconnect, the response comprising at least a portion of the one or more values.

19. The device of claim 18, wherein the controller is further configured to: The number of unfulfilled memory requests in or at the CXL memory device is controlled based on one or more of the values.

20. The device of claim 18, wherein the controller is further configured to: The number of unfulfilled memory requests in or at the CXL memory device is controlled to prevent the number of unfulfilled memory requests in or at the CXL memory device from exceeding the number of memory requests indicated by the one or more values.

21. The device of claim 18, wherein the controller is further configured to: The number of unfulfilled memory requests in or at the CXL memory device is controlled to prevent the number of unfulfilled memory requests in or at the CXL memory device from exceeding the number of memory requests indicated by one or more values. This control occurs during a period in which the controller operates under an integral-based flow control system, which indicates one or more integrals that can be used to allow the controller to issue memory requests to the CXL memory device.

22. The device of claim 18, wherein the controller is further configured to: The number of unfulfilled memory requests in or at the CXL memory device is compared with the number of memory requests that can be served by the CXL memory device using one or more of the values; and A memory request is sent to the CXL memory device in response to the fact that the number of memory requests that are not completed in or at the CXL memory device is less than the number of memory requests that can be served by the CXL memory device.

23. The device of claim 18, wherein the controller is further configured to: The number of unfulfilled memory requests in or at the CXL memory device is compared with the number of memory requests that can be served by the CXL memory device using one or more of the values; and The transmission of memory requests to the CXL memory device is stopped in response to the fact that the number of unfulfilled memory requests in or at the CXL memory device is greater than or equal to the number of memory requests that can be served by the CXL memory device.

24. The device of claim 18, wherein the controller is further configured to: During initialization, a request to read one or more values ​​stored in at least one register of the CXL memory device is sent to the CXL memory device via the interconnect.

25. The device of claim 24, wherein the initialization operation responds to at least one of the following: The CXL memory device is powered on; or The CXL memory device is connected to the controller or a device associated with the controller.

26. The device of claim 18, wherein the one or more values ​​indicating the number of memory requests that can be served by the CXL memory device include at least one of the following: The first value; The first value and the second value; The first value and the third value; or The second value and the third value.

27. The device of claim 18, wherein the interconnect is configured to conform to at least one CXL standard.

28. The device of claim 18, wherein the controller comprises a CXL controller.

29. The device of claim 18, wherein a write memory request and a read memory request that may not be completed in or at the CXL memory device includes one or more of the following: a write memory request or a read memory request pending or existing in or at the CXL memory device; a write memory request or a read memory request that has been received in or at the CXL memory device but has not yet been processed by the CXL memory device; a write memory request or a read memory request that has been received by the CXL memory device but has not yet been responded to by the CXL memory device; or a write memory request or a read memory request in progress in a downstream or back-end component of the CXL memory device.

30. The device of claim 18, wherein the at least one register mapped to the CXL device configuration space of the CXL memory device is either separate from or integrated with the controller.

31. The device of claim 18, wherein the controller is further configured to determine the number of memory requests served by the CXL memory device based on the number of memory requests served by the CXL memory device, while providing a specified performance parameter defined by the Quality of Service (QoS) parameter.

32. A memory device comprising: An interface configured to be coupled to a host device via interconnects; and At least one register is configured to: It can be read by the host device via the interconnect; and Store one or more values ​​that indicate the number of memory requests that can be served by a Compute High-Speed ​​Link (CXL) memory device associated with the memory device; and The at least one register, mapped to the CXL memory device associated with the memory device, comprises one or more of the following: A first register contains at least one first value, the at least one first value indicating the total number of combinations of write and read requests that may not be completed in or at the CXL memory device; A second register contains at least one second value indicating the number of write requests that may not have been completed in or at the CXL memory device; or A third register contains at least one third value indicating the number of read requests that may not have been completed in or at the CXL memory device.

33. The memory device of claim 32, wherein the one or more values ​​indicating the number of memory requests that can be served by the CXL memory device include at least one of the following: The first value; The first value and the second value; The first value and the third value; or The second value and the third value.

34. The memory device of claim 32, wherein the interconnect is configured to conform to at least one CXL standard.

35. The memory device of claim 34, wherein the CXL memory device comprises a type 1 CXL device, a type 2 CXL device, or a type 3 CXL device.

36. The memory device of claim 32, wherein a write memory request and a read memory request that may not be completed in or at the CXL memory device includes one or more of the following: a write memory request or read memory request pending or existing in or at the CXL memory device; a write memory request or read memory request that has been received in or at the CXL memory device but has not yet been processed by the CXL memory device; a write memory request or read memory request that has been received by the CXL memory device but has not yet been responded to by the CXL memory device; or a write memory request or read memory request in progress in a downstream or back-end component of the CXL memory device.

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