Test apparatus and method for a high-speed low-latency interconnect interface facing a silicon dielectric layer

Abstract

The application relates to a testing device and method for a multi-channel high-speed low-delay interconnection interface of a silicon medium layer. The device comprises a standard testing port for interactive testing instructions, an asynchronous bypass port for directly accessing IO ports of channels of a physical layer of the interconnection interface, a built-in self-test engine for realizing loopback testing and data checking between different layers, a redundant data channel for repairing a damaged data channel, and a delay chain testing circuit for testing functions and linearity of a delay chain. The device is used for embedding and distributing testing and repairing logics in the physical layer and the link layer, realizing internal testing control without an external controller, testing and rapidly screening a sample, and ensuring the performance of the sample.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a test apparatus and method for high-speed, low-latency interconnect interfaces for silicon dielectric layers. Background Technology

[0002] With the development of semiconductor technology, heterogeneous acceleration platforms that integrate multiple computing chips have emerged in high-intensity data processing. Different types of computing chips on heterogeneous computing platforms need to be interconnected at high speed through a large number of I / O ports. Therefore, multi-channel high-speed interconnect interfaces for silicon dielectric layers have emerged.

[0003] In device fabrication, process variations can easily lead to performance deviations in prototypes. Since high-speed interconnect interfaces often operate at high frequencies, performance deviations caused by the process can result in chip malfunctions. Therefore, how to test prototypes and quickly screen them is an urgent problem to be solved. Summary of the Invention

[0004] Therefore, it is necessary to provide a test device and method for high-speed, low-latency interconnect interfaces on silicon dielectric layers that can independently test and repair the aforementioned technical problems.

[0005] In a first aspect, this application provides a test apparatus for multi-channel high-speed, low-latency interconnect interfaces on silicon dielectric layers. The apparatus includes:

[0006] The standard test port is used for interactive test commands;

[0007] Asynchronous bypass ports are I / O ports used to directly access the physical layer channels of the interconnect interface;

[0008] It has a built-in self-test engine for implementing loopback testing and data verification between different levels;

[0009] Redundant data channels are used to repair damaged data channels;

[0010] Delay chain test circuit, used to test the functionality and linearity of delay chains.

[0011] In one embodiment, the standard test port is located at the physical layer of the interconnect interface and is used to interact with standard test commands, including:

[0012] Serial test input port and serial test output port.

[0013] In one embodiment, an asynchronous bypass port is provided in the interconnect interface for direct access to the I / O port of the interconnect interface from within the core.

[0014] Secondly, this application also provides a testing method for high-speed, low-latency interconnect interfaces on silicon dielectric layers. The method includes:

[0015] Test the data channel between the transmitter chip and the receiver chip connected by the interconnect interface;

[0016] Test the data channels inside the physical layer of the interconnect interface;

[0017] Test the channel between the physical layer and the data link layer of the interconnect interface;

[0018] The damaged data channel was identified based on the test results.

[0019] Remap and repair the damaged data channel;

[0020] Test the functionality and linearity of the delay chain within the interconnect interface;

[0021] Test the quality of the data output from the interconnect interface.

[0022] In one embodiment, a built-in self-test is used to test the data channel between the transmitter chip and the receiver chip connected by the interconnect interface.

[0023] In one embodiment, the data channels inside the physical layer of the interconnect interface are tested using a built-in self-test;

[0024] The built-in self-test tests the channel between the physical layer and the link layer of the interconnect interface.

[0025] In one embodiment, testing the delay chain functionality and linearity within the interconnect interface includes:

[0026] Test the zero latency, delay step size, maximum latency, and linearity of the actual delay chain design.

[0027] In one embodiment, testing the zero latency, delay step size, maximum latency, and linearity of a practical delay chain design includes:

[0028] A self-excited oscillating clock is generated by a ring oscillator;

[0029] Record the number of cycles of the self-excited oscillation clock within the number of cycles of multiple known clock cycles and estimate the period of the self-excited oscillation clock.

[0030] The delay of the delay chain is obtained by using the self-excited oscillation clock period;

[0031] Repeatedly iterate to calculate the delay of the delay chain, and obtain the zero delay, delay step size, maximum delay and linearity of the delay chain.

[0032] In one embodiment, the ring oscillator counter is constructed using a delay chain and an inverter.

[0033] In one embodiment, testing the data quality output from the interconnect interface further includes:

[0034] By adjusting the reference voltage, the data eye width under different reference voltages is tested, and a two-dimensional data eye diagram output by the interconnect interface is obtained.

[0035] The aforementioned test apparatus and method for high-speed, low-latency interconnect interfaces on silicon dielectric layers utilize multiple standard test ports for interactive test commands, asynchronous bypass ports for direct access to the I / O ports of the physical layer channels of the interconnect interface, a built-in self-test engine for loopback testing and data verification between different layers, redundant data channels for repairing damaged data channels, and a delay chain test circuit for performing functional and linearity tests on the delay chain. Based on this application, the test apparatus can perform channel repair testing internally, embedding the test and repair logic within the physical and link layers. Almost all required tests can be executed internally without the need for an external controller. This application enables sample testing and rapid screening, ensuring sample performance. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a top-level test architecture diagram of the test apparatus in one embodiment;

[0038] Figure 2 This is a block diagram of the top-level design of the delay line in one embodiment;

[0039] Figure 3 This is a schematic diagram of the MISR register in one embodiment;

[0040] Figure 4 This is a flowchart of a test method in one embodiment. Detailed Implementation

[0041] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0042] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0043] In the description of this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "setting," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0044] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0045] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0046] With the rise of artificial intelligence and big data, traditional CPU computing platforms can no longer meet the needs of high-intensity data applications. Heterogeneous acceleration platforms integrating various computing chips such as CPUs, GPUs, FPGAs, and AI accelerators have emerged. Different types of computing chips on heterogeneous computing platforms require high-speed interconnection through numerous I / O ports. Traditional PCB substrate interconnection or SIP interconnection can no longer meet these requirements, necessitating the use of special high-speed, low-latency interconnect interfaces on the silicon dielectric for chip interconnection. Simultaneously, high-bandwidth memory (HBM) for high-intensity data applications also requires interconnection with computing chips using multi-channel high-speed, low-latency interconnect interfaces on the silicon dielectric layer.

[0047] In one embodiment, a testing apparatus is provided that can perform tests on high-speed, low-latency interconnect interfaces for analyzing and repairing data paths between damaged transmitter and receiver chips. The apparatus incorporates testing and repair logic, allowing tests to be performed directly within the apparatus without the need for an external controller.

[0048] In one embodiment, the device includes: a standard test port for interactive test commands; an asynchronous bypass port for directly accessing the I / O port of the physical layer of the interconnect interface; a built-in self-test engine for implementing loopback testing and data verification between different layers; a redundant data channel for detecting whether the channel is damaged and repairing the damaged data channel; and a delay chain test circuit for performing functional and linearity tests on the delay chain.

[0049] Figure 1 The diagram shown is a top-level test architecture diagram of a test device for a high-speed, low-latency interconnect interface on a silicon dielectric layer in one embodiment. Figure 1 As shown, this interconnect interface connects the transmitter and receiver chips, and includes a link layer and a physical layer. P1500 controllers are located at both the link and physical layers. A loopback BIST is established between the link and physical layers, and another loopback BIST is located within the physical layer. The physical layer also includes redundant channels for channel repair and several test interfaces.

[0050] The test apparatus provided in this embodiment is illustrated using a multi-channel high-speed low-latency interconnect interface for silicon dielectric layers as an example. The test and repair logic of this test apparatus is set in the physical layer and link layer of the interface. The high-speed low-latency interconnect interface allows external controllers in the physical layer and link to perform test and repair operations: except for the optional link layer loopback BIST, all required tests can be performed at the physical layer independently of the external controller.

[0051] In one embodiment, standard test ports are located at the physical layer of the interconnect interface for exchanging standard test commands, including serial test input ports and serial test output ports.

[0052] For example, a test port is provided at the link layer of the interconnect interface. This test port can be a test port conforming to the IEEE 1500 standard, used by the high-speed low-latency interconnect interface to transmit P1500 commands to other cores. For the link layer, the test port is a pass-through interface in the physical layer. The high-speed low-latency interconnect interface can control this port either using the P1500 controller within the physical layer or a separately designed P1500 controller at the link layer.

[0053] In this embodiment, functional testing is performed using the IEEE 1500 standard test port, which employs an asymmetric wrapper serial port (WSP), a separate WSI (serial test input port), and a WSO (serial test output port) for each channel. Internally at the physical layer, all WSP port signals, including WRST_n and WRCK, are driven by the embedded microprocessor MCF.

[0054] like Figure 2 The diagram shows the top-level architecture of the delay chain design. The MCF connection drives the P1500 port, including the clock signal WRCK and the reset signal WRST_n. Figure 2 As shown, the MCF is connected to the P1500 controller inside the physical layer and also to the P1500 controller in the link layer. During testing, the P1500 port can be controlled by either the P1500 controller inside the physical layer or the P1500 controller in the link layer.

[0055] When the internal engine using P1500 instructions is activated or during channel repair, the device's physical layer takes over the MCF pin for WSP signal transmission. The physical layer drives WRST_n high by default unless a command to set WRST_n to valid is issued. WRCK remains constant at 0 and toggles only when the embedded P1500 controller is triggered to send a supported command.

[0056] The built-in self-test engine of the high-speed low-latency interconnect interface test device in this embodiment is used to implement built-in self-test, including interface BIST (Built-in Self Test) and loopback BIST.

[0057] The physical layer interface BIST uses commands from a built-in test architecture to test and train the interface between the transmitter and receiver chips. This can be used to, for example, repair the data path between the transmitter and receiver chips or train and optimize the timing of data transmission.

[0058] The physical layer loopback BIST is used to test the internal paths of the physical layer. The internal logic of the physical layer generates data patterns and drives and receives data through I / O ports.

[0059] The link layer loopback BIST is used to test the channel between the link layer and the physical layer. The data generation and comparison during channel testing are both completed by the link layer.

[0060] In one embodiment, the asynchronous bypass port is set in the interconnect interface for direct access to the I / O port of the interconnect interface from within the core.

[0061] For example, the asynchronous bypass interface allows the link layer to directly access the channel ports (DWORD IO) in the physical layer, which can serve as interfaces for the core. During the EXTEST boundary scan test, the link layer can send data to or receive data from the data channel IO ports via the asynchronous bypass interface.

[0062] Figure 3 This is a schematic diagram of the MISR register structure in one embodiment, such as... Figure 3 The data loopback architecture shown in the diagram sends a selected data mode through the data task mode sending path when reading and writing data, and loops back the data through the task mode receiving path of their respective signals.

[0063] Because both the read strobe signal WDQS and the write strobe signal RDQS are unidirectional signals, dedicated built-in loopback receive and transmit paths are configured in the physical layer to loop back these two signals. Each data channel has an error state, which is "sticky" once an error is detected in the channel. The error state of each channel is stored in an error state bit register. An overall error counter exists in the data channel DWORD. Whenever an error occurs on any channel of the DWORD byte, this counter increments and is recorded in the corresponding register. It stops incrementing when it reaches its maximum value.

[0064] The test apparatus disclosed in this embodiment for multi-channel high-speed low-latency interconnect interfaces on silicon dielectric layers, by setting up multiple test ports for functional testing, asynchronous bypass ports for accessing the channel input / output ports of the physical layer of the interconnect interface, a built-in self-test engine for implementing built-in self-test, redundant data channels for remapping and repairing damaged data channels, and a counter for latency testing, embeds the testing and repair logic in the physical layer and the link layer, which can realize the testing and rapid screening of samples and ensure the performance of samples.

[0065] In one embodiment, a testing method for a multi-channel high-speed, low-latency interconnect interface for silicon dielectric layers is provided, including testing the data channels in the interconnect interface, testing the delay chain function and linearity inside the interconnect interface, and testing the data eye quality output by the interconnect interface.

[0066] The high-speed low-latency interconnect interface uses IEEE 1500 instructions to identify and repair damaged data channels. The interconnect interface can perform all repair and remapping functions on its own, repairing the hardware channels built into the high-speed low-latency interconnect interface, and automatically performing most data channel repair operations without the need for external control logic.

[0067] In the testing and repair of the data channel DWORD, redundant data channels are designed in the data channel. These redundant data channels are used to repair other data channels and can increase data throughput in the event of a short circuit or open circuit at the micro-bump or damage to the data path.

[0068] During data channel repair, if the damaged channel has been remapped and repaired, once the data channel in the high-speed low-latency interconnect interface has been identified and remapped, relevant information needs to be programmed into the CCB registers. Therefore, the CCB can optionally reroute to the required redundant data channel. For identified damaged pins, the high-speed low-latency interconnect interface makes them all tri-state outputs.

[0069] This embodiment utilizes a control state machine for data channel repair and independent data channel testing, repair, and remapping mechanisms. The main control FSM (finite-state machine) is responsible for the sequence of each data channel repair step, and each BIST engine has a state machine and AND / OR logic to execute data channel testing, analysis, repair, and remapping algorithms.

[0070] The data channel repair and remapping function provided in this embodiment is used to test, analyze, and repair the data channels inside a damaged high-speed, low-latency interconnect interface, such as... Figure 4 The flowchart shown in one embodiment illustrates a test method for a high-speed, low-latency interconnect interface for silicon dielectric layers, comprising the following steps:

[0071] Step 401: Test the data channel between the transmitter chip and the receiver chip connected by the interconnect interface.

[0072] The built-in self-test of the interface is used to test the data channel between the transmitter chip and the receiver chip connected by the interconnect interface.

[0073] Step 402: Test the data channel inside the physical layer of the interconnect interface.

[0074] The data channels inside the physical layer of the interconnect interface are tested through the built-in self-test of the physical layer loopback.

[0075] Step 403: Test the channel between the physical layer and the link layer of the interconnect interface.

[0076] The built-in self-test of the link layer loopback is used to test the channel between the physical layer and the link layer of the interconnect interface.

[0077] Step 404: Obtain the damaged data channel based on the test results.

[0078] Step 405: Remap and repair the damaged data channel.

[0079] The data channel is repaired based on the configured redundant data channels. The data channel repair is completed after all enabled data channel repairs have been performed.

[0080] Step 406: Test the delay chain functionality and linearity within the interconnect interface.

[0081] This embodiment can also test the functionality and linearity of the delay chain within the interconnect interface. The delay chain functionality and linearity test includes testing the zero latency, delay step size, maximum latency, and linearity of the actual delay chain design.

[0082] Step 407: Test the quality of the data output from the interconnect interface.

[0083] This embodiment can also train a data eye, then draw and output the acquired data eye, and analyze the quality of the data eye based on the data eye image.

[0084] In this embodiment, when repairing the data channel, the data channel repair control state machine is used to control the execution of the input / output signal line repair process. Once the high-speed low-latency interconnect interface issues a data channel repair command, the state machine controlling the data channel repair will sequentially execute the repair steps for each data channel, depending on whether special steps are enabled in the relevant configuration. These repair steps include EXTEST connectivity test, loopback BIST test, MISR high-speed test, and data channel remapping.

[0085] The MISR high-speed test is only performed if no damaged data channels are found during the EXTEST and BIST loopback phases. Built-in data channel repair must be triggered after the high-speed, low-latency interconnect interface is initialized. The completion and error conditions of each channel repair are captured by an internal status register, which allows observation of the data channel repair status.

[0086] In this embodiment, once the high-speed low-latency interconnect interface is in loopback mode, the test data pattern can be generated either on the loopback BIST engine built into the physical layer or by the link layer and software. The loopback process includes the following steps.

[0087] (A1): Initialization.

[0088] The initialization of the loopback BIST includes starting VDD, VAA, and VDDQ through an initialization process, as well as starting the clock and resetting the high-speed, low-latency interconnect interface through the initialization process.

[0089] (A2): Set the loopback frequency.

[0090] Lock the system clock of the high-speed, low-latency interconnect interface to the required loopback frequency.

[0091] (A3) Data transmission mode and verification.

[0092] Enable the loopback path on the interconnect interface and send the data pattern. Then check and verify the data pattern that has passed through the loopback path.

[0093] When a data pattern is looped back within I / O, it either precedes the PAD (physical layer core side, loopback without passing through the PAD) or follows the PAD (loopback with passing through the PAD). The loopback path uses the data transmitter used in the normal operating mode path, and for the receiving path, it uses the data receiver used in the normal operating mode. The data transmitter is denoted as TX, and the data receiver as RX. Furthermore, depending on whether it's an intra-physical layer loopback or a link-to-physical layer loopback, the data pattern can be sent and verified by the physical layer or link layer pattern generator and pattern checker in the high-speed low-latency interconnect interface.

[0094] In one embodiment, testing the zero delay, delay step size, maximum delay, and linearity of an actual delay chain design includes: exciting a self-oscillating clock using a ring oscillator; recording the number of cycles of the self-oscillating clock within a number of cycles of a plurality of known-period clocks and estimating the self-oscillating clock period; deriving the delay of the delay chain from the self-oscillating clock period; and repeatedly iteratively calculating the delay of the delay chain to obtain the zero delay, delay step size, maximum delay, and linearity of the delay chain.

[0095] This embodiment of the test apparatus for multi-channel high-speed, low-latency interconnect interfaces on silicon dielectric layers can also perform delay chain testing, performing minimum delay and linearity tests on the delay chain. Specifically, delay chain testing is used to test the change in linear time of the delay chain with delay configuration, i.e., minimum delay and delay step size. An important feature of the delay chain test logic is that it does not use a clock with a period of one UI generated by the PLL.

[0096] Typically, the delay provided by a delay chain can be represented by the delay step size and the number of delay steps as follows:

[0097] Delay chain delay = (dly_sel * stepsize) + zerodelay

[0098] Among them, the delay chain time constant zerodelay represents the minimum delay of the delay chain, while stepsize represents the delay step size of the delay chain. Both of these parameters are dependent on the fabrication process and will change with the application environment, process, temperature and voltage. The purpose of delay chain testing is to measure these two parameters. dly_sel is digitally encoded data used to represent the number of delay steps of the delay chain.

[0099] As mentioned earlier, the delay test in this embodiment requires two counters. The first counter is a down counter driven by the system clock, and the second counter is a ring oscillation counter driven by the output clock of a ring oscillator consisting of a delay chain and an inverter.

[0100] When performing delay chain testing, the period of the ring oscillator is represented as twice the delay chain delay. The goal of the delay chain linearity test in this embodiment is to test the minimum delay and linearity of the delay chain. It can be seen that the period (Tro) of the ring oscillator is linearly related to the delay chain delay steps (dly_sel), expressed as:

[0101] Tro=a*dly_sel+b

[0102] Although the period of the ring oscillator is linearly related to the delay chain delay, there is still a certain tolerance because the linearity of the delay chain is not ideal. The minimum mean method is used to fit the obtained sample set.

[0103] The runtime for testing a single delay step can be expressed as:

[0104] Running time = Ring oscillator counter count value (Nup) × Ring oscillator period (Tro)

[0105] = System clock cycle (Tclk) × Down counter count value (Ndown)

[0106] By transforming the above formula, we can obtain:

[0107] a*dly_sel+b=(Tclk×Ndown) / Nup

[0108] It can be seen that by finding the parameters a and b of the linear function, the delay step dly_sel can be calculated.

[0109] The delay steps are calculated using an iterative method. A certain degree of deviation is allowed in the sampled count values ​​of the ring oscillator counter during the calculation. One iteration of the test includes the following steps:

[0110] (B1): Initialization.

[0111] Initialize the delay step count dly_sel to zero.

[0112] Reset the count value of the ring oscillator counter and initialize the lower counter, setting its initial value.

[0113] (B2): The counter starts counting.

[0114] First, the down counter starts counting down.

[0115] After the counter is reset to zero, the value of the ring oscillator counter is recorded. When recording the value of the ring oscillator counter, the counter is sampled twice, and both sampled count values ​​are recorded.

[0116] The difference in the final value of the ring oscillator counter is caused by whether the step size of dly_sel is normalized.

[0117] (B3): Calculate the delay step based on the counter's count value.

[0118] In ps units, the stepsize_i between dly_sel = i and dly_sel = ji + 1 can be calculated using the following formula:

[0119] PeriodRO_i = System clock cycle × Next counter count value / [Ring oscillation counter count value at step i - 4] PeriodRO_j = System clock cycle × Next counter count value / [Ring oscillation counter count value at step j - 4]

[0120] stepsize_ji=(PeriodRO_j-PeriodRO_i) / 2

[0121] Because the clocks of the lower counter and the ring oscillator counter are not synchronized, there will be a certain error in the counter when calculating the final delay step. In this embodiment, the error of the delay step can be guaranteed to be within 0.1ps, which is comparable to the minimum test time that can be met, and has high accuracy.

[0122] In one embodiment, testing the data eye quality output by the interconnect interface includes: adjusting the reference voltage to test the data eye width under different reference voltages, thereby obtaining a two-dimensional data eye diagram output by the interconnect interface.

[0123] This embodiment of the test apparatus for multi-channel high-speed, low-latency interconnect interfaces on silicon dielectric layers can also perform two-dimensional data eye scanning. Two-dimensional data eye scanning can be performed automatically based on built-in training. The data eye training includes status registers for recording the eye width, which indicate the positions of the left and right edges of the eye. Through two-dimensional data eye scanning, the quality of the data eye can be intuitively obtained.

[0124] For example, the two-dimensional data eye scanning in this embodiment includes the following steps:

[0125] (C1): Set the initial voltage value.

[0126] (C2): Set the test reference voltage and perform a two-dimensional data eye scan under the test voltage.

[0127] Set the test voltage starting from the initial value.

[0128] Training of the data eye is triggered under the test voltage. The status register inside the interconnect interface is polled to wait for the training to complete, and the scan data eye signal is read after the data eye training is completed. There are no restrictions on the specific data eye training method. It can be achieved by setting a delay value during sampling to repeatedly acquire data and then identifying the data eye based on the sampling area. Other methods can also be used to train the data eye. This embodiment does not limit the training method of the data eye.

[0129] By reading the register, we can check whether training errors have occurred and the left and right boundaries of the data eye to ensure that the complete data eye signal is obtained.

[0130] After the two-dimensional data eye scan at the current voltage is completed, if the test voltage has not yet reached the maximum voltage, the test voltage is increased to perform another data eye training, and the data eye is read after the training is completed.

[0131] (C3): Analyze and plot the data eye.

[0132] All read data eye signals can be output by plotting. The data eye quality is then analyzed based on the obtained data eye diagram.

[0133] In this embodiment, the two-dimensional data eye scan can depict data eyes that pass through the PHY-DRAM interface, or data eyes that only pass through the internal loopback path of the physical layer PHY.

[0134] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0135] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0136] It should also be understood that the terms “including / comprise” or “have” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A test apparatus for high-speed, low-latency interconnect interfaces on silicon dielectric layers, characterized in that, The interconnect interface is used to connect the transmitter chip and the receiver chip, and includes a link layer and a physical layer. The device includes: The standard test port is located at the physical layer of the interconnect interface and is used to exchange standard test commands; Asynchronous bypass port, used for direct access to the I / O port of the physical layer of the interconnect interface; The built-in self-test engine is used to implement loopback testing and data verification between different layers, including interface BIST and loopback BIST. The physical layer interface BIST uses commands from the built-in test architecture to test and train the interface between the transmitter and receiver chips. The physical layer loopback BIST is used to test the internal path of the physical layer. The internal logic of the physical layer generates data patterns and drives and receives data through I / O ports. The link layer loopback BIST is used to test the channel between the link layer and the physical layer. Data generation and data comparison during channel testing are completed by the link layer. Redundant data channels are used to repair damaged data channels; Delay chain test circuit, used to test the functionality and linearity of delay chains.

2. The apparatus according to claim 1, characterized in that, The standard test port is located at the physical layer of the interconnect interface and is used to exchange standard test commands, including: Serial test input port and serial test output port.

3. The apparatus according to claim 1, characterized in that, The asynchronous bypass port is located in the interconnect interface and is used for direct access to the I / O port of the interconnect interface from within the core.

4. A test method for high-speed, low-latency interconnect interfaces on silicon dielectric layers, characterized in that, The testing method is implemented by the testing apparatus according to any one of claims 1-3, and the testing method includes: The built-in self-test is used to test the data channel between the transmitter chip and the receiver chip connected by the interconnect interface. The data channels inside the physical layer of the interconnect interface are tested using a built-in self-test. The built-in self-test is used to test the channel between the physical layer and the link layer of the interconnect interface; The damaged data channel was identified based on the test results. Remap and repair the damaged data channel; Test the delay chain functionality and linearity within the interconnect interface; Test the quality of the data output from the interconnect interface.

5. The method according to claim 4, characterized in that, The test of the delay chain functionality and linearity within the interconnect interface includes: Test the zero latency, delay step size, maximum latency, and linearity of the actual delay chain design.

6. The method according to claim 5, characterized in that, The test of the actual delay chain design includes zero latency, delay step size, maximum latency, and linearity, including: A self-excited oscillating clock is generated by a ring oscillator; Record the number of cycles of the self-excited oscillation clock within the number of cycles of multiple known clock cycles and estimate the period of the self-excited oscillation clock; The delay of the delay chain is obtained through the self-excited oscillation clock period; The delay of the delay chain is repeatedly iterated to obtain the zero delay, delay step size, maximum delay, and linearity of the delay chain.

7. The method according to claim 6, characterized in that, The ring oscillator is constructed using a delay chain and an inverter.

8. The method according to claim 4, characterized in that, The test of the data quality output by the interconnect interface includes: By adjusting the reference voltage, the data eye width under different reference voltages is tested, and the two-dimensional data eye diagram output by the interconnect interface is obtained.

Images