Circuit arrangement and display device

Abstract

The present application provides a circuit device and a display device. The circuit device includes: a color reduction circuit that performs color reduction processing from input image data of which pixel data is m bits to color-reduced image data of which pixel data is n bits, and performs error diffusion processing to a spatial direction or a temporal direction in the color reduction processing; a storage circuit that stores the color-reduced image data; and an image conversion circuit that outputs output image data by performing image conversion processing as at least one of mapping processing or scaling processing on the color-reduced image data stored in the storage circuit, in which interpolation processing of generating pixel data of the output image data from a plurality of pixel data of the color-reduced image data is performed.

Description

Technical Field

[0001] This invention relates to circuit devices and display devices, etc. Background Technology

[0002] Patent Document 1 discloses a display device comprising: a pseudo-grayscale processing unit that reduces the RGB components of display data from 6 bits to 3-5 bits; a frame memory that stores the reduced display data; a grayscale correction unit that uses a bit transformation table to multiply the RGB components of the reduced display data stored in the frame memory to 6 bits; and a driving unit that uses the multiplyed display data to drive the display device.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2002-221950

[0004] In Patent Document 1, after subtracting the display data and storing it in the frame memory, a bit transformation table is simply used to restore the subtracted display data to its original bit depth. Therefore, the image quality is simply reduced in proportion to the number of bits of display data reduced during subtraction. Summary of the Invention

[0005] One aspect of this disclosure relates to a circuit apparatus comprising: a subtraction circuit that performs subtraction processing from input image data with m-bit pixel data to subtracted image data with n-bit pixel data, and performs error diffusion processing in the subtraction processing in a spatial or temporal direction, wherein m is an integer greater than or equal to 2, and n is an integer greater than or equal to 1 and less than m; a storage circuit that stores the subtracted image data; and an image transformation circuit that performs image transformation processing on the subtracted image data stored in the storage circuit as at least one of a mapping process and a scaling process to output output image data, wherein the image transformation processing includes interpolation processing to generate pixel data of the output image data based on multiple pixel data of the subtracted image data.

[0006] Furthermore, other aspects of this disclosure relate to a display device comprising: the circuitry described above; and an image display unit that displays an image based on the output image data. Attached Figure Description

[0007] Figure 1 This is an example of the structure of a display device and a circuit device.

[0008] Figure 2 This is the first detailed structural example of a display device and circuit device.

[0009] Figure 3 This is an illustration of error propagation processing in the spatial direction.

[0010] Figure 4 This is an illustration of FRC as an example of error diffusion processing in the time direction.

[0011] Figure 5 This is a detailed structural example of a distortion correction circuit.

[0012] Figure 6 This is a diagram illustrating the operation of the distortion correction circuit.

[0013] Figure 7 This is an explanatory diagram of the interpolation process in the first detailed structural example.

[0014] Figure 8 These are examples of images before and after distortion correction.

[0015] Figure 9 This is the second detailed structural example of a display device and circuit device.

[0016] Figure 10 This is the first example of interpolation processing in the second detailed structural example.

[0017] Figure 11 This is the second example of interpolation processing in the second detailed structural example.

[0018] Figure 12 This is the third detailed structural example of a display device and circuit device.

[0019] Label Explanation

[0020] 50: Display device; 100: Circuit device; 105: Input circuit; 110: Distortion correction circuit; 112: Coordinate counter; 113: Coordinate transformation circuit; 114: Interpolation circuit; 115: Storage circuit; 130: Output circuit; 140: Color subtraction circuit; 150: Image transformation circuit; 160: Color space transformation circuit; 200: Processing device; 300: Image display unit; 350: HUD; GZB: Reference coordinates; GZC: Pixel coordinates; IMA: Input image data; IMB: Subtracted image data; IMC: Output image data; IMD: Image data; P1~P16: Pixel data; PXD: Pixel data. Detailed Implementation

[0021] The preferred embodiments of this disclosure will now be described in detail. Furthermore, the embodiments described below are not intended to unduly limit the scope of the claims, and not all structures described in these embodiments are necessarily essential structural elements.

[0022] 1. Display device and circuit device

[0023] Figure 1The diagram shows a structural example of the display device 50 and circuit device 100 in this embodiment. The display device 50 includes the circuit device 100, the processing device 200, and the image display unit 300. As an example, the display device 50 is a head-up display device or a display installed on the dashboard of an automobile.

[0024] The processing device 200 sends the input image data IMA to the circuit device 100. The pixel data of each pixel in the input image data IMA is 30 bits. Specifically, the pixel data is 30-bit color data with 10 bits of R color data, 10 bits of G color data, and 10 bits of B color data. The processing device 200 is a so-called SoC, such as a CPU or a processor in a microcomputer. SoC is an abbreviation for System on Chip. CPU is an abbreviation for Central Processing Unit.

[0025] The circuit device 100 includes an input circuit 105, a color subtraction circuit 140, a storage circuit 115, an image transformation circuit 150, and an output circuit 130. The circuit device 100 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate.

[0026] Input circuit 105 receives input image data (IMA) from processing device 200. Input circuit 105 can be a receiver circuit for various communication interfaces; for example, it could be a receiver circuit for LVDS, DVI, a display port, GMSL, or GVIF. LVDS is an abbreviation for Low Voltage Differential Signaling, DVI for Digital Visual Interface, GMSL for Gigabit Multimedia Serial Link, and GVIF for Gigabit Video Interface.

[0027] The color subtraction circuit 140 subtracts the pixel data of each pixel in the input image data IMA from 30 bits to 24 bits, and outputs the result as the subtracted image data IMB. Specifically, the color subtraction circuit 140 subtracts the color data of each color from 10 bits to 8 bits. The pixel data of each pixel in the subtracted image data IMB becomes 24-bit color data with 8 bits of R color data, 8 bits of G color data, and 8 bits of B color data.

[0028] Furthermore, the subtraction circuit 140 performs spatial or temporal error diffusion processing during the subtraction process. Error diffusion processing diffuses the error between the 30-bit pixel data before subtraction and the 24-bit pixel data after subtraction. When the subtracted image is viewed evenly within the range where the error has been diffused, it exhibits colors comparable to those before subtraction. Spatial error diffusion processing diffuses the subtraction error in a pixel to the pixel data of surrounding pixels. Temporal error diffusion diffuses the subtraction error of pixels in a frame to the pixel data of pixels in subsequent frames.

[0029] Storage circuit 115 temporarily stores the subtracted image data IMB, functioning as a buffer for image transformation processing performed by image transformation circuit 150. Storage circuit 115 is, for example, a line buffer. Image transformation processing involves the movement of pixel positions, but a line buffer with a number of lines greater than the maximum vertical movement of pixel positions is used. Alternatively, storage circuit 115 can also be a frame buffer that buffers one frame of subtracted image data IMB.

[0030] Image transformation circuit 150 performs image transformation processing on the subtracted color image data IMB, outputting the result as output image data IMC. Image transformation processing deforms or enlarges / reduces the image through coordinate transformation; specifically, it includes mapping processing, scaling processing, or a combination of these. Mapping processing transforms the image based on any mapping between the coordinates on the subtracted color image data IMB and the coordinates on the output image data IMC. Scaling processing enlarges or reduces the image based on a reference point on the image.

[0031] Furthermore, the image transformation circuit 150 performs interpolation processing during image transformation to generate pixel data for the output image data IMC based on multiple pixel data of the subtracted image data IMB. Each pixel in the output image data IMC is 30 bits. That is, in the interpolation processing, the image transformation circuit 150 calculates 10 bits of R-color data for the output image data IMC based on the 8 bits of R-color data of the subtracted image data IMB, calculates 10 bits of G-color data for the output image data IMC based on the 8 bits of G-color data of the subtracted image data IMB, and calculates 10 bits of B-color data for the output image data IMC based on the 8 bits of B-color data of the subtracted image data IMB. Additionally, as in... Figure 9 As described later, the image transformation circuit 150 can also output 24-bit output image data (IMC) for each pixel.

[0032] The output circuit 130 sends the output image data IMC to the image display unit 300. The output circuit 130 can be a transmitting circuit of various communication interfaces, such as LVDS, DVI, display port, GMSL or GVIF, etc.

[0033] The image display unit 300 displays an image based on the output image data IMC. Specifically, the image display unit 300 includes: a display panel; a display controller that controls the display timing; and a display driver that drives the display panel to display an image by means of the output image data IMC and a timing control signal from the display controller. The display panel may be a liquid crystal display panel or a self-emissive display panel, etc. However, the structure of the image display unit 300 is not limited to this; for example, it may also be... Figure 2 The HUD 350 will be discussed later.

[0034] Furthermore, while the above assumes the input image data IMA and output image data IMC are 30-bit color and the subtractive image data IMB is 24-bit color, this is not a limitation. When m is an integer greater than or equal to 2 and n is an integer greater than or equal to 1 but less than m, the input image data IMA and output image data IMC can be m-bit color, and the subtractive image data IMB can be n-bit color. As an example, the input image data IMA and output image data IMC could also be 24-bit color, and the subtractive image data IMB 18-bit color.

[0035] In this embodiment described above, the circuit device 100 includes a color subtraction circuit 140, a storage circuit 115, and an image transformation circuit 150. The color subtraction circuit 140 performs color subtraction processing from input image data IMA with m-bit pixel data to subtracted image data IMB with n-bit pixel data, and performs error diffusion processing in the spatial or temporal directions during the color subtraction process. The storage circuit 115 stores the subtracted image data IMB. The image transformation circuit 150 performs image transformation processing on the subtracted image data IMB stored in the storage circuit 115 and outputs output image data IMC, performing interpolation processing in this image transformation process. The image transformation process is at least one of mapping processing or scaling processing. The interpolation processing is the process of generating pixel data for the output image data IMC based on multiple pixel data of the subtracted image data IMB.

[0036] According to this embodiment, the input image data IMA is stored in the storage circuit 115 after color subtraction. Therefore, compared with the case where the input image data IMA is directly stored in the storage circuit 115, the storage capacity is reduced by (1-24 / 30)×100%=20%. As a result, the circuit device 100 can be reduced in cost.

[0037] Furthermore, by performing error diffusion processing in the spatial or temporal directions during color subtraction, and averaging the range of the diffused error, grayscale information equivalent to 30 bits of color is preserved, and the image data is subtracted to 24 bits of color. Then, by performing image transformation processing on this 24-bit color subtracted image data IMB, the pixel data is averaged in the spatial direction, thus obtaining output image data IMC with a smoother grayscale than the subtracted image data IMB. Specifically, the mapping or scaling processing as image transformation is accompanied by coordinate transformation, but in this coordinate transformation, there are cases where the coordinates of the transformation destination are inconsistent with the pixel raster. The pixel data of such pixels is interpolated based on the pixel data of surrounding pixels, and the pixel data is averaged in this interpolation process. By averaging the pixel data, the grayscale becomes smoother, and an improvement in image quality can be expected.

[0038] Furthermore, in the aforementioned Patent Document 1, a method is described in which display data is subtracted in color and stored in a frame memory, and then the bit depth is restored. However, neither the subtracted display data stored in the frame memory is disclosed or instructed to undergo image transformation processing, nor is interpolation processing performed in the image transformation processing.

[0039] 2. Detailed structural example 1

[0040] The following explanation will be based on the case where the display device 50 is a head-up display device and the image conversion circuit 150 is a distortion correction circuit 110.

[0041] Figure 2 A first detailed structural example of the display device 50 and circuit device 100 is shown. The display device 50 includes a processing device 200, a circuit device 100, and a HUD 350. HUD is short for Head-Up Display. Additionally, regarding... Figure 1 The parts with the same structure as the example are omitted.

[0042] The HUD 350 displays a virtual image in the user's field of vision based on the output image data IMC received from the circuit device 100. The HUD 350 includes a display controller, a display driver, a display panel, and a projection optics system. The display panel may be a liquid crystal display panel or an OLED display panel, etc. OLED is an abbreviation for Organic Light Emitting Diode. The projection optics system includes lenses or reflectors, etc., that project the image displayed on the display panel onto a screen. The screen can be any transparent object with a projection surface that reflects the projected light. For example, the screen may be the windshield of a movable body carrying the display device 50.

[0043] Furthermore, the structure of the HUD 350 is not limited to the structure described above. For example, the HUD 350 may replace the display panel and projection optics system by including a laser source, a reflector that reflects the laser, and an actuator that drives the reflector in a scanning laser manner. Alternatively, the HUD 350 may replace the display panel and projection optics system by including a laser source and a digital mirror device. The digital mirror device includes an array of micromirrors and an actuator that drives each micromirror.

[0044] The circuit device 100 includes an input circuit 105, a color reduction circuit 140, a storage circuit 115, a distortion correction circuit 110, and an output circuit 130. The distortion correction circuit 110 is... Figure 1 An example of an image transformation circuit 150.

[0045] A detailed example illustrating the error diffusion processing performed by the subtractive color circuit 140. Figure 3 A diagram illustrating the error propagation process in spatial orientation.

[0046] The subtraction circuit 140 selects the target pixel from the input image data IMA and performs subtraction processing on the pixel data of that pixel. Here, it is assumed that pixels are selected sequentially using a so-called raster scan method. Figure 3 In the image, the pixel being processed is represented by a shaded line, and its surrounding 3×3 pixels are shown. The subtraction circuit 140 adds the error propagated from the surrounding pixels to the 30-bit color pixel data, subtracts the added 30-bit color pixel data from the original 30-bit color pixel data, and sets the difference as the error data Δr. When the coordinates of the pixel being processed are set to (Xs, Ys), the subtraction circuit 140 propagates Δr×C1 towards the pixel at (Xs+1, Ys). Similarly, the subtraction circuit 140 propagates Δr×C2, Δr×C3, and Δr×C4 towards the pixels at (Xs-1, Ys+1) and (Xs, Ys+1). C1 to C4 are coefficients, and C1+C2+C3+C4=1. Through this spatial error propagation, the subtracted image data IMB includes information equivalent to the original 30-bit color.

[0047] Figure 4 An explanatory diagram of FRC (Frame Rate Control) is shown as an example of error diffusion processing in the temporal direction. FRC is an abbreviation for Frame Rate Control. The input image data IMA before FRC and the subtracted image data IMB after FRC have the same frame rate. Here, R-color data is used as an example, but the same processing is performed on G-color data and B-color data.

[0048] Figure 4The 4×4 pixels after FRC are shown. First, let's focus on the top left pixel. The high 8 bits of the 10-bit R-color data of the input image data IMA are set to R, and the low 2 bits are set to error data. Here, the error is set to 0.25. The subtractive circuit 140 sets the R-color data in the subtracted image data IMB to R+1 in frame F1, and to R in frames F2, F3, and F4. The average of the R-color data in frames F1 to F4 is R+0.25, and the subtractive image data IMB includes information equivalent to 30 bits of color before subtraction.

[0049] The error also propagates temporally for other pixels, but the timing of propagation differs among adjacent pixels. For example, in frames F1, F2, F3, and F4, the top-left pixel becomes R+1, R, R, R, while the adjacent pixel to its right becomes R, R, R+1, R, with the timing of R+1 differing. Furthermore, as a result, the average value for 4×4 pixels in each frame is R+0.25. This can also be interpreted as the error propagating spatially when viewed frame by frame, including information equivalent to the 30 bits of color before subtraction.

[0050] Furthermore, this example illustrates the case with an error of 0.25, but in the case of an error of 0.5 or 0.75, FRC is also performed with different timings, where the average of 4 frames is 0.5 or 0.75 and the spread occurs in adjacent pixels.

[0051] Next, the distortion correction circuit 110 will be described. The distortion correction circuit 110 performs distortion correction on the subtractive image data IMB using a coordinate transformation between the pixel coordinates in the subtractive image data IMB and the pixel coordinates in the output image data IMC, and outputs the result as the output image data IMC. Distortion correction refers to image correction for HUD display that achieves distortion-free or reduced distortion by applying an image distortion opposite to that experienced when the image is projected from the HUD350. Image distortion is caused by the HUD's optical system. Image distortion caused by the optical system includes image distortion caused by the curvature of the screen, image distortion caused by the HUD's projection optical system, or both.

[0052] Figure 5 A detailed structural example of the distortion correction circuit 110 is shown. The distortion correction circuit 110 includes a coordinate counter 112, a coordinate transformation circuit 113, and an interpolation circuit 114. Figure 6 This diagram illustrates the operation of the distortion correction circuit 110. Here, the distortion correction circuit 110 is described as an example of a reverse warp engine.

[0053] Coordinate counter 112 outputs the pixel coordinates GZC = (x, y) on the output image data IMC. Coordinate transformation circuit 113 transforms the pixel coordinates (x, y) into the coordinates GZB = (u, v) on the subtractive image data IMB. Specifically, coordinate transformation circuit 113 uses a polynomial or table to establish a correspondence between the pixel coordinates (x, y) and the reference coordinates (u, v) for coordinate transformation. Coordinate transformation circuit 113 transforms the reference coordinates (u, v) into the read addresses of multiple surrounding pixels. Storage circuit 115 outputs multiple pixel data PXDs from these read addresses. Interpolation circuit 114 performs interpolation processing on the read multiple pixel data to obtain the pixel data of pixel coordinates (x, y) in the output image data IMC.

[0054] exist Figure 6 The diagram illustrates an example of reading out the pixel data P1 to P16 of the surrounding 4×4 pixels at reference coordinates (u, v). When u and v are integer values, the reference coordinates (u, v) correspond to the pixel grid of the subtractive image data IMB; however, u and v are real values ​​and are not limited to integer values. That is, the reference coordinates (u, v) do not necessarily correspond to the pixel grid of the subtractive image data IMB. The interpolation circuit 114 calculates the pixel data at reference coordinates (u, v) by interpolating the 4×4 pixel data P1 to P16, and uses it as the pixel data at pixel coordinates (x, y) in the output image data IMC.

[0055] Figure 7 A diagram illustrating the interpolation process in the first detailed structural example is shown. The pixel data P1 to P16 read from the storage circuit 115 are 24-bit color. The interpolation circuit 114 performs interpolation with 30-bit operations to calculate the 30-bit color pixel data PC(x, y) from the 24-bit color pixel data P1 to P16. Specifically, the 30-bit operation refers to performing 10-bit operations on each color data. Figure 7 The middle section shows the mathematical formula for the interpolation process. PC(x, y) is the pixel data at pixel coordinates (x, y) in the output image data IMC. αi(u, v) are the interpolation coefficients, set according to the reference coordinates (u, v). α1 + α2 + ... + α16 = 4. Furthermore, when α1 to α16 are considered as 4×4 matrices corresponding to P1 to P16, the sum of each row is 1, and the sum of each column is 1. The interpolation process is, for example, bilinear interpolation, but is not limited to this; it can also be bicubic interpolation, etc.

[0056] Figure 8 Examples of images before and after distortion correction are shown. Here, an example is shown where an 8-bit black and white input image is subtracted to 1-bit black and white, and then restored to 8-bit black and white through distortion correction.

[0057] The left image shows a portion of the subtracted image after spatial error diffusion has been applied. The original 8-bit black and white image was a gradient image that increased in density from the upper left to the lower right of the region. Subtraction binarizes the image, but the gradient information is reflected through spatial error diffusion. That is, the density of black pixels increases from the upper left to the lower right of the region.

[0058] The right image is a region cropped from the distortion-corrected image that corresponds to the left image. However, because the rectangular region in the left image is moved to a distorted rhombus or similar region after distortion correction, the left and right images represent roughly the same portion, but not exactly the same portion. In distortion correction, an 8-bit black and white image is generated from a 1-bit black and white image, but at this time, pixel data is averaged in the spatial direction through interpolation. This allows for a distortion-corrected image that improves gradation while inheriting the error diffusion effect included in the subtractive image. Furthermore, as in... Figure 4 As explained in the text, FRC also includes spatial direction error propagation, thereby achieving the same effect as described above.

[0059] As described above, by performing distortion correction after color reduction, the storage capacity of the line buffer or frame memory can be saved, and output image data with improved gradation compared to the case of simple color reduction can be obtained.

[0060] In this embodiment described above, the image transformation circuit 150 is a distortion correction circuit 110. During the mapping process, the distortion correction circuit 110 transforms the pixel coordinates (x, y) on the output image data IMC into reference coordinates (u, v) on the subtracted image data IMB. Based on the surrounding pixel data P1 to P16 of the reference coordinates (u, v) in the subtracted image data IMB, the distortion correction circuit 110 generates pixel data PC(x, y) of the pixel coordinates (x, y) in the output image data IMC.

[0061] In the mapping process, the reference coordinates (u, v) are not necessarily consistent with the pixel grid of the subtractive image data IMB, so interpolation based on the surrounding pixel data is necessary. Through this interpolation process, the pixel data is averaged in the spatial direction, thus achieving the effect of inheriting the error diffusion included in the subtractive image and improving the gradation of the output image data IMC.

[0062] Furthermore, in this embodiment, the distortion correction circuit 110 performs distortion correction processing on the subtractive image data IMB using the mapping process described above. The distortion correction processing is based on the output image data IMC to correct image distortion caused by the optical system of the HUD 350 that projects the image onto the projection surface.

[0063] According to this embodiment, in the distortion correction process, image distortion is applied to the image that is opposite to the image distortion when the image is projected from the HUD 350. Therefore, by applying image distortion correction to the image, the image distortion during projection is eliminated, resulting in a HUD display with no distortion or reduced distortion.

[0064] In addition, in this embodiment, the subtraction circuit 140 performs error diffusion processing in the spatial direction. The distortion correction circuit 110 generates output image data IMC with m-bit pixel data through interpolation processing.

[0065] According to this embodiment, the input image data IMA of m-bit color is subtracted to the subtracted image data IMB of n-bit color and then stored in the storage circuit 115. Interpolation processing is then used to generate the output image data IMC of m-bit color based on the subtracted image data IMB of n-bit color. For example, in... Figure 8 As explained, by interpolation, the image data is converted from n-bit color to m-bit color, thereby inheriting the error diffusion effect of the subtractive image data IMB and improving the gradation of the output image data IMC.

[0066] Furthermore, in this embodiment, the color subtraction circuit 140 can also perform frame rate control processing as an error diffusion process in the time direction. The distortion correction circuit 110 can also generate output image data IMC with m-bit pixel data through interpolation processing.

[0067] As in Figure 4 As explained, in FRC, errors spread not only in the temporal direction but also in the spatial direction, resulting in FRC image data containing information equivalent to the m-bit color before subtraction. Therefore, by using interpolation to convert n-bit color multi-grayscale to m-bit color, it is possible to obtain output image data IMC that inherits the error spread contained in the subtractive image data IMB and improves gradation.

[0068] In addition, in this embodiment, the storage circuit 115 is a row buffer that stores multiple rows of image data of the subtracted image data IMB, or a frame memory that stores frame image data of the subtracted image data IMB.

[0069] Since both the line buffer and frame memory are image memories, they have a large storage capacity. For example, if the pixel data of the input image data IMA increases from 24 bits to 30 bits, a 1.25-fold increase in storage capacity is required. However, according to this embodiment, since the color is reduced to 24 bits, the storage capacity does not increase. Alternatively, even if the pixel data of the input image data IMA remains unchanged at 24 bits, storage capacity can be saved, for example, by reducing the color to 18 bits.

[0070] 3. Detailed structural example 2

[0071] Figure 9 The diagram shows a second detailed structural example of the display device 50 and the circuit device 100. In this second detailed structural example, the distortion correction circuit 110 outputs 24-bit color output image data (IMC). Additionally, for... Figure 1 or Figure 2 The parts with the same structure as the example are omitted.

[0072] Figure 10 The first example of interpolation processing in the second detailed structural example is shown. Interpolation circuit 114 performs interpolation processing using 30-bit operations, similar to the first detailed structural example, to obtain 30-bit color pixel data PC(x, y). Interpolation circuit 114 removes the lower 2 bits from each of the 10-bit color data of pixel data PC(x, y) to obtain 24-bit color pixel data. Distortion correction circuit 110 outputs this 24-bit color pixel data as the pixel data of output image data IMC.

[0073] Figure 11 This illustrates the second example of interpolation processing in the second detailed structural example. The interpolation circuit 114 calculates the sum of pixel data Pi and interpolation coefficients αi using 30-bit arithmetic, and divides this 30-bit sum by 16 to obtain the 24-bit color pixel data PC(x, y). Since α1 + α2 + ... + α16 = 4, dividing the sum by 16 is equivalent to dividing each color data by 4, reducing the 10-bit color data to 8 bits. The distortion correction circuit 110 outputs the 24-bit color pixel data PC(x, y) as the pixel data of the output image data IMC.

[0074] In this embodiment, the color is the same 24-bit before and after distortion correction, but it is reduced to 24 bits after interpolation using 30-bit operations during distortion correction. Therefore, the timing of the 30-bit operation, such as when... Figure 8 As explained, a distortion-corrected image is obtained by inheriting the error diffusion effect included in the subtractive image and improving gradation. Furthermore, by subtracting the image to 24-bit color, the error diffusion effect included in the subtractive image is appropriately reflected in the distortion-corrected image, resulting in distortion-corrected output image data IMC that includes grayscale information equivalent to 30 bits of color.

[0075] 4. Detailed structural example of the third section

[0076] Figure 12 The diagram shows a third detailed structural example of the display device 50 and the circuit device 100. In this third detailed structural example, the circuit device 100 further includes a color space conversion circuit 160. Additionally, regarding... Figure 1 or Figure 2The parts with the same structure as the example are omitted.

[0077] The processing device 200 sends 24-bit color image data IMD to the circuit device 100. The input circuit 105 receives the image data IMD from the processing device 200.

[0078] The color space transformation circuit 160 transforms the 24-bit color image data IMD to output 30-bit color input image data IMA. Specifically, the image data IMD represents colors in a specified color space. The color space transformation circuit 160 transforms the specified color space of the image data IMD to the RGB color space. For example, assuming the specified color space is YUV, the YUV components of the pixel data in the image data IMD are set as DDy, DDu, DDv, and the RGB components of the pixel data in the input image data IMA are set as DAr, DAg, DAb. The color space transformation circuit 160 calculates the pixel data (DAr, DAg, DAb) of the input image data IMA by multiplying the pixel data (DDy, DDu, DDv) of the image data IMD by a 3x3 transformation matrix representing the color space transformation.

[0079] Furthermore, the above assumes that the image data IMD is set to 24-bit color and the input image data IMA is set to 30-bit color, but this is not a limitation. Alternatively, when m is an integer greater than or equal to 2 and k is an integer greater than or equal to 1 and less than m, the image data IMD can be k-bit color and the input image data IMA can be m-bit color.

[0080] Furthermore, in this embodiment, the circuit device 100 includes a color space transformation circuit 160. The color space transformation circuit 160 generates input image data IMA with m-bit pixel data by performing color space transformation on image data IMD with k-bit pixel data.

[0081] According to this embodiment, even when image data IMD in a color space other than RGB is input to the circuit device 100, the image data IMD can be converted into image data in the RGB color space. Furthermore, by bit-expanding the pixel data from k bits to m bits during color space conversion, a smooth grayscale input image data IMA is obtained with minimal loss of grayscale in the image data IMD during color space conversion. Then, after temporarily subtracting the color from the input image data IMA and storing it in the storage circuit 115, distortion correction is performed, enabling the generation of output image data IMC containing grayscale information equivalent to that of the input image data IMA without increasing the storage capacity of the storage circuit 115.

[0082] The circuit apparatus of this embodiment described above includes a color subtraction circuit, a storage circuit, and an image transformation circuit. The color subtraction circuit performs color subtraction processing from input image data with m-bit pixel data to subtracted image data with n-bit pixel data, and performs error diffusion processing in either the spatial or temporal direction during the color subtraction process. m is an integer of 2 or more. n is an integer of 1 or more and less than m. The storage circuit stores the subtracted image data. The image transformation circuit performs at least one of mapping processing or scaling processing on the subtracted image data stored in the storage circuit, i.e., image transformation processing, and outputs output image data. In the image transformation processing, interpolation processing is performed to generate pixel data of the output image data based on multiple pixel data of the subtracted image data.

[0083] According to this embodiment, since the input image data is stored in the storage circuit after color subtraction, storage capacity can be saved compared to the case where the input image data is directly stored in the storage circuit. This reduces the cost of the circuit device. Furthermore, by performing error diffusion processing in the spatial or temporal direction during color subtraction, and averaging the range of the diffused error, grayscale information equivalent to m bits of color is maintained, and the image data is subtracted to n bits of color. Then, interpolation processing is performed in the image transformation processing of the subtracted n-bit color image data, thereby averaging the pixel data in the spatial direction. Therefore, output image data with a smoother grayscale than the subtracted image data can be obtained.

[0084] In this embodiment, the image transformation circuit can also transform the pixel coordinates on the output image data into reference coordinates on the subtracted image data during the mapping process. The image transformation circuit can also generate pixel data for the pixel coordinates in the output image data based on multiple pixel data surrounding the reference coordinates in the subtracted image data.

[0085] In the mapping process, the reference coordinates may not be consistent with the pixel grid of the subtractive image data, so interpolation based on the data of multiple surrounding pixels is necessary. Through this interpolation process, the pixel data is averaged in the spatial direction, thus obtaining output image data that inherits the error diffusion effect included in the subtractive image and improves the gradation.

[0086] Furthermore, in this embodiment, the image transformation circuit can also perform distortion correction processing on the subtracted image data through mapping processing.

[0087] Alternatively, in this embodiment, distortion correction processing can also be a process for correcting image distortion caused by the optical system of a head-up display that projects images onto a projection surface based on output image data.

[0088] According to this embodiment, in the distortion correction process, image distortion is applied to the image in the opposite manner to the image distortion when the image is projected onto the head-up display. Therefore, by applying image distortion correction to the image, the image distortion during projection is eliminated, resulting in a head-up display with no distortion or reduced distortion.

[0089] In addition, in this embodiment, the subtraction circuit can also perform error diffusion processing in the spatial direction. The image transformation circuit can also generate output image data with m-bit pixel data through interpolation processing.

[0090] According to this embodiment, m-bit color input image data is stored in a storage circuit after being subtracted to n-bit color subtracted image data. Interpolation processing is then used to generate m-bit color output image data based on the n-bit color subtracted image data. By converting n-bit color to m-bit color through interpolation, the effect of error diffusion inherent in the subtracted image data is inherited, and the gradation of the output image data is improved.

[0091] Furthermore, in this embodiment, the color subtraction circuit can also perform frame rate control processing as an error diffusion process in the time direction. The image transformation circuit can also generate output image data with m-bit pixel data through interpolation processing.

[0092] In frame rate control processing, errors spread not only in the temporal direction but also in the spatial direction. The image data after frame rate control processing includes information equivalent to m-bit color before color subtraction. Therefore, by interpolating from n-bit color to m-bit color, the effect of error spread included in the subtractive image data is inherited, and the gradation of the output image data is improved.

[0093] Furthermore, in this embodiment, the circuit device may also include a color space transformation circuit. The color space transformation circuit can also generate input image data with m-bit pixel data by performing color space transformation on image data with k-bit pixel data. k is an integer greater than or equal to 1 and less than m.

[0094] According to this embodiment, even when image data in a color space different from the color space of the output image data is input to the circuit device, the color space of the image data can be transformed to the same color space as the output image data. Furthermore, by bit-expanding the pixel data from k bits to m bits during color space transformation, smooth grayscale input image data is obtained with minimal loss of grayscale in the image data during the color space transformation. Then, after temporarily subtracting the color from the input image data and storing it in the storage circuit, distortion correction is performed. This allows output image data containing grayscale information equivalent to the grayscale information of the input image data to be obtained without increasing the storage capacity of the storage circuit.

[0095] Alternatively, in this embodiment, the storage circuit may be a row buffer that stores multiple rows of image data after color reduction, or a frame memory that stores frame image data after color reduction.

[0096] Since both the line buffer and the frame memory are image memories, they have a large storage capacity. For example, if the pixel data of the input image data increases from 24 bits to 30 bits, a 1.25-fold increase in storage capacity is required. However, according to this embodiment, the number of bits is reduced to 24, so the storage capacity does not increase. Alternatively, even if the pixel data of the input image data remains unchanged at 24 bits, storage capacity can be saved, for example, by reducing the number of bits to 18.

[0097] Furthermore, the display device of this embodiment includes a circuit device and an image display unit that displays an image based on the output image data.

[0098] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the novel aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, in the specification or drawings, a term described at least once with a broader or synonymous term can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure and operation of circuit devices, processing devices, image display units, and display devices are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit device, characterized in that, include: A color subtraction circuit performs color subtraction processing from input image data with m-bit pixel data to subtracted image data with n-bit pixel data, and performs error diffusion processing in the spatial or temporal direction during the color subtraction processing, where m is an integer greater than or equal to 2, and n is an integer greater than or equal to 1 and less than m. A storage circuit that stores the subtracted image data; as well as An image transformation circuit performs image coordinate transformation processing on the subtracted image data stored in the storage circuit, which is at least one of mapping processing and scaling processing, and transforms the position coordinates on the image to output m-bit pixel data. In the image coordinate transformation processing, the pixel coordinates on the output image data and the coordinates of the subtracted image data, i.e., the reference coordinates, are transformed. For a certain pixel coordinate on the output image data, the pixel data of the output image data is generated by interpolating multiple pixel data at multiple positions around the reference coordinate corresponding to the pixel coordinate in the subtracted image data.

2. The circuit device according to claim 1, characterized in that, In the mapping process, the image transformation circuit transforms the pixel coordinates on the output image data into reference coordinates on the subtracted image data, and generates pixel data of the pixel coordinates in the output image data based on the plurality of pixel data surrounding the reference coordinates in the subtracted image data.

3. The circuit device according to claim 1 or 2, characterized in that, The image transformation circuit performs distortion correction processing on the subtracted image data through the mapping process.

4. The circuit device according to claim 3, characterized in that, The distortion correction process is a process for correcting image distortion caused by the optical system of the head-up display, which projects the image onto a projection surface based on the output image data.

5. The circuit device according to claim 1 or 2, characterized in that, The subtractive color circuit performs the error diffusion process in the spatial direction. The image transformation circuit generates output image data with m-bit pixel data through the interpolation process.

6. The circuit device according to claim 1 or 2, characterized in that, The color reduction circuit performs frame rate control processing as an error diffusion process in the time direction. The image transformation circuit generates output image data with m-bit pixel data through the interpolation process.

7. The circuit device according to claim 1 or 2, characterized in that, The circuit device includes a color space transformation circuit, which generates the input image data with pixel data of m bits by performing color space transformation on the image data with pixel data of k bits, where k is an integer greater than or equal to 1 and less than m.

8. The circuit device according to claim 1 or 2, characterized in that, The storage circuit is either a row buffer that stores multiple rows of image data after color reduction, or a frame memory that stores frame image data after color reduction.

9. A display device, characterized in that, The display device includes: The circuit device according to any one of claims 1 to 8; and An image display unit displays an image based on the output image data.

Images