Optical module sensitivity test method and system

Abstract

The application relates to a kind of optical module sensitivity test method and system.The method comprises: converting optical signal into corresponding reference electrical signal when receiving optical signal, and attenuating and amplifying reference electrical signal to obtain attenuated and amplified electrical signal when receiving attenuation control signal, determining corresponding first sensitivity based on reference electrical signal, and determining corresponding second sensitivity based on attenuated and amplified electrical signal, since attenuated and amplified electrical signal is signal after signal attenuation processing, so attenuated and amplified electrical signal has less interference signal compared with reference electrical signal, so the precision of second sensitivity obtained based on attenuated and amplified electrical signal is higher than that of first sensitivity, the first sensitivity obtained after different signal processing, second sensitivity and preset sensitivity range are compared, so as to determine the final sensitivity test result, to improve the sensitivity test quality.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method and system for testing the sensitivity of optical modules. Background Technology

[0002] With the increasing demands of communication systems on the transmission rate and capacity of optical modules, high-capacity, high-speed optical modules have been rapidly developed. In order to better utilize optical modules, sensitivity testing is required before their application. However, the current sensitivity testing process for optical modules is affected by interference signals, resulting in poor test quality and the inability to obtain highly accurate test results. Summary of the Invention

[0003] To address the aforementioned technical problems, this application provides a method and system for testing the sensitivity of optical modules.

[0004] Firstly, this application provides a method for testing the sensitivity of an optical module, including:

[0005] When an optical signal is acquired, it is converted into a corresponding reference electrical signal;

[0006] Upon receiving the attenuation control signal, the reference electrical signal is subjected to attenuation and amplification processing to obtain an attenuated and amplified electrical signal;

[0007] A first sensitivity is determined based on the reference electrical signal, and a second sensitivity is determined based on the attenuated and amplified electrical signal.

[0008] The sensitivity test result is determined based on the comparison between the first sensitivity, the second sensitivity, and the preset sensitivity range.

[0009] Secondly, this application provides an optical module sensitivity testing system. The system includes an optical module, a bit error rate tester, a sensitivity test board, a sensitivity device, and a computer. The optical module provides an optical signal to the sensitivity test board via an optical fiber. The bit error rate tester provides a preset bit error rate value to the sensitivity test board. The sensitivity test board performs a sensitivity test on the optical signal according to the preset bit error rate value to obtain a test signal, and transmits the test signal to the computer through the sensitivity device. The computer determines the sensitivity test result based on the test signal. The test signal includes a reference electrical signal after photoelectric conversion of the optical signal and an attenuated and amplified electrical signal after attenuation and amplification processing of the reference electrical signal.

[0010] Based on the above optical module sensitivity testing method, when an optical signal is received, it is converted into a corresponding reference electrical signal. When an attenuation control signal is received, the reference electrical signal is attenuated and amplified to obtain an attenuated and amplified electrical signal. The corresponding first sensitivity is determined based on the reference electrical signal, and the corresponding second sensitivity is determined based on the attenuated and amplified electrical signal. Since the attenuated and amplified electrical signal has undergone signal attenuation processing, it has less interference signal compared to the reference electrical signal. Therefore, the second sensitivity obtained based on the attenuated and amplified electrical signal is more accurate than the first sensitivity. The first sensitivity, the second sensitivity obtained after different signal processing, and the preset sensitivity range are compared to select the best result for the final sensitivity test, thereby improving the quality of sensitivity testing. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a structural block diagram of an optical module sensitivity testing system in one embodiment;

[0014] Figure 2 This is a block diagram of the internal structure of the sensitivity test board in one embodiment;

[0015] Figure 3 This is a schematic diagram of the control circuit in one embodiment;

[0016] Figure 4 This is a block diagram of the internal structure of the sensitivity test board in one embodiment;

[0017] Figure 5 This is a schematic diagram of the structure of the first step-down sub-circuit in one embodiment;

[0018] Figure 6 This is a schematic diagram of the second step-down sub-circuit in one embodiment;

[0019] Figure 7 This is a block diagram of the internal structure of the sensitivity test board in one embodiment;

[0020] Figure 8 This is a schematic diagram of the indicator light circuit in one embodiment;

[0021] Figure 9 This is a schematic diagram of the connector circuit in one embodiment;

[0022] Figure 10 This is a schematic diagram of the connector circuit in one embodiment;

[0023] Figure 11 This is a schematic diagram of the optical device interface circuit in one embodiment;

[0024] Figure 12 This is a schematic diagram of the attenuation amplifier circuit in one embodiment;

[0025] Figure 13 This is a flowchart illustrating a method for testing the sensitivity of an optical module in one embodiment;

[0026] Figure 14 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] In one embodiment, this embodiment provides an optical module sensitivity testing system. The system includes an optical module, a bit error rate tester, a sensitivity test board, a sensitivity device, and a computer. The optical module provides an optical signal to the sensitivity test board via an optical fiber. The bit error rate tester provides a preset bit error rate value to the sensitivity test board. The sensitivity test board performs a sensitivity test on the optical signal according to the preset bit error rate value to obtain a test signal, and transmits the test signal to the computer through the sensitivity device. The computer determines the sensitivity test result based on the test signal. The test signal includes a reference electrical signal after photoelectric conversion of the optical signal and an attenuated and amplified electrical signal after attenuation and amplification processing of the reference electrical signal.

[0029] Specifically, such as Figure 1As shown, the optical module is connected to the sensitivity test board via optical fiber. The bit error rate tester and the sensitivity device (CDR) are electrically connected to the sensitivity test board. The sensitivity device establishes a communication connection with the computer device via wireless or wired connection. Wireless connection methods include Bluetooth connection, WIFI connection or NFC radio frequency connection, etc. Wired connection methods include connection via data transmission cable. In this embodiment, the sensitivity device establishes a communication connection with the computer device via USB data transmission cable.

[0030] The optical module provides an optical signal to the sensitivity test board. Testers can adjust the preset bit error rate (BER) value by debugging the bit error rate meter, allowing the sensitivity test board to perform sensitivity testing on the optical signal under the given BER value. The preset BER value can be customized according to testing requirements, and the sensitivity obtained will differ under different preset BER values. The sensitivity test board outputs a test signal indicating the sensitivity of the optical signal. This test signal includes a reference electrical signal after photoelectric conversion and an attenuated and amplified reference electrical signal. In other words, the sensitivity test board performs photoelectric conversion on the optical signal to output the corresponding reference electrical signal, and also attenuates the reference electrical signal. The amplified output signal is attenuated and amplified. The sensitivity test board transmits the test signal to the computer via a sensitivity device. The sensitivity device can also visualize the test signal, acting as an oscilloscope to display the signal, allowing testers to intuitively see the fluctuations of the reference signal and the attenuated and amplified signal. The computer analyzes the reference signal and the attenuated and amplified signal to determine the final sensitivity test result. By comparing the attenuated and amplified signal with the unattenuated and amplified reference signal, the computer can more accurately determine the sensitivity test result of the optical module, thus improving the quality of optical module sensitivity testing.

[0031] In one embodiment, the sensitivity test board includes an optical device interface circuit, an attenuation amplification circuit, a control circuit, a step-down circuit, and a connector circuit, wherein:

[0032] The step-down circuit provides the corresponding operating voltages for the control circuit and the attenuation amplifier circuit, respectively;

[0033] The optical device interface circuit converts the optical signal into a reference electrical signal and transmits it to the connector circuit and the attenuation amplification circuit.

[0034] When the attenuation amplification circuit receives an attenuation control signal from the control circuit, it performs attenuation amplification processing on the reference electrical signal to generate an attenuation amplified electrical signal, and then transmits the attenuation amplified electrical signal to the connector circuit.

[0035] The connector circuit transmits the reference electrical signal and the attenuated amplified electrical signal to the computer device through a sensitivity device.

[0036] The computer device determines the sensitivity test result based on the comparison between the first sensitivity corresponding to the reference electrical signal, the second sensitivity corresponding to the attenuated amplified signal, and the preset sensitivity range.

[0037] Specifically, such as Figure 2 As shown, the attenuation amplifier circuit is electrically connected to the optical device interface circuit, control circuit, step-down circuit, and connector circuit, respectively. The step-down circuit is also connected to the control circuit, and the optical device interface circuit is also connected to the connector circuit. The tester can directly operate the control circuit to control it to output an attenuation control signal to the attenuation amplifier circuit, or transmit operation instructions to the control circuit through computer equipment to control it to output an attenuation control signal to the attenuation amplifier circuit. The attenuation control signal is used to drive the attenuation amplifier circuit to work. When the attenuation amplifier circuit receives the attenuation control signal, it performs signal attenuation and amplification processing on the reference electrical signal transmitted by the optical device interface circuit. The attenuation amplifier circuit is prohibited from working when it does not receive the attenuation control signal. That is, the tester can start or stop the attenuation amplifier circuit through the control circuit according to the test requirements.

[0038] like Figure 3 As shown, the control circuit mainly consists of the control chip U2 and peripheral devices. The control chip can be any model with data processing and control functions; in this embodiment, the ADUC7023 chip is used to control and analyze the entire 25G optical module receiver sensitivity test board circuit. The SDA0 pin of the ADUC7023 chip is used to connect to the I2C SDA data line, and the SCL0 pin is used to connect to the I2C SCL clock line, mainly for downloading code and modulation. The SCL1 / SDA1 ports of the ADUC7023 chip are used for I2C communication with the attenuation amplifier circuit to change the internal register values ​​of the attenuation amplifier circuit. The RSI port of the ADUC7023 chip is used to monitor the voltage.

[0039] The ADUC7023 chip is a fully integrated 1MSPS, 12-bit data acquisition system that integrates a high-performance multi-channel ADC, a 16-bit / 32-bit MCU, and Flash / EE memory within a single chip. This enables the chip to perform digital diagnostics in optical transceivers and modules based on fixed and tunable frequency lasers, and ensures precise control of the optical driver and diagnostic process.

[0040] The optical device interface circuit is used to convert optical signals into corresponding reference electrical signals, that is, to perform photoelectric conversion processing on the optical signals, and then transmit the reference electrical signals to the connector circuit and the attenuation amplifier circuit respectively.

[0041] The attenuation amplifier circuit attenuates and amplifies the reference electrical signal during operation, filtering out interference signals to improve the effective accuracy of the reference signal. The attenuation amplifier circuit then transmits the attenuated and amplified electrical signal to the connector circuit.

[0042] The connector circuit transmits the reference electrical signal and the attenuation amplification electrical signal to the sensitivity device. The sensitivity device can be an oscilloscope or other device or equipment capable of displaying signals. The sensitivity device visualizes the reference electrical signal and the attenuation amplification electrical signal so that the tester can intuitively see the fluctuation of the reference electrical signal and the attenuation amplification electrical signal. The sensitivity device also synchronizes the reference electrical signal and the attenuation amplification electrical signal to the computer device, so that the computer device can determine the final sensitivity test result based on the reference electrical signal and the attenuation amplification electrical signal.

[0043] Based on the above components, it can be seen that the 25G optical module receiver sensitivity test board saves production costs by eliminating many discrete components for burst reception.

[0044] In one embodiment, such as Figure 4 As shown, the step-down circuit includes a first step-down sub-circuit and a second step-down sub-circuit. The first step-down sub-circuit converts the power supply voltage into a first operating voltage and transmits the first operating voltage to the control circuit. The second step-down sub-circuit converts the power supply voltage into a second operating voltage and transmits the second operating voltage to the attenuation amplifier circuit.

[0045] Specifically, the power supply voltage is determined by the selected power supply and can be customized according to the test scenario. In this embodiment, the power supply voltage is set to 5V, and the first step-down sub-circuit converts the 5V power supply voltage into the first working voltage. The first working voltage is the working voltage of the control circuit. Therefore, the first working voltage matches the selection of the control circuit. In this embodiment, the first working voltage is set to 3.3V, that is, the first step-down sub-circuit steps down the 5V to 3.3V.

[0046] The second step-down sub-circuit converts the 5V power supply voltage into a second operating voltage, which is the operating voltage of the attenuation amplifier circuit. Similarly, the second operating voltage is matched with the selection of the attenuation amplifier circuit. In this embodiment, the second operating voltage is set to 1.8V, that is, the second step-down sub-circuit steps down the 5V to 1.8V.

[0047] In one specific embodiment, the first buck converter sub-circuit includes a first buck converter chip, a first power supply filter circuit, a first feedback circuit, and a first high-frequency filter circuit. The first buck converter chip can be any chip with voltage conversion function; in this embodiment, the AZ1117IH-3.3TRG1 DC-DC converter IC is used as the first buck converter chip. Figure 5 As shown, the input terminal VIN of the first buck converter chip is electrically connected to the first power supply filter circuit, pin 1 of the interface sub-circuit J5, and the power supply voltage. The first power supply filter circuit includes a capacitor C34 and an electrolytic capacitor C26 connected in parallel to ground. Specifically, the first ends of capacitors C34 and C26 are electrically connected to the input terminal VIN of the first buck converter chip, and the second ends are grounded. The first power supply filter circuit filters the power supply voltage before supplying power to the first buck converter chip. A first feedback circuit and a first high-frequency filter circuit are connected in parallel between the feedback pin and the first output pin of the first buck converter chip. The first output pin of the first buck converter chip is also connected to a second output pin and outputs a first operating voltage. The first feedback circuit adjusts the output voltage of the first buck converter chip; in this embodiment, the first feedback circuit sets the output voltage to 3.3V. The first high-frequency filter circuit filters the output voltage to improve the operating voltage quality.

[0048] The first feedback circuit includes resistors R21 and R27, and capacitor C33. Resistors R21 and R27 are connected in series, while capacitor C33 is connected in parallel with resistor R21. The connection point between resistors R21 and R27 is connected to the feedback pin of the first buck converter chip, and the first end of capacitor C33 is also connected to the feedback pin of the first buck converter chip. The second end of capacitor C33 and the second end of resistor R21 are grounded, and the first end of resistor R27 is connected to the first output pin of the first buck converter chip.

[0049] The first high-frequency filter circuit consists of capacitor C27, capacitor C35, resistor R20 and light-emitting diode D3. Resistor R20 and light-emitting diode D3 are connected in series and then connected in parallel with capacitor C27 and capacitor C35. One end of the parallel connection is electrically connected to the first output terminal of the first step-down converter chip, and the other end of the parallel connection is electrically connected to the second terminal of resistor R21 in the first feedback circuit and grounded.

[0050] In one specific embodiment, the second buck converter sub-circuit includes a second buck converter chip, a second power supply filter circuit, a second feedback circuit, and a second high-frequency filter circuit. The second buck converter chip can be any chip with voltage conversion functionality; in this embodiment, the AZ1117IH-1.8TRG1 DC-DC converter IC is used as the second buck converter chip. Figure 6As shown, the connection relationships between the second buck converter chip, the second power supply filter circuit, the second feedback circuit, and the second high-frequency filter circuit are the same as those of the first buck sub-circuit. Specifically, resistors R17 and R22, and capacitor C30 form the second feedback circuit, used to set the output voltage of the second buck sub-circuit to 1.8V. Capacitors C29 and C32, and resistor R16 form the second high-frequency filter circuit, which is used to filter the output voltage to improve the operating voltage quality.

[0051] In one embodiment, such as Figure 7 As shown, the sensitivity test board also includes an indicator light circuit, which is electrically connected to the attenuation amplifier circuit. The indicator light circuit determines the corresponding indicator light state based on the attenuation amplifier circuit's reception state of the attenuation control signal.

[0052] Specifically, the indicator light circuit displays the operating status of the attenuation amplifier circuit, allowing testers to visually observe its operation. The indicator light status is determined based on the attenuation amplifier circuit's reception of the attenuation control signal. When the attenuation amplifier circuit receives the attenuation control signal (i.e., the signal has been received), the indicator light indicates that the attenuation amplifier circuit is in the operating state. When the attenuation amplifier circuit does not receive the attenuation control signal (i.e., the signal has not been received), the indicator light indicates that the attenuation amplifier circuit is in the off state.

[0053] In one embodiment, the indicator light circuit is in an indicator light state when the attenuation amplifier circuit receives the attenuation control signal, and the indicator light circuit is in an off state when the attenuation amplifier circuit does not receive the attenuation control signal.

[0054] Specifically, when the attenuation amplifier circuit receives the attenuation control signal, it transmits a low-level signal to the indicator light circuit, thereby setting the indicator light to the display state; when the attenuation amplifier circuit does not receive the attenuation control signal, it transmits a high-level signal to the indicator light circuit, thereby setting the indicator light to the off state.

[0055] In one specific embodiment, the indicator light circuit includes resistors R13, R14, and R15, a light-emitting diode D2, and a field-effect transistor Q1. The field-effect transistor can be any type of MOSFET; in this embodiment, an SI2312BDS-T1-GE3 MOSFET is selected as the field-effect transistor Q1. Figure 8As shown, the first end of resistor R14 and the first end of resistor R15 are electrically connected to the output terminal of the first step-down sub-circuit. The second end of resistor R14 and the first end of resistor R13 are electrically connected to the attenuation amplifier circuit. The second end of resistor R15 is electrically connected to the drain of the field-effect transistor via LED D2. The gate of the field-effect transistor is electrically connected to the second end of resistor R13. The source of the field-effect transistor is grounded.

[0056] The field-effect transistor can be any type of MOSFET. In this embodiment, the SI2312BDS-T1-GE3 MOSFET is selected. It is mainly used to determine the working status of the indicator light. When a high-level signal is received, the field-effect transistor is in the cutoff state, so the LED is not lit; when the field-effect transistor receives a low-level signal, it is in the conduction state, so the LED is lit.

[0057] In one embodiment, the connector circuit includes a first sub-connector circuit, a second sub-connector circuit, a third sub-connector circuit, and a fourth sub-connector circuit. The first pins of the first sub-connector circuit and the second sub-connector circuit are connected to the attenuation amplification circuit. The first pins of the third sub-connector circuit and the fourth sub-connector circuit are connected to the optical device interface circuit. The second pins of the first sub-connector circuit, the second sub-connector circuit, the third sub-connector circuit, and the fourth sub-connector circuit are connected to the bit error rate tester.

[0058] Specifically, such as Figure 9 and Figure 10 As shown, the first sub-connector circuit is denoted as J1, the second sub-connector circuit as J2, the third sub-connector circuit as J4, and the fourth sub-connector circuit as J7. All four sub-connector circuits are 7-pin 25G_SMA connector circuits. The first pin (pin 2) of the first and second sub-connector circuits is electrically connected to the attenuation amplifier circuit. The first pin (pin 2) of the third and fourth sub-connector circuits is connected to the optical device interface circuit. The second pins (pins 4 and 5) of the first, second, third, and fourth sub-connector circuits are electrically connected to the bit error rate tester.

[0059] The first and second sub-connector circuits are used to transmit the attenuated and amplified electrical signal from the attenuation amplification circuit to the bit error rate tester. The third and fourth sub-connector circuits are used to transmit the reference electrical signal from the optical device interface circuit to the bit error rate tester.

[0060] In one embodiment, such as Figure 11As shown, the optical device interface circuit includes an optical device receiver ROSA1, a ferrite bead FB4, and multiple capacitors (C10, C11, C12, C13, C14, C15, C36, C37). The optical device receiver is used to convert optical signals into electrical signals. C13, C14, FB4, and C15 form a filter circuit, which filters both high-frequency and low-frequency signals to reduce interference. Pins 4 and 5 of the optical device receiver convert the optical signal into a differential electrical signal, which is then amplified by limiting and transmitted to the attenuation amplifier circuit, thereby improving the sensitivity quality.

[0061] This optical module sensitivity test board uses a flexible PCB design to effectively connect the ROSA1's flexible printed circuit board (PCB) and immersion gold pads, facilitating high-speed signal transmission between the ROSA1 and the sensitivity test board. This results in high performance consistency, with power range controllable within 2dB and high / low temperature performance controllable within ±0.8dB for mass production. Therefore, compared to previous optical module sensitivity test boards, the detection accuracy is significantly improved. To minimize electromagnetic radiation from high-speed signal transmission, numerous grounding vias are placed close to both sides of the signal lines on the sensitivity test board. The signal lines are the connection lines between the connector circuit and the optical device interface circuit and attenuation / amplification circuit. Specifically, the optical device interface circuit is connected to two SMA connector circuits via two signal lines, and the attenuation / amplification circuit is also connected to two other SMA connector circuits via two signal lines. By obtaining different electrical signals through two branches for sensitivity testing and comparative analysis, the test quality can be improved.

[0062] In one embodiment, such as Figure 12As shown, the attenuation amplifier circuit includes a laser driver chip and peripheral components. The laser driver chip can be any transceiver chip with dual CDRs for remote direct-modulation laser (DML) applications. In this embodiment, the MALD37030 chip is selected as the laser driver chip, which features an adaptive / programmable equalizer CTLE and a flexible output driver. Using the MALD37030 chip provides design flexibility and simplifies the manufacturing process by minimizing power consumption and reducing the number of components. Pins 32 and 33 of the MALD37030 chip are directly connected to the ROSA1 flexible board via AC coupling capacitors for receiving modulation signal inputs. Pins 5 and 6 of the MALD37030 chip are directly connected to the 25G_SMA connector circuit via AC coupling capacitors (C1 and C2) for receiving modulation signal outputs. Capacitor C6, ferrite bead FB2, capacitor C4, and capacitor C5 form a high-frequency filter circuit to filter the signal entering the laser driver chip. Pins 15 and 16 of the MALD37030 chip are connected to the aforementioned control chip to achieve I2C communication. Pin 39 of the MALD37030 chip is connected to the indicator light circuit, mainly used to indicate whether the attenuation amplifier circuit has received an attenuation control signal. Pins 46 and 35 of the MALD37030 chip are used to connect to the 1.8V output voltage of the second step-down sub-circuit. The ferrite bead FB3 and capacitor C9 are mainly used to filter interference signals.

[0063] In one specific embodiment, the optical module outputs an optical signal that passes through an adjustable optical attenuator and enters the ROSA1 under test. The differential signal from the ROSA1 enters the laser driver chip through a 1uF filter capacitor. The program implements high-frequency deemphasis and controls the output amplitude of the laser driver chip to 1.8V. The laser driver chip attenuates and amplifies the reference electrical signal. The amplified signal is then output through a connector circuit to a sensitivity device (CDR) before entering the receiving end of the computer equipment. The computer equipment can synchronously control the bit error rate detector and the adjustable optical attenuator to monitor in real time the minimum optical power value that the ROSA1 can receive under a specified preset bit error rate, i.e., the sensitivity value. This method not only provides a relatively accurate sensitivity value but also improves the sensitivity detection quality of the optical module.

[0064] In one embodiment, Figure 13 This is a flowchart illustrating a method for testing the sensitivity of an optical module in one embodiment. (Refer to...) Figure 13 This paper provides a method for testing the sensitivity of optical modules. This embodiment primarily applies this method to an optical module sensitivity testing system, and the specific steps of the optical module sensitivity testing method are as follows:

[0065] Step S210: When an optical signal is acquired, the optical signal is converted into a corresponding reference electrical signal.

[0066] Specifically, the optical device interface circuit receives the optical signal provided by the 25G optical module and converts the optical signal into a corresponding reference electrical signal. Then, the reference electrical signal is transmitted to the connector circuit and the attenuation amplifier circuit respectively.

[0067] Step S220: Upon receiving the attenuation control signal, the reference electrical signal is subjected to attenuation and amplification processing to obtain an attenuated and amplified electrical signal.

[0068] Specifically, when the control circuit transmits the attenuation control signal to the attenuation amplifier circuit, the attenuation amplifier circuit will attenuate and amplify the reference electrical signal and output the attenuated and amplified electrical signal to the connector circuit. The connector circuit then transmits the reference electrical signal and the attenuated and amplified electrical signal to the computer equipment through the sensitivity device.

[0069] Step S230: Determine the corresponding first sensitivity based on the reference electrical signal, and determine the corresponding second sensitivity based on the attenuated amplified electrical signal.

[0070] Specifically, the computer equipment will determine the corresponding first sensitivity based on the analysis of the reference electrical signal, and determine the corresponding second sensitivity based on the analysis of the attenuated and amplified electrical signal.

[0071] Step S240: Determine the sensitivity test result based on the comparison result between the first sensitivity, the second sensitivity and the preset sensitivity range.

[0072] Specifically, the computer equipment compares the first sensitivity and the second sensitivity with preset sensitivity ranges, which are the sensitivities obtained after different signal processing procedures. The two sensitivities are compared with the same preset sensitivity range, which indicates the sensitivity range corresponding to a specified preset bit error value. That is, the preset sensitivity ranges corresponding to different preset bit error values ​​are different. Under normal circumstances, it can be found that the accuracy of the second sensitivity, which is obtained after signal attenuation and amplification processing, is higher than that of the first sensitivity. In this way, the test sensitivity with higher test quality can be selected as the sensitivity test result.

[0073] In one embodiment, determining the sensitivity test result based on the comparison result between the first sensitivity, the second sensitivity, and the preset sensitivity range includes:

[0074] When both the first sensitivity and the second sensitivity are within the preset sensitivity range, the sensitivity test result is determined based on the difference between the first sensitivity, the second sensitivity and the target sensitivity, wherein the target sensitivity is the sensitivity corresponding to the preset bit error rate within the preset sensitivity range.

[0075] Specifically, if both the first sensitivity and the second sensitivity are within the preset sensitivity range, it means that the sensitivity test of the optical module is relatively accurate. However, in order to improve the test accuracy, the first sensitivity, the second sensitivity and the target sensitivity within the preset sensitivity range are compared. Thus, a sensitivity is selected from the first sensitivity and the second sensitivity as the sensitivity test result. That is, the sensitivity closer to the target sensitivity can be selected as the sensitivity test result, or the sensitivity farther away from the target sensitivity can be selected as the sensitivity test result.

[0076] In one embodiment, determining the sensitivity test result based on the difference between the first sensitivity, the second sensitivity, and the target sensitivity includes:

[0077] Determine the first difference between the first sensitivity and the target sensitivity, and the second difference between the second sensitivity and the target sensitivity, respectively;

[0078] When the first difference is less than the second difference, an attenuation anomaly signal is generated, and the first sensitivity and the attenuation anomaly signal are determined as the sensitivity test result, or...

[0079] When the second difference is less than the first difference, the second sensitivity is determined as the sensitivity test result.

[0080] Specifically, the differences between the first sensitivity, the second sensitivity, and the target sensitivity are calculated separately to obtain the corresponding first difference and second difference. The sensitivity corresponding to the smaller difference is selected as the sensitivity test result, that is, the sensitivity closer to the target sensitivity is selected as the sensitivity test result, indicating that the tested sensitivity is closer to the expected sensitivity.

[0081] Under normal circumstances, the second difference between the second sensitivity of the attenuated and amplified electrical signal after signal attenuation and amplification processing and the target sensitivity should be less than the first difference between the first sensitivity of the reference electrical signal without signal attenuation and amplification processing and the target sensitivity. This indicates that the attenuated and amplified electrical signal has less interference compared to the reference electrical signal, and therefore the second sensitivity of the attenuated and amplified electrical signal is closer to the target sensitivity. Thus, the second sensitivity is taken as the sensitivity test result. However, if the first difference is less than or equal to the second difference, it indicates that the amount of interference in the attenuated and amplified signal after attenuation and amplification processing is greater than or equal to the amount of interference in the reference electrical signal. This confirms a fault in the attenuation amplification circuit, which cannot filter out the interference signal in the reference electrical signal, resulting in an attenuation anomaly signal. The attenuation anomaly signal indicates that the attenuation amplification circuit is malfunctioning, and the second sensitivity and the attenuation anomaly signal are taken as the sensitivity test results.

[0082] In one embodiment, determining the sensitivity test result based on the comparison result between the first sensitivity, the second sensitivity, and the preset sensitivity range includes:

[0083] When the first sensitivity is within the preset sensitivity range and the second sensitivity is outside the preset sensitivity range, the first sensitivity is determined as the sensitivity test result; or,

[0084] When the second sensitivity is within the preset sensitivity range and the first sensitivity is outside the preset sensitivity range, an attenuation anomaly signal is generated, and the second sensitivity and the attenuation anomaly signal are determined as the sensitivity test result.

[0085] Specifically, when the first sensitivity or the second sensitivity is within the preset sensitivity range, only the sensitivity within the preset sensitivity range is selected as the sensitivity test result. That is, the sensitivity obtained by the test only meets the test requirements if it is within the preset sensitivity range.

[0086] The above-mentioned optical module sensitivity testing method is derived using unique technical features of optical module sensitivity testing methods, and achieves the beneficial effect of solving the technical problems raised in the background art.

[0087] Figure 13 This is a flowchart illustrating a method for testing the sensitivity of an optical module in one embodiment. It should be understood that, although... Figure 13 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 13At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0088] In one embodiment, an optical module sensitivity testing device is provided, comprising multiple virtual modules for implementing the method steps to be performed by the aforementioned computer device.

[0089] Figure 14 An internal structural diagram of a computer device in one embodiment is shown. Figure 14 As shown, the computer device includes a processor, memory, network interface, input device, and display screen connected via a system bus. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores an operating system and may also store a computer program. When executed by the processor, this computer program enables the processor to implement a method for testing the sensitivity of an optical module. The internal memory may also store a computer program, which, when executed by the processor, enables the processor to perform the optical module sensitivity testing method. The display screen can be an LCD screen or an e-ink screen. The input device can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0090] Those skilled in the art will understand that Figure 14 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0091] In one embodiment, the optical module sensitivity testing device provided in this application can be implemented as a computer program, and the computer program can be implemented in the form of, for example, Figure 14 The device operates on the computer shown. The computer's memory can store the various program modules that make up the optical module sensitivity testing apparatus. The computer program, composed of these program modules, causes the processor to execute the steps in the optical module sensitivity testing methods of the various embodiments of this application described in this specification.

[0092] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in any of the above embodiments.

[0093] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in any of the above embodiments.

[0094] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0095] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0096] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for testing the sensitivity of an optical module, characterized in that, The method includes: When an optical signal is acquired, it is converted into a corresponding reference electrical signal; When the attenuation control signal is received, the reference electrical signal is attenuated and amplified to obtain an attenuated and amplified electrical signal. In this case, by attenuating and amplifying the reference electrical signal in the working state through the attenuation amplification circuit, interference signals in the reference electrical signal can be filtered out to improve the effective accuracy of the reference signal. A first sensitivity is determined based on the reference electrical signal, and a second sensitivity is determined based on the attenuated and amplified electrical signal. The sensitivity test result is determined based on the comparison between the first sensitivity, the second sensitivity, and the preset sensitivity range.

2. The method according to claim 1, characterized in that, The step of determining the sensitivity test result based on the comparison result between the first sensitivity, the second sensitivity, and the preset sensitivity range includes: When both the first sensitivity and the second sensitivity are within the preset sensitivity range, the sensitivity test result is determined based on the difference between the first sensitivity, the second sensitivity and the target sensitivity, wherein the target sensitivity is the sensitivity corresponding to the preset bit error rate within the preset sensitivity range.

3. The method according to claim 2, characterized in that, Determining the sensitivity test result based on the difference between the first sensitivity, the second sensitivity, and the target sensitivity includes: Determine the first difference between the first sensitivity and the target sensitivity, and the second difference between the second sensitivity and the target sensitivity, respectively; When the first difference is less than the second difference, an attenuation anomaly signal is generated, and the first sensitivity and the attenuation anomaly signal are determined as the sensitivity test result, or... When the second difference is less than the first difference, the second sensitivity is determined as the sensitivity test result.

4. The method according to claim 1, characterized in that, The step of determining the sensitivity test result based on the comparison result between the first sensitivity, the second sensitivity, and the preset sensitivity range includes: When the first sensitivity is within the preset sensitivity range and the second sensitivity is outside the preset sensitivity range, the first sensitivity is determined as the sensitivity test result; or, When the second sensitivity is within the preset sensitivity range and the first sensitivity is outside the preset sensitivity range, an attenuation anomaly signal is generated, and the second sensitivity and the attenuation anomaly signal are determined as the sensitivity test result.

5. A sensitivity testing system for optical modules, characterized in that, The system includes an optical module, a bit error rate tester, a sensitivity test board, a sensitivity device, and a computer. The optical module provides an optical signal to the sensitivity test board via an optical fiber. The bit error rate tester provides a preset bit error rate value to the sensitivity test board. The sensitivity test board performs a sensitivity test on the optical signal according to the preset bit error rate value to obtain a test signal, and transmits the test signal to the computer through the sensitivity device. The computer determines the sensitivity test result based on the test signal. The test signal includes a reference electrical signal after photoelectric conversion of the optical signal and an attenuated and amplified electrical signal after attenuation and amplification processing of the reference electrical signal. The attenuation and amplification circuit attenuates and amplifies the reference electrical signal during operation, which can filter out interference signals in the reference electrical signal to improve the effective accuracy of the reference signal. The computer device determines the sensitivity test result based on the comparison between the first sensitivity corresponding to the reference electrical signal, the second sensitivity corresponding to the attenuated amplified electrical signal, and the preset sensitivity range.

6. The system according to claim 5, characterized in that, The sensitivity test board includes an optical device interface circuit, an attenuation amplification circuit, a control circuit, a step-down circuit, and a connector circuit, wherein: The step-down circuit provides the corresponding operating voltages for the control circuit and the attenuation amplifier circuit, respectively; The optical device interface circuit converts the optical signal into a reference electrical signal and transmits it to the connector circuit and the attenuation amplification circuit. When the attenuation amplification circuit receives an attenuation control signal from the control circuit, it performs attenuation amplification processing on the reference electrical signal to generate an attenuation amplified electrical signal, and then transmits the attenuation amplified electrical signal to the connector circuit. The connector circuit transmits the reference electrical signal and the attenuated amplified electrical signal to the computer device through a sensitivity device.

7. The system according to claim 6, characterized in that, The step-down circuit includes a first step-down sub-circuit and a second step-down sub-circuit. The first step-down sub-circuit converts the power supply voltage into a first operating voltage and transmits the first operating voltage to the control circuit. The second step-down sub-circuit converts the power supply voltage into a second operating voltage and transmits the second operating voltage to the attenuation amplifier circuit.

8. The system according to claim 6, characterized in that, The sensitivity test board also includes an indicator light circuit, which is electrically connected to the attenuation amplifier circuit. The indicator light circuit determines the corresponding indicator light status based on the attenuation amplifier circuit's reception status of the attenuation control signal.

9. The system according to claim 8, characterized in that, The indicator light circuit is in an illuminated state when the attenuation amplifier circuit receives the attenuation control signal, and in an off state when the attenuation amplifier circuit does not receive the attenuation control signal.

10. The system according to claim 6, characterized in that, The connector circuit includes a first sub-connector circuit, a second sub-connector circuit, a third sub-connector circuit, and a fourth sub-connector circuit. The first pins of the first sub-connector circuit and the second sub-connector circuit are connected to the attenuation and amplification circuit. The first pins of the third sub-connector circuit and the fourth sub-connector circuit are connected to the optical device interface circuit. The second pins of the first sub-connector circuit, the second sub-connector circuit, the third sub-connector circuit, and the fourth sub-connector circuit are connected to the bit error rate tester.

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