A low scan power consumption scan cell and scan chain

By designing a low-power scanning unit, the problem of high power consumption in scanning tests is solved, achieving dynamic power reduction and improved testing efficiency during the scanning phase.

CN116859225BActive Publication Date: 2026-06-3058TH RES INST OF CETC
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Patent Information

Application Number
CN202310855919.8
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-07-13
Publication Date
2026-06-30
Estimated Expiration
2043-07-13

AI Technical Summary

Technical Problem

In the existing technology, scanning-based designs have high power consumption problems during testing, including excessively high average power consumption and excessively high peak power consumption, which leads to chip hotspots, premature circuit damage and reduced reliability.

Method used

A low-scan-power scanning unit is adopted, including a SI-D two-input selection unit, a first-level latch unit, a second-level latch unit, and a clock network. Power gating is controlled by a high-threshold PMOS transistor to reduce switching activities and dynamic power consumption during the scanning phase.

Benefits of technology

It effectively reduces dynamic power consumption during the scanning phase, decreases the average power consumption and peak power of the scan chain, and improves test efficiency and circuit reliability.

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Abstract

This invention discloses a low-scan-power scanning unit and scanning chain, belonging to the field of integrated circuit design-for-test (DTBT). The invention uses a low-scan-power scanning unit, adding an OR gate to control the switching activity of two tri-state gates in the secondary latch unit during the scanning phase, and using a high-threshold PMOS as a power supply gating to control the power supply VDD of the two inverters inside the secondary latch unit, thus reducing the dynamic power consumption of the secondary latch and unnecessary dynamic power consumption of the combinational logic during the scanning phase. Additionally, a test vector output port P is added, whose signal originates from the output of the primary latch unit inside the scanning unit, reducing the transmission path delay during the scanning phase. This invention is applicable to the DTBT stage of digital circuits; by simply adding an OR gate and a high-threshold PMOS, without affecting the original logic circuit function, it achieves the goal of reducing dynamic power consumption during the shift phase.
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Citation Information

Patent Citations

  • Methods and arrangements for an enhanced scanable latch circuit

    US20050122136A1

  • State retention power gating latch circuit

    US20060255849A1

  • Scan register and methods of using the same

    US7457998B1