Multilayer ceramic electronic component

Abstract

Provided is a laminated ceramic electronic component with high moisture resistance reliability. The laminated ceramic capacitor includes a laminate (10) including a plurality of ceramic layers (20) and a plurality of internal conductor layers (30), and a pair of external electrodes (40) disposed at both ends in a length direction (L) of the laminate, the internal conductor layers including a first internal conductor layer (31) and a second internal conductor layer (32), the external electrodes including a first external electrode (40A) including a first base electrode layer (50A) connected to the first internal conductor layer, and a second external electrode (40B) including a second base electrode layer (50B) connected to the second internal conductor layer, the first base electrode layer and the second base electrode layer having a metal portion (70) and a plurality of non-metal portions (80) present within the metal portion, in a cross section perpendicular to a width direction (W), an average area of the non-metal portions in a first total body constituted by the non-metal portions with a circularity of 0.4 or less is 12 μm 2 The following.

Description

Technical Field

[0001] This invention relates to laminated ceramic electronic components. Background Technology

[0002] Previously, multilayer ceramic capacitors were known as multilayer ceramic electronic components. Typically, a multilayer ceramic capacitor comprises: a laminate obtained by alternately stacking multiple dielectric layers and internal electrode layers; and external electrodes disposed on both ends of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, and the external electrodes include a base electrode layer formed by sintering.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2003-243249 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] Here, the base electrode layer of the external electrode, in addition to serving as an electrical connection with the internal electrode layer, also serves to prevent moisture from seeping into the end face of the laminate from the outside. However, the base electrode layer mostly contains non-metallic portions such as voids. In this case, these non-metallic portions become pathways for moisture infiltration, which may reduce the moisture resistance reliability.

[0008] Therefore, the purpose of this invention is to provide a laminated ceramic electronic component with high moisture resistance and reliability.

[0009] means for solving problems

[0010] The laminated ceramic electronic component of the present invention comprises: a laminate including a plurality of ceramic layers and a plurality of internal conductor layers alternately laminated in a lamination direction, and including a first main surface and a second main surface opposite to each other in the lamination direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the lamination direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the lamination direction and the length direction; and a pair of external electrodes respectively disposed at two ends in the length direction of the laminate, the internal conductor layers including: a first internal conductor layer extending to the first end surface; and a second internal conductor layer extending to the second end surface, the external electrodes having: a first external electrode including a first base electrode layer connected to the first internal conductor layer; and a second external electrode including a second base electrode layer connected to the second internal conductor layer, the first base electrode layer and the second base electrode layer having a metal portion and a plurality of non-metal portions present within the metal portion, wherein, in a cross-sectional view perpendicular to the width direction, the average area of ​​the non-metal portions in a first totality composed of non-metal portions with a roundness of 0.4 or less is 12 μm. 2 the following.

[0011] Invention Effects

[0012] According to the present invention, it is possible to provide laminated ceramic electronic components with high moisture resistance and reliability. Attached Figure Description

[0013] Figure 1 This is a perspective view of the stacked ceramic capacitor according to the embodiment.

[0014] Figure 2 yes Figure 1 Sectional view II-II.

[0015] Figure 3 yes Figure 2 Sectional view III-III.

[0016] Figure 4A yes Figure 2 IVA-IVA sectional view.

[0017] Figure 4B yes Figure 2 IVB-IVB sectional view.

[0018] Figure 5 Based on Figure 2 The enlarged cross-sectional view is obtained from the SEM photograph of the portion shown in R1.

[0019] Figure 6 This is a diagram showing an example of a non-metallic part with relatively low roundness.

[0020] Figure 7AThis is a diagram showing a stacked ceramic capacitor with a dual-connection structure.

[0021] Figure 7B This is a diagram showing a triplet structure of a multilayer ceramic capacitor.

[0022] Figure 7C This is a diagram showing a four-cell stacked ceramic capacitor.

[0023] Explanation of reference numerals in the attached figures

[0024] 1. Multilayer ceramic capacitors (multilayer ceramic electronic components);

[0025] 10-layer stack;

[0026] 20. Dielectric layer (ceramic layer);

[0027] 30. Internal electrode layer (internal conductor layer);

[0028] 31 First internal electrode layer (first internal conductor layer);

[0029] 32 Second internal electrode layer (second internal conductor layer);

[0030] 40 External electrodes;

[0031] 40A First external electrode;

[0032] 40B Second external electrode;

[0033] 50. Substrate electrode layer;

[0034] 50A First substrate electrode layer;

[0035] 50B Second base electrode layer;

[0036] 70 Metal Division;

[0037] 80 Non-metallic Department;

[0038] L represents the length direction;

[0039] T indicates the stacking direction;

[0040] W represents the width direction;

[0041] LS1 First end face;

[0042] LS2 Second end face;

[0043] TS1 First Main Page;

[0044] TS2 Second Main Face;

[0045] WS1 First side view;

[0046] WS2 Second side view. Detailed Implementation

[0047] Hereinafter, the multilayer ceramic capacitor 1, which is an embodiment of the multilayer ceramic electronic component of this disclosure, will be described with reference to the accompanying drawings. Figure 1 This is a perspective view of the stacked ceramic capacitor 1 according to the embodiment. Figure 2 yes Figure 1 Sectional view II-II. Figure 3 yes Figure 2 Sectional view III-III. Figure 4A yes Figure 2 IVA-IVA sectional view. Figure 4B yes Figure 2 IVB-IVB sectional view.

[0048] like Figure 1 As shown, the multilayer ceramic capacitor 1 of the embodiment has a generally rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a multilayer body 10 having a generally rectangular parallelepiped shape, and a pair of external electrodes 40 disposed separately from each other at both ends of the multilayer body 10.

[0049] exist Figure 1 In the diagram, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the multilayer body 10. This stacking direction T is also the thickness and height direction of the multilayer ceramic capacitor 1 and the multilayer body 10. Figure 1 In the diagram, arrow L represents the length direction of the multilayer ceramic capacitor 1 and the multilayer body 10, which is orthogonal to the stacking direction T. Figure 1 In the diagram, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the multilayer body 10, which is orthogonal to the stacking direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the multilayer body 10 along the length direction L.

[0050] exist Figures 1 to 4B The diagram shows an XYZ orthogonal coordinate system. The length direction L of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the X direction. The width direction W of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the Y direction. The stacking direction T of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the Z direction. Here, Figure 2 The cross section shown is also known as the LT section. Figure 3 The cross-section shown is also known as the WT cross-section. Figure 4A and Figure 4B The cross-section shown is also called the LW cross-section.

[0051] like Figures 1 to 4BAs shown, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that are opposite each other in the lamination direction T, a first end surface LS1 and a second end surface LS2 that are opposite each other in the length direction L that is orthogonal to the lamination direction T, and a first side surface WS1 and a second side surface WS2 that are opposite each other in the width direction W that is orthogonal to the lamination direction T and the length direction L.

[0052] like Figure 1 As shown, the laminate 10 has a generally rectangular parallelepiped shape. It should be noted that the length L of the laminate 10 is not necessarily longer than its width W. It is preferable that the corners and edges of the laminate 10 be rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. It should also be noted that some or all of the surfaces constituting the laminate 10 may have irregularities or protrusions.

[0053] The dimensions of the laminate 10 are not particularly limited, but when the length direction L of the laminate 10 is set as dimension L, dimension L is preferably 0.2 mm or more and 6 mm or less. Furthermore, when the lamination direction T of the laminate 10 is set as dimension T, dimension T is preferably 0.05 mm or more and 5 mm or less. Additionally, when the width direction W of the laminate 10 is set as dimension W, dimension W is preferably 0.1 mm or more and 5 mm or less.

[0054] like Figure 2 and Figure 3 As shown, the laminate 10 has an inner layer 11 and a first main surface side outer layer 12 and a second main surface side outer layer 13 configured to sandwich the inner layer 11 in the lamination direction T.

[0055] The inner layer 11 includes multiple dielectric layers 20, which are multiple ceramic layers, and multiple internal electrode layers 30, which are multiple internal conductor layers, alternately stacked in the stacking direction T. The inner layer 11 includes internal electrode layers 30 located from the side closest to the first main surface TS1 to the side closest to the second main surface TS2 in the stacking direction T. In the inner layer 11, the multiple internal electrode layers 30 are arranged opposite each other, separated by dielectric layers 20. The inner layer 11 is the part that generates electrostatic capacitance and essentially functions as a capacitor.

[0056] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material may be, for example, a dielectric ceramic comprising BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, the dielectric material may be a material obtained by adding byproducts such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds to these main components. A dielectric material comprising BaTiO3 as a main component is particularly preferred.

[0057] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The number of stacked dielectric layers 20 is preferably 15 or more and 1200 or less. It should be noted that the number of dielectric layers 20 is the total number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0058] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 serving as a plurality of first internal conductor layers, and a plurality of second internal electrode layers 32 serving as a plurality of second internal conductor layers. The first internal electrode layers 31 and second internal electrode layers 32 are alternately arranged along the stacking direction T, separated by a dielectric layer 20. The first internal electrode layers 31 extend to a first end face LS1. The second internal electrode layers 32 extend to a second end face LS2. It should be noted that, hereinafter, without distinguishing between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 are sometimes collectively referred to as internal electrode layers 30.

[0059] like Figure 4A As shown, the first internal electrode layer 31 has a first opposing portion 31A and a first lead-out portion 31B. The first opposing portion 31A is the region that sandwiches the dielectric layer 20 in the middle and opposes the second internal electrode layer 32, and is located inside the laminate 10. The first lead-out portion 31B is the portion that extends from the first opposing portion 31A to the first end face LS1 and is exposed on the first end face LS1.

[0060] like Figure 4B As shown, the second internal electrode layer 32 has a second opposing portion 32A and a second lead-out portion 32B. The second opposing portion 32A is the region that sandwiches the dielectric layer 20 in the middle and opposes the first internal electrode layer 31, and is located inside the laminate 10. The second lead-out portion 32B is the portion that extends from the second opposing portion 32A to the second end face LS2 and is exposed on the second end face LS2.

[0061] In this embodiment, a capacitor is formed by the first opposing portion 31A and the second opposing portion 32A being opposed to each other through the dielectric layer 20, thus exhibiting the characteristics of a capacitor.

[0062] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape can be rounded, or the corners of the rectangular shape can be formed at an angle. The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape can be rounded, or the corners of the rectangular shape can be formed at an angle.

[0063] The width W of the first opposing portion 31A and the width W of the first lead-out portion 31B can be formed to the same size, or either one can be made smaller. The width W of the second opposing portion 32A and the width W of the second lead-out portion 32B can be formed to the same size, or either one can be made narrower.

[0064] The first internal electrode layer 31 and the second internal electrode layer 32 are made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may also be made of, for example, an Ag-Pd alloy.

[0065] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 1000 or less.

[0066] like Figure 2 and Figure 3 As shown, the first main surface side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the inner electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the inner electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer 12 and the second main surface side outer layer 13 may both be the same as the dielectric layers 20 used in the inner layer 11.

[0067] It should be noted that the laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first inner electrode layer 31 and the second counter portion 32A of the second inner electrode layer 32 are opposed to each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figure 4A and Figure 4B The diagram shows the width W and length L of the counter electrode portion 11E. It should be noted that the counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0068] It should be noted that the laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 includes a portion of the dielectric layer 20 located between the counter electrode portion 11E and the first side WS1. The second side outer layer WG2 includes a portion of the dielectric layer 20 located between the counter electrode portion 11E and the second side WS2. Figure 3 , Figure 4A and Figure 4B The diagram shows the width W range of the first side outer layer WG1 and the second side outer layer WG2. It should be noted that the side outer layer is also referred to as the W gap or side gap.

[0069] It should be noted that the laminate 10 has an end-face side outer layer. The end-face side outer layer has a first end-face side outer layer LG1 and a second end-face side outer layer LG2. The first end-face side outer layer LG1 includes a dielectric layer 20 and a first lead-out portion 31B located between the counter electrode portion 11E and the first end face LS1. That is, the first end-face side outer layer LG1 is an assembly of portions of multiple dielectric layers 20 on the first end face LS1 side and multiple first leads-out portions 31B. The second end-face side outer layer LG2 includes a dielectric layer 20 and a second lead-out portion 32B located between the counter electrode portion 11E and the second end face LS2. That is, the second end-face side outer layer LG2 is an assembly of portions of multiple dielectric layers 20 on the second end face LS2 side and multiple second leads-out portions 32B. Figure 2 , Figure 4A and Figure 4B The diagram shows the length direction L of the first end-face side outer layer LG1 and the second end-face side outer layer LG2. It should be noted that the end-face side outer layer is also referred to as the L-gap or end gap.

[0070] like Figure 1 and Figure 2 As shown, the external electrode 40 has a first external electrode 40A disposed on the first end face LS1 side of the laminate 10, and a second external electrode 40B disposed on the second end face LS2 side of the laminate 10.

[0071] It should be noted that the basic structures of the first external electrode 40A and the second external electrode 40B are the same. Furthermore, the first external electrode 40A and the second external electrode 40B have a shape that is approximately symmetrical about the cross-section WT relative to the center of the length direction L of the multilayer ceramic capacitor 1. Therefore, hereinafter, without distinguishing between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B will sometimes be collectively referred to as external electrode 40.

[0072] A first external electrode 40A is disposed on a first end face LS1. The first external electrode 40A contacts the first lead-out portion 31B of each of the plurality of first internal electrode layers 31 exposed on the first end face LS1. Thus, the first external electrode 40A is electrically connected to the plurality of first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0073] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B contacts the second lead-out portion 32B of each of the plurality of second internal electrode layers 32 exposed on the second end face LS2. Thus, the second external electrode 40B is electrically connected to the plurality of second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0074] As described above, within the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 are opposed to each other across the dielectric layer 20, thereby forming a capacitor. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0075] like Figure 2 , Figure 4A and Figure 4B As shown, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. Additionally, the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0076] A first base electrode layer 50A is disposed on a first end face LS1. The first base electrode layer 50A is connected to the first lead-out portion 31B of each of the plurality of first internal electrode layers 31 exposed on the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of a first main face TS1 and a portion of a second main face TS2, as well as a portion of a first side face WS1 and a portion of a second side face WS2.

[0077] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B contacts the second lead-out portion 32B of each of the plurality of second internal electrode layers 32 exposed on the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0078] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are sintered layers. The sintered layer preferably includes a metallic component, a glass component, or a ceramic component, or both. The metallic component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloys, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component can be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material can be used. The ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0079] The sintered layer is obtained, for example, by applying a conductive paste comprising glass and metal to the laminate 10 and then sintering it. The sintered layer can be formed by co-firing the raw material of the laminate 10, i.e., the pre-firing laminate sheet having multiple internal electrodes and dielectric layers, with the conductive paste applied to the laminate sheet. Alternatively, it can be formed by applying the conductive paste to the laminate 10 and then sintering it after firing the laminate sheet to obtain the laminate 10. It should be noted that in the co-firing case described above, it is preferable to form the sintered layer by sintering a structure in which ceramic material is added instead of glass. In this case, it is particularly preferable to use a ceramic material of the same type as the dielectric layer 20 as the added ceramic material. It should be noted that the sintered layer can also consist of multiple layers.

[0080] The thickness of the first base electrode layer 50A located on the first end face LS1, corresponding to the length direction L, is preferably, for example, 10 μm or more and 200 μm or less at the center of the stacking direction T and the width direction W of the first base electrode layer 50A.

[0081] The thickness of the second base electrode layer 50B located on the second end face LS2, corresponding to the length direction L, is preferably 10 μm or more and 200 μm or less at the center of the stacking direction T and width direction W of the second base electrode layer 50B.

[0082] When a first base electrode layer 50A is also provided on a portion of at least one of the first main surfaces TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on that portion, corresponding to the stacking direction T, is preferably 3 μm or more and 40 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided on that portion.

[0083] When a first base electrode layer 50A is also provided on a portion of at least one of the first side WS1 or the second side WS2, the thickness of the first base electrode layer 50A provided on that portion, corresponding to the width direction W, is preferably 3 μm or more and 40 μm or less at the center of the length direction L and the stacking direction T of the first base electrode layer 50A provided on that portion.

[0084] When a second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on that portion, corresponding to the stacking direction T, is preferably 3 μm or more and 40 μm or less at the center of the length direction L and width direction W of the second base electrode layer 50B provided on that portion.

[0085] When a second base electrode layer 50B is also provided on a portion of at least one of the first side WS1 or the second side WS2, the thickness of the second base electrode layer 50B provided on that portion, corresponding to the width direction W, is preferably 3 μm or more and 40 μm or less at the center of the length direction L and the stacking direction T of the second base electrode layer 50B provided on that portion.

[0086] The first plating layer 60A is configured to cover the first substrate electrode layer 50A.

[0087] The second plating layer 60B is configured to cover the second base electrode layer 50B.

[0088] The first plating layer 60A and the second plating layer 60B may also include at least one material selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a double-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0089] The first plating layer 60A is configured to cover the first substrate electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0090] The second plating layer 60B is configured to cover the second base electrode layer 50B. In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0091] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being eroded by solder during the mounting of the multilayer ceramic capacitor 1. Additionally, the Sn plating layer improves the wettability of the solder during the mounting of the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thicknesses of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B are preferably 2 μm or more and 10 μm or less.

[0092] It should be noted that the external electrode 40 in this embodiment may, for example, have a conductive resin layer comprising conductive particles and a thermosetting resin. The conductive resin layer may also be configured to cover the sintered layer. When the conductive resin layer is configured to cover the sintered layer, the conductive resin layer is disposed between the sintered layer and the plating layers (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the sintered layer or may cover only a portion of the sintered layer.

[0093] The conductive resin layer, including a thermosetting resin, is more flexible than, for example, the conductive layer of a sintered product including a coating film or a conductive paste. Therefore, even when subjected to physical impact or thermal cycling-induced impact on the multilayer ceramic capacitor 1, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses crack formation in the multilayer ceramic capacitor 1.

[0094] The metal constituting the conductive particles can also be Ag, Cu, Ni, Sn, Bi, or alloys thereof. Ag is preferred as the conductive particles. Conductive particles can be, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is difficult to oxidize and has high weather resistance. Therefore, Ag metal powder is suitable as a conductive particle.

[0095] Alternatively, the conductive particles can also be metal powder with an Ag coating on its surface. When using metal powder with an Ag coating, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy thereof. To maintain the properties of Ag and to make the base metal cheaper, it is preferable to use Ag-coated metal powder.

[0096] In addition, conductive particles can also be obtained by subjecting Cu or Ni to an anti-oxidation treatment. Alternatively, conductive particles can also be obtained by coating the surface of metal powder with Sn, Ni, or Cu. When using metal powder obtained by coating the surface of metal powder with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy thereof.

[0097] There are no particular limitations on the shape of the conductive particles. Conductive particles can be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical and flat metal powders.

[0098] The conductive particles contained in the conductive resin layer primarily serve to ensure the layer's electrical conductivity. Specifically, multiple conductive particles contact each other to form electrical pathways within the conductive resin layer.

[0099] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, and polyimide resin. Epoxy resin, with its excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin of the conductive resin layer preferably includes a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may also be various known compounds such as phenolic, amine, anhydride, imidazole, reactive ester, and amide-imide compounds.

[0100] It should be noted that the conductive resin layer can also be formed from multiple layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0101] The above describes the basic structure of the multilayer ceramic capacitor 1 according to the embodiment. It should be noted that when the length dimension of the multilayer ceramic capacitor 1, including the laminate 10 and the external electrode 40, is defined as dimension L, dimension L is preferably 0.2 mm or more and 6 mm or less. Furthermore, when the lamination direction dimension of the multilayer ceramic capacitor 1 is defined as dimension T, dimension T is preferably 0.05 mm or more and 5 mm or less. Additionally, when the width dimension of the multilayer ceramic capacitor 1 is defined as dimension W, dimension W is preferably 0.1 mm or more and 5 mm or less.

[0102] Therefore, through research and experimentation, the inventors of this application have reached the following conclusion: In order to improve the moisture resistance reliability of multilayer ceramic capacitors, it is desirable to set the non-metallic portions included in the base electrode layers that are in direct contact with the laminate, namely the first base electrode layer 50A and the second base electrode layer 50B of this embodiment, in an appropriate state. This point will be explained below.

[0103] Figure 5 Based on Figure 2 The enlarged cross-sectional view is obtained from the SEM (scanning electron microscope) image of the portion shown in R1. Figure 5 It is a portion of the LT section perpendicular to the width direction W of the laminate 10 in the multilayer ceramic capacitor 1. Figure 5 The image shows a portion of the first base electrode layer 50A, a portion of the first Ni plating layer 61A, and a portion of the laminate 10. Figure 5 The image shows a dielectric layer 20 and a plurality of first internal electrode layers 31 in the laminate 10. A first base electrode layer 50A is in contact with the first internal electrode layer 31 exposed at the first end face LS1 of the laminate 10.

[0104] The second base electrode layer 50B in this embodiment also has the same... Figure 5 The same cross-sectional structure. Therefore, based on Figure 5 The structure of the first base electrode layer 50A described is also the structure of the second base electrode layer 50B. Therefore, in the following description, without distinguishing between the first base electrode layer 50A and the second base electrode layer 50B, the first base electrode layer 50A and the second base electrode layer 50B are sometimes collectively referred to as base electrode layer 50.

[0105] like Figure 5 As shown, the base electrode layer 50 has a metal portion 70 and a plurality of non-metal portions 80 present in the metal portion 70.

[0106] The metal portion 70 includes at least one metallic component selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc., contained in the aforementioned sintered layer forming the base electrode layer 50. A plurality of non-metallic portions 80 are dispersed within such a metal portion 70.

[0107] The non-metallic portion 80 is primarily voids, but not entirely voids; it may also include a portion of glass components containing Ba or Si. Alternatively, the non-metallic portion 80 may be entirely composed of glass components containing Ba or Si. The roundness and average area of ​​the multiple non-metallic portions 80 vary.

[0108] In the substrate electrode layer 50 of this embodiment, in Figure 5In the LT cross-section shown perpendicular to the width direction W, the average area of ​​the non-metallic portion 80 in the first aggregate, which is composed of non-metallic portions 80 with a roundness of 0.4 or less, is preferably 12 μm. 2 the following.

[0109] Furthermore, in the substrate electrode layer 50 of this embodiment, in Figure 5 In the LT cross-section shown perpendicular to the width direction W, the proportion of non-metallic portion 80 is preferably 17.2% or less.

[0110] In the multilayer ceramic capacitor 1 of this embodiment, the non-metallic portion 80 with low roundness in the non-metallic portion 80 of the substrate electrode layer 50 has a relatively small area. In multilayer ceramic capacitors having a substrate electrode layer, the substrate electrode layer typically includes a non-metallic portion such as the non-metallic portion 80 of this embodiment.

[0111] The non-metallic portion 80 becomes a pathway for moisture to penetrate from the outside to the inside, sometimes reducing the moisture resistance reliability of the multilayer ceramic capacitor 1. This is especially true when the proportion of the non-metallic portion 80 in the base electrode layer 50 is high, leading to a decrease in moisture resistance reliability. Furthermore, even when the proportion of the non-metallic portion 80 is not high, for example, when the non-metallic portion 80 is elongated, the orientation of the non-metallic portion 80 along its length or the degree of connection between multiple non-metallic portions 80 can create a structure where moisture can easily penetrate. To improve the moisture resistance reliability of the multilayer ceramic capacitor 1, increasing the thickness of the base electrode layer 50 is considered. However, in this case, the size of the multilayer ceramic capacitor 1 becomes larger, hindering component miniaturization. Additionally, without changing the size of the multilayer ceramic capacitor 1, increasing the thickness of the base electrode layer 50 correspondingly reduces the size of the laminate 10, thereby causing a decrease in the capacitor's capacitance.

[0112] Figure 6 This is an example of a non-metallic portion 80 with relatively low roundness. The roundness of this non-metallic portion 80 is 0.25. When there are multiple such non-metallic portions 80 with low roundness and these non-metallic portions 80 are large in size, there is a possibility that moisture can easily penetrate.

[0113] In this embodiment, in the LT cross-section of the substrate electrode layer 50, when the entirety composed of non-metallic portions 80 with a roundness of 0.4 or less is defined as the first overall structure, the average area of ​​the plurality of non-metallic portions 80 constituting the first overall structure is 12 μm. 2 Below, in Figure 5 The region shown is specifically 6.3 μm. 2Therefore, even when the base electrode layer 50 includes a non-metallic portion 80, the non-metallic portion 80, which has low roundness and is prone to moisture penetration, is small in size, making it difficult for the non-metallic portion 80 to become a path for moisture penetration. Thus, moisture resistance reliability is improved.

[0114] It should be noted that, in this embodiment, the average area of ​​the plurality of non-metallic portions 80 constituting the first overall structure is preferably 2 μm. 2 Above and 12μm 2 Below, 2μm is more preferred. 2 Above and 9μm 2 The following results in further improved moisture resistance reliability.

[0115] In the LT cross-section of the multilayer ceramic capacitor 1 of this embodiment, the proportion of non-metallic portions 80 in the base electrode layer 50 may be, for example, 1% or more and 30% or less, but preferably 17.2% or less. Furthermore, the proportion of non-metallic portions 80 in the base electrode layer 50 is preferably, for example, 1.5% or more and 17.2% or less, and more preferably, for example, 5% or more and 15% or less. Even when the base electrode layer 50 includes non-metallic portions 80 and the proportion of non-metallic portions 80 in the base electrode layer 50 is within such a range, the effect of this embodiment, namely, improved moisture resistance reliability, is achieved.

[0116] Next, the measurement methods for various parameters such as the roundness of the non-metallic portion 80, the average area of ​​the non-metallic portion 80, and the proportion of the non-metallic portion 80 in the substrate electrode layer 50 in this embodiment will be described.

[0117] First, the multilayer ceramic capacitor 1 is ground from either the first side WS1 or the second side WS2 until it reaches half the width W dimension. This exposes the LT cross-section at the center of the width W of the multilayer ceramic capacitor 1. Next, the exposed LT cross-section is observed using a SEM. Specifically, the portion of the LT cross-section including the substrate electrode layer 50 is photographed to obtain a reflected electron image. In the reflected electron image, differences in resistance values ​​are reflected as contrast; the metal portion 70 appears whiter, and the non-metal portion 80 appears darker than the metal portion 70. It should be noted that the magnification is set to 2000x, and the portion of the substrate electrode layer 50 in the reflected electron image is defined as the analysis area.

[0118] The reflected electron images of four locations, including two locations of the first base electrode layer 50A and two locations of the second base electrode layer 50B, are obtained. Figure 2R1, R2, R3, and R4 indicate the locations where reflected electron images were obtained at four locations. R1 is the portion of the first base electrode layer 50A that contacts the inner layer 11 of the laminate 10, closest to the first main surface TS1. R2 is the portion of the first base electrode layer 50A that contacts the inner layer 11 of the laminate 10, closest to the second main surface TS2. R3 is the portion of the second base electrode layer 50B that contacts the inner layer 11 of the laminate 10, closest to the first main surface TS1. R4 is the portion of the second base electrode layer 50B that contacts the inner layer 11 of the laminate 10, closest to the second main surface TS2. It should be noted that the length of the stacking direction T of R1, R2, R3, and R4 is all set to 80 μm.

[0119] In the substrate electrode layer 50, the dimensions (thickness) of the four regions corresponding to the reflected electron image acquisition positions R1, R2, R3, and R4, respectively, along the length direction L, tend to become thinner, which has a significant impact on moisture resistance reliability. Therefore, from the perspective of moisture resistance reliability, the state of these parts of the substrate electrode layer 50 is important.

[0120] Using the image analysis software "WinROOF (Made by Mitani Shoji)," the acquired reflected electron image is binarized to identify the metal portion 70 and the multiple non-metal portions 80 present within the metal portion 70. Using this binarized image, various parameters, such as the area of ​​each non-metal portion 80 present within the substrate electrode layer 50, are calculated. Furthermore, the proportion of non-metal portions 80 present in the substrate electrode layer 50 is calculated.

[0121] The area of ​​the non-metallic portion 80 is calculated based on the binarized image obtained by binarizing the reflected electron image. It should be noted that the area of ​​the non-metallic portion 80 is less than 2.0 μm. 2 In the case of a value of 80, this might not be the non-metallic part but rather noise. Therefore, to eliminate the influence of noise, a value less than 2.0 μm will be used. 2 The non-metallic portion 80 is excluded from the analysis.

[0122] For each non-metallic part 80, the roundness of the non-metallic part 80 is calculated using the following formula (1) based on the area of ​​the non-metallic part 80 and the circumference (length of the outline) of the non-metallic part 80.

[0123] Roundness = 4π × (area) / (circumference) 2 …(1)

[0124] All non-metallic parts 80 identified within the analysis range of reflected electron images obtained at positions R1, R2, R3, and R4 from four locations (except those with an area less than 2.0 μm) are included. 2The set of non-metallic portions 80 with a roundness of 0.4 or less in the non-metallic portions (with a value of 0.4) is defined as the first total. Based on the area of ​​each non-metallic portion 80 constituting the first total, the average area of ​​the non-metallic portions 80 in the first total is calculated.

[0125] Based on the area of ​​the analysis object range and the area of ​​the non-metallic part 80, the proportion of the non-metallic part 80 in the substrate electrode layer 50 is calculated by the following formula (2).

[0126] The proportion of non-metallic parts (%) = (area of ​​non-metallic parts / area of ​​the analysis object) × 100…(2)

[0127] For each of the four parts (R1, R2, R3, R4), the proportion of non-metallic parts 80 is calculated. Then, the average value is calculated as the proportion of non-metallic parts 80 in this embodiment.

[0128] As described above, the measurement range used to calculate the average area of ​​the non-metallic portions 80 in the first totality composed of non-metallic portions 80 with a roundness of 0.4 or less is the set of the analysis ranges of the four parts (R1, R2, R3, R4) mentioned above. Specifically, the measurement range is the portion on the first main surface TS1 side and the portion on the second main surface TS2 side of the first base electrode layer 50A and the second base electrode layer 50B that are in contact with the inner layer portion 11 of the laminate 10. More specifically, the measurement range is the portion of the first base electrode layer 50A and the second base electrode layer 50B from the position in the lamination direction of the boundary between the inner layer portion 11 and the outer layer portion 12 on the first main surface side of the laminate 10 to a position 80 μm toward the center of the lamination direction of the laminate 10, and the portion from the position in the lamination direction of the boundary between the inner layer portion 11 and the outer layer portion 13 on the second main surface side of the laminate 10 to a position 80 μm toward the center of the lamination direction of the laminate 10.

[0129] Next, the manufacturing method of the multilayer ceramic capacitor 1 according to this embodiment will be described. The multilayer ceramic capacitor 1 of this embodiment only needs to meet the above-described requirements, and its manufacturing method is not limited. However, a preferred manufacturing method includes the following steps. Each step will be described in detail below.

[0130] Prepare a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 include a binder and a solvent. The binder and solvent can be known materials. For example, a paste containing conductive materials is obtained by adding an organic binder and an organic solvent to metal powder.

[0131] For example, by using a printing plate with a pattern designed to resemble the shape of the internal electrode layer 30 in this embodiment, a conductive paste for the internal electrode layer 30 is printed on a dielectric sheet using screen printing or gravure printing. This prepares a dielectric sheet having a pattern of the first internal electrode layer 31 and a dielectric sheet having a pattern of the second internal electrode layer 32.

[0132] A predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 are stacked to form a portion of the first main surface side outer layer 12 on the first main surface TS1 side. Dielectric sheets with the pattern of the first internal electrode layer 31 and dielectric sheets with the pattern of the second internal electrode layer 32 are sequentially and alternately stacked thereon to form a portion of the inner layer 11. A predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 are stacked on this inner layer 11 to form a portion of the second main surface side outer layer 13 on the second main surface TS2 side. This yields a laminated sheet.

[0133] Next, the laminated sheets are pressed along the lamination direction using a hydrostatic press or similar mechanism to produce a laminated block.

[0134] Next, the laminated blocks are cut into specified sizes to create individual pieces, resulting in multiple smaller laminated pieces. These smaller pieces can then be ground using methods such as tumbling to give the corners and edges a rounded shape.

[0135] Next, the stacked pieces are fired to obtain the stack 10. The firing temperature at this time is also based on the material of the dielectric layer 20 or the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0136] A conductive paste, forming a base electrode layer 50, is applied to both ends of the laminate 10. In this embodiment, the base electrode layer 50 is a sintered layer. For example, a conductive paste comprising glass and metal components can be applied to the laminate 10 by impregnation or other methods, followed by a sintering process to form the sintered layer. The sintering temperature is preferably 700°C or higher and 900°C or lower.

[0137] It should be noted that the laminated sheets before firing and the conductive paste applied to the laminated sheets can also be fired simultaneously. In this case, it is preferable to form a sintered layer by firing a structure in which ceramic material is added instead of glass. At this time, it is particularly preferable to use a ceramic material of the same type as the dielectric layer 20 as the added ceramic material. In this case, the laminated sheets before firing are coated with conductive paste, and the laminated sheets and the conductive paste applied to the laminated sheets are fired simultaneously to form a laminated body 10 with a sintered layer.

[0138] By changing the shape and particle size distribution of the copper powder added to the conductive paste, the roundness of the non-metallic portion 80 present inside the substrate electrode layer 50 can be controlled. Using spherical copper powder with a wider particle size distribution improves the roundness of the non-metallic portion 80. Conversely, using flat copper powder with a wider particle size distribution decreases the roundness of the non-metallic portion 80.

[0139] By changing the particle size of the copper powder and glass components and the firing temperature, the average area of ​​the non-metallic portion 80 located inside the substrate electrode layer 50 can be controlled. The smaller the particle size of the copper powder and glass components and the higher the firing temperature, the smaller the average area of ​​the non-metallic portion 80. Conversely, the larger the particle size of the copper powder and glass components and the lower the firing temperature, the larger the average area of ​​the non-metallic portion 80.

[0140] By varying the amount of glass component added and the firing temperature, the proportion of non-metallic portion 80 in the substrate electrode layer 50 can be controlled. A higher amount of glass component and a lower firing temperature result in a higher proportion of non-metallic portion 80. Conversely, a lower amount of glass component and a higher firing temperature result in a lower proportion of non-metallic portion 80. The conductive paste comprises 50 vol% to 80 vol% copper powder, 5 vol% to 20 vol% glass component, other solvents, and resin components.

[0141] Subsequently, a plating layer is formed on the surface of the base electrode layer 50, including the sintered layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Additionally, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as plating layers. During the plating process, either electrolytic plating or electroless plating can be used. However, to improve the plating deposition rate in electroless plating, pretreatment using a catalyst or the like is required, which complicates the process. Therefore, electrolytic plating is generally preferred. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0142] It should be noted that when a conductive resin layer is provided, the conductive resin layer can also be configured as a sintered layer. When a conductive resin layer is provided, after applying a conductive resin paste comprising a thermosetting resin and a metal component onto the sintered layer, heat treatment is performed at a temperature of 250–550°C or higher. This causes the thermosetting resin to heat-cur, forming a conductive resin layer. The atmosphere during this heat treatment is preferably N2. Furthermore, to prevent resin scattering and oxidation of the various metal components, the oxygen concentration is preferably 100 ppm or less.

[0143] Through the above manufacturing processes, a multilayer ceramic capacitor 1 is manufactured.

[0144] It should be noted that the structure of the multilayer ceramic capacitor 1 is not limited to... Figures 1-4B The structure shown. For example, the multilayer ceramic capacitor 1 could also be... Figure 7A , Figure 7B and Figure 7C The stacked ceramic capacitors shown are of two-connected, three-connected, and four-connected structures.

[0145] Figure 7A The stacked ceramic capacitor 1 shown is a dual-structure stacked ceramic capacitor 1. As an internal electrode layer 30, in addition to the first internal electrode layer 33 and the second internal electrode layer 34, it also has a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. Figure 7B The stacked ceramic capacitor 1 shown is a stacked ceramic capacitor 1 with a triple structure having a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layer 35. Figure 7C The illustrated multilayer ceramic capacitor 1 is a four-connected multilayer ceramic capacitor 1 having a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. Thus, by providing the floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portions are divided into multiple parts. Consequently, multiple capacitor components are formed between the opposing internal electrode layers 30, forming a structure in which these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is lower, and a high withstand voltage can be achieved for the multilayer ceramic capacitor 1. It should be noted that the multilayer ceramic capacitor 1 of this embodiment can of course also be a multi-connected structure with four or more layers.

[0146] It should be noted that the multilayer ceramic capacitor 1 can be a two-terminal multilayer ceramic capacitor with two external electrodes, or a multi-terminal multilayer ceramic capacitor with multiple external electrodes.

[0147] It should be noted that, in the above embodiments, a multilayer ceramic electronic component is exemplified as a multilayer ceramic capacitor in which the dielectric layer 20, made of dielectric ceramic, is used as the ceramic layer. However, the multilayer ceramic electronic component of this disclosure is not limited to this. For example, the ceramic electronic component of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer and thermistors using semiconductor ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, and examples of semiconductor ceramics include spinel ceramics.

[0148] The multilayer ceramic capacitor 1 according to the above-described embodiments has the following effects.

[0149] The multilayer ceramic capacitor 1 of the embodiment includes: a multilayer body 10, which includes a dielectric layer 20, which are multiple ceramic layers, alternately stacked in the stacking direction T, and an internal electrode layer 30, which are multiple internal conductor layers, and includes a first main surface TS1 and a second main surface TS2 opposite to each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the stacking direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the stacking direction T and the length direction L; and a pair of external electrodes 40, which are respectively disposed separately at both ends of the multilayer body 10 in the length direction L, and the internal electrode layer 30 includes a first end surface LS1 extending to the first end surface LS1 as a first electrode layer TS1. The first internal electrode layer 31 of the internal conductor layer and the second internal electrode layer 32 extending to the second end face LS2 as the second internal conductor layer are included. The external electrode 40 has: a first external electrode 40A, which includes a first base electrode layer 50A connected to the first internal electrode layer 31; and a second external electrode 40B, which includes a second base electrode layer 50B connected to the second internal electrode layer 32. The first base electrode layer 50A and the second base electrode layer 50B have metal portions 70 and a plurality of non-metal portions 80 present in the metal portions 70. In a cross-sectional view perpendicular to the width direction W, the average area of ​​the non-metal portions 80 in the first whole composed of non-metal portions 80 with a roundness of 0.4 or less is 12 μm. 2 the following.

[0150] As a result, the non-metallic portions 80 of the first base electrode layer 50A and the second base electrode layer 50B are less likely to become pathways for moisture to penetrate from the outside to the inside, resulting in higher moisture resistance reliability of the multilayer ceramic capacitor 1.

[0151] In the multilayer ceramic capacitor 1 of the embodiment, it is preferable that the first base electrode layer 50A and the second base electrode layer 50B are sintered layers.

[0152] Therefore, when forming the first base electrode layer 50A and the second base electrode layer 50B, a simpler method can be used compared to forming them by thin film formation methods such as sputtering or vapor deposition. Furthermore, by forming the sintered layer simultaneously with the firing of the laminate 10, the manufacturing process can be simplified.

[0153] In the multilayer ceramic capacitor 1 of the embodiment, it is preferable that, in a cross-sectional view perpendicular to the width direction W, the proportion of non-metallic portions 80 in the first base electrode layer 50A and the second base electrode layer 50B is 17.2% or less.

[0154] As a result, the non-metallic portions 80 of the first base electrode layer 50A and the second base electrode layer 50B are also less likely to become pathways for moisture to penetrate from the outside to the inside, resulting in higher moisture resistance reliability of the multilayer ceramic capacitor 1.

[0155] This invention is not limited to the structures described in the above embodiments, and can be applied by appropriate modifications without changing the spirit of the invention. It should be noted that structures obtained by combining two or more of the desired structures described in the above embodiments also belong to this invention.

[0156] [Example]

[0157] The following describes the embodiments. Multiple batches of multilayer ceramic capacitors, manufactured according to the manufacturing method described in the above embodiments, with varying average areas of the non-metallic portions in the first overall structure within the base electrode layer, were prepared as test materials for Examples 1 to 6 and the comparative examples. Examples 1 to 6 are multilayer ceramic capacitors satisfying the present invention, while the comparative examples are multilayer ceramic capacitors other than those of the present invention. Test materials from the same batch were manufactured under the same manufacturing conditions, and the specifications of the base electrode layer were identical. For each batch (Examples 1 to 6 and the comparative examples), 72 test materials were prepared. Next, the prepared test materials were subjected to a moisture resistance reliability test. Furthermore, the test materials after the moisture resistance reliability test were ground, and parameters such as the average area of ​​the non-metallic portions in the first overall structure were measured using the above-described measurement method.

[0158] It should be noted that the samples were prepared according to the following specifications during manufacturing.

[0159] • Dimensions of the multilayer ceramic capacitor: L×W×T=1.6mm×0.8mm×0.8mm

[0160] • Dielectric layer: BaTiO3

[0161] • Capacitance: 10μF

[0162] Rated voltage: 25V

[0163] • Substrate electrode layer: comprising electrodes of conductive metal (Cu) and glass composition (the thickness of the substrate electrode layer disposed on the first end face and the second end face respectively: 36 μm)

[0164] • Coating layer: Forms a bilayer consisting of a Ni coating layer (2μm) and a Sn coating layer (4μm).

[0165] • Internal electrode layer: Ni

[0166] Table 1 shows the measurement results of the average area of ​​the non-metallic portion in the first overall sample and the proportion of the non-metallic portion in the substrate electrode layer for the samples of Examples 1 to 6 and the comparative examples. It should be noted that the measurement results are the average values ​​of 10 samples randomly selected from each of the 72 samples.

[0167] The moisture resistance reliability test was conducted at 85°C / 85% RH. The IR value (insulation resistance) before and after the test was measured at the rated voltage to confirm the change. Specifically, the IR value was measured after a 60-second charging time at the rated voltage. Samples whose IR value after the moisture resistance test decreased by more than 10% compared to the IR value before the test (samples with an IR value less than 1 / 10 of the original value) were classified as "NG samples" (unacceptable for moisture resistance reliability). Samples whose IR value after the moisture resistance test decreased by more than 0.3% but less than 10% compared to the IR value before the test were classified as "IR-decreased samples" (samples with decreased IR value). These results are presented in Table 1.

[0168] [Table 1]

[0169]

[0170] According to Table 1, the average area of ​​the non-metallic portion in the first total exceeds 12 μm. 2 At that time, the sample exhibiting poor moisture resistance reliability was deemed unacceptable. On the other hand, as in Examples 1 to 6, if the average area of ​​the non-metallic portion in the first aggregate is 12 μm... 2 The moisture resistance reliability results are good. Therefore, the average area of ​​the non-metallic portion in the first overall structure is 12 μm. 2 The following are preferred in terms of ensuring moisture resistance reliability.

[0171] It should be noted that although no sample with NG moisture resistance reliability was produced in Example 1, a sample with decreased IR was produced in the moisture resistance reliability test. Therefore, it can be said that the average area of ​​the non-metallic portion in the first overall sample is more preferably 9 μm. 2 the following.

[0172] For example, the average area of ​​the non-metallic portion constituting the first total is preferably 2 μm. 2 Above and 12μm 2 Below, 2μm is more preferred. 2 Above and 9μm 2 The following is an example. Therefore, moisture resistance reliability is improved.

[0173] Furthermore, the proportion of non-metallic portions in the substrate electrode layer is preferably 17.2% or less. For example, the proportion of non-metallic portions in the substrate electrode layer is preferably 1.5% or more and 17.2% or less.

Claims

1. A laminated ceramic electronic component, comprising: A laminate includes a plurality of ceramic layers and a plurality of internal conductor layers alternately stacked in a stacking direction, and includes a first main surface and a second main surface opposite to each other in the stacking direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction and the length direction. as well as A pair of external electrodes are respectively disposed at both ends of the laminate along its length. The internal conductor layer includes: The first internal conductor layer extending to the first end face; and The second internal conductor layer extends to the second end face. The external electrode has: A first external electrode, comprising a first base electrode layer connected to the first internal conductor layer; and The second external electrode includes a second base electrode layer connected to the second internal conductor layer. The first base electrode layer and the second base electrode layer have a metal portion and a plurality of non-metal portions present within the metal portion. In a cross-sectional view perpendicular to the width direction, The average area of ​​the non-metallic portion in the first aggregate, which is composed of non-metallic portions with a roundness of 0.4 or less, is 12 μm. 2 the following.

2. The laminated ceramic electronic component according to claim 1, wherein, The first substrate electrode layer and the second substrate electrode layer are sintered layers.

3. The laminated ceramic electronic component according to claim 1 or 2, wherein, In a cross-sectional view perpendicular to the width direction, The proportion of the non-metallic portion in the first base electrode layer and the second base electrode layer is 17.2% or less.

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