Global data lines for multi-array synchronous random access memory (SRAM)

Abstract

Various aspects include a circuit having single-rail static operating global data lines for a synchronous random access memory (SRAM). The circuit can include one or more auto tri-state drivers coupled to the single-rail static operating global data lines of the SRAM. The circuit can include one or more sense amplifiers coupled to the one or more auto tri-state drivers. The circuit can include latches coupled to the single-rail static operating global data lines. Some embodiments can include a method for operating global data lines of a multi-array SRAM. The method can include connecting single-rail static operating global data lines of the SRAM to one or more auto tri-state drivers of the SRAM, and operating the one or more auto tri-state drivers without a strobe signal. The method can include operating the single-rail global data lines of the SRAM with a static signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application Serial No. 63 / 336,918, filed April 29, 2022, and U.S. Application Serial No. 18 / 076,388, filed December 6, 2022, which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to synchronous random access memory (SRAM), and more specifically, to the global data line of a multi-array SRAM. Background Technology

[0004] High-density SRAM devices with two or more subarrays can use a global data line to fetch output data from bit cells of the subarrays. The global data line can be heavily loaded because it may operate across different bit cells in different subarrays (such as blocks 0 through 3). The load placed on the global data line consumes a significant portion of the SRAM device's total timing and power budget. Summary of the Invention

[0005] Various aspects include circuitry with a single-rail statically operating global data line having synchronous random access memory (SRAM). This circuitry may include one or more automatic tri-state drivers coupled to the single-rail statically operating global data line of the SRAM. The circuitry may include one or more sense amplifiers coupled to the one or more automatic tri-state drivers. The circuitry may include latches coupled to the single-rail statically operating global data line.

[0006] Some embodiments may include a method of operating the global data lines of a multi-array SRAM. This method may include connecting a single-rail static operating global data line of the SRAM to one or more automatic tri-state drivers of the SRAM, and operating the one or more automatic tri-state drivers without a strobe signal. This method may also include operating the single-rail global data lines of the SRAM using static signals. Attached Figure Description

[0007] The foregoing and additional features and advantages of this disclosure will become clearer from the following detailed description with reference to the accompanying drawings, in which:

[0008] Figure 1 Circuits according to some embodiments disclosed herein are shown.

[0009] Figure 2 A circuit including an automatic tri-state driver for SRAM is shown according to some embodiments disclosed herein.

[0010] Figure 3 Some embodiments according to the disclosure herein are shown. Figure 2 The details of the circuit.

[0011] Figure 4 The following diagram illustrates some embodiments disclosed herein. Figure 2 and Figure 3 The timing diagram related to the circuit.

[0012] Figure 5 This is a flowchart illustrating techniques for operating global data lines of a multi-array SRAM according to some embodiments disclosed herein. Detailed Implementation

[0013] Reference will now be made in detail to the embodiments disclosed herein, examples of which are illustrated in the accompanying drawings. Several specific details are set forth in the following detailed description to provide a thorough understanding of the inventive concept. However, it should be understood that those skilled in the art can practice the inventive concept without these specific details. In other instances, well-known methods, processes, components, circuits, and networks have not been described in detail to avoid unnecessarily obscuring various aspects of the embodiments.

[0014] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the inventive concept, a first circuit may be referred to as a second circuit, and similarly, a second circuit may be referred to as a first circuit.

[0015] The terminology used in the description of this invention is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. As used in the description of the invention and the appended claims, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. It will also be understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. Components and features in the accompanying drawings are not necessarily drawn to scale.

[0016] The embodiments disclosed herein include components of multi-array SRAMs with improved power characteristics and enhanced channel availability. The SRAM components disclosed herein may include one or more circuits having a single-rail statically operating global data line, static signals, and one or more automatic tri-state drivers operating using dynamic operation.

[0017] Figure 1 A circuit 100 according to some embodiments disclosed herein is shown. Circuit 100 may include a first portion 105 having a first sense amplifier (amp) SA0 and a second sense amplifier SA1. The first sense amplifier SA0 may receive a sense amplifier enable SA0_EN input signal. The second sense amplifier SA1 may receive a sense amplifier enable SA1_EN input signal. The first sense amplifier SA0 may be coupled to one or more bit lines associated with block 0. The second sense amplifier SA1 may be coupled to one or more bit lines associated with block 1. The output of the first sense amplifier SA0 may be coupled to a first input of a NAND gate 110. The output of the second sense amplifier SA1 may be coupled to a second input of the NAND gate 110. The output of the NAND gate 110 may be coupled to a first tri-state static driver 115.

[0018] The first tri-state static driver 115 can receive a strobe signal (i.e., SEC_SELO). The first tri-state static driver 115 can be coupled to the global data line 120. The global data line 120 can be coupled to the second tri-state static driver 125. The second tri-state static driver 125 can receive a strobe signal (i.e., SEC_SEL1). Circuit 100 may include a second portion 130 having a first sense amplifier SA0 and a second sense amplifier SA1. The second portion 130 can be coupled to the second tri-state static driver 125.

[0019] The first sense amplifier SA0 of the second part 130 can be coupled to one or more bit lines associated with block 0 of the second part 130. The second sense amplifier SA1 of the second part 130 can be coupled to one or more bit lines associated with block 1 of the second part 130. The output of the first sense amplifier SA0 of the second part 130 can be coupled to the first input of NAND gate 135. The output of the second sense amplifier SA1 of the second part 130 can be coupled to the second input of NAND gate 135. The output of NAND gate 135 can be coupled to the second tri-state static driver 125. The global data line 120 can be coupled to latch 140. Latch 140 can receive latch signal 145 (e.g., LATCH not), i.e., ... Figure 1 shown ) and global data line precharge signal 150 (e.g., GDL_PRECHARGE not, i.e., as Figure 1 shown ).

[0020] Figure 2Circuitry 200 including an auto-tri-state dynamic driver (e.g., 215, 225) of SRAM 202 is shown according to some embodiments disclosed herein. For improved power characteristics and channel availability, a single-rail static global data line 220 is preferred over a dual-rail global data line. For reduced power consumption, static signals on the global data line 220 are preferred over dynamic (i.e., pulsed) signals. Static global data lines can be characterized by high (H) / low (L) signal transitions H->L, H->H, L->H, and L->L. Conversely, dynamic global data lines can be characterized by H / L signal transitions H->L, H->H, L->H, and L->H->L. For improved circuit speed characteristics, an auto-tri-state driver (e.g., 215, 225) is preferred over a static driver.

[0021] Circuit 200 may include a first portion 205 having a sense amplifier SA0. The sense amplifier SA0 may receive an SA0_EN input signal. The sense amplifier SA0 may be coupled to one or more bit lines associated with block 0. Alternatively or additionally, the sense amplifier SA0 may be coupled to one or more bit lines associated with block 1. The output of the sense amplifier SA0 may be directly coupled to a first automatic tri-state driver 215. Portion 205 of circuit 200 does not need to include NAND gates as portion 105 of circuit 100. The first automatic tri-state driver 215 does not need to include a strobe signal, such as the strobe signal SEC_SELO of circuit 100.

[0022] The first automatic tri-state driver 215 can receive an output signal from the sense amplifier SA0. The first automatic tri-state driver 215 can be coupled to a single-rail static global data line 220. The single-rail static global data line 220 can be coupled to a second automatic tri-state driver 225. Circuit 200 may include a second portion 230 with a sense amplifier SA1. The sense amplifier SA1 can receive an input signal (e.g., SA1_EN). The second portion 230 can be coupled to the second automatic tri-state driver 225. The second automatic tri-state driver 225 does not need to include a strobe signal, such as the strobe signal SEC_SEL1 of circuit 100. The tri-state drivers (e.g., 215, 225) are automatic because they convert dynamic signals to static signals without any strobe signal.

[0023] The sense amplifier SA1 of the second part 230 can be coupled to one or more bit lines associated with block 2 of the second part 230. Alternatively or additionally, the sense amplifier SA1 of the second part 230 can be coupled to one or more bit lines associated with block 3 of the second part 230. The output of the sense amplifier SA1 of the second part 230 can be directly coupled to the automatic tri-state driver 225. Part 230 of circuit 200 does not need to include NAND gates like part 130 of circuit 100.

[0024] The single-rail static global data line 220 can be coupled to latch 240. Latch 240 can receive a latch enable signal 245 (e.g., LATEN). Latch 240 does not need to receive a global data line precharge signal 150 like latch 140 in circuit 100, and the single-rail static global data line 220 does not need to be precharged because it operates statically rather than pulsed. Circuit 200 may include a data output buffer 255 coupled to the single-rail static global data line 220, which can output an output signal Dout.

[0025] Figure 3 Some embodiments according to the disclosure herein are shown. Figure 2 Details of circuit 200 are shown. Specifically, details of the sensing amplifier SA0 of portion 205 of circuit 200 and the automatic three-state driver 215 of circuit 200 are shown. It should be understood that the sensing amplifier SA1 of portion 230 is the same as or similar to the sensing amplifier SA0, therefore, details of the sensing amplifier SA1 are not shown. Similarly, the second automatic three-state driver 225 is the same as or similar to the first automatic three-state driver 215, therefore, details of the second automatic three-state driver 225 are not shown.

[0026] The sense amplifier SA0 may include P-type transistors P1 and P2, N-type transistors N1, N2, and N3. Node SL may be coupled to transistors P1 and N1. Node SL may be coupled to line 305 from a bit line (e.g., from b1). Node SLB may be coupled to transistors P2 and N2. Node SLB may be coupled to line 310 from a bit line (e.g., from blb). The gate of transistor N3 may receive the SA0_EN input signal.

[0027] The automatic tri-state driver 215 may include P-type transistors P3, P4, P5, and P6. The automatic tri-state driver 215 may also include N-type transistors N4, N5, N6, and N7. Transistors P4 and N5 may be coupled to node NODE1. Transistors P6 and N6 may be coupled to node NODE2. Transistors P5 and N7 include a dynamic driver 315. Transistors P5 and N7 of the dynamic driver 315 may be coupled to nodes NODE1 and NODE2, respectively. The dynamic driver 315 may receive a Datah_l signal at the gate of transistor P5 and a Datal signal at the gate of transistor N7. The dynamic driver 315 may be coupled to a single-rail static operation global data line 220. The single-rail static operation global data line 220 may consume approximately 1 / 4 of the power of a dual-rail dynamic operation (i.e., pulse signal) global data line and approximately 1 / 2 of the power of a single-rail dynamic operation (i.e., pulse signal) global data line.

[0028] Using a dynamic driver 315 can improve circuit speed because dynamic gates are significantly faster than static gates for heavy-load circuits. Furthermore, the automatic tri-state driver 215 does not require a strobe signal (e.g., Figure 1 The SEC_SEL method improves circuit speed, reduces the number of gates (i.e., reduces circuit area), and eliminates stack gates and timing complexity. Furthermore, using a single-rail static global data line 220 improves routing channel availability and delivers at least twice the performance of a dual-rail system.

[0029] More specifically, circuit 200 may include a single-rail statically operating global data line 220 of SRAM 202. One or more automatic tri-state drivers (e.g., 215, 225) may be coupled to the single-rail statically operating global data line 220 of SRAM 202. Circuit 200 may include one or more sense amplifiers (e.g., SA0, SA1) respectively directly coupled to one or more automatic tri-state drivers (e.g., 215, 225). Circuit 200 may include one or more bit cells of one or more subarrays (e.g., block 0, block 1, block 2, block 3) coupled to one or more sense amplifiers (e.g., SA0, SA1). Circuit 200 may include a latch 240 coupled to the single-rail statically operating global data line 220. In some embodiments, the latch is configured to receive a latch enable signal and is configured not to receive a precharge signal.

[0030] In some embodiments, one or more automatic tri-state drivers (e.g., 215, 225) include a first automatic tri-state driver 215 coupled to a single-track static global data line 220 of SRAM 202, a first sense amplifier SA0 directly coupled to the first automatic tri-state driver 215, a second automatic tri-state driver 225 coupled to the single-track static global data line 220 of SRAM 202, and a second sense amplifier SA1 directly coupled to the second automatic tri-state driver 225.

[0031] In some embodiments, the first automatic tri-state driver 215 includes a P-type transistor P3, a P-type transistor P4, an N-type transistor N4 coupled to transistor P3, an N-type transistor N5 coupled to transistor P4, a first node NODE1 coupled to transistors P4 and N5, a P-type transistor P5, a P-type transistor P6, an N-type transistor N6, an N-type transistor N7 coupled to transistor P5, and a second node NODE2 coupled to transistors P6 and N6. In some embodiments, the first node NODE1 is directly coupled to the gate of transistor P5, the second node NODE2 is directly coupled to the gate of transistor N7, and transistors P5 and N7 are directly coupled to the single-rail static operation global data line 220.

[0032] In some embodiments, the first sensing amplifier SA0 includes P-type transistors P1 and P2, N-type transistors N1 and N2, a first node SL coupled to transistors P1 and N1, and a second node SLB coupled to transistors P2 and N2. In some embodiments, the second node SLB is directly coupled to transistors P3 and N4 of the first automatic tri-state driver 215.

[0033] In some embodiments, the second automatic tri-state driver 225 includes a P-type transistor P3, a P-type transistor P4, an N-type transistor N4 coupled to transistor P3, an N-type transistor N5 coupled to transistor P4, a first node NODE1 coupled to transistors P4 and N5, a P-type transistor P5, a P-type transistor P6, an N-type transistor N6, an N-type transistor N7 coupled to transistor P5, and a second node NODE2 coupled to transistors P6 and N6. In some embodiments, the first node NODE1 is directly coupled to the gate of transistor P5, the second node NODE2 is directly coupled to the gate of transistor N7, and transistors P5 and N7 are directly coupled to the single-rail static operation global data line 220.

[0034] In some embodiments, the second sensing amplifier SA1 includes P-type transistor P1, P-type transistor P2, N-type transistor N1, N-type transistor N2, a first node SL coupled to transistors P1 and N1, and a second node SLB coupled to transistors P2 and N2. In some embodiments, the second node SLB is directly coupled to transistors P3 and N4 of the second automatic tri-state driver 225.

[0035] Figure 4 The following diagram illustrates some embodiments disclosed herein. Figure 2 and Figure 3 The timing diagram 400 is related to the circuit. Timing diagram 400 includes a clock signal CLK, a sense amplifier enable signal SA_EN (e.g., SA0_EN and / or SA1_EN), node SL, node SLB, Datah_l signal, Datal signal, latch enable signal LATEN, and static operation global data line signals. At 405, the clock signal CLK can transition to a high level, which causes the sense amplifier enable signal SA_EN to transition to a high level at 410. Furthermore, the transition of the clock signal CLK to a high level causes the latch enable signal LATEN to transition from a high level to a low level at 415, thereby turning off the latch (e.g., ...). Figure 2 (of 240).

[0036] After the SA_EN signal transitions high at 410, the SL and SLB nodes can resolve to specific high and / or low levels, as shown at 420. This allows the Datah_l signal to transition from high to low at 425. The transition of the Datah_l signal from high to low allows the global data line to transition from low to high at 430. The LATEN signal can transition from low to high at 435, thereby reactivating the latch. The SA_EN signal can transition back from high to low at 440.

[0037] The SA_EN signal can transition from low to high at 445. The SL and SLB nodes can transition to specific high and / or low levels, as shown at 450, which allows the Data1 signal to transition from low to high at 455, and the global data line signals to transition from high to low at 460.

[0038] Figure 5 This is a flowchart 500 illustrating techniques for operating global data lines of a multi-array SRAM according to some embodiments disclosed herein. Referring now to... Figure 2 and Figure 5At 505, one or more auto tri-state drivers (e.g., 215, 225) of SRAM 202 convert dynamic signals to static signals when no strobe signal (e.g., SEC_SEL) is present. At 510, the single-rail static global data line 220 of SRAM 202 receives static signals from one or more auto tri-state drivers (e.g., 215, 225). At 515, the single-rail global data line 220 of SRAM 202 outputs data to a data output buffer (e.g., 255).

[0039] The various operations described above can be performed by any suitable component capable of performing the operations, such as various hardware and / or software components, circuits and / or modules.

[0040] The blocks or steps and functions of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly in hardware, as software modules executed by a processor, or a combination of both. If implemented in software, these functions can be stored or transmitted as one or more instructions or code on a tangible, non-transitory computer-readable medium. The software modules can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0041] The following discussion aims to provide a brief overview of one or more suitable machines that can implement certain aspects of the inventive concept. Typically, one or more machines include a system bus, a processor, memory (e.g., RAM, ROM, or other state-saving media), storage devices, video interfaces, and input / output interface ports attached to this system bus. One or more machines can be controlled at least in part by input from conventional input devices such as keyboards, mice, etc., and by instructions received from another machine, interaction with a virtual reality (VR) environment, biometric feedback, or other input signals. As used herein, the term "machine" is intended to broadly encompass a single machine, a virtual machine, or a system of communication-coupled machines, virtual machines, or devices operating together. Exemplary machines include computing devices such as personal computers, workstations, servers, portable computers, handheld devices, telephones, tablets, etc., and transportation devices such as private or public transportation equipment, such as cars, trains, taxis, etc.

[0042] One or more machines may include embedded controllers, such as programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), embedded computers, smart cards, etc. One or more machines may utilize one or more connections to one or more remote machines, such as via network interfaces, modems, or other communication coupling. Machines may be interconnected via physical and / or logical networks (such as intranets, the Internet, local area networks, wide area networks, etc.). Those skilled in the art will understand that network communications can utilize various wired and / or wireless short-range or long-range carriers and protocols, including radio frequency (RF), satellite, microwave, and Institute of Electrical and Electronics Engineers (IEEE) 545.11. Optics, infrared, cables, lasers, etc.

[0043] Embodiments of this disclosure can be described by reference to or in conjunction with associated data (including functions, programs, data structures, applications, etc.), which, when accessed by a machine, enable the machine to perform tasks or define abstract data types or low-level hardware contexts. Associated data can be stored, for example, in volatile and / or non-volatile memory (e.g., RAM, ROM, etc.), or in other storage devices and their associated storage media (including hard disk drives, floppy disks, optical storage, magnetic tape, flash memory, memory sticks, digital video disks, bio-storage devices, etc.). Associated data can be transmitted in a transmission environment including physical and / or logical networks in the form of packets, serial data, parallel data, propagated signals, etc., and can be used in compressed or encrypted formats. Associated data can be used in a distributed environment and stored locally and / or remotely for machine access.

[0044] Having described and illustrated the principles of this disclosure with reference to the illustrated embodiments, it should be understood that the illustrated embodiments may be modified in arrangement and detail without departing from such principles, and may be combined in any desired manner. Furthermore, although the foregoing discussion focuses on specific embodiments, other configurations are also contemplated. In particular, although expressions such as "embodiments according to the concept of the invention" are used herein, these phrases are intended to generally refer to the possibilities of embodiments and not to limit the inventive concept to specific embodiment configurations. As used herein, these terms may refer to the same or different embodiments that can be combined into other embodiments.

[0045] Embodiments of this disclosure may include a non-transitory machine-readable medium comprising instructions executable by one or more processors, including instructions for performing elements of the inventive concept described herein.

[0046] The foregoing illustrative embodiments should not be construed as limiting the inventive concept. Although several embodiments have been described, those skilled in the art will readily understand that various modifications to these embodiments are possible without departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A circuit for a synchronous random access memory (SRAM), comprising: The SRAM has a single-track static operation global data line; as well as An automatic tri-state driver is coupled to the single-rail static operation global data line of the SRAM. The automatic three-state driver includes: The first automatic tri-state driver is coupled to the single-rail static operation global data line of the SRAM; The first sensing amplifier is directly coupled to the first automatic three-state driver; The first line is directly coupled to the first sense amplifier and directly coupled to the first automatic tri-state driver; The second automatic tri-state driver is coupled to the single-rail static operation global data line of the SRAM; The second sensing amplifier is directly coupled to the second automatic tri-state driver; and The second bit line is directly coupled to the second sense amplifier and directly coupled to the second automatic tri-state driver.

2. The circuit of claim 1 further includes one or more bit cells coupled to one or more subarrays of the first sense amplifier and one or more bit cells coupled to one or more subarrays of the second sense amplifier.

3. The circuit according to claim 1 further includes a latch coupled to the single-rail static operation global data line.

4. The circuit according to claim 3, wherein, The latch is configured to receive a latch enable signal and is configured not to receive a precharge signal.

5. The circuit according to claim 1, wherein, Each of the first sensing amplifier and the second sensing amplifier includes: P-type transistor P1; P-type transistor P2; N-type transistor N1; N-type transistor N2; The first node is coupled to transistor P1 and transistor N1; and The second node is coupled to transistors P2 and N2.

6. The circuit according to claim 5, wherein, Each of the first sensing amplifier and the second sensing amplifier includes an N-type transistor N3 coupled to transistors N1 and N2.

7. The circuit according to claim 5, wherein, The second node is directly coupled to the automatic tri-state driver.

8. The circuit according to claim 1, wherein, Each of the first automatic tri-state driver and the second automatic tri-state driver includes: P-type transistor P3; P-type transistor P4; N-type transistor N4 is coupled to transistor P3; N-type transistor N5 is coupled to transistor P4; and The first node is coupled to transistor P4 and transistor N5.

9. The circuit according to claim 8, wherein, Each of the first automatic tri-state driver and the second automatic tri-state driver further includes: P-type transistor P5; P-type transistor P6; N-type transistor N6; N-type transistor N7 is coupled to transistor P5; and The second node is coupled to transistors P6 and N6, where: The transistors P3 and P4 of the first automatic three-state driver are directly coupled to the third bit line; The transistors P3 and P4 of the second automatic tri-state driver are directly coupled to the fourth bit line; In the first automatic three-state driver, transistors P6 and N6 are directly coupled to the first bit line; and The transistors P6 and N6 of the second automatic tri-state driver are directly coupled to the second bit line.

10. The circuit according to claim 9, wherein, The first node is directly coupled to the gate of transistor P5.

11. The circuit according to claim 10, wherein, The second node is directly coupled to the gate of transistor N7.

12. The circuit according to claim 11, wherein, Transistor P5 and transistor N7 are directly coupled to the single-rail static operation global data line.

13. The circuit according to claim 1, wherein, The first automatic three-state driver includes: P-type transistor P3; P-type transistor P4; N-type transistor N4 is coupled to transistor P3; N-type transistor N5 is coupled to transistor P4; The first node is coupled to transistor P4 and transistor N5; P-type transistor P5; P-type transistor P6; N-type transistor N6; N-type transistor N7 is coupled to transistor P5; The second node is coupled to transistors P6 and N6, where: The first node is directly coupled to the gate of transistor P5; The second node is directly coupled to the gate of transistor N7; and Transistor P5 and transistor N7 are directly coupled to the single-rail static operation global data line.

14. The circuit according to claim 13, wherein, The first sensing amplifier includes: P-type transistor P1; P-type transistor P2; N-type transistor N1; N-type transistor N2; The first node is coupled to transistor P1 and transistor N1; and The second node is coupled to transistors P2 and N2. The second node is directly coupled to transistors P3 and N4 of the first automatic tri-state driver.

15. The circuit according to claim 1, wherein, The second automatic tri-state driver includes: P-type transistor P3; P-type transistor P4; N-type transistor N4 is coupled to transistor P3; N-type transistor N5 is coupled to transistor P4; The first node is coupled to transistor P4 and transistor N5; P-type transistor P5; P-type transistor P6; N-type transistor N6; N-type transistor N7 is coupled to transistor P5; The second node is coupled to transistors P6 and N6, where: The first node is directly coupled to the gate of transistor P5; The second node is directly coupled to the gate of transistor N7; and Transistor P5 and transistor N7 are directly coupled to the single-rail static operation global data line: The transistors P3 and P4 of the first automatic three-state driver are directly coupled to the third bit line; The transistors P3 and P4 of the second automatic tri-state driver are directly coupled to the fourth bit line; In the first automatic three-state driver, transistors P6 and N6 are directly coupled to the first bit line; and The transistors P6 and N6 of the second automatic tri-state driver are directly coupled to the second bit line.

16. The circuit according to claim 15, wherein, The second sensing amplifier includes: P-type transistor P1; P-type transistor P2; N-type transistor N1; N-type transistor N2; The first node is coupled to transistor P1 and transistor N1; and The second node is coupled to transistors P2 and N2. The second node is directly coupled to transistors P3 and N4 of the second automatic tri-state driver.

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